Freescale Semiconductor Mcf5480 Users Manual MCF5485 Reference
MCF5482 to the manual 710a7783-54b3-4687-a8c8-7060b4d7ef8c
2015-02-09
: Freescale-Semiconductor Freescale-Semiconductor-Mcf5480-Users-Manual-552182 freescale-semiconductor-mcf5480-users-manual-552182 freescale-semiconductor pdf
Open the PDF directly: View PDF 
.
Page Count: 1032
| Download | |
| Open PDF In Browser | View PDF |
MCF548x Reference Manual Devices Supported: MCF5485 MCF5484 MCF5483 MCF5482 MCF5481 MCF5480 Document Number: MCF5485RM Rev. 3 01/2006 How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) support@freescale.com Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064, Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong +800 26668334 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006. All rights reserved. MCF5485RM Rev. 3 01/2006 Overview Signal Descriptions ColdFire Core Enhanced Multiply-Accumulate Unit (EMAC) Memory Management Unit (MMU) Floating-Point Unit (FPU) Local Memory Debug Support System Integration Unit (SIU) Internal Clocks and Bus Architecture General Purpose Timers (GPT) Slice Timers (SLT) Interrupt Controller (INTC) Edge Port Module (EPORT) General Purpose I/O (GPIO) System SRAM FlexBus SDRAM Controller (SDRAMC) PCI Bus Controller (PCI) PCI Bus Arbiter (PCIARB) FlexCAN Integrated Secuity Engine (SEC) IEEE 1149.1 Test Access Port (JTAG) Multichannel DMA (MCD) Comm Timer Module (CTM) Programmable Serial Controller (PSC) I2C interface DMA Serial Peripheral Interface (DSPI) USB 2.0 Device Controller Fast Ethernet Controller (FEC) Mechanical Data 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Register Memory Map Quick Reference Index A IND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 A IND Overview Signal Descriptions ColdFire Core Enhanced Multiply-Accumulate Unit (EMAC) Memory Management Unit (MMU) Floating-Point Unit (FPU) Local Memory Debug Support System Integration Unit (SIU) Internal Clocks and Bus Architecture General Purpose Timers (GPT) Slice Timers (SLT) Interrupt Controller (INTC) Edge Port Module (EPORT) General Purpose I/O (GPIO) System SRAM FlexBus SDRAM Controller (SDRAMC) PCI Bus Controller (PCI) PCI Bus Arbiter (PCIARB) FlexCAN Integrated Secuity Engine (SEC) IEEE 1149.1 Test Access Port (JTAG) Multichannel DMA (MCD) Comm Timer Module (CTM) Programmable Serial Controller (PSC) I2C interface DMA Serial Peripheral Interface (DSPI) USB 2.0 Device Controller Fast Ethernet Controller (FEC) Mechanical Data Register Memory Map Quick Reference Index Contents Paragraph Number Title Page Number Chapter 1 Overview 1.1 1.2 1.3 1.4 1.4.1 1.4.2 1.4.3 1.4.4 1.4.4.1 1.4.4.2 1.4.5 1.4.6 1.4.6.1 1.4.6.2 1.4.6.3 1.4.6.4 1.4.6.5 1.4.6.6 1.4.6.7 1.4.7 1.4.8 1.4.9 1.4.10 1.4.11 1.4.11.1 1.4.11.2 1.4.11.3 MCF548x Family Overview ........................................................................................... 1-1 MCF548x Block Diagram .............................................................................................. 1-2 MCF548x Family Products ............................................................................................. 1-3 MCF548x Family Features ............................................................................................. 1-3 ColdFire V4e Core Overview ..................................................................................... 1-5 Debug Module (BDM) ................................................................................................ 1-6 JTAG ........................................................................................................................... 1-6 On-Chip Memories ..................................................................................................... 1-7 Caches ..................................................................................................................... 1-7 System SRAM ........................................................................................................ 1-7 PLL and Chip Clocking Options ................................................................................ 1-7 Communications I/O Subsystem ................................................................................ 1-8 DMA Controller ...................................................................................................... 1-8 10/100 Fast Ethernet Controller (FEC) ................................................................... 1-8 USB 2.0 Device (Universal Serial Bus) ................................................................. 1-8 Programmable Serial Controllers (PSCs) ............................................................... 1-9 I2C (Inter-Integrated Circuit) ................................................................................. 1-9 DMA Serial Peripheral Interface (DSPI) ................................................................ 1-9 Controller Area Network (CAN) .......................................................................... 1-10 DDR SDRAM Memory Controller ........................................................................... 1-10 Peripheral Component Interconnect (PCI) ............................................................... 1-10 Flexible Local Bus (FlexBus) ................................................................................... 1-10 Security Encryption Controller (SEC) ...................................................................... 1-11 System Integration Unit (SIU) .................................................................................. 1-11 Timers ................................................................................................................... 1-11 Interrupt Controller ............................................................................................... 1-12 General Purpose I/O ............................................................................................. 1-12 Chapter 2 Signal Descriptions 2.1 2.1.1 2.2 2.2.1 2.2.1.1 2.2.1.2 2.2.1.3 Introduction ..................................................................................................................... 2-1 Block Diagram ............................................................................................................ 2-1 MCF548x External Signals ........................................................................................... 2-16 FlexBus Signals ........................................................................................................ 2-16 Address/Data Bus (AD[31:0]) .............................................................................. 2-16 Chip Select (FBCS[5:0]) ....................................................................................... 2-17 Address Latch Enable (ALE) ................................................................................ 2-17 MCF548x Reference Manual, Rev. 3 Freescale Semiconductor v Contents Paragraph Number 2.2.1.4 2.2.1.5 2.2.1.6 2.2.1.7 2.2.1.8 2.2.1.9 2.2.2 2.2.2.1 2.2.2.2 2.2.2.3 2.2.2.4 2.2.2.5 2.2.2.6 2.2.2.7 2.2.2.8 2.2.2.9 2.2.2.10 2.2.2.11 2.2.2.12 2.2.2.13 2.2.2.14 2.2.3 2.2.3.1 2.2.3.2 2.2.3.3 2.2.3.4 2.2.3.5 2.2.3.6 2.2.3.7 2.2.3.8 2.2.3.9 2.2.3.10 2.2.3.11 2.2.3.12 2.2.3.13 2.2.3.14 2.2.3.15 2.2.3.16 2.2.4 2.2.4.1 2.2.5 Title Page Number Read/Write (R/W) ................................................................................................. 2-17 Transfer Burst (TBST) .......................................................................................... 2-17 Transfer Size (TSIZ[1:0]) ..................................................................................... 2-17 Byte Selects (BE/BWE[3:0]) ................................................................................ 2-18 Output Enable (OE) .............................................................................................. 2-18 Transfer Acknowledge (TA) ................................................................................. 2-18 SDRAM Controller Signals ...................................................................................... 2-18 SDRAM Data Bus (SDDATA[31:0]) ................................................................... 2-18 SDRAM Address Bus (SDADDR[12:0]) ............................................................. 2-18 SDRAM Bank Addresses (SDBA[1:0]) ............................................................... 2-19 SDRAM Row Address Strobe (RAS) ................................................................... 2-19 SDRAM Column Address Strobe (CAS) ............................................................. 2-19 SDRAM Chip Selects (SDCS[3:0]) ...................................................................... 2-19 SDRAM Write Data Byte Mask (SDDM[3:0]) .................................................... 2-19 SDRAM Data Strobe (SDDQS[3:0]) .................................................................... 2-19 SDRAM Clock (SDCLK[1:0]) ............................................................................. 2-19 Inverted SDRAM Clock (SDCLK[1:0]) ............................................................... 2-19 SDRAM Write Enable (SDWE) ........................................................................... 2-19 SDRAM Clock Enable (SDCKE) ......................................................................... 2-19 SDR SDRAM Data Strobe (SDRDQS) ................................................................ 2-19 SDRAM Reference Voltage (VREF) ................................................................... 2-20 PCI Controller Signals .............................................................................................. 2-20 PCI Address/Data Bus (PCIAD[31:0]) ................................................................. 2-20 Command/Byte Enables (PCICXBE[3:0]) ........................................................... 2-20 Device Select (PCIDEVSEL) ............................................................................... 2-20 Frame (PCIFRM) .................................................................................................. 2-20 Initialization Device Select (PCIIDSEL) .............................................................. 2-20 Initiator Ready (PCIIRDY) ................................................................................... 2-20 Parity (PCIPAR) ................................................................................................... 2-20 Parity Error (PCIPERR) ....................................................................................... 2-20 Reset (PCIRESET) ............................................................................................... 2-21 System Error (PCISERR) ..................................................................................... 2-21 Stop (PCISTOP) ................................................................................................... 2-21 Target Ready (PCITRDY) .................................................................................... 2-21 External Bus Grant (PCIBG[4:1]) ........................................................................ 2-21 External Bus Grant/Request Output (PCIBG0/PCIREQOUT) ............................ 2-21 External Bus Request (PCIBR[4:0]) ..................................................................... 2-21 External Request/Grant Input (PCIBR0/PCIGNTIN) .......................................... 2-21 Interrupt Control Signals .......................................................................................... 2-21 Interrupt Request (IRQ[7:1]) ................................................................................ 2-21 Clock and Reset Signals ........................................................................................... 2-22 MCF548x Reference Manual, Rev. 3 vi Freescale Semiconductor Contents Paragraph Number 2.2.5.1 2.2.5.2 2.2.5.3 2.2.6 2.2.6.1 2.2.6.2 2.2.6.3 2.2.6.4 2.2.6.5 2.2.6.6 2.2.7 2.2.7.1 2.2.7.2 2.2.7.3 2.2.7.4 2.2.7.5 2.2.7.6 2.2.7.7 2.2.7.8 2.2.7.9 2.2.7.10 2.2.7.11 2.2.7.12 2.2.7.13 2.2.7.14 2.2.8 2.2.8.1 2.2.8.2 2.2.8.3 2.2.8.4 2.2.8.5 2.2.9 2.2.9.1 2.2.9.2 2.2.9.3 2.2.9.4 2.2.9.5 2.2.9.6 2.2.10 2.2.10.1 2.2.10.2 Title Page Number Reset In (RSTI) ..................................................................................................... 2-22 Reset Out (RSTO) ................................................................................................. 2-22 Clock In (CLKIN) ................................................................................................. 2-22 Reset Configuration Pins .......................................................................................... 2-22 AD[12:8]—CLKIN to SDCLK Ratio (CLKCONFIG[4:0]) ................................ 2-22 AD5—FlexBus Size Configuration (FBSIZE) ..................................................... 2-23 AD4—32-bit FlexBus Configuration (FBMODE) ............................................... 2-23 AD3—Byte Enable Configuration (BECONFIG) ................................................ 2-23 AD2—Auto Acknowledge Configuration (AACONFIG) .................................... 2-24 AD[1:0]—Port Size Configuration (PSCONFIG) ................................................ 2-24 Ethernet Module Signals ........................................................................................... 2-24 Management Data (E0MDIO, E1MDIO) ............................................................. 2-24 Management Data Clock (E0MDC, E1MDC) ...................................................... 2-25 Transmit Clock (E0TXCLK, E1TXCLK) ............................................................ 2-25 Transmit Enable (E0TXEN, E1TXEN) ................................................................ 2-25 Transmit Data 0 (E0TXD0, E1TXD0) ................................................................. 2-25 Collision (E0COL, E1COL) ................................................................................. 2-25 Receive Clock (E0RXCLK, E1RXCLK) ............................................................. 2-25 Receive Data Valid (E0RXDV, E1RXDV) .......................................................... 2-25 Receive Data 0 (E0RXD0, E1RXD0) .................................................................. 2-25 Carrier Receive Sense (E0CRS, E1CRS) ............................................................. 2-25 Transmit Data 1–3 (E0TXD[3:1], E1TXD[3:1]) .................................................. 2-25 Transmit Error (E0TXER, E1TXER) ................................................................... 2-26 Receive Data 1–3 (E0RXD[3:1], E1RXD[3:1]) ................................................... 2-26 Receive Error (E0RXER, E1RXER) .................................................................... 2-26 Universal Serial Bus (USB) ...................................................................................... 2-26 USB Differential Data (USBD+, USBD–) ........................................................... 2-26 USBVBUS ............................................................................................................ 2-26 USBRBIAS ........................................................................................................... 2-26 USBCLKIN .......................................................................................................... 2-26 USBCLKOUT ...................................................................................................... 2-26 DMA Serial Peripheral Interface (DSPI) Signals ..................................................... 2-26 DSPI Synchronous Serial Data Output (DSPISOUT) .......................................... 2-26 DSPI Synchronous Serial Data Input (DSPISIN) ................................................. 2-27 DSPI Serial Clock (DSPISCK) ............................................................................. 2-27 DSPI Peripheral Chip Select/Slave Select (DSPICS0/SS) ................................... 2-27 DSPI Chip Selects (DSPICS[2:3]) ........................................................................ 2-27 DSPI Peripheral Chip Select 5/Peripheral Chip Select Strobe (DSPICS5/PCSS) 2-27 FlexCAN Signals ...................................................................................................... 2-27 FlexCAN Transmit (CANTX0, CANTX1) .......................................................... 2-27 FlexCAN Receive (CANRX0, CANRX1) ........................................................... 2-27 MCF548x Reference Manual, Rev. 3 Freescale Semiconductor vii Contents Paragraph Number 2.2.11 2.2.11.1 2.2.11.2 2.2.12 2.2.12.1 2.2.12.2 2.2.12.3 2.2.12.4 2.2.13 2.2.13.1 2.2.13.2 2.2.14 2.2.14.1 2.2.14.2 2.2.15 2.2.15.1 2.2.15.2 2.2.15.3 2.2.15.4 2.2.15.5 2.2.15.6 2.2.15.7 2.2.16 2.2.16.1 2.2.17 2.2.17.1 2.2.17.2 2.2.17.3 2.2.17.4 2.2.17.5 2.2.17.6 2.2.17.7 2.2.17.8 2.2.17.9 2.2.17.10 2.2.17.11 Title Page Number I2C I/O Signals .......................................................................................................... 2-27 Serial Clock (SCL) ............................................................................................... 2-28 Serial Data (SDA) ................................................................................................. 2-28 PSC Module Signals ................................................................................................. 2-28 Transmit Serial Data Output (PSC0TXD, PSC1TXD, PSC2TXD, PSC3TXD) .. 2-28 Receive Serial Data Input (PSC0RXD, PSC1RXD, PSC2RXD, PSC3RXD) ..... 2-28 Clear-to-Send (PSCnCTS/PSCBCLK) ................................................................. 2-28 Request-to-Send (PSCnRTS/PSCFSYNC) ........................................................... 2-28 DMA Controller Module Signals ............................................................................. 2-28 DMA Request (DREQ[1:0]) ................................................................................. 2-28 DMA Acknowledge (DACK[1:0]) ....................................................................... 2-28 Timer Module Signals .............................................................................................. 2-29 Timer Inputs (TIN[3:0]) ....................................................................................... 2-29 Timer Outputs (TOUT[3:0]) ................................................................................. 2-29 Debug Support Signals ............................................................................................. 2-29 Processor Clock Output (PSTCLK) ...................................................................... 2-29 Processor Status Debug Data (PSTDDATA[7:0]) ............................................... 2-29 Development Serial Clock/Test Reset (DSCLK/TRST) ...................................... 2-29 Breakpoint/Test Mode Select (BKPT/TMS) ........................................................ 2-30 Development Serial Input/Test Data Input (DSI/TDI) ......................................... 2-30 Development Serial Output/Test Data Output (DSO/TDO) ................................. 2-30 Test Clock (TCK) ................................................................................................. 2-30 Test Signals ............................................................................................................... 2-30 Test Mode (MTMOD[3:0]) .................................................................................. 2-30 Power and Reference Pins ........................................................................................ 2-31 Positive Pad Supply (EVDD) ............................................................................... 2-31 Positive Core Supply (IVDD) ............................................................................... 2-31 Ground (VSS) ....................................................................................................... 2-31 USB Power (USBVDD) ....................................................................................... 2-31 USB Oscillator Power (USB_OSCVDD) ............................................................. 2-31 USB PHY Power (USB_PHYVDD) .................................................................... 2-31 USB Oscillator Analog Power (USB_OSCAVDD) ............................................. 2-31 USB PLL Analog Power (USB_PLLVDD) ......................................................... 2-31 SDRAM Memory Supply (SDVDD) .................................................................... 2-31 PLL Analog Power (PLLVDD) ............................................................................ 2-31 PLL Analog Ground (PLLVSS) ........................................................................... 2-31 MCF548x Reference Manual, Rev. 3 viii Freescale Semiconductor Contents Paragraph Number Title Page Number Chapter 3 ColdFire Core 3.1 3.2 3.2.1 3.2.1.1 3.2.1.2 3.2.1.3 3.2.2 3.3 3.3.1 3.3.1.1 3.3.1.2 3.3.2 3.3.2.1 3.3.2.2 3.3.3 3.3.4 3.3.5 3.3.5.1 3.3.5.2 3.3.5.3 3.3.5.4 3.3.5.5 3.3.5.6 3.3.6 3.4 3.4.1 3.4.1.1 3.4.1.2 3.4.2 3.4.2.1 3.5 3.6 3.6.1 3.6.2 3.7 3.7.1 3.7.2 3.7.3 Core Overview ................................................................................................................ 3-1 Features ........................................................................................................................... 3-1 Enhanced Pipelines ..................................................................................................... 3-2 Instruction Fetch Pipeline (IFP) .............................................................................. 3-3 Operand Execution Pipeline (OEP) ........................................................................ 3-4 Harvard Memory Architecture ............................................................................... 3-6 Debug Module Enhancements .................................................................................... 3-6 Programming Model ....................................................................................................... 3-7 User Programming Model .......................................................................................... 3-9 Data Registers (D0–D7) ......................................................................................... 3-9 Address Registers (A0–A6) .................................................................................... 3-9 User Stack Pointer (A7) ............................................................................................. 3-9 Program Counter (PC) ............................................................................................ 3-9 Condition Code Register (CCR) ............................................................................. 3-9 EMAC Programming Model .................................................................................... 3-10 FPU Programming Model ......................................................................................... 3-10 Supervisor Programming Model ............................................................................... 3-11 Status Register (SR) .............................................................................................. 3-12 Vector Base Register (VBR) ................................................................................ 3-12 Cache Control Register (CACR) .......................................................................... 3-13 Access Control Registers (ACR0–ACR3) ............................................................ 3-13 RAM Base Address Registers (RAMBAR0 and RAMBAR1) ............................ 3-13 Module Base Address Register (MBAR) ............................................................. 3-13 Programming Model Table ....................................................................................... 3-13 Data Format Summary .................................................................................................. 3-15 Data Organization in Registers ................................................................................. 3-15 Integer Data Format Organization in Registers .................................................... 3-15 Integer Data Format Organization in Memory ..................................................... 3-16 EMAC Data Representation ..................................................................................... 3-17 Floating-Point Data Formats and Types ............................................................... 3-17 Addressing Mode Summary ......................................................................................... 3-18 Instruction Set Summary .............................................................................................. 3-19 Additions to the Instruction Set Architecture ........................................................... 3-19 Instruction Set Summary .......................................................................................... 3-22 Instruction Execution Timing ....................................................................................... 3-27 MOVE Instruction Execution Timing ...................................................................... 3-28 One-Operand Instruction Execution Timing ............................................................ 3-30 Two-Operand Instruction Execution Timing ............................................................ 3-31 MCF548x Reference Manual, Rev. 3 Freescale Semiconductor ix Contents Paragraph Number 3.7.4 3.7.5 3.7.6 3.7.7 3.8 3.8.1 3.8.2 3.9 Title Page Number Miscellaneous Instruction Execution Timing ........................................................... 3-32 Branch Instruction Execution Timing ....................................................................... 3-33 EMAC Instruction Execution Times ........................................................................ 3-34 FPU Instruction Execution Times ............................................................................. 3-35 Exception Processing Overview ................................................................................... 3-36 Exception Stack Frame Definition ............................................................................ 3-38 Processor Exceptions ................................................................................................ 3-39 Precise Faults ................................................................................................................ 3-42 Chapter 4 Enhanced Multiply-Accumulate Unit (EMAC) 4.1 4.1.1 4.1.2 4.2 4.2.1 4.2.1.1 4.2.2 4.3 4.3.1 4.3.2 4.3.3 Introduction ..................................................................................................................... 4-1 MAC Overview ........................................................................................................... 4-2 General Operation ....................................................................................................... 4-2 Memory Map/Register Definition .................................................................................. 4-5 MAC Status Register (MACSR) ................................................................................. 4-5 Fractional Operation Mode ..................................................................................... 4-8 Mask Register (MASK) ............................................................................................ 4-10 EMAC Instruction Set Summary .................................................................................. 4-11 EMAC Instruction Execution Timing ....................................................................... 4-11 Data Representation .................................................................................................. 4-12 EMAC Opcodes ........................................................................................................ 4-13 Chapter 5 Memory Management Unit (MMU) 5.1 5.2 5.2.1 5.2.2 5.2.3 5.2.3.1 5.2.3.2 5.2.3.3 5.2.3.4 5.2.3.5 5.2.3.6 5.2.3.7 5.2.3.8 Features ........................................................................................................................... 5-1 Virtual Memory Management Architecture ................................................................... 5-1 MMU Architecture Features ....................................................................................... 5-1 MMU Architecture Location ...................................................................................... 5-2 MMU Architecture Implementation ........................................................................... 5-3 Precise Faults .......................................................................................................... 5-4 MMU Access .......................................................................................................... 5-4 Virtual Mode ........................................................................................................... 5-4 Virtual Memory References ................................................................................... 5-4 Instruction and Data Cache Addresses ................................................................... 5-4 Supervisor/User Stack Pointers .............................................................................. 5-5 Access Error Stack Frame ...................................................................................... 5-5 Expanded Control Register Space .......................................................................... 5-5 MCF548x Reference Manual, Rev. 3 x Freescale Semiconductor Contents Paragraph Number 5.2.3.9 5.2.3.10 5.2.3.11 5.3 5.4 5.4.1 5.4.2 5.4.3 5.5 5.5.1 5.5.2 5.5.3 5.5.3.1 5.5.3.2 5.5.3.3 5.5.3.4 5.5.3.5 5.5.3.6 5.5.3.7 5.5.4 5.5.5 5.6 5.6.1 5.6.2 5.6.3 5.7 Title Page Number Changes to ACRs and CACR ................................................................................. 5-5 ACR Address Improvements .................................................................................. 5-6 Supervisor Protection .............................................................................................. 5-7 Debugging in a Virtual Environment .............................................................................. 5-7 Virtual Memory Architecture Processor Support ........................................................... 5-7 Precise Faults .............................................................................................................. 5-7 Supervisor/User Stack Pointers ................................................................................. 5-7 Access Error Stack Frame Additions .......................................................................... 5-8 MMU Definition ............................................................................................................. 5-9 Effective Address Attribute Determination ................................................................ 5-9 MMU Functionality .................................................................................................. 5-10 MMU Organization ................................................................................................... 5-10 MMU Base Address Register (MMUBAR) ......................................................... 5-10 MMU Memory Map ............................................................................................. 5-11 MMU Control Register (MMUCR) ..................................................................... 5-11 MMU Operation Register (MMUOR) .................................................................. 5-12 MMU Status Register (MMUSR) ......................................................................... 5-14 MMU Fault, Test, or TLB Address Register (MMUAR) ..................................... 5-15 MMU Read/Write Tag and Data Entry Registers (MMUTR and MMUDR) ...... 5-16 MMU TLB ................................................................................................................ 5-18 MMU Operation ....................................................................................................... 5-19 MMU Implementation .................................................................................................. 5-20 TLB Address Fields .................................................................................................. 5-20 TLB Replacement Algorithm ................................................................................... 5-21 TLB Locked Entries .................................................................................................. 5-22 MMU Instructions ......................................................................................................... 5-23 Chapter 6 Floating-Point Unit (FPU) 6.1 6.1.1 6.1.1.1 6.2 6.2.1 6.2.2 6.2.3 6.2.3.1 6.2.3.2 6.2.3.3 6.2.3.4 Introduction ..................................................................................................................... 6-1 Overview ..................................................................................................................... 6-1 Notational Conventions .......................................................................................... 6-1 Operand Data Formats and Types .................................................................................. 6-3 Signed-Integer Data Formats ...................................................................................... 6-3 Floating-Point Data Formats ....................................................................................... 6-3 Floating-Point Data Types .......................................................................................... 6-4 Normalized Numbers .............................................................................................. 6-4 Zeros ....................................................................................................................... 6-4 Infinities .................................................................................................................. 6-4 Not-A-Number ........................................................................................................ 6-5 MCF548x Reference Manual, Rev. 3 Freescale Semiconductor xi Contents Paragraph Number 6.2.3.5 6.3 6.3.1 6.3.2 6.3.3 6.3.4 6.4 6.4.1 6.4.2 6.5 6.5.1 6.5.2 6.6 6.6.1 6.6.1.1 6.6.1.2 6.6.1.3 6.6.1.4 6.6.1.5 6.6.1.6 6.6.1.7 6.6.1.8 6.6.2 6.7 6.7.1 6.7.2 6.7.3 Title Page Number Denormalized Numbers .......................................................................................... 6-5 Register Definition .......................................................................................................... 6-7 Floating-Point Data Registers (FP0–FP7) .................................................................. 6-7 Floating-Point Control Register (FPCR) .................................................................... 6-7 Floating-Point Status Register (FPSR) ....................................................................... 6-9 Floating-Point Instruction Address Register (FPIAR) .............................................. 6-10 Floating-Point Computational Accuracy ...................................................................... 6-11 Intermediate Result ................................................................................................... 6-11 Rounding the Result .................................................................................................. 6-12 Floating-Point Post-Processing ..................................................................................... 6-14 Underflow, Round, and Overflow ............................................................................ 6-14 Conditional Testing ................................................................................................... 6-15 Floating-Point Exceptions ............................................................................................. 6-17 Floating-Point Arithmetic Exceptions ...................................................................... 6-18 Branch/Set on Unordered (BSUN) ....................................................................... 6-19 Input Not-A-Number (INAN) ............................................................................... 6-20 Input Denormalized Number (IDE) ...................................................................... 6-20 Operand Error (OPERR) ....................................................................................... 6-21 Overflow (OVFL) ................................................................................................. 6-21 Underflow (UNFL) ............................................................................................... 6-22 Divide-by-Zero (DZ) ............................................................................................ 6-22 Inexact Result (INEX) .......................................................................................... 6-23 Floating-Point State Frames ...................................................................................... 6-23 Instructions .................................................................................................................... 6-25 Floating-Point Instruction Overview ........................................................................ 6-25 Floating-Point Instruction Execution Timing ........................................................... 6-27 Key Differences between ColdFire and M68000 FPU Programming Models ......... 6-28 Chapter 7 Local Memory 7.1 7.2 7.3 7.4 7.4.1 7.5 7.5.1 7.6 7.7 7.8 Interactions between Local Memory Modules ............................................................... 7-1 SRAM Overview ............................................................................................................ 7-1 SRAM Operation ............................................................................................................ 7-2 SRAM Register Definition ............................................................................................. 7-2 SRAM Base Address Registers (RAMBAR0/RAMBAR1) ....................................... 7-2 SRAM Initialization ........................................................................................................ 7-4 SRAM Initialization Code .......................................................................................... 7-5 Power Management ........................................................................................................ 7-6 Cache Overview .............................................................................................................. 7-6 Cache Organization ......................................................................................................... 7-7 MCF548x Reference Manual, Rev. 3 xii Freescale Semiconductor Contents Paragraph Number 7.8.1 7.8.2 7.9 7.9.1 7.9.1.1 7.9.1.2 7.9.2 7.9.2.1 7.9.2.2 7.9.2.3 7.9.2.4 7.9.3 7.9.4 7.9.4.1 7.9.4.2 7.9.5 7.10 7.10.1 7.10.2 7.11 7.12 7.12.1 7.12.2 7.13 Title Page Number Cache Line States: Invalid, Valid-Unmodified, and Valid-Modified ......................... 7-8 The Cache at Start-Up ................................................................................................. 7-8 Cache Operation ........................................................................................................... 7-10 Caching Modes ......................................................................................................... 7-12 Cacheable Accesses .............................................................................................. 7-12 Cache-Inhibited Accesses ..................................................................................... 7-13 Cache Protocol .......................................................................................................... 7-14 Read Miss ............................................................................................................. 7-14 Write Miss (Data Cache Only) ............................................................................. 7-14 Read Hit ................................................................................................................ 7-15 Write Hit (Data Cache Only) ................................................................................ 7-15 Cache Coherency (Data Cache Only) ....................................................................... 7-15 Memory Accesses for Cache Maintenance ............................................................... 7-15 Cache Filling ......................................................................................................... 7-15 Cache Pushes ........................................................................................................ 7-16 Cache Locking .......................................................................................................... 7-17 Cache Register Definition ............................................................................................. 7-19 Cache Control Register (CACR) .............................................................................. 7-19 Access Control Registers (ACR0–ACR3) ................................................................ 7-22 Cache Management ....................................................................................................... 7-23 Cache Operation Summary ........................................................................................... 7-26 Instruction Cache State Transitions .......................................................................... 7-26 Data Cache State Transitions .................................................................................... 7-27 Cache Initialization Code .............................................................................................. 7-30 Chapter 8 Debug Support 8.1 8.1.1 8.2 8.2.1 8.3 8.3.1 8.3.2 8.3.3 8.4 8.4.1 8.4.2 8.4.3 8.4.4 Introduction ..................................................................................................................... 8-1 Overview ..................................................................................................................... 8-1 Signal Descriptions ......................................................................................................... 8-2 Processor Status/Debug Data (PSTDDATA[7:0]) ..................................................... 8-3 Real-Time Trace Support ................................................................................................ 8-5 Begin Execution of Taken Branch (PST = 0x5) ......................................................... 8-6 Processor Stopped or Breakpoint State Change (PST = 0xE) .................................... 8-7 Processor Halted (PST = 0xF) .................................................................................... 8-8 Memory Map/Register Definition .................................................................................. 8-9 Revision A Shared Debug Resources ....................................................................... 8-11 Configuration/Status Register (CSR) ........................................................................ 8-11 PC Breakpoint ASID Control Register (PBAC) ....................................................... 8-14 BDM Address Attribute Register (BAAR) ............................................................... 8-15 MCF548x Reference Manual, Rev. 3 Freescale Semiconductor xiii Contents Paragraph Number 8.4.5 8.4.6 8.4.7 8.4.8 8.4.9 8.4.10 8.4.11 8.4.11.1 8.5 8.5.1 8.5.2 8.5.2.1 8.5.2.2 8.5.3 8.5.3.1 8.5.3.2 8.5.3.3 8.6 8.6.1 8.6.1.1 8.6.2 8.7 8.7.1 8.7.2 8.8 8.8.1 8.8.2 8.8.3 8.8.3.1 8.9 Title Page Number Address Attribute Trigger Registers (AATR, AATR1) ............................................ 8-16 Trigger Definition Register (TDR) ........................................................................... 8-17 Program Counter Breakpoint and Mask Registers (PBRn, PBMR) ......................... 8-20 Address Breakpoint Registers (ABLR/ABLR1, ABHR/ABHR1) ........................... 8-21 Data Breakpoint and Mask Registers (DBR/DBR1, DBMR/DBMR1) .................... 8-22 PC Breakpoint ASID Register (PBASID) ................................................................ 8-24 Extended Trigger Definition Register (XTDR) ........................................................ 8-25 Resulting Set of Possible Trigger Combinations .................................................. 8-27 Background Debug Mode (BDM) ................................................................................ 8-28 CPU Halt ................................................................................................................... 8-28 BDM Serial Interface ................................................................................................ 8-30 Receive Packet Format ......................................................................................... 8-30 Transmit Packet Format ........................................................................................ 8-31 BDM Command Set .................................................................................................. 8-31 ColdFire BDM Command Format ........................................................................ 8-33 Command Sequence Diagrams ............................................................................. 8-33 Command Set Descriptions .................................................................................. 8-35 Real-Time Debug Support ............................................................................................ 8-51 Theory of Operation .................................................................................................. 8-51 Emulator Mode ..................................................................................................... 8-53 Concurrent BDM and Processor Operation .............................................................. 8-53 Debug C Definition of PSTDDATA Outputs .............................................................. 8-54 User Instruction Set .................................................................................................. 8-54 Supervisor Instruction Set ......................................................................................... 8-60 ColdFire Debug History ................................................................................................ 8-61 ColdFire Debug Classic: The Original Definition .................................................... 8-61 ColdFire Debug Revision B ...................................................................................... 8-62 ColdFire Debug Revision C ...................................................................................... 8-62 Debug Interrupts and Interrupt Requests (Emulator Mode) ................................. 8-62 Freescale-Recommended BDM Pinout ........................................................................ 8-63 Chapter 9 System Integration Unit (SIU) 9.1 9.2 9.3 9.3.1 9.3.1.1 9.3.1.2 9.3.1.3 Introduction ..................................................................................................................... 9-1 Features ........................................................................................................................... 9-1 Memory Map/Register Definition .................................................................................. 9-1 Module Base Address Register (MBAR) ................................................................... 9-2 System Breakpoint Control Register (SBCR) ........................................................ 9-3 SEC Sequential Access Control Register (SECSACR) ......................................... 9-4 Reset Status Register (RSR) ................................................................................... 9-5 MCF548x Reference Manual, Rev. 3 xiv Freescale Semiconductor Contents Paragraph Number 9.3.1.4 Title Page Number JTAG Device Identification Number (JTAGID) .................................................... 9-5 Chapter 10 Internal Clocks and Bus Architecture 10.1 10.1.1 10.1.2 10.1.3 10.1.4 10.1.5 10.1.6 10.1.6.1 10.1.6.2 10.2 10.2.1 10.2.2 10.3 10.3.1 10.3.2 10.3.2.1 10.3.2.2 10.3.2.3 10.3.3 10.3.3.1 10.3.3.2 10.3.3.3 10.3.3.4 10.3.3.5 10.3.3.6 10.3.3.7 10.3.3.8 10.3.3.9 10.3.3.10 10.3.3.11 Introduction ................................................................................................................... 10-1 Block Diagram .......................................................................................................... 10-1 Clocking Overview ................................................................................................... 10-2 Internal Bus Overview .............................................................................................. 10-2 XL Bus Features ....................................................................................................... 10-3 Internal Bus Transaction Summaries ........................................................................ 10-3 XL Bus Interface Operations .................................................................................... 10-3 Basic Transfer Protocol ........................................................................................ 10-3 Address Pipelines .................................................................................................. 10-4 PLL ............................................................................................................................... 10-5 PLL Memory Map/Register Descriptions ................................................................. 10-5 System PLL Control Register (SPCR) ..................................................................... 10-5 XL Bus Arbiter ............................................................................................................. 10-6 Features ..................................................................................................................... 10-6 Arbiter Functional Description ................................................................................. 10-6 Prioritization ......................................................................................................... 10-6 Bus Grant Mechanism .......................................................................................... 10-7 Watchdog Functions ............................................................................................. 10-8 XLB Arbiter Register Descriptions .......................................................................... 10-8 Arbiter Configuration Register (XARB_CFG) .................................................... 10-9 Arbiter Version Register (XARB_VER) ............................................................ 10-10 Arbiter Status Register (XARB_SR) .................................................................. 10-11 Arbiter Interrupt Mask Register (XARB_IMR) ................................................. 10-11 Arbiter Address Capture Register (XARB_ADRCAP) ...................................... 10-13 Arbiter Bus Signal Capture Register (XARB_SIGCAP) ................................... 10-13 Arbiter Address Tenure Time Out Register (XARB_ADRTO) ......................... 10-14 Arbiter Data Tenure Time Out Register (XARB_DATTO) ............................... 10-15 Arbiter Bus Activity Time Out Register (XARB_BUSTO) ............................... 10-16 Arbiter Master Priority Enable Register (XARB_PRIEN) ................................. 10-16 Arbiter Master Priority Register (XARB_PRI) .................................................. 10-17 Chapter 11 General Purpose Timers (GPT) 11.1 Introduction ................................................................................................................... 11-1 MCF548x Reference Manual, Rev. 3 Freescale Semiconductor xv Contents Paragraph Number 11.1.1 11.1.2 11.2 11.3 11.3.1 11.3.2 11.3.3 11.3.4 11.4 11.4.1 11.4.2 Title Page Number Overview ................................................................................................................... 11-1 Modes of Operation .................................................................................................. 11-1 External Signals ............................................................................................................ 11-2 Memory Map/Register Definition ................................................................................ 11-2 GPT Enable and Mode Select Register (GMSn) ...................................................... 11-3 GPT Counter Input Register (GCIRn) ...................................................................... 11-5 GPT PWM Configuration Register (GPWMn) ........................................................ 11-6 GPT Status Register (GSRn) .................................................................................... 11-7 Functional Description .................................................................................................. 11-8 Timer Configuration Method .................................................................................... 11-8 Programming Notes .................................................................................................. 11-8 Chapter 12 Slice Timers (SLT) 12.1 12.1.1 12.2 12.2.1 12.2.2 12.2.3 12.2.4 Introduction ................................................................................................................... 12-1 Overview ................................................................................................................... 12-1 Memory Map/Register Definition ................................................................................ 12-1 SLT Terminal Count Register (STCNTn) ................................................................ 12-2 SLT Control Register (SCRn) ................................................................................... 12-2 SLT Timer Count Register (SCNTn) ........................................................................ 12-3 SLT Status Register (SSRn) ..................................................................................... 12-4 Chapter 13 Interrupt Controller 13.1 13.1.1 13.1.1.1 13.2 13.2.1 13.2.1.1 13.2.1.2 13.2.1.3 13.2.1.4 13.2.1.5 13.2.1.6 13.2.1.7 Introduction ................................................................................................................... 13-1 68K/ColdFire Interrupt Architecture Overview ....................................................... 13-1 Interrupt Controller Theory of Operation ............................................................. 13-2 Memory Map/Register Descriptions ............................................................................. 13-4 Register Descriptions ................................................................................................ 13-5 Interrupt Pending Registers (IPRH, IPRL) ........................................................... 13-5 Interrupt Mask Register (IMRH, IMRL) .............................................................. 13-7 Interrupt Force Registers (INTFRCH, INTFRCL) ............................................... 13-8 Interrupt Request Level Register (IRLR) ........................................................... 13-10 Interrupt Acknowledge Level and Priority Register (IACKLPR) ...................... 13-10 Interrupt Control Registers 1–63 (ICRn) ............................................................ 13-11 Software and Level n IACK Registers (SWIACKR, L1IACK–L7IACK) ......... 13-13 MCF548x Reference Manual, Rev. 3 xvi Freescale Semiconductor Contents Paragraph Number Title Page Number Chapter 14 Edge Port Module (EPORT) 14.1 14.2 14.3 14.3.1 14.3.2 14.3.2.1 14.3.2.2 14.3.2.3 14.3.2.4 14.3.2.5 14.3.2.6 Introduction ................................................................................................................... 14-1 Interrupt/General-Purpose I/O Pin Descriptions ........................................................... 14-1 Memory Map/Register Definition ................................................................................ 14-2 Memory Map ............................................................................................................ 14-2 Register Descriptions ................................................................................................ 14-2 EPORT Pin Assignment Register (EPPAR) ......................................................... 14-3 EPORT Data Direction Register (EPDDR) .......................................................... 14-3 Edge Port Interrupt Enable Register (EPIER) ...................................................... 14-4 Edge Port Data Register (EPDR) .......................................................................... 14-4 Edge Port Pin Data Register (EPPDR) ................................................................. 14-5 Edge Port Flag Register (EPFR) ........................................................................... 14-5 Chapter 15 GPIO 15.1 15.1.1 15.1.2 15.2 15.3 15.3.1 15.3.2 15.3.2.1 15.3.2.2 15.3.2.3 15.3.2.4 15.3.2.5 15.3.2.6 15.3.2.7 15.3.2.8 15.3.2.9 15.3.2.10 15.3.2.11 15.3.2.12 15.3.2.13 15.3.2.14 15.3.2.15 15.3.2.16 Introduction ................................................................................................................... 15-1 Overview ................................................................................................................... 15-2 Features ..................................................................................................................... 15-3 External Pin Description ............................................................................................... 15-3 Memory Map/Register Definition ................................................................................ 15-7 Register Overview .................................................................................................... 15-7 Register Descriptions ................................................................................................ 15-8 Port x Output Data Registers (PODR_x) .............................................................. 15-8 Port x Data Direction Registers (PDDR_x) ........................................................ 15-11 Port x Pin Data/Set Data Registers (PPDSDR_x) ............................................. 15-14 Port x Clear Output Data Registers (PCLRR_x) ................................................ 15-18 Port x Pin Assignment Registers (PAR_x) ......................................................... 15-21 FlexBus Chip Select Pin Assignment Register (PAR_FBCS) ........................... 15-22 DMA Pin Assignment Register (PAR_DMA) ................................................... 15-23 FEC/I2C/IRQ Pin Assignment Register (PAR_FECI2CIRQ) ........................... 15-23 PCI Grant Pin Assignment Register (PAR_PCIBG) .......................................... 15-25 PCI Request Pin Assignment Register (PAR_PCIBR) ...................................... 15-26 PSC3 Pin Assignment Register (PAR_PSC3) .................................................... 15-27 PSC2 Pin Assignment Register (PAR_PSC2) .................................................... 15-28 PSC1 Pin Assignment Register (PAR_PSC1) .................................................... 15-28 PSC0 Pin Assignment Register (PAR_PSC0) .................................................... 15-29 DSPI Pin Assignment Register (PAR_DSPI) ..................................................... 15-30 General Purpose Timer Pin Assignment Register (PAR_TIMER) .................... 15-31 MCF548x Reference Manual, Rev. 3 Freescale Semiconductor xvii Contents Paragraph Number 15.4 15.4.1 Title Page Number Functional Description ................................................................................................ 15-32 Overview ................................................................................................................. 15-32 Chapter 16 32-Kbyte System SRAM 16.1 16.1.1 16.1.2 16.1.3 16.2 16.2.1 16.2.2 16.2.3 16.2.4 16.2.5 16.3 Introduction ................................................................................................................... 16-1 Block Diagram .......................................................................................................... 16-1 Features ..................................................................................................................... 16-2 Overview ................................................................................................................... 16-2 Memory Map/Register Definition ................................................................................ 16-2 System SRAM Configuration Register (SSCR) ....................................................... 16-3 Transfer Count Configuration Register (TCCR) ..................................................... 16-4 Transfer Count Configuration Register—DMA Read Channel (TCCRDR) ............ 16-5 Transfer Count Configuration Register—DMA Write Channel (TCCRDW) .......... 16-6 Transfer Count Configuration Register—SEC (TCCRSEC) .................................... 16-7 Functional Description .................................................................................................. 16-8 Chapter 17 FlexBus 17.1 17.1.1 17.1.2 17.1.3 17.2 17.3 17.4 17.4.1 17.4.2 17.4.3 17.4.4 17.4.5 17.4.6 17.4.7 17.4.8 17.4.9 17.5 17.5.1 17.5.1.1 Introduction ................................................................................................................... 17-1 Overview ................................................................................................................... 17-1 Features ..................................................................................................................... 17-1 Modes of Operation .................................................................................................. 17-1 Byte Lanes .................................................................................................................... 17-2 Address Latch ............................................................................................................... 17-2 External Signals ............................................................................................................ 17-3 Chip-Select (FBCS[5:0]) .......................................................................................... 17-4 Address/Data Bus (AD[31:0]) .................................................................................. 17-4 Address Latch Enable (ALE) .................................................................................... 17-4 Read/Write (R/W) ..................................................................................................... 17-4 Transfer Burst (TBST) .............................................................................................. 17-4 Transfer Size (TSIZ[1:0]) ......................................................................................... 17-4 Byte Selects (BE/BWE[3:0]) .................................................................................... 17-5 Output Enable (OE) .................................................................................................. 17-5 Transfer Acknowledge (TA) ..................................................................................... 17-5 Chip-Select Operation ................................................................................................... 17-6 General Chip-Select Operation ................................................................................. 17-6 8-, 16-, and 32-Bit Port Sizing .............................................................................. 17-6 MCF548x Reference Manual, Rev. 3 xviii Freescale Semiconductor Contents Paragraph Number 17.5.1.2 17.5.2 17.5.2.1 17.5.2.2 17.5.2.3 17.6 17.6.1 17.6.2 17.6.3 17.6.4 17.6.4.1 17.6.5 17.6.5.1 17.6.5.2 17.6.5.3 17.6.5.4 17.6.6 17.6.7 17.6.8 Title Page Number Global Chip-Select Operation ............................................................................... 17-6 Chip-Select Registers ................................................................................................ 17-7 Chip-Select Address Registers (CSAR0–CSAR5) ............................................... 17-8 Chip-Select Mask Registers (CSMR0–CSMR5) .................................................. 17-9 Chip-Select Control Registers (CSCR0–CSCR5) .............................................. 17-10 Functional Description ................................................................................................ 17-12 Data Transfer Operation ......................................................................................... 17-12 Data Byte Alignment and Physical Connections .................................................... 17-12 Address/Data Bus Multiplexing .............................................................................. 17-13 Bus Cycle Execution ............................................................................................... 17-13 Data Transfer Cycle States ................................................................................. 17-14 FlexBus Timing Examples ...................................................................................... 17-15 Basic Read Bus Cycle ......................................................................................... 17-15 Basic Write Bus Cycle ........................................................................................ 17-16 Bus Cycle Multiplexing ...................................................................................... 17-17 Timing Variations ............................................................................................... 17-21 Burst Cycles ............................................................................................................ 17-26 Misaligned Operands .............................................................................................. 17-31 Bus Errors ............................................................................................................... 17-32 Chapter 18 SDRAM Controller (SDRAMC) 18.1 18.2 18.2.1 18.2.2 18.2.3 18.3 18.3.1 18.3.2 18.3.3 18.3.4 18.3.5 18.3.6 18.3.7 18.3.8 18.3.9 18.3.10 18.3.11 18.3.12 Introduction ................................................................................................................... 18-1 Overview ....................................................................................................................... 18-1 Features ..................................................................................................................... 18-1 Terminology .............................................................................................................. 18-1 Block Diagram .......................................................................................................... 18-2 External Signal Description .......................................................................................... 18-2 SDRAM Data Bus (SDDATA[31:0]) ....................................................................... 18-2 SDRAM Address Bus (SDADDR[12:0]) ................................................................. 18-2 SDRAM Bank Addresses (SDBA[1:0]) ................................................................... 18-2 SDRAM Row Address Strobe (RAS) ....................................................................... 18-3 SDRAM Column Address Strobe (CAS) ................................................................. 18-3 SDRAM Chip Selects (SDCS[3:0]) .......................................................................... 18-3 SDRAM Write Data Byte Mask (SDDM[3:0]) ........................................................ 18-3 SDRAM Data Strobe (SDDQS[3:0]) ........................................................................ 18-3 SDRAM Clock (SDCLK[1:0]) ................................................................................. 18-3 Inverted SDRAM Clock (SDCLK[1:0]) ................................................................... 18-3 SDRAM Write Enable (SDWE) ............................................................................... 18-3 SDRAM Clock Enable (SDCKE) ............................................................................. 18-4 MCF548x Reference Manual, Rev. 3 Freescale Semiconductor xix Contents Paragraph Number 18.3.13 18.3.14 18.3.15 18.4 18.4.1 18.4.2 18.4.3 18.4.4 18.4.5 18.4.5.1 18.5 18.5.1 18.5.1.1 18.5.1.2 18.5.1.3 18.5.1.4 18.5.1.5 18.5.1.6 18.5.1.7 18.5.2 18.5.2.1 18.5.2.2 18.6 18.6.1 18.6.2 18.7 18.7.1 18.7.2 18.7.3 18.7.4 18.7.5 18.7.6 18.8 18.8.1 18.8.2 18.8.3 18.8.4 18.8.5 18.8.6 18.8.7 18.8.8 Title Page Number SDR SDRAM Data Strobe (SDRDQS) .................................................................... 18-4 SDRAM Memory Supply (SDVDD) ........................................................................ 18-4 SDRAM Reference Voltage (VREF) ....................................................................... 18-4 Interface Recommendations ......................................................................................... 18-4 Supported Memory Configurations .......................................................................... 18-4 SDRAM SDR Connections ...................................................................................... 18-6 SDRAM DDR Component Connections .................................................................. 18-6 SDRAM DDR DIMM Connections ......................................................................... 18-7 DDR SDRAM Layout Considerations ..................................................................... 18-8 Termination Example ........................................................................................... 18-9 SDRAM Overview ....................................................................................................... 18-9 SDRAM Commands ................................................................................................. 18-9 Row and Bank Active Command (ACTV) ......................................................... 18-10 Read Command (READ) .................................................................................... 18-10 Write Command (WRITE) ................................................................................. 18-10 Precharge All Banks Command (PALL) ............................................................ 18-11 Load Mode/Extended Mode Register Command (LMR, LEMR) ...................... 18-11 Auto Refresh Command (REF) .......................................................................... 18-13 Self-Refresh (SREF) and Power-Down (PDWN) Commands ........................... 18-13 Power-Up Initialization ........................................................................................... 18-13 SDR Initialization ............................................................................................... 18-14 DDR Initialization .............................................................................................. 18-14 Functional Overview ................................................................................................... 18-15 Page Management ................................................................................................... 18-15 Transfer Size ........................................................................................................... 18-15 Memory Map/Register Definition .............................................................................. 18-16 SDRAM Drive Strength Register (SDRAMDS) .................................................... 18-17 SDRAM Chip Select Configuration Registers (CSnCFG) ..................................... 18-18 SDRAM Mode/Extended Mode Register (SDMR) ................................................ 18-19 SDRAM Control Register (SDCR) ......................................................................... 18-20 SDRAM Configuration Register 1 (SDCFG1) ....................................................... 18-21 SDRAM Configuration Register 2 (SDCFG2) ....................................................... 18-23 SDRAM Example ....................................................................................................... 18-24 SDRAM Signal Drive Strength Settings ................................................................ 18-25 SDRAM Chip Select Settings ................................................................................. 18-25 SDRAM Configuration 1 Register Settings ............................................................ 18-26 SDRAM Configuration 2 Register Settings ............................................................ 18-27 SDRAM Control Register Settings and PALL command ...................................... 18-27 Set the Extended Mode Register ............................................................................. 18-29 Set the Mode Register and Reset DLL ................................................................... 18-29 Issue a PALL command .......................................................................................... 18-30 MCF548x Reference Manual, Rev. 3 xx Freescale Semiconductor Contents Paragraph Number 18.8.9 18.8.10 18.8.11 18.8.12 Title Page Number Perform Two Refresh Cycles .................................................................................. 18-31 Clear the Reset DLL Bit in the Mode Register ...................................................... 18-32 Enable Automatic Refresh and Lock Mode Register ............................................ 18-33 Initialization Code ................................................................................................... 18-34 Chapter 19 PCI Bus Controller 19.1 19.1.1 19.1.2 19.1.3 19.2 19.2.1 19.2.2 19.2.3 19.2.4 19.2.5 19.2.6 19.2.7 19.2.8 19.2.9 19.2.10 19.2.11 19.2.12 19.2.13 19.3 19.3.1 19.3.1.1 19.3.1.2 19.3.1.3 19.3.1.4 19.3.1.5 19.3.1.6 19.3.1.7 19.3.1.8 19.3.1.9 19.3.1.10 19.3.1.11 19.3.2 19.3.2.1 Introduction ................................................................................................................... 19-1 Block Diagram .......................................................................................................... 19-1 Overview ................................................................................................................... 19-1 Features ..................................................................................................................... 19-1 External Signal Description .......................................................................................... 19-2 Address/Data Bus (PCIAD[31:0]) ............................................................................ 19-2 Command/Byte Enables (PCICXBE[3:0]) ............................................................... 19-2 Device Select (PCIDEVSEL) ................................................................................... 19-3 Frame (PCIFRAME) ................................................................................................. 19-3 Initialization Device Select (PCIIDSEL) .................................................................. 19-3 Initiator Ready (PCIIRDY) ....................................................................................... 19-3 Parity (PCIPAR) ....................................................................................................... 19-3 PCI Clock (CLKIN) .................................................................................................. 19-3 Parity Error (PCIPERR) ............................................................................................ 19-3 Reset (PCIRESET) .................................................................................................. 19-3 System Error (PCISERR) ........................................................................................ 19-3 Stop (PCISTOP) ...................................................................................................... 19-3 Target Ready (PCITRDY) ....................................................................................... 19-4 Memory Map/Register Definition ................................................................................ 19-4 PCI Type 0 Configuration Registers ......................................................................... 19-6 Device ID/Vendor ID Register (PCIIDR)—PCI Dword Addr 0 .......................... 19-7 PCI Status/Command Register (PCISCR)—PCI Dword Addr 1 ......................... 19-7 Revision ID/Class Code Register (PCICCRIR)—PCI Dword 3 .......................... 19-9 Configuration 1 Register (PCICR1)—PCI Dword 3 .......................................... 19-10 Base Address Register 0 (PCIBAR0)—PCI Dword 4 ........................................ 19-11 Base Address Register 1 (PCIBAR1)—PCI Dword 5 ........................................ 19-12 CardBus CIS Pointer Register PCICCPR—PCI Dword A ................................ 19-12 Subsystem ID/Subsystem Vendor ID Registers PCISID—PCI Dword B .......... 19-12 Expansion ROM Base Address PCIERBAR—PCI Dword C ............................ 19-13 Capabilities Pointer (Cap_Ptr) PCICPR—PCI Dword D ................................... 19-13 Configuration 2 Register (PCICR2)—PCI Dword F .......................................... 19-13 General Control/Status Registers ............................................................................ 19-13 Global Status/Control Register (PCIGSCR) ....................................................... 19-14 MCF548x Reference Manual, Rev. 3 Freescale Semiconductor xxi Contents Paragraph Number 19.3.2.2 19.3.2.3 19.3.2.4 19.3.2.5 19.3.2.6 19.3.2.7 19.3.2.8 19.3.2.9 19.3.2.10 19.3.2.11 19.3.3 19.3.3.1 19.3.3.2 19.4 19.4.1 19.4.1.1 19.4.1.2 19.4.1.3 19.4.1.4 19.4.1.5 19.4.2 19.4.2.1 19.4.3 19.4.4 19.4.4.1 19.4.4.2 19.4.4.3 19.4.4.4 19.4.4.5 19.4.5 19.4.5.1 19.4.5.2 19.4.5.3 19.4.5.4 19.4.5.5 19.4.6 19.4.6.1 19.4.6.2 19.4.6.3 19.4.6.4 19.4.6.5 Title Page Number Target Base Address Translation Register 0 (PCITBATR0) ............................. 19-15 Target Base Address Translation Register 1 (PCITBATR1) ............................. 19-16 Target Control Register (PCITCR) ..................................................................... 19-16 Initiator Window 0 Base/Translation Address Register (PCIIW0BTAR) ......... 19-17 Initiator Window 1 Base/Translation Address Register (PCIIW1BTAR) ......... 19-18 Initiator Window 2 Base/Translation Address Register (PCIIW2BTAR) ......... 19-19 Initiator Window Configuration Register (PCIIWCR) ....................................... 19-19 Initiator Control Register (PCIICR) ................................................................... 19-20 Initiator Status Register (PCIISR) ...................................................................... 19-21 Configuration Address Register (PCICAR) ....................................................... 19-22 Communication Subsystem Interface Registers ..................................................... 19-23 Comm Bus FIFO Transmit Interface .................................................................. 19-23 Comm Bus FIFO Receive Interface ................................................................... 19-35 Functional Description ................................................................................................ 19-48 PCI Bus Protocol .................................................................................................... 19-48 PCI Bus Background .......................................................................................... 19-48 Basic Transfer Control ........................................................................................ 19-49 PCI Transactions ................................................................................................. 19-49 PCI Bus Commands ............................................................................................ 19-51 Addressing .......................................................................................................... 19-52 Initiator Arbitration ................................................................................................. 19-55 Priority Scheme .................................................................................................. 19-56 Configuration Interface ........................................................................................... 19-56 XL Bus Initiator Interface ....................................................................................... 19-56 Endian Translation .............................................................................................. 19-58 Configuration Mechanism .................................................................................. 19-60 Interrupt Acknowledge Transactions .................................................................. 19-62 Special Cycle Transactions ................................................................................. 19-62 Transaction Termination ..................................................................................... 19-63 XL Bus Target Interface ........................................................................................ 19-63 Reads from Local Memory ................................................................................. 19-64 Local Memory Writes ......................................................................................... 19-64 Data Translation .................................................................................................. 19-64 Target Abort ........................................................................................................ 19-66 Latrule Disable .................................................................................................... 19-66 Communication Subsystem Initiator Interface ....................................................... 19-66 Access Width ...................................................................................................... 19-67 Addressing .......................................................................................................... 19-67 Data Translation .................................................................................................. 19-68 Initialization ........................................................................................................ 19-68 Restart and Reset ................................................................................................ 19-68 MCF548x Reference Manual, Rev. 3 xxii Freescale Semiconductor Contents Paragraph Number 19.4.6.6 19.4.6.7 19.4.6.8 19.4.6.9 19.4.7 19.4.8 19.4.8.1 19.4.8.2 19.5 19.5.1 19.5.2 19.5.2.1 19.6 Title Page Number PCI Commands ................................................................................................... 19-69 FIFO Considerations ........................................................................................... 19-69 Alarms ................................................................................................................. 19-69 Bus Errors ........................................................................................................... 19-70 PCI Clock Scheme .................................................................................................. 19-70 Interrupts ................................................................................................................. 19-70 PCI Bus Interrupts .............................................................................................. 19-70 Internal Interrupt ................................................................................................. 19-70 Application Information ............................................................................................. 19-70 XL Bus-Initiated Transaction Mapping .................................................................. 19-70 Address Maps ......................................................................................................... 19-71 Address Translation ............................................................................................ 19-72 XL Bus Arbitration Priority ........................................................................................ 19-75 Chapter 20 PCI Bus Arbiter Module 20.1 20.1.1 20.1.2 20.1.3 20.2 20.2.1 20.2.2 20.2.3 20.2.4 20.2.5 20.2.6 20.2.7 20.3 20.3.1 20.3.2 20.4 20.4.1 20.4.2 20.4.2.1 20.4.2.2 20.4.2.3 20.4.2.4 20.4.3 20.5 Introduction ................................................................................................................... 20-1 Block Diagram .......................................................................................................... 20-1 Overview ................................................................................................................... 20-1 Features ..................................................................................................................... 20-2 External Signal Description .......................................................................................... 20-2 Frame (PCIFRM) ...................................................................................................... 20-2 Initiator Ready (PCIIRDY) ....................................................................................... 20-2 PCI Clock (CLKIN) .................................................................................................. 20-2 External Bus Grant (PCIBG[4:1]) ............................................................................ 20-2 External Bus Grant/Request Output (PCIBG0/PCIREQOUT) ................................ 20-3 External Bus Request (PCIBR[4:1]) ......................................................................... 20-3 External Request/Grant Input (PCIBR0/PCIGNTIN) .............................................. 20-3 Register Definition ........................................................................................................ 20-3 PCI Arbiter Control Register (PACR) ...................................................................... 20-3 PCI Arbiter Status Register (PASR) ......................................................................... 20-5 Functional Description .................................................................................................. 20-5 External PCI Requests .............................................................................................. 20-5 Arbitration ................................................................................................................. 20-6 Hidden Bus Arbitration ......................................................................................... 20-6 Arbitration Scheme ............................................................................................... 20-6 Arbitration Latency ............................................................................................... 20-7 Arbitration Examples ............................................................................................ 20-7 Master Time-Out ....................................................................................................... 20-9 Reset ............................................................................................................................ 20-10 MCF548x Reference Manual, Rev. 3 Freescale Semiconductor xxiii Contents Paragraph Number 20.6 Title Page Number Interrupts ..................................................................................................................... 20-10 Chapter 21 FlexCAN 21.1 21.1.1 21.1.2 21.1.3 21.1.4 21.1.4.1 21.1.4.2 21.1.4.3 21.1.4.4 21.1.4.5 21.2 21.2.1 21.2.2 21.3 21.3.1 21.3.2 21.3.2.1 21.3.2.2 21.3.2.3 21.3.2.4 21.3.2.5 21.3.2.6 21.3.2.7 21.3.2.8 21.4 21.4.1 21.4.2 21.4.3 21.4.4 21.4.5 21.4.5.1 21.4.6 21.4.6.1 21.4.6.2 21.4.6.3 21.4.6.4 Introduction ................................................................................................................... 21-1 Block Diagram .......................................................................................................... 21-1 The CAN System ...................................................................................................... 21-2 Features ..................................................................................................................... 21-3 Modes of Operation .................................................................................................. 21-3 Normal Mode ........................................................................................................ 21-3 Freeze Mode ......................................................................................................... 21-3 Module Disabled Mode ........................................................................................ 21-4 Loop-Back Mode .................................................................................................. 21-4 Listen-Only Mode ................................................................................................. 21-4 External Signals ............................................................................................................ 21-5 CANTX[1:0] ............................................................................................................. 21-5 CANRX[1:0] ............................................................................................................. 21-5 Memory Map/Register Definition ................................................................................ 21-5 FlexCAN Memory Map ............................................................................................ 21-5 Register Descriptions ................................................................................................ 21-6 FlexCAN Module Configuration Register (CANMCR) ....................................... 21-6 FlexCAN Control Register (CANCTRL) ............................................................. 21-8 FlexCAN Timer Register (TIMER) .................................................................... 21-10 Rx Mask Registers .............................................................................................. 21-11 FlexCAN Error Counter Register (ERRCNT) .................................................... 21-14 FlexCAN Error and Status Register (ERRSTAT) .............................................. 21-15 Interrupt Mask Register (IMASK) ...................................................................... 21-17 Interrupt Flag Register (IFLAG) ........................................................................ 21-18 Functional Overview ................................................................................................... 21-19 Message Buffer Structure ....................................................................................... 21-19 Message Buffer Memory Map ................................................................................ 21-22 Transmit Process ..................................................................................................... 21-23 Arbitration Process ................................................................................................. 21-24 Receive Process ...................................................................................................... 21-24 Self-Received Frames ......................................................................................... 21-25 Message Buffer Handling ....................................................................................... 21-25 Serial Message Buffers (SMBs) ......................................................................... 21-26 Transmit Message Buffer Deactivation .............................................................. 21-26 Receive Message Buffer Deactivation ................................................................ 21-26 Locking and Releasing Message Buffers ........................................................... 21-27 MCF548x Reference Manual, Rev. 3 xxiv Freescale Semiconductor Contents Paragraph Number 21.4.7 21.4.7.1 21.4.7.2 21.4.8 21.4.9 21.4.9.1 21.4.10 21.5 21.5.1 Title Page Number CAN Protocol Related Frames ............................................................................... 21-27 Remote Frames ................................................................................................... 21-27 Overload Frames ................................................................................................. 21-28 Time Stamp ............................................................................................................. 21-28 Bit Timing ............................................................................................................... 21-28 Configuring the FlexCAN Bit Timing ................................................................ 21-29 FlexCAN Error Counters ....................................................................................... 21-30 FlexCAN Initialization Sequence ............................................................................... 21-31 Interrupts ................................................................................................................. 21-31 Chapter 22 Integrated Security Engine (SEC) 22.1 22.2 22.3 22.4 22.4.1 22.4.2 22.4.2.1 22.4.2.2 22.4.3 22.4.4 22.4.4.1 22.4.4.2 22.4.4.3 22.4.4.4 22.4.4.5 22.5 22.6 22.6.1 22.6.2 22.6.3 22.6.4 22.6.4.1 22.6.4.2 22.6.4.3 22.6.4.4 22.6.4.5 22.6.4.6 22.6.4.7 Features ......................................................................................................................... 22-1 ColdFire Security Architecture ..................................................................................... 22-1 Block Diagram .............................................................................................................. 22-2 Overview ....................................................................................................................... 22-2 Bus Interface ............................................................................................................. 22-2 SEC Controller Unit .................................................................................................. 22-3 Static EU Access ................................................................................................... 22-3 Dynamic EU Access ............................................................................................. 22-3 Crypto-Channels ....................................................................................................... 22-3 Execution Units (EUs) .............................................................................................. 22-4 Data Encryption Standard Execution Unit (DEU) ................................................ 22-4 Arc Four Execution Unit (AFEU) ........................................................................ 22-5 Advanced Encryption Standard Execution Unit (AESU) ..................................... 22-6 Message Digest Execution Unit (MDEU) ............................................................ 22-6 Random Number Generator (RNG) ...................................................................... 22-8 Memory Map/Register Definition ................................................................................ 22-8 Controller .................................................................................................................... 22-10 EU Access ............................................................................................................... 22-11 Multiple EU Assignment ........................................................................................ 22-11 Multiple Channels ................................................................................................... 22-11 Controller Registers ................................................................................................ 22-11 EU Assignment Control Registers (EUACRH and EUACRL) .......................... 22-11 EU Assignment Status Registers (EUASRH and EUASRL) ............................. 22-13 SEC Interrupt Mask Registers (SIMRH and SIMRL) ........................................ 22-14 SEC Interrupt Status Registers (SISRH and SISRL) .......................................... 22-14 SEC Interrupt Control Registers (SICRH and SICRL) ...................................... 22-14 SEC ID Register (SIDR) ..................................................................................... 22-16 SEC Master Control Register (SMCR) ............................................................... 22-17 MCF548x Reference Manual, Rev. 3 Freescale Semiconductor xxv Contents Paragraph Number 22.6.4.8 22.7 22.7.1 22.7.1.1 22.7.1.2 22.7.1.3 22.7.1.4 22.7.1.5 22.8 22.8.1 22.8.2 22.8.3 22.8.4 22.8.5 22.9 22.9.1 22.9.2 22.9.3 22.9.4 22.9.5 22.10 22.10.1 22.10.2 22.10.3 22.10.4 22.10.5 22.11 22.11.1 22.11.2 22.11.3 22.11.4 22.11.5 22.12 22.12.1 22.12.2 22.12.3 22.12.4 22.12.5 22.13 22.13.1 22.13.1.1 Title Page Number Master Error Address Register (MEAR) ............................................................ 22-18 Channels ...................................................................................................................... 22-18 Crypto-Channel Registers ....................................................................................... 22-19 Crypto-Channel Configuration Registers (CCCRn) ........................................... 22-19 Crypto-Channel Pointer Status Registers (CCPSRHn and CCPSRLn) .............. 22-21 Crypto-Channel Current Descriptor Pointer Register (CDPRn) ........................ 22-27 Fetch Register (FRn) ........................................................................................... 22-27 Data Packet Descriptor Buffer (CDBUFn) ......................................................... 22-28 ARC Four Execution Unit (AFEU) ............................................................................ 22-28 AFEU Register Map ............................................................................................... 22-28 AFEU Reset Control Register (AFRCR) ................................................................ 22-28 AFEU Status Register (AFSR) ............................................................................... 22-29 AFEU Interrupt Status Register (AFISR) ............................................................... 22-31 AFEU Interrupt Mask Register (AFIMR) .............................................................. 22-32 Data Encryption Standard Execution Units (DEU) .................................................... 22-34 DEU Register Map .................................................................................................. 22-34 DEU Reset Control Register (DRCR) .................................................................... 22-34 DEU Status Register (DSR) .................................................................................... 22-35 DEU Interrupt Status Register (DISR) ................................................................... 22-37 DEU Interrupt Mask Register (DIMR) ................................................................... 22-39 Message Digest Execution Unit (MDEU) .................................................................. 22-40 MDEU Register Map .............................................................................................. 22-40 MDEU Reset Control Register (MDRCR) ............................................................. 22-41 MDEU Status Register (MDSR) ............................................................................. 22-41 MDEU Interrupt Status Register (MDISR) ............................................................ 22-43 MDEU Interrupt Mask Register (MDIMR) ............................................................ 22-44 RNG Execution Unit (RNG) ...................................................................................... 22-46 RNG Register Map ................................................................................................. 22-46 RNG Reset Control Register (RNGRCR) .............................................................. 22-46 RNG Status Register (RNGSR) .............................................................................. 22-47 RNG Interrupt Status Register (RNGISR) .............................................................. 22-48 RNG Interrupt Mask Register (RNGIMR) ............................................................. 22-49 Advanced Encryption Standard Execution Units (AESU) ....................................... 22-50 AESU Register Map ............................................................................................... 22-50 AESU Reset Control Register (AESRCR) ............................................................. 22-50 AESU Status Register (AESSR) ............................................................................. 22-51 AESU Interrupt Status Register (AESISR) ............................................................ 22-53 AESU Interrupt Mask Register (AESIMR) ............................................................ 22-54 Descriptors .................................................................................................................. 22-56 Descriptor Structure ................................................................................................ 22-56 Descriptor Header ............................................................................................... 22-57 MCF548x Reference Manual, Rev. 3 xxvi Freescale Semiconductor Contents Paragraph Number 22.13.1.2 22.13.1.3 22.13.1.4 22.13.2 22.13.3 22.13.4 22.13.4.1 22.13.4.2 22.14 22.14.1 22.14.1.1 22.14.1.2 22.14.2 22.14.2.1 22.14.2.2 22.14.3 22.14.3.1 22.14.3.2 22.14.3.3 22.14.4 22.14.5 22.14.5.1 22.14.5.2 22.14.5.3 22.14.6 22.14.6.1 22.14.6.2 22.14.6.3 22.14.6.4 Title Page Number Descriptor Length and Pointer Fields ................................................................. 22-60 Null Fields .......................................................................................................... 22-61 Next Descriptor Pointer ...................................................................................... 22-61 Descriptor Chaining ................................................................................................ 22-61 Descriptor Type Formats ....................................................................................... 22-62 Descriptor Classes ................................................................................................... 22-64 Dynamic Descriptors .......................................................................................... 22-64 Static Descriptors ................................................................................................ 22-65 EU Specific Data Packet Descriptors ........................................................................ 22-67 AFEU Mode Options and Data Packet Descriptors ................................................ 22-67 Dynamically Assigned AFEU ............................................................................ 22-68 Statically Assigned AFEU .................................................................................. 22-69 DEU Mode Options and Data Packet Descriptors .................................................. 22-72 Dynamically Assigned DEU ............................................................................... 22-73 Statically Assigned DEU .................................................................................... 22-74 MDEU Mode Options and Data Packet Descriptors .............................................. 22-77 Recommended Settings for MDEU Mode Register ........................................... 22-78 Dynamically Assigned MDEU ........................................................................... 22-78 Statically Assigned MDEU ................................................................................ 22-79 RNG Data Packet Descriptors ................................................................................ 22-82 AESU Mode Options and Data Packet Descriptors ................................................ 22-83 Dynamically Assigned AESU ............................................................................ 22-84 Statically Assigned AESU .................................................................................. 22-85 AESU-CCM Mode Descriptor ........................................................................... 22-88 Multi-Function Data Packet Descriptors ................................................................ 22-90 Snooping ............................................................................................................. 22-91 Dynamic Multi-Function Descriptor Formats .................................................... 22-91 Static Multi-Function Descriptor Formats .......................................................... 22-95 SSLv3.1/TLS 1.0 Processing Descriptors ........................................................ 22-102 Chapter 23 IEEE 1149.1 Test Access Port (JTAG) 23.1 23.1.1 23.1.2 23.1.3 23.2 23.2.1 23.2.1.1 23.2.1.2 Introduction ................................................................................................................... 23-1 Block Diagram .......................................................................................................... 23-1 Features ..................................................................................................................... 23-2 Modes of Operation .................................................................................................. 23-2 External Signal Description .......................................................................................... 23-2 Detailed Signal Description ...................................................................................... 23-2 Test Mode 0 (MTMOD0) ..................................................................................... 23-2 Test Clock Input (TCK) ........................................................................................ 23-3 MCF548x Reference Manual, Rev. 3 Freescale Semiconductor xxvii Contents Paragraph Number 23.2.1.3 23.2.1.4 23.2.1.5 23.2.1.6 23.3 23.3.1 23.3.2 23.3.2.1 23.3.2.2 23.3.2.3 23.3.2.4 23.3.2.5 23.3.2.6 23.4 23.4.1 23.4.2 23.4.3 23.4.3.1 23.4.3.2 23.4.3.3 23.4.3.4 23.4.3.5 23.4.3.6 23.4.3.7 23.5 23.5.1 23.5.2 Title Page Number Test Mode Select/Breakpoint (TMS/BKPT) ........................................................ 23-3 Test Data Input/Development Serial Input (TDI/DSI) ......................................... 23-3 Test Reset/Development Serial Clock (TRST/DSCLK) ...................................... 23-4 Test Data Output/Development Serial Output (TDO/DSO) ................................. 23-4 Memory Map/Register Definition ................................................................................ 23-4 Memory Map ............................................................................................................ 23-4 Register Descriptions ................................................................................................ 23-4 Instruction Shift Register (IR) .............................................................................. 23-4 IDCODE Register ................................................................................................. 23-4 Bypass Register .................................................................................................... 23-5 JTAG_CFM_CLKDIV Register ........................................................................... 23-5 TEST_CTRL Register .......................................................................................... 23-5 Boundary Scan Register ....................................................................................... 23-6 Functional Description .................................................................................................. 23-6 JTAG Module ........................................................................................................... 23-6 TAP Controller ......................................................................................................... 23-6 JTAG Instructions ..................................................................................................... 23-7 External Test Instruction (EXTEST) .................................................................... 23-8 IDCODE Instruction ............................................................................................. 23-8 SAMPLE/PRELOAD Instruction ......................................................................... 23-8 ENABLE_TEST_CTRL Instruction .................................................................... 23-9 HIGHZ Instruction ................................................................................................ 23-9 CLAMP Instruction .............................................................................................. 23-9 BYPASS Instruction ............................................................................................. 23-9 Initialization/Application Information .......................................................................... 23-9 Restrictions ............................................................................................................... 23-9 Nonscan Chain Operation ......................................................................................... 23-9 Chapter 24 Multichannel DMA 24.1 24.1.1 24.1.2 24.1.2.1 24.1.2.2 24.1.2.3 24.1.2.4 24.1.2.5 24.1.3 24.2 Introduction ................................................................................................................... 24-1 Block Diagram .......................................................................................................... 24-1 Overview ................................................................................................................... 24-2 Master DMA Engine (MDE) ................................................................................ 24-2 Address and Data Sequencer (ADS) ..................................................................... 24-2 Priority-Task Decoder (PTD) ............................................................................... 24-2 Logic Unit with Redundancy Check (LURC) ...................................................... 24-2 Debug Unit ............................................................................................................ 24-2 Features ..................................................................................................................... 24-2 External Signals ............................................................................................................ 24-3 MCF548x Reference Manual, Rev. 3 xxviii Freescale Semiconductor Contents Paragraph Number 24.2.1 24.2.2 24.3 24.3.1 24.3.1.1 24.3.1.2 24.3.1.3 24.3.1.4 24.3.1.5 24.3.2 24.3.3 24.3.3.1 24.3.3.2 24.3.3.3 24.3.3.4 24.3.3.5 24.3.3.6 24.3.3.7 24.3.3.8 24.3.3.9 24.3.3.10 24.3.3.11 24.3.3.12 24.3.3.13 24.3.3.14 24.3.3.15 24.3.3.16 24.3.4 24.3.4.1 24.3.4.2 24.3.4.3 24.3.4.4 24.4 24.4.1 24.4.2 24.4.3 24.4.4 24.4.5 24.4.6 24.4.7 24.4.8 Title Page Number DREQ[1:0] ............................................................................................................... 24-3 DACK[1:0] .............................................................................................................. 24-3 Memory Map/Register Definitions ............................................................................... 24-3 DMA Task Memory .................................................................................................. 24-3 Task Table ............................................................................................................ 24-3 Task Descriptor Table ........................................................................................... 24-3 Variable Table ...................................................................................................... 24-4 Function Descriptor Table .................................................................................... 24-4 Context Save Space .............................................................................................. 24-4 Memory Structure ..................................................................................................... 24-4 DMA Registers ......................................................................................................... 24-5 DMA Register Map .............................................................................................. 24-5 Task Base Address Register (TaskBAR) .............................................................. 24-6 Current Pointer (CP) ............................................................................................. 24-7 End Pointer (EP) ................................................................................................... 24-8 Variable Pointer (VP) ........................................................................................... 24-8 PTD Control (PTD) .............................................................................................. 24-9 DMA Interrupt Pending (DIPR) ......................................................................... 24-10 DMA Interrupt Mask Register (DIMR) .............................................................. 24-10 Task Control Registers (TCRn) .......................................................................... 24-11 Priority Registers (PRIORn) ............................................................................... 24-12 Initiator Mux Control Register (IMCR) ............................................................. 24-13 Task Size Registers (TSKSZ[0:1]) ..................................................................... 24-14 Debug Comparator Registers (DBGCOMPn) .................................................... 24-16 Debug Control (DBGCTL) ................................................................................. 24-16 Debug Status (DBGSTAT) ................................................................................. 24-18 PTD Debug Registers ......................................................................................... 24-19 External Request Module Registers ........................................................................ 24-20 External Request Module Register Map ............................................................. 24-20 External Request Base Address Register (EREQBAR) ..................................... 24-20 External Request Address Mask Register (EREQMASK) ................................. 24-21 External Request Control Register (EREQCTRL) ............................................. 24-21 Functional Description ................................................................................................ 24-22 Tasks ....................................................................................................................... 24-22 Descriptors .............................................................................................................. 24-23 Task Initialization ................................................................................................... 24-23 Initiators .................................................................................................................. 24-23 Prioritization ........................................................................................................... 24-24 Context Switch ........................................................................................................ 24-24 Data Movement ....................................................................................................... 24-24 Data Manipulation .................................................................................................. 24-24 MCF548x Reference Manual, Rev. 3 Freescale Semiconductor xxix Contents Paragraph Number 24.4.8.1 24.4.9 24.4.9.1 24.4.9.2 24.4.9.3 24.4.10 24.4.11 24.4.12 24.5 24.5.1 24.5.2 24.5.2.1 24.6 24.6.1 24.6.2 24.6.3 Title Page Number LURC Features ................................................................................................... 24-25 Line Buffers ............................................................................................................ 24-26 Combine Write Enable ....................................................................................... 24-26 Read Line Enable ................................................................................................ 24-26 Speculative Prefetch ........................................................................................... 24-26 Termination of Loop ............................................................................................... 24-27 Interrupts ................................................................................................................. 24-27 Debug Unit .............................................................................................................. 24-27 Programming Model ................................................................................................... 24-27 Register Initialization .............................................................................................. 24-27 Task Memory .......................................................................................................... 24-28 Task Table .......................................................................................................... 24-28 Timing Diagrams ........................................................................................................ 24-30 Level-Triggered Requests ....................................................................................... 24-30 Edge-Triggered Requests ........................................................................................ 24-30 Pipelined Requests .................................................................................................. 24-31 Chapter 25 Comm Timer Module (CTM) 25.1 25.1.1 25.1.2 25.1.3 25.2 25.2.1 25.2.2 25.2.2.1 25.2.2.2 25.3 25.3.1 25.3.2 25.3.2.1 25.3.3 25.3.3.1 Introduction ................................................................................................................... 25-1 Block Diagrams ........................................................................................................ 25-1 Overview ................................................................................................................... 25-2 Comm Timer External Clock[7:0] ............................................................................ 25-3 Memory Map/Register Definition ................................................................................ 25-3 Timer Module Register Map ..................................................................................... 25-3 Register Descriptions ................................................................................................ 25-4 Comm Timer Configuration Register (CTCRn)—Fixed Timer Channel ............. 25-4 Comm Timer Configuration Register (CTCRn)—Variable Timer Channel ........ 25-5 Functional Description .................................................................................................. 25-7 Variable Timer in Baud Clock Generator Mode ...................................................... 25-7 Fixed Timer in Initiator Mode .................................................................................. 25-7 Fixed Timer in Initiator Mode Example ............................................................... 25-7 Variable Timer in Initiator Mode .............................................................................. 25-8 Variable Timer in Initiator Mode Example .......................................................... 25-8 Chapter 26 Programmable Serial Controller (PSC) 26.1 Introduction ................................................................................................................... 26-1 MCF548x Reference Manual, Rev. 3 xxx Freescale Semiconductor Contents Paragraph Number 26.1.1 26.1.2 26.1.3 26.1.4 26.2 26.2.1 26.2.2 26.2.3 26.2.4 26.2.5 26.3 26.3.1 26.3.2 26.3.3 26.3.3.1 26.3.3.2 26.3.3.3 26.3.3.4 26.3.3.5 26.3.3.6 26.3.3.7 26.3.3.8 26.3.3.9 26.3.3.10 26.3.3.11 26.3.3.12 26.3.3.13 26.3.3.14 26.3.3.15 26.3.3.16 26.3.3.17 26.3.3.18 26.3.3.19 26.3.3.20 26.3.3.21 26.3.3.22 26.3.3.23 26.3.3.24 26.3.3.25 26.3.3.26 26.3.3.27 Title Page Number Block Diagram .......................................................................................................... 26-1 Overview ................................................................................................................... 26-1 Features ..................................................................................................................... 26-1 Modes of Operation .................................................................................................. 26-1 Signal Description ......................................................................................................... 26-2 PSCnCTS/PSCBCLK ............................................................................................... 26-2 PScnrts/pscfsync ....................................................................................................... 26-2 PSCnrxd .................................................................................................................... 26-2 pscntxd ...................................................................................................................... 26-3 Signal Properties in Each Mode ................................................................................ 26-3 Memory Map/Register Definition ................................................................................ 26-3 Overview ................................................................................................................... 26-3 Module Memory Map ............................................................................................... 26-3 Register Descriptions ................................................................................................ 26-5 Mode Register 1(PSCMR1n) ................................................................................ 26-5 Mode Register 2 (PSCMR2n) ............................................................................... 26-6 Status Register (PSCSRn) ..................................................................................... 26-8 Clock Select Register (PSCCSRn) ..................................................................... 26-10 Command Register (PSCCRn) ........................................................................... 26-11 Receiver Buffer (PSCRBn) and Transmitter Buffer (PSCTBn) ......................... 26-14 Input Port Change Register (PSCIPCRn) ........................................................... 26-17 Auxiliary Control Register (PSCACRn) ............................................................ 26-18 Interrupt Status Register (PSCISRn) .................................................................. 26-18 Interrupt Mask Register (PSCIMRn) .................................................................. 26-19 Counter Timer Registers (PSCCTURn, PSCCTLRn) ........................................ 26-21 Input Port (PSCIPn) ............................................................................................ 26-21 Output Port Bit Set (PSCOPSETn) ..................................................................... 26-22 Output Port Bit Reset (PSCOPRESETn) ............................................................ 26-22 PSC/IrDA Control Register (PSCSICRn) .......................................................... 26-23 Infrared Control Register 1 (PSCIRCR1n) ......................................................... 26-24 Infrared Control Register 2 (PSCIRCR2n) ......................................................... 26-24 Infrared SIR Divide Register (PSCIRSDRn) ..................................................... 26-25 Infrared MIR Divide Register (PSCIRMDRn) ................................................... 26-25 Infrared FIR Divide Register (PSCIRFDRn) ..................................................... 26-26 Rx and Tx FIFO Counter Register (PSCRFCNTn, PSCTFCNTn) .................... 26-27 Rx and Tx FIFO Data Register (PSCRFDRn, PSCTFDRn) .............................. 26-27 Rx and Tx FIFO Status Register (PSCRFSRn, PSCTFSRn) ............................. 26-28 Rx and Tx FIFO Control Register (PSCRFCRn, PSCTFCRn) .......................... 26-30 Rx and Tx FIFO Alarm Register (PSCRFARn, PSCTFARn) ............................ 26-32 Rx and Tx FIFO Read Pointer (PSCRFRPn, PSCTFRPn) ................................. 26-32 Rx and Tx FIFO Write Pointer (PSCRFWPn, PSCTFWPn) .............................. 26-33 MCF548x Reference Manual, Rev. 3 Freescale Semiconductor xxxi Contents Paragraph Number 26.3.3.28 26.3.3.29 26.4 26.4.1 26.4.2 26.4.3 26.4.4 26.4.5 26.4.5.1 26.4.5.2 26.4.5.3 26.4.6 26.4.7 26.4.7.1 26.4.7.2 26.4.8 26.4.8.1 26.4.9 26.4.9.1 26.4.9.2 26.4.10 26.4.10.1 26.4.10.2 26.4.10.3 26.5 26.5.1 26.5.2 26.5.2.1 26.5.2.2 26.5.2.3 26.5.2.4 26.6 26.6.1 26.6.1.1 26.7 26.7.1 26.7.2 26.7.2.1 26.7.2.2 26.7.2.3 26.7.2.4 Title Page Number Rx and Tx FIFO Last Read Frame Pointer (PSCRLRFPn, PSCTLRFPn) ......... 26-33 Rx and Tx FIFO Last Write Frame Pointer (PSCRLWFPn, PSCTLWFPn) ...... 26-34 Functional Description ................................................................................................ 26-35 UART Mode ........................................................................................................... 26-35 Multidrop Mode ...................................................................................................... 26-36 Modem8 Mode ........................................................................................................ 26-37 Modem16 Mode ...................................................................................................... 26-38 AC97 Mode ............................................................................................................. 26-39 Transmitter .......................................................................................................... 26-40 Receiver .............................................................................................................. 26-40 Low Power Mode ............................................................................................... 26-40 SIR Mode ................................................................................................................ 26-41 MIR Mode ............................................................................................................... 26-41 Data Format ........................................................................................................ 26-41 Serial Interaction Pulse (SIP) .............................................................................. 26-42 FIR Mode ................................................................................................................ 26-42 Data Format ........................................................................................................ 26-42 PSC FIFO System ................................................................................................... 26-43 RX FIFO ............................................................................................................. 26-44 TX FIFO ............................................................................................................. 26-45 Looping Modes ....................................................................................................... 26-46 Automatic Echo Mode ........................................................................................ 26-46 Local Loopback Mode ........................................................................................ 26-46 Remote Loopback Mode ..................................................................................... 26-47 Resets .......................................................................................................................... 26-47 General .................................................................................................................... 26-47 Description of Reset Operation ............................................................................... 26-47 Reset ................................................................................................................... 26-47 CRSRX ............................................................................................................... 26-47 CRSTX ............................................................................................................... 26-47 CRSES ................................................................................................................ 26-47 Interrupts ..................................................................................................................... 26-48 Description of Interrupt Operation ......................................................................... 26-48 Processor Interrupt .............................................................................................. 26-48 Software Environment ................................................................................................ 26-48 General .................................................................................................................... 26-48 Configuration .......................................................................................................... 26-49 UART Mode ....................................................................................................... 26-49 Modem8 Mode .................................................................................................... 26-50 Modem16 Mode .................................................................................................. 26-51 AC97 Mode ........................................................................................................ 26-51 MCF548x Reference Manual, Rev. 3 xxxii Freescale Semiconductor Contents Paragraph Number 26.7.2.5 26.7.2.6 26.7.2.7 26.7.3 26.7.3.1 26.7.3.2 Title Page Number SIR Mode ............................................................................................................ 26-52 MIR Mode .......................................................................................................... 26-53 FIR Mode ............................................................................................................ 26-54 Programming .......................................................................................................... 26-55 MIR Mode .......................................................................................................... 26-55 FIR Mode ............................................................................................................ 26-56 Chapter 27 DMA Serial Peripheral Interface (DSPI) 27.1 27.2 27.3 27.4 27.4.1 27.4.2 27.5 27.5.1 27.5.2 27.5.2.1 27.5.2.2 27.5.2.3 27.5.2.4 27.5.2.5 27.5.2.6 27.6 27.6.1 27.6.2 27.6.3 27.6.4 27.6.5 27.6.6 27.6.7 27.6.8 27.6.9 27.7 27.7.1 27.7.2 27.7.2.1 27.7.2.2 27.7.2.3 Overview ....................................................................................................................... 27-1 Features ......................................................................................................................... 27-1 Block Diagram .............................................................................................................. 27-2 Modes of Operation ...................................................................................................... 27-2 Master Mode ............................................................................................................. 27-2 Slave Mode ............................................................................................................... 27-2 Signal Description ......................................................................................................... 27-3 Overview ................................................................................................................... 27-3 Detailed Signal Descriptions .................................................................................... 27-3 DSPI Peripheral Chip Select/Slave Select (DSPICS0/SS) ................................... 27-3 DSPI Peripheral Chip Selects 2–3 (DSPICS[2:3]) ............................................... 27-3 DSPI Peripheral Chip Select 5/Peripheral Chip Select Strobe (DSPICS5/PCSS) 27-3 DSPI Serial Input (DSPISIN) ............................................................................... 27-4 DSPI Serial Output (DSPISOUT) ........................................................................ 27-4 DSPI Serial Clock (DSPISCK) ............................................................................. 27-4 Memory Map and Registers .......................................................................................... 27-4 DSPI Module Configuration Register (DMCR) ....................................................... 27-5 DSPI Transfer Count Register (DTCR) .................................................................... 27-7 DSPI Clock and Transfer Attributes Registers 0–7 (DCTARn) ............................... 27-7 DSPI Status Register (DSR) ................................................................................... 27-11 DSPI DMA/Interrupt Request Select Register (DIRSR) ........................................ 27-13 DSPI Tx FIFO Register (DTFR) ............................................................................ 27-15 DSPI Rx FIFO Register (DRFR) ............................................................................ 27-16 DSPI Tx FIFO Debug Registers 0–3 (DTFDRn) ................................................... 27-17 DSPI Rx FIFO Debug Registers 0–3 (DRFDRn) ................................................... 27-17 Functional Description ................................................................................................ 27-18 Start and Stop of DSPI Transfers ............................................................................ 27-19 Serial Peripheral Interface (SPI) ............................................................................ 27-20 Master Mode ....................................................................................................... 27-20 Slave Mode ......................................................................................................... 27-20 FIFO Disable Operation ..................................................................................... 27-21 MCF548x Reference Manual, Rev. 3 Freescale Semiconductor xxxiii Contents Paragraph Number 27.7.2.4 27.7.2.5 27.7.3 27.7.3.1 27.7.3.2 27.7.3.3 27.7.3.4 27.7.3.5 27.7.4 27.7.4.1 27.7.4.2 27.7.4.3 27.7.4.4 27.7.4.5 27.7.5 27.7.6 27.7.6.1 27.7.6.2 27.7.6.3 27.7.6.4 27.7.6.5 27.7.6.6 27.8 27.8.1 27.8.2 27.8.3 27.8.4 27.8.4.1 27.8.4.2 Title Page Number Tx FIFO Buffering Mechanism .......................................................................... 27-21 Rx FIFO Buffering Mechanism .......................................................................... 27-22 DSPI Baud Rate and Clock Delay Generation ....................................................... 27-22 Baud Rate Generator ........................................................................................... 27-23 CS to SCK Delay (tCSC) .................................................................................... 27-23 After DSPISCK Delay (tASC) ........................................................................... 27-23 Delay after Transfer (tDT) ................................................................................... 27-23 Peripheral Chip Select Strobe Enable (PCSS) .................................................... 27-24 Transfer Formats ..................................................................................................... 27-25 Classic SPI Transfer Format (CPHA = 0) .......................................................... 27-25 Classic SPI Transfer Format (CPHA = 1) .......................................................... 27-26 Modified SPI Transfer Format (MTFE = 1, CPHA = 0) .................................... 27-27 Modified SPI Transfer Format (MTFE = 1, CPHA = 1) .................................... 27-28 Continuous Selection Format ............................................................................. 27-29 Continuous Serial Communications Clock ............................................................. 27-30 Interrupts/DMA Requests ....................................................................................... 27-31 End of Queue Interrupt Request ......................................................................... 27-32 Transmit FIFO Fill Interrupt or DMA Request .................................................. 27-32 Transfer Complete Interrupt Request ................................................................. 27-32 Transmit FIFO Underflow Interrupt Request ..................................................... 27-32 Receive FIFO Drain Interrupt or DMA Request ................................................ 27-32 Receive FIFO Overflow Interrupt Request ......................................................... 27-32 Initialization and Application Information ................................................................. 27-33 How to Change Queues .......................................................................................... 27-33 Baud Rate Settings .................................................................................................. 27-33 Delay Settings ......................................................................................................... 27-34 Calculation of FIFO Pointer Addresses .................................................................. 27-35 Address Calculation for the First-in Entry and Last-in Entry in the Tx FIFO ... 27-36 Address Calculation for the First-in Entry and Last-in Entry in the Rx FIFO ... 27-36 Chapter 28 Interface I2C 28.1 28.1.1 28.1.2 28.1.3 28.2 28.3 28.3.1 28.3.2 Introduction ................................................................................................................... 28-1 Block Diagram .......................................................................................................... 28-1 I2C Overview ............................................................................................................ 28-2 Features ..................................................................................................................... 28-2 External Signals ............................................................................................................ 28-2 Memory Map/Register Definition ................................................................................ 28-3 I2C Register Map ...................................................................................................... 28-3 Register Descriptions ................................................................................................ 28-3 MCF548x Reference Manual, Rev. 3 xxxiv Freescale Semiconductor Contents Paragraph Number 28.3.2.1 28.3.2.2 28.3.2.3 28.3.2.4 28.3.2.5 28.3.2.6 28.4 28.4.1 28.4.2 28.4.3 28.4.4 28.4.5 28.4.6 28.4.7 28.4.8 28.5 28.5.1 28.5.2 28.5.3 28.5.4 28.5.5 28.5.6 28.5.7 Title Page Number I2C Address Register (I2ADR) ............................................................................. 28-3 I2C Frequency Divider Register (I2FDR) ............................................................ 28-4 I2C Control Register (I2CR) ................................................................................. 28-5 I2C Status Register (I2SR) .................................................................................... 28-5 I2C Data I/O Register (I2DR) ............................................................................... 28-7 I2C Interrupt Control Register (I2ICR) ................................................................ 28-7 Functional Description .................................................................................................. 28-8 START Signal ........................................................................................................... 28-9 Slave Address Transmission ..................................................................................... 28-9 STOP Signal ............................................................................................................. 28-9 Data Transfer ............................................................................................................ 28-9 Acknowledge .......................................................................................................... 28-10 Repeated Start ......................................................................................................... 28-11 Clock Synchronization and Arbitration .................................................................. 28-11 Handshaking and Clock Stretching ......................................................................... 28-12 Initialization Sequence ................................................................................................ 28-12 Transfer Initiation and Interrupt ............................................................................. 28-13 Post-Transfer Software Response ........................................................................... 28-14 Generation of STOP ................................................................................................ 28-15 Generation of Repeated START ............................................................................. 28-16 Slave Mode ............................................................................................................. 28-16 Arbitration Lost ....................................................................................................... 28-18 Flow Control ........................................................................................................... 28-18 Chapter 29 USB 2.0 Device Controller 29.1 29.1.1 29.1.2 29.1.3 29.1.3.1 29.1.3.2 29.1.3.3 29.1.3.4 29.1.3.5 29.2 29.2.1 29.2.2 29.2.2.1 29.2.2.2 Introduction ................................................................................................................... 29-1 Overview ................................................................................................................... 29-1 Features ..................................................................................................................... 29-1 Block Diagram .......................................................................................................... 29-2 Controller and Synchronization ............................................................................ 29-2 Descriptor RAM ................................................................................................... 29-2 FIFO Controller .................................................................................................... 29-3 FIFO RAM Manager ............................................................................................ 29-3 Integrated USB 2.0 Transceiver ........................................................................... 29-3 Memory Map/Register Definition ................................................................................ 29-4 USB Memory Map .................................................................................................... 29-4 USB Request, Control, and Status Registers ............................................................ 29-9 USB Status Register (USBSR) ............................................................................. 29-9 USB Control Register (USBCR) ........................................................................ 29-10 MCF548x Reference Manual, Rev. 3 Freescale Semiconductor xxxv Contents Paragraph Number 29.2.2.3 29.2.2.4 29.2.2.5 29.2.2.6 29.2.2.7 29.2.2.8 29.2.2.9 29.2.2.10 29.2.2.11 29.2.2.12 29.2.2.13 29.2.2.14 29.2.2.15 29.2.2.16 29.2.3 29.2.3.1 29.2.3.2 29.2.3.3 29.2.3.4 29.2.3.5 29.2.3.6 29.2.3.7 29.2.3.8 29.2.4 29.2.4.1 29.2.4.2 29.2.4.3 29.2.4.4 29.2.4.5 29.2.4.6 29.2.4.7 29.2.4.8 29.2.4.9 29.2.4.10 29.2.5 29.2.5.1 29.2.5.2 29.2.5.3 29.2.5.4 29.2.5.5 Title Page Number USB Descriptor RAM Control Register (DRAMCR) ........................................ 29-12 USB Descriptor RAM Data Register (DRAMDR) ............................................ 29-13 USB Interrupt Status Register (USBISR) ........................................................... 29-14 USB Interrupt Mask Register (USBIMR) .......................................................... 29-15 USB Application Interrupt Status Register (USBAISR) .................................... 29-16 USB Application Interrupt Mask Register (USBAIMR) .................................... 29-17 Endpoint Info Register (EPINFO) ...................................................................... 29-18 USB Configuration Value Register (CFGR) ...................................................... 29-19 USB Configuration Attribute Register (CFGAR) .............................................. 29-19 USB Device Speed Register (SPEEDR) ............................................................. 29-20 USB Frame Number Register (FRMNUMR) ..................................................... 29-21 USB Endpoint Transaction Number Register (EPTNR) .................................... 29-21 USB Application Interface Update Register (IFUR) .......................................... 29-22 USB Configuration Interface Register (IFRn) .................................................... 29-22 USB Counter Registers ........................................................................................... 29-23 USB Packet Passed Count Register (PPCNT) .................................................... 29-23 USB Dropped Packet Counter Register (DPCNT) ............................................. 29-24 USB CRC Error Counter Register (CRCECNT) ................................................ 29-24 USB Bitstuffing Error Counter Register (BSECNT) .......................................... 29-24 USB PID Error Counter Register (PIDECNT) ................................................... 29-25 USB Framing Error Counter Register (FRMECNT) .......................................... 29-25 USB Transmitted Packet Counter Register (TXPCNT) ..................................... 29-26 USB Counter Overflow Register (CNTOVR) .................................................... 29-26 Endpoint Context Registers .................................................................................... 29-27 Endpoint n Attribute Control Register (EP0ACR, EPnOUTACR, EPnINACR) 29-27 Endpoint n Max Packet Size Register (EP0MPSR, EPnOUTMPSR, EPnINMPSR) ......................................................................................................................... 29-28 Endpoint n Interface Number Register (EP0IFR, EPnOUTIFR, EPnINIFR) .... 29-29 Endpoint n Status Register (EP0SR, EPnOUTSR, EPnINSR) ........................... 29-30 bmRequest Type Register (BMRTR) ................................................................. 29-31 bRequest Type Register (BRTR) ........................................................................ 29-32 wValue Register (WVALUER) .......................................................................... 29-32 wIndex Register (WINDEXR) ........................................................................... 29-33 wLength Register (WLENGTHR) ...................................................................... 29-33 Endpoint n Sync Frame Register (EPnOUTSFR, EPnINSFR) .......................... 29-33 USB Endpoint FIFO Registers ............................................................................... 29-34 USB Endpoint n Status and Control Register (EPnSTAT) ................................ 29-34 USB Endpoint n Interrupt Status Register (EPnISR) ......................................... 29-35 USB Endpoint n Interrupt Mask Register (EPnIMR) ......................................... 29-37 USB Endpoint n FIFO RAM Configuration Register (EPnFRCFGR) .............. 29-38 USB Endpoint n FIFO Data Register (EPnFDR) ............................................... 29-39 MCF548x Reference Manual, Rev. 3 xxxvi Freescale Semiconductor Contents Paragraph Number 29.2.5.6 29.2.5.7 29.2.5.8 29.2.5.9 29.2.5.10 29.2.5.11 29.2.5.12 29.3 29.3.1 29.4 29.4.1 29.4.1.1 29.4.1.2 29.4.1.3 29.4.1.4 29.4.1.5 29.4.2 29.4.2.1 29.4.2.2 29.4.3 29.4.3.1 29.4.3.2 29.4.3.3 29.4.3.4 29.4.3.5 29.4.3.6 29.4.3.7 29.4.3.8 Title Page Number USB Endpoint n FIFO Status Register (EPnFSR) ............................................. 29-40 USB Endpoint n FIFO Control Register (EPnFCR) ........................................... 29-42 USB Endpoint n FIFO Alarm Register (EPnFAR) ............................................ 29-44 USB Endpoint n FIFO Read Pointer (EPnFRP) ................................................. 29-45 USB Endpoint n FIFO Write Pointer (EPnFWP) ............................................... 29-45 USB Endpoint n Last Read Frame Pointer (EPnLRFP) ..................................... 29-46 USB Endpoint n Last Write Frame Pointer (EPnLWFP) ................................... 29-47 Functional Description ................................................................................................ 29-47 Interrupts ................................................................................................................. 29-47 Software Interface ....................................................................................................... 29-47 Device Initialization ................................................................................................ 29-47 USB Descriptor Download ................................................................................. 29-48 USB Interrupt Register ....................................................................................... 29-49 Endpoint Registers .............................................................................................. 29-49 FIFO Sizes ......................................................................................................... 29-50 Enable the Device ............................................................................................... 29-50 Exception Handling ................................................................................................ 29-50 Unable to Fill or Empty FIFO Due to Temporary Problem ............................... 29-50 Catastrophic Error ............................................................................................... 29-50 Data Transfer Operations ........................................................................................ 29-50 USB Packets ....................................................................................................... 29-51 Sending Packets .................................................................................................. 29-51 Receiving Packets ............................................................................................... 29-51 USB Transfers .................................................................................................... 29-52 Control Transfers ................................................................................................ 29-53 Bulk Traffic ........................................................................................................ 29-54 Interrupt Traffic .................................................................................................. 29-54 Isochronous Operations ...................................................................................... 29-55 Chapter 30 Fast Ethernet Controller (FEC) 30.1 30.1.1 30.1.2 30.1.3 30.1.4 30.1.5 30.1.5.1 30.1.5.2 30.1.5.3 Introduction ................................................................................................................... 30-1 MCF548x Family Products ....................................................................................... 30-1 Block Diagram .......................................................................................................... 30-1 Overview ................................................................................................................... 30-2 Features ..................................................................................................................... 30-3 Modes of Operation .................................................................................................. 30-3 Full and Half Duplex Operation ........................................................................... 30-3 Interface Options .................................................................................................. 30-3 Address Recognition Options ............................................................................... 30-4 MCF548x Reference Manual, Rev. 3 Freescale Semiconductor xxxvii Contents Paragraph Number 30.1.5.4 30.2 30.2.1 30.2.2 30.2.3 30.2.4 30.2.5 30.2.6 30.2.7 30.2.8 30.2.9 30.2.10 30.2.11 30.2.12 30.3 30.3.1 30.3.2 30.3.3 30.3.3.1 30.3.3.2 30.3.3.3 30.3.3.4 30.3.3.5 30.3.3.6 30.3.3.7 30.3.3.8 30.3.3.9 30.3.3.10 30.3.3.11 30.3.3.12 30.3.3.13 30.3.3.14 30.3.3.15 30.3.3.16 30.3.3.17 30.3.3.18 30.3.3.19 30.3.3.20 30.3.3.21 30.3.3.22 30.3.3.23 Title Page Number Internal Loopback ................................................................................................. 30-4 External Signals ............................................................................................................ 30-4 Transmit Clock (EnTXCLK) .................................................................................... 30-4 Receive Clock (EnRXCLK) ..................................................................................... 30-4 Transmit Enable (EnTXEN) ..................................................................................... 30-4 Transmit Data[3:0] (EnTXD[3:0]) ............................................................................ 30-4 Transmit Error (EnTXER) ........................................................................................ 30-5 Receive Data Valid (EnRXDV) ................................................................................ 30-5 Receive Data[3:0] (EnRXD[3:0]) ............................................................................. 30-5 Receive Error (EnRXER) ......................................................................................... 30-5 Carrier Sense (EnCRS) ............................................................................................. 30-5 Collision (EnCOL) .................................................................................................... 30-5 Management Data Clock (EnMDC) ......................................................................... 30-5 Management Data (EnMDIO) .................................................................................. 30-5 Memory Map/Register Definition ................................................................................ 30-6 Top Level Module Memory Map ............................................................................. 30-6 Detailed Memory Map (Control/Status Registers) ................................................... 30-7 MIB Block Counters Memory Map .......................................................................... 30-8 Ethernet Interrupt Event Register (EIR) ............................................................. 30-10 Interrupt Mask Register (EIMR) ........................................................................ 30-12 Ethernet Control Register (ECR) ........................................................................ 30-13 MII Management Frame Register (MMFR) ....................................................... 30-14 MII Speed Control Register (MSCR) ................................................................. 30-15 MIB Control Register (MIBC) ........................................................................... 30-17 Receive Control Register (RCR) ........................................................................ 30-17 Receive Hash Register (RHR) ............................................................................ 30-18 Transmit Control Register (TCR) ....................................................................... 30-19 Physical Address Low Register (PALR) ............................................................ 30-20 Physical Address High Register (PAHR) ........................................................... 30-21 Opcode/Pause Duration Register (OPD) ............................................................ 30-22 Individual Address Upper Register (IAUR) ....................................................... 30-22 Individual Address Lower Register (IALR) ....................................................... 30-23 Group Address Upper Register (GAUR) ............................................................ 30-24 Group Address Lower Register (GALR) ............................................................ 30-24 FEC Transmit FIFO Watermark Register (FECTFWR) .................................... 30-25 FEC Receive FIFO Data Register (FECRFDR) ................................................. 30-26 FEC Receive FIFO Status Register (FECRFSR) ................................................ 30-26 FEC Receive FIFO Control Register (FECRFCR) ............................................. 30-28 FEC Receive FIFO Last Read Frame Pointer Register (FECRLRFP) ............... 30-30 FEC Receive FIFO Last Write Frame Pointer Register (FECRLWFP) ............. 30-30 FEC Receive FIFO Alarm Register (FECRFAR) .............................................. 30-31 MCF548x Reference Manual, Rev. 3 xxxviii Freescale Semiconductor Contents Paragraph Number 30.3.3.24 30.3.3.25 30.3.3.26 30.3.3.27 30.3.3.28 30.3.3.29 30.3.3.30 30.3.3.31 30.3.3.32 30.3.3.33 30.3.3.34 30.3.3.35 30.4 30.4.1 30.4.1.1 30.4.1.2 30.4.2 30.4.2.1 30.4.2.2 30.4.3 30.4.4 30.4.5 30.4.6 30.4.7 30.4.8 30.4.9 30.4.10 30.4.11 30.4.12 30.4.12.1 30.4.12.2 30.4.13 30.4.14 Title Page Number FEC Receive FIFO Read Pointer Register (FECRFRP) ..................................... 30-32 FEC Receive FIFO Write Pointer Register (FECRFWP) ................................... 30-33 FEC Transmit FIFO Data Register (FECTFDR) ................................................ 30-33 FEC Transmit FIFO Status Register (FECTFSR) .............................................. 30-34 FEC Transmit FIFO Control Register (FECTFCR) ........................................... 30-36 FEC Transmit FIFO Last Read Frame Pointer Register (FECTLRFP) .............. 30-37 FEC Transmit FIFO Last Write Frame Pointer Register (FECTLWFP) ............ 30-38 FEC Transmit FIFO Alarm Register (FECTFAR) ............................................. 30-39 FEC Transmit FIFO Read Pointer Register (FECTFRP) ................................... 30-40 FEC Transmit FIFO Write Pointer Register (FECTFWP) ................................. 30-40 FEC FIFO Reset Register (FECFRST) ............................................................... 30-41 FEC CRC and Transmit Frame Control Word Register (FECCTCWR) ............ 30-42 Functional Description ................................................................................................ 30-43 Initialization Sequence ............................................................................................ 30-43 Hardware Controlled Initialization ..................................................................... 30-43 User Initialization (Prior to Asserting ECR[ETHER_EN]) ................................ 30-43 Frame Control/Status Words .................................................................................. 30-44 Receive Frame Status Word (RFSW) ................................................................. 30-44 Transmit Frame Control Word (TFCW) ............................................................. 30-45 Network Interface Options ...................................................................................... 30-46 FEC Frame Transmission ....................................................................................... 30-46 FEC Frame Reception ............................................................................................. 30-47 Ethernet Address Recognition ................................................................................ 30-48 Hash Algorithm ....................................................................................................... 30-49 Full Duplex Flow Control ....................................................................................... 30-52 Inter-Packet Gap (IPG) Time .................................................................................. 30-53 Collision Handling .................................................................................................. 30-53 Internal and External Loopback .............................................................................. 30-53 Ethernet Error-Handling Procedure ........................................................................ 30-54 Transmission Errors ............................................................................................ 30-54 Reception Errors ................................................................................................. 30-55 MII Data Frame ...................................................................................................... 30-55 MII Management Frame Structure ......................................................................... 30-56 Chapter 31 Mechanical Data 31.1 31.2 31.3 31.3.1 Package ......................................................................................................................... 31-1 Pinout ............................................................................................................................ 31-1 Mechanical Diagrams ................................................................................................... 31-8 MCF5485/5484 Mechanical Diagram ...................................................................... 31-8 MCF548x Reference Manual, Rev. 3 Freescale Semiconductor xxxix Contents Paragraph Number 31.3.2 31.4 31.5 31.6 Title Page Number MCF5483/5482 Mechanical Diagram .................................................................... 31-12 MCF5481/5480 Mechanical Diagram ........................................................................ 31-16 Mechanicals 388-pin PBGA Package Outline ............................................................ 31-20 Case Drawing .............................................................................................................. 31-20 Appendix A MCF548x Memory Map MCF548x Reference Manual, Rev. 3 xl Freescale Semiconductor About This Book The primary objective of this reference manual is to define the functionality of the MCF548x processors for use by software and hardware developers. The information in this book is subject to change without notice, as described in the disclaimers on the title page of this book. As with any technical documentation, it is the readers’ responsibility to be sure they are using the most recent version of the documentation. To locate any published errata or updates for this document, refer to the world-wide web at http://www.freescale.com/coldfire. Audience This manual is intended for system software and hardware developers and applications programmers who want to develop products for the MCF548x. It is assumed that the reader understands operating systems, microprocessor system design, basic principles of software and hardware, and basic details of the ColdFire architecture. Organization Following is a summary and a brief description of the major sections of this manual: • Chapter 1, “Overview,” includes general descriptions of the modules and features incorporated in the MCF548x, focussing in particular on new features. • Chapter 2, “Signal Descriptions,” provides an alphabetical listing of MCF548x signals, including which are inputs or outputs, how they are multiplexed, and the state of each signal at reset. • Part I, “Processor Core,” is intended for system designers who need to understand the operation of the MCF548x ColdFire core and its enhanced multiply/accumulate (EMAC) execution unit. It describes the programming and exception models, Harvard memory implementation, and debug module. Part 1 contains the following chapters: — Chapter 3, “ColdFire Core,” provides an overview of the microprocessor core of the MCF548x. The chapter begins with a description of enhancements from the V3 ColdFire core, and then fully describes the V4e programming model as it is implemented on the MCF548x. It also includes a full description of exception handling, data formats, an instruction set summary, and a table of instruction timings. — Chapter 4, “Enhanced Multiply-Accumulate Unit (EMAC),” describes the MCF548x enhanced multiply/accumulate unit, which executes integer multiply, multiply-accumulate, and miscellaneous register instructions. The EMAC is integrated into the operand execution pipeline (OEP). — Chapter 5, “Memory Management Unit (MMU),” describes describes the ColdFire virtual memory management unit (MMU), which provides virtual-to-physical address translation and memory access control. — Chapter 6, “Floating-Point Unit (FPU),” describes instructions implemented in the floating-point unit (FPU) designed for use with the ColdFire family of microprocessors. MCF548x Reference Manual, Rev. 3 Freescale Semiconductor xli • • — Chapter 7, “Local Memory,” describes the MCF548x implementation of the ColdFire V4e local memory specification. — Chapter 8, “Debug Support,” describes the Revision C enhanced hardware debug support in the MCF548x. This revision of the ColdFire debug architecture encompasses earlier revisions. Part II, “System Integration Unit,” describes the system integration unit, which provides overall control of the bus and serves as the interface between the ColdFire core processor complex and internal peripheral devices. It includes a general description of the SIU and individual chapters that describe components of the SIU, such as the interrupt controller, general purpose timers, slice timers, and GPIOs. Part II contains the following chapters: — Chapter 9, “System Integration Unit (SIU),” describes the SIU programming model, bus arbitration, and system-protection functions for the MCF548x. — Chapter 10, “Internal Clocks and Bus Architecture,” describes the clocking and internal buses of the MCF548x and discusses the main functional blocks controlling the XL bus and the XL bus arbiter. — Chapter 11, “General Purpose Timers (GPT),” describes the functionality of the four general purpose timers, GPT0–GPT3. — Chapter 12, “Slice Timers (SLT),” describes the two slice timers, shorter term periodic interrupts, used in the MCF548x. — Chapter 13, “Interrupt Controller,” describes operation of the interrupt controller portion of the SIU. Includes descriptions of the registers in the interrupt controller memory map and the interrupt priority scheme. — Chapter 14, “Edge Port Module (EPORT),” describes EPORT module functionality. — Chapter 15, “GPIO,” describes the operation and programming model of the parallel port pin assignment, direction-control, and data registers. Part III, “On-Chip Integration,” describes the on-chip integration for the MCF548x device. It includes descriptions of the system SRAM, FlexBus interface, SDRAM controller, PCI, and SEC cryptography accelerator. Part III contains the following chapters: — Chapter 16, “32-Kbyte System SRAM,” describes the MCF548x on-chip system SRAM implementation. It covers general operations, configuration, and initialization. — Chapter 17, “FlexBus,” describes data transfer operations, error conditions, and reset operations. It describes transfers initiated by the MCF548x and by an external master, and includes detailed timing diagrams showing the interaction of signals in supported bus operations. — Chapter 18, “SDRAM Controller (SDRAMC),” describes configuration and operation of the synchronous DRAM controller component of the SIU. It includes a description of signals involved in DRAM operations, including chip select signals and their address, mask, and control registers. — Chapter 19, “PCI Bus Controller,” details the operation of the PCI bus controller for the MCF548x. — Chapter 20, “PCI Bus Arbiter Module,” describes the MCF548x PCI bus arbiter module, including timing for request and grant handshaking, the arbitration process, and the register in the PCI bus arbiter programing model. MCF548x Reference Manual, Rev. 3 xlii Freescale Semiconductor Suggested Reading • • — Chapter 21, “FlexCAN,” describes the MCF548 implementation of the controller area network (CAN) protocol. This chapter describes FlexCAN module operation and provides a programming model. — Chapter 22, “Integrated Security Engine (SEC),” provides an overview of the MCF548x security encryption controller. — Chapter 23, “IEEE 1149.1 Test Access Port (JTAG),” describes configuration and operation of the MCF548x JTAG test implementation. It describes the use of JTAG instructions and provides information on how to disable JTAG functionality. Part IV, “Communications Subsystem,” contains chapters that discuss the operation and configuration of the communications I/O subsystem including the MCF548x multichannel DMA, communications timer, PSC, FEC, DSPI, and USB2, and I2C. — Chapter 24, “Multichannel DMA,” provides an overview of the multichannel DMA controller module including the operation of the external DMA request signals. — Chapter 25, “Comm Timer Module (CTM),” contains a detailed description of the communications timer module, which functions as a baud clock generator or as a DMA task initiator. — Chapter 26, “Programmable Serial Controller (PSC),” provides an overview of asynchronous, synchronous, and IrDA 1.1 compliant receiver/transmitter serial communications of the MCF548x. — Chapter 27, “DMA Serial Peripheral Interface (DSPI),” describes the use of the DMA serial peripheral interface (DSPI) implemented on the MCF548x processor, including details of the DSPI data transfers. The chapter concludes with timing diagrams and the DSPI features that support Tx and Rx FIFO queue management. — Chapter 28, “I2C Interface,” describes the MCF548x I2C module, including I2C protocol, clock synchronization, and the registers in the I2C programing model. It also provides programming examples. — Chapter 29, “USB 2.0 Device Controller,” provides an overview of the USB 2.0 device controller module used in the MCF548x. — Chapter 30, “Fast Ethernet Controller (FEC),” provides a feature-set overview, a functional block diagram, and transceiver connection information for both MII (Media Independent Interface) and 7-wire serial interfaces. It also provides describes operation and the programming model. Part V, “Mechanical,” provides a pinout and both electrical and functional descriptions of the MCF548x signals. It also describes how these signals interact to support the variety of bus operations shown in timing diagrams. — Chapter 31, “Mechanical Data,” provides a functional pin listing and package diagram for the MCF548x. Suggested Reading This section lists additional reading that provides background for the information in this manual as well as general information about the ColdFire architecture. MCF548x Reference Manual, Rev. 3 Freescale Semiconductor xliii General Information The following documentation provides useful information about the ColdFire architecture and computer architecture in general: • ColdFire Programmers Reference Manual (CFPRM) • Using Microprocessors and Microcomputers: The Motorola Family, William C. Wray, Ross Bannatyne, Joseph D. Greenfield • Computer Architecture: A Quantitative Approach, Second Edition, by John L. Hennessy and David A. Patterson. • Computer Organization and Design: The Hardware/Software Interface, Second Edition, David A. Patterson and John L. Hennessy. ColdFire Documentation The ColdFire documentation is available from the sources listed on the back cover of this manual. Document order numbers are included in parentheses for ease in ordering. • ColdFire Programmers Reference Manual, R1.0 (CFPRM) • Reference manuals—These books provide details about individual ColdFire implementations and are intended to be used in conjunction with The ColdFire Programmers Reference Manual. These include the following: — ColdFire CF4e Core User's Manual (V4ECFUM) — MCF5475 Reference Manual (MCF5475RM) — MCF5485 Reference Manual (MCF5485RM) Additional literature on ColdFire implementations is being released as new processors become available. For a current list of ColdFire documentation, refer to the World Wide Web at http://www.freescale.com/coldfire. Conventions This document uses the following notational conventions: MNEMONICS In text, instruction mnemonics are shown in uppercase. mnemonics In code and tables, instruction mnemonics are shown in lowercase. italics Italics indicate variable command parameters. Book titles in text are set in italics. 0x0 Prefix to denote hexadecimal number 0b0 Prefix to denote binary number REG[FIELD] Abbreviations for registers are shown in uppercase. Specific bits, fields, or ranges appear in brackets. For example, RAMBAR[BA] identifies the base address field in the RAM base address register. nibble A 4-bit data unit byte An 8-bit data unit word A 16-bit data unit MCF548x Reference Manual, Rev. 3 xliv Freescale Semiconductor Acronyms and Abbreviations longword x n ¬ & | A 32-bit data unit In some contexts, such as signal encodings, x indicates a don’t care. Used to express an undefined numerical value NOT logical operator AND logical operator OR logical operator Register Conventions This reference manual uses the register diagram format shown below. R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset R DFL W Reset Reg Addr 0 0 0 0x00C Table i. Example Register Diagram Acronyms and Abbreviations Table ii lists acronyms and abbreviations used in this document. Table ii. . Acronyms and Abbreviated Terms Term Meaning ADC Analog-to-digital conversion ALU Arithmetic logic unit AVEC Autovector BDM Background debug mode BIST Built-in self test BSDL Boundary-scan description language CODEC Code/decode comm bus Internal communications bus DAC Digital-to-analog conversion DMA Direct memory access DSP Digital signal processing MCF548x Reference Manual, Rev. 3 Freescale Semiconductor xlv Table ii. . Acronyms and Abbreviated Terms (continued) Term Meaning EA Effective address EDO Extended data output (DRAM) FIFO First-in, first-out GPIO General-purpose I/O 2 I C Inter-integrated circuit IEEE Institute for Electrical and Electronics Engineers IFP Instruction fetch pipeline IPL Interrupt priority level JEDEC Joint Electron Device Engineering Council JTAG Joint Test Action Group LIFO Last-in, first-out LRU Least recently used LSB Least-significant byte lsb Least-significant bit MAC Multiple accumulate unit MBAR Memory base address register MSB Most-significant byte msb Most-significant bit Mux Multiplex NOP No operation OEP Operand execution pipeline PC Program counter PCLK Processor clock PLL Phase-locked loop PLRU Pseudo least recently used POR Power-on reset PQFP Plastic quad flat pack RISC Reduced instruction set computing Rx Receive SIM System integration module SOF Start of frame TAP Test access port TTL Transistor-to-transistor logic Tx Transmit MCF548x Reference Manual, Rev. 3 xlvi Freescale Semiconductor Terminology and Notational Conventions Table ii. . Acronyms and Abbreviated Terms (continued) Term Meaning UART Universal asynchronous/synchronous receiver transmitter XLB bus Internal 64-bit bus Terminology and Notational Conventions Table iii shows notational conventions used throughout this document. Table iii. Notational Conventions Instruction Operand Syntax Opcode Wildcard cc Logical condition (example: NE for not equal) Register Specifications An Ay,Ax Any address register n (example: A3 is address register 3) Source and destination address registers, respectively Dn Any data register n (example: D5 is data register 5) Dy,Dx Source and destination data registers, respectively Rc Any control register (example VBR is the vector base register) Rm MAC registers (ACC, MAC, MASK) Rn Any address or data register Rw Destination register w (used for MAC instructions only) Ry,Rx Xi Any source and destination registers, respectively index register i (can be an address or data register: Ai, Di) Register Names ACC MAC accumulator register CCR Condition code register (lower byte of SR) MACSR MAC status register MASK MAC mask register PC Program counter SR Status register Port Name PSTDDATA Processor status/debug data port Miscellaneous Operands #Immediate data following the 16-bit operation word of the instruction Effective address MCF548x Reference Manual, Rev. 3 Freescale Semiconductor xlvii Table iii. Notational Conventions (continued) Instruction y, x