Fujitsu Microsoft 65 Nm Process Technology_2_7_06 65nm CMOS Technology
User Manual: Fujitsu 65nm CMOS Process Technology 65nm CMOS Process Technology - Fujitsu United States
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65nm CMOS Process Technology Paul Kim Senior Manager, Foundry Services Fujitsu Microelectronics America, Inc. Leading-edge Technology Fujitsu 65nm New 300mm Fabs – Mie, Japan 300mm Fab No.2 •Process •65nm/90nm CMOS Logic •Structural Features •Seismic-vibration control construction •Clean room area: 24,000 sq. meters •Production Capacity •10,000 wafers per month (FY07 projection) •Maximum capacity of 25,000 wafers per month •Planned Start of Operation •April 2007 300mm Fab No.1 •Process •90nm/65nm CMOS Logic •Structural Features •Seismic-control construction •Clean room area: 12,000 sq. meters •Production Capacity •15,000 wafers per month (FY06) •Start of Operation •April 2005 February 7, 2006 2 DesignCon 2006 Leading-edge Technology Fujitsu 65nm CMOS Technology Roadmap Physical Gate Length (nm) 1000 180nm 180nm 500 130nm 130nm 90nm 90nm 65nm 65nm 200 45nm 45nm CS80 / 80A CS90A 100 CS100/CS100A (90nm) L actual=40-80nm SiOC (k:2.9) low-k Dual Damascene Cu CS100A CS200A CS90 50 CS100HP 20 10 1998 2000 CS200 2002 2004 2006 2008 CS200/CS200A (65nm) L actual=30-50nm NCS (Nano-Clustering Silica) 2010 Year (Production Start) February 7, 2006 3 DesignCon 2006 Leading-edge Technology Fujitsu 65nm February 7, 2006 Proven Track Record of 90nm Complex Designs and Products 4 DesignCon 2006 Leading-edge Technology Fujitsu 65nm Proven Track Record of 90nm Complex Designs and Products – continued Chip Size (mm2) High-performance Products PC CPU (Transmeta) Large-scale FPGA (Lattice) Others Low-power Products Multimedia processor Digital AV products Others February 7, 2006 350-450 High End Low Power 250-350 200-250 100-200 50-100 20-50 0 5 5 10 Tape Out Number DesignCon 2006 Leading-edge Technology Fujitsu 65nm 65nm, CS200 / 200A Features Features Ultra-high-speed performance (CS200) LG = 30nm, on-current enhance Compared to 90nm technology, CS200 offers: 1.3 times faster speed 0.6 times lower power 2 times higher density 3 variations of Vth on a chip (CS200A) (1.8V & 2.5V) or (1.8V & 3.3V) I/O combination available 11-layer copper interconnects with robust, very low K ILD February 7, 2006 6 DesignCon 2006 CS200 / 200A Transistor Variations Leading-edge Technology Fujitsu 65nm Leakage current Large CS200: Ultra High Speed CS200A: Wide Speed Range + Low Power Consumption HS-Tr Server/ Network STD-Tr CS200A HVt-Tr HS-Tr High End Server Mobile Computing STD-Tr LL-Tr Digital Consumer Cellular Phone Speed February 7, 2006 CS200 7 HS:High speed STD:Standard LL:Low leakage Fast DesignCon 2006 Leading-edge Technology Leading-edge Transistors Performance Large Fujitsu 65nm 90nm node Leakage 65nm node tpd × P Small 45nm node Fast February 7, 2006 Propagation Delay 8 Slow DesignCon 2006 Leading-edge Technology Fujitsu 65nm Ultra-Thin Gate Insulator / Mobility Improvement 1nm-thick Gate Oxide Nitrided-SiO2 Si substrate Normalized gm (∝ mobility) Poly-Si Surface Cleaning 2.0E-3 40% increase 1.5E-3 After optimize 1.0E-3 5.0E-4 Before 0.0 -0.5 1.5 3.5 5.5 Electric Field [MV/cm] February 7, 2006 9 DesignCon 2006 Leading-edge Technology Fujitsu 65nm Speed Performance Improvements 65nm CS200 (ps/gate) 90nm CS100 Delay (ps/gate) Improvement Inverter 5.7 7.0 19% 2-input NAND 8.7 11.4 24% 23.1 30.8 25% 2-input NAND + 200 grid interconnect load February 7, 2006 10 DesignCon 2006 Leading-edge Technology Fujitsu 65nm High-Performance Competitive Transistors Ion vs Ioff Characteristics of nMOSFETs Ioff (A/um) 10-6 10-7 Company 1) B Company 2) 70nA/μm A Fujitsu 10-8 Ref. 1, 2) 2004 Symposium on VLSI Technology Vd=1.0V 10-9 0.7 February 7, 2006 0.8 0.9 1.0 1.1 Ion (uA/um) 11 1.2 1.3 DesignCon 2006 Leading-edge Technology Fujitsu 65nm Advanced Cu and Low-k Dielectric constant High Low Four Generations of Experience CS80/80A 6-Cu layers ILD FSG CS90A 7-Cu layers ILD hybrid low-k CS100/100A/150 10-Cu layers ILD full low-k ILD: Inter-layer Dielectric 180nm node February 7, 2006 130nm node 90nm node 12 CS200/200A/250 11-Cu layers ILD hybrid Ultra-low K 65nm node DesignCon 2006 Leading-edge Technology Fujitsu 65nm Fujitsu’s Low-k Leads ITRS 500 3.0 <2.7 <2.4 2.5 <2.1 <1.9 300 200 2.0 k Width [nm] 400 k Intermediate Wire Pitch 1.5 130nm 130nm 90nm 90nm 100 1.0 65nm 65nm 45nm 45nm CMOS Technology Node 0 2000 2005 32nm 32nm 2010 2015 Products Year CS90 SiLK TM/SiO K=2.7/4.1 February 7, 2006 2 CS100 Full- SiOC K=2.9/2.9 13 CS200 NCS/ SiOC CS300 Full - NCS K=2.25/2.9 K=2.25/2.25 DesignCon 2006 Leading-edge Technology Fujitsu 65nm Low-k Advantages of 65nm Ultra low-k impacts on speed and power dissipation CS100A (90nm) with SiOC/SiOC Rsh: 90mΩ/sq., C: 56fF/1000 grid CS200A (65nm) with SiOC/SiOC Rsh: 150mΩ/sq., C: 52fF/1000 grid CS200A (65nm) with NCS/SiOC Rsh: 150mΩ/sq., C: 40fF/1000 grid February 7, 2006 14 DesignCon 2006 Leading-edge Technology Fujitsu 65nm 11-Layer Copper Interconnects Cu 11-layer Stack-via Chain February 7, 2006 15 DesignCon 2006 Leading-edge Technology Fujitsu 65nm The Fujitsu Ecosystem 3rd Party Application Application 3rd Party Test & & Software Software Library Support Support Vendors Houses Packaging, Packaging, Library Library Assembly Assembly Development Development & & Test Test Process Process Technology Technology IP IP Design Design Development Development Methodology Methodology & & Support Support EDA Design Design 3rd Party Vendors Services Services IP Vendors 3rd Party Design Houses February 7, 2006 16 DesignCon 2006 Leading-edge Technology Fujitsu 65nm Fujitsu Technology Access Flexible collaboration models provide easy access to Fujitsu’s leading-edge process for the development of highly complex silicon products ASIC Flow COT Flow Custom Flow Customer Fujitsu Customer Fujitsu Customer Fujitsu RTL Design Logical Synthesis DFT Insertion Formal Verification Floorplanning Physical Synthesis Clock Tree Synthesis Routing Timing & SI Verification STA / ECO Physical Verification Test Validation February 7, 2006 17 DesignCon 2006 Leading-edge Technology Fujitsu 65nm Design Flow & Methodology Reference design flow - Fujitsu’s leading-edge design methodology focuses on timing, signal and power integrity closure Support for both Cadence SOCEncounter and Synopsys Galaxy platforms In-house CAD software development augments leading third-party EDA solutions Ensures silicon correlation and a fast path to silicon success by TM TM combining Fujitsu’s strengths in process, CAD tool and methodology development with design experience and expertise Production proven flows used on 100+ multi-million-gate designs at 180, 130 and 90nm Constantly updated and improved to address all issues at each process node February 7, 2006 18 DesignCon 2006 Leading-edge Technology Fujitsu 65nm Fujitsu Design Services Library and tool support Methodology development and support High-speed I/O design and expertise Vertical expertise and IP cores RTL design Synthesis and physical synthesis Design partitioning and floorplanning Static timing analysis Test insertion and ATPG generation Place and route Timing and SI closure Formal verification Physical verification Test and product engineering February 7, 2006 19 DesignCon 2006 Leading-edge Technology Fujitsu 65nm Fujitsu Worldwide Design Centers Global Presence Local design centers around the world provide design services for all phases of the development process Skilled engineering teams experienced in development of large complex designs at 130nm and below 100+ multi-million gate designs taped out February 7, 2006 20 DesignCon 2006 Leading-edge Technology Fujitsu 65nm Summary Fujitsu Objective Helping customers accelerate their innovation, differentiate their products and enhance their competitive advantage, therefore helping them succeed Leading-edge technologies Strength in process technologies 90nm, 65nm and beyond Partnerships and customer collaborations Flexible customer engagements and close collaborations Early customer engagements Tailored support and services to meet customer needs System-level LSI solutions ASIC and ASSP/SoC, including10GbE switch chip and WiMAX SoC Full design and development environments and support February 7, 2006 21 DesignCon 2006
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