Getac Technology PR533A RFID module User Manual PR533 USB NFC integrated reader solution

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Date Submitted	2017-07-14 00:00:00
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Document Title	PR533 USB NFC integrated reader solution
Document Creator	FrameMaker 10.0.2
Document Author:	NXP Semiconductors

PR533
USB NFC integrated reader solution
Rev. 3.6 — 27 October 2014
206436
Product short data sheet
COMPANY PUBLIC
1. General description
The PR5331C3HN is a highly integrated transceiver module for contactless reader/writer
communication at 13.56 MHz.
A dedicated ROM code is implemented to handle different RF protocols by an integrated
microcontroller. The system host controller communicates with the PR5331C3HN by
using the USB or the HSU link.
The protocol between the host controller and the PR5331C3HN, on top of this physical
link is the CCID protocol.
1.1 RF protocols
PR5331C3HN supports the PCD mode for FeliCa (212 kbps and 424 kbps),
ISO/IEC14443 Type A and B (from 106 kbps to 848 kbps), MIFARE (106 kbps), B' cards
(106 kbps), picoPass tag (106 kbps) and Innovision Jewel cards (106 kbps)
The Initiator passive mode (from 106 kbps to 424 kbps) can be supported through the
PC/SC transparent mode.
1.2 Interfaces
The PR5331C3HN supports a USB 2.0 full speed interface (bus powered or host powered
mode).
Alternatively to the USB interface, a High Speed UART (from 9600b up to 1.2 Mb) can be
used to connect the PR533 to a host.
The PR5331C3HN has also a master I2C-bus interface that allows to connect one of the
following peripherals:
• An external EEPROM: in this case the PR5331C3HN is configured as master and is
able to communicate with external EEPROM (address A0h) which can store
configuration data like PID, UID and RF parameters. When a USB host interface is
used, these parameters are retrieved from the EEPROM at startup of the device
• A TDA8029 contact smart card reader
1.3 Standards compliancy
PR5331C3HN offers commands in order for applications to be compliant with “EMV
Contactless Communication Protocol Specification V2.0.1”.
PR5331C3HN supports RF protocols ISO/IEC 14443A and B such as compliancy with
Smart eID standard can be achieved at application level.
PR533
NXP Semiconductors
USB NFC integrated reader solution
Support of USB 2.0 full speed, interoperable with USB 3.0 hubs.
The PR533C3HN in PCD mode is compliant with EMV contactless specification V2.0.1.
1.4 Supported operating systems
•
•
•
•
•
•
Microsoft Windows 2000
Microsoft Windows XP (32 and 64 bits)
Microsoft Windows 2003 Server (32 and 64 bits)
Microsoft Windows 2008 Server (32 and 64 bits)
Microsoft Windows Vista (32 and 64 bits)
Microsoft Windows 7 (32 and 64 bits)
The PR533 is supported by the following OS through the PCSC-Lite driver:
•
•
•
•
•
GNU/Linux using libusb 1.0.x and later
Mac OS Leopard (1.5.6 and newer)
Mac OS Snow Leopard (1.6.X)
Solaris
FreeBSD
2. Features and benefits
 USB 2.0 full speed host interface and CCID protocol support
 Integrated microcontroller implements high-level RF protocols
 Buffered output drivers to connect an antenna with minimum number of external
components
 Integrated RF level detector
 Integrated data mode detector
 Supports ISO/IEC 14443A Reader/Writer mode up to 848 kbit/s
 Supports ISO/IEC 14443B Reader/Writer mode up to 848 kbit/s
 Supports contactless communication according to the FeliCa protocol at 212 kbit/s and
424 kbit/s
 Supports MIFARE encryption
 Typical operating distance in Read/Write mode for communication to
ISO/IEC 14443A/MIFARE, ISO/IEC 14443B or FeliCa cards up to 50 mm depending
on antenna size and tuning
 I2C-bus master interface allows to connect an external I2C EEPROM for configuration
data storage or to control a TDA8029 contact smart card reader
 Low-power modes
 Hard power-down mode
 Soft power-down mode
 Only one external oscillator required (27.12 MHz Crystal oscillator)
 Power modes
 USB bus power mode
 2.5 V to 3.6 V power supply operating range in non-USB bus power mode
PR533_SDS
Product short data sheet
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.6 — 27 October 2014
206436
© NXP Semiconductors N.V. 2014. All rights reserved.
2 of 36
PR533
NXP Semiconductors
USB NFC integrated reader solution
 Dedicated I/O ports for external device control
3. Quick reference data
Table 1.
Quick reference data
Symbol
Parameter
VBUS
bus supply voltage
Conditions
Min
Typ
Max
Unit
4.02
5.25
2.5
3.3
3.6
[1]
2.5
3.3
3.6
[1]
2.5
3.3
3.6
(non-USB mode);
VBUS = VDDD; VSSD = 0 V
VDDA
VDDD
analog supply voltage
digital supply voltage
VDDA = VDDD = VDD(TVDD) =
VDD(PVDD); VSSA = VSSD =
VSS(PVSS) = VSS(TVSS) = 0 V
VDD(TVDD)
TVDD supply voltage
VDD(PVDD)
PVDD supply voltage
VDD(SVDD)
SVDD supply voltage
VSSA = VSSD = VSS(PVSS) =
VSS(TVSS) = 0 V; reserved for
future use
IBUS
bus supply current
Ipd
power-down current
[1]
2.5
3.3
3.6
1.6
3.6
VDDD
maximum load current (USB
mode); measured on VBUS
150
mA
maximum inrush current limitation; at power-up
(curlimoff = 0)
100
mA
VDDD 0.1 -
VDDA = VDDD = VDD(TVDD) = VDD(PVDD) = 3 V; not powered from USB
hard power-down;
RF level detector off
10
A
soft power-down; RF level
detector on
30
A
250
A
15
mA
VDDS = 3 V
30
mA
analog supply current
RF level detector on
mA
IDD(TVDD)
TVDD supply current
during RF transmission;
VDD(TVDD) = 3 V
60
100
mA
Ptot
total power dissipation
Tamb = 30 to +85 C
0.55
Tamb
ambient temperature
30
+85
C
ICCSL
suspended low-power
device supply current
RF level detector on, (without resistor on DP/DM)
IDDD
digital supply current
RF level detector on,
VDD(SVDD) switch off
IDD(SVDD)
SVDD supply current
IDDA
[1]
[1]
VDDD, VDDA and VDD(TVDD) must always be at the same supply voltage.
PR533_SDS
Product short data sheet
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.6 — 27 October 2014
206436
© NXP Semiconductors N.V. 2014. All rights reserved.
3 of 36
PR533
NXP Semiconductors
USB NFC integrated reader solution
4. Ordering information
Table 2.
Ordering information
Type number
Package
Name
PR5331C3HN/C360[1][2][3]
PR5331C3HN/C370[1][2][3]
Description
Version
HVQFN40 plastic thermal enhanced very thin quad flat package; no leads;
40 terminals; body 6  6  0.85 mm
SOT618-1
[1]
60 or 70 refers to the ROM code version described in the User Manual. For differences of romcode versions refer to the release note of
the product.
[2]
Refer to Section 14.4 “Licenses”.
[3]
MSL 2 (Moisture Sensitivity Level).
5. Block diagram
The following block diagram describes hardware blocks controlled by PR5331C3HN
firmware or which can be accessible for data transaction by a host baseband.
RSTPD_N
VBUS
RSTOUT_N
SUPPLY
SUPERVISOR
DVSS
DVDD
OSCOUT
AVSS
REGULATOR
3.3 V
SVDD
SVDD
SWITCH
27 MHz OSC
AND
FRAC N
PLL
OSCIN
P70_IRQ
SIGIN
SIGOUT
P34
PCR
48 MHz
DELATT
USB
DEVICE
TVDD
I0
MATX
80C51 CPU
I1
44 k ROM
1.2 k BYTES RAM
I2C
MASTER
P50_SCL
PVDD
Product short data sheet
COMPANY PUBLIC
RX
VMID
TX1
P30 P31
TX2
P32_INT0
GPIOs
PR533_SDS
AVDD
TVSS
SDA
Fig 1.
NFC
ANALOG
FRONT END
AND
CLUART
P33_INT0
P35
aaa-000043
Block diagram
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Rev. 3.6 — 27 October 2014
206436
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PR533
NXP Semiconductors
USB NFC integrated reader solution
6. Pinning information
31 P33_INT1
32 P50_SCL
33 SDA
34 P34
35 SIGOUT
36 SIGIN
37 SVDD
38 RSTPD_N
terminal 1
index area
39 DVDD
40 VBUS
6.1 Pinning
DVSS
30 P32_INT0
LOADMOD
29 P31
TVSS1
28 P30
TX1
27 DELATT
TVDD
TX2
TVSS2
24 DM
AVDD
23 DVSS
VMID
22 RSTOUT_N
26 PVDD
PR533
25 DP
P35 20
TESTEN 19
I1 18
I0 17
OSCOUT 16
OSCIN 15
DVSS 14
AUX2 13
AUX1 12
21 P70_IRQ
AVSS 11
RX 10
aaa-000044
Transparent top view
Fig 2. Pin configuration for HVQFN 40 (SOT618-1)
6.2 Pin description
Table 3.
PR533 pin description
Symbol
Pin
Type Pad ref
voltage
Description
DVSS
digital ground
LOADMOD
TVSS1
TX1
TVDD
TX2
TVSS2
transmitter ground: supplies the output stage of TX2
AVDD
analog power supply
VMID
AVDD
internal reference voltage: This pin delivers the internal reference voltage.
RX
10
AVDD
receiver input: Input pin for the reception signal, which is the load modulated
13.56 MHz energy carrier from the antenna circuit
AVSS
11
AUX1
12
DVDD
auxiliary output 1: This pin delivers analog and digital test signals
AUX2
13
DVDD
auxiliary output 2: This pin delivers analog and digital test signals
DVSS
14
PR533_SDS
Product short data sheet
COMPANY PUBLIC
DVDD
load modulation output provides digital signal for FeliCa and MIFARE card
operating mode
transmitter ground: supplies the output stage of TX1
TVDD
transmitter 1: transmits modulated 13.56 MHz energy carrier
transmitter power supply: supplies the output stage of TX1 and TX2
TVDD
transmitter 2: delivers the modulated 13.56 MHz energy carrier
analog ground
digital ground
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Rev. 3.6 — 27 October 2014
206436
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PR533
NXP Semiconductors
USB NFC integrated reader solution
Table 3.
PR533 pin description …continued
Symbol
Pin
Type Pad ref
voltage
Description
OSCIN
15
AVDD
crystal oscillator input: input to the inverting amplifier of the oscillator. This pin
is also the input for an externally generated clock (fclk = 27.12 MHz).
OSCOUT
16
AVDD
crystal oscillator output: output of the inverting amplifier of the oscillator.
I0
17
DVDD
I1
18
DVDD
interface mode lines: selects the used host interface; in test mode I0 is used
as test signals.
TESTEN
19
DVDD
test enable pin:
when set to 1 enable the test mode.
when set to 0 reset the TCB and disable the access to the test mode.
P35
20
I/O
DVDD
general purpose I/O signal
P70_IRQ
21
I/O
PVDD
interrupt request: output to signal an interrupt event to the host (Port 7 bit 0)
RSTOUT_N
22
PVDD
output reset signal; when LOW it indicates that the circuit is in reset state.
DVSS
23
DM
24
I/O
PVDD
USB D data line in USB mode or TX in HSU mode; in test mode this signal
is used as input and output test signal
DP
25
I/O
PVDD
USB D+ data line in USB mode or RX in HSU mode; in test mode this signal
is used as input and output test signal.
PVDD
26
DELATT
27
PVDD
optional output for an external 1.5 k resistor connection on D+.
P30
28
I/O
PVDD
general purpose I/O signal. Can be configured to act either as RX line of the
second serial interface UART or general purpose I/O.
digital ground
I/O pad power supply
In test mode this signal is used as input and output test signal.
P31
29
I/O
PVDD
general purpose I/O signal. Can be configured to act either as TX line of the
second serial interface UART or general purpose I/O.
In test mode this signal is used as input and output test signal.
P32_INT0
30
I/O
PVDD
general purpose I/O signal. Can also be used as an interrupt source
In test mode this signal is used as input and output test signal.
P33_INT1
31
I/O
PVDD
general purpose I/O signal. Can be used to generate an HZ state on the output of the selected interface for the Host communication and to enter into
power-down mode without resetting the internal state of PR533.
P50_SCL
32
I/O
DVDD
I2C-bus clock line - open-drain in output mode
SDA
33
I/O
DVDD
I2C-bus data line - open-drain in output mode
P34
34
I/O
SVDD
general purpose I/O signal or clock signal for the SAM
SIGOUT
35
SVDD
contactless communication interface output: delivers a serial data stream
according to NFCIP-1 and output signal for the SAM.
In test mode this signal is used as input and output test signal.
In test mode this signal is used as test signal output.
SIGIN
36
SVDD
contactless communication interface input: accepts a digital, serial data
stream according to NFCIP-1 and input signal from the SAM.
In test mode this signal is used as test signal input.
SVDD
37
PR533_SDS
Product short data sheet
COMPANY PUBLIC
output power for SAM power supply. Switched on by Firmware with an overload detection. Used as a reference voltage for SAM communication.
All information provided in this document is subject to legal disclaimers.
Rev. 3.6 — 27 October 2014
206436
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PR533
NXP Semiconductors
USB NFC integrated reader solution
Table 3.
PR533 pin description …continued
Symbol
Pin
Type Pad ref
voltage
Description
RSTPD_N
38
reset and power-down: When LOW, internal current sources are switched off,
the oscillator is inhibited, and the input pads are disconnected from the outside world.
PVDD
With a negative edge on this pin the internal reset phase starts.
DVDD
39
digital power supply
VBUS
40
USB power supply.
[1]
Pin types: I= Input, O = Output, I/O = Input/Output, P = Power and G = Ground.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VDDA
VDDD
Conditions
Min
Max
Unit
analog supply voltage
0.5
+4
digital supply voltage
0.5
+4
VDD(TVDD)
TVDD supply voltage
0.5
+4
VDD(PVDD)
PVDD supply voltage
0.5
+4
VDD(SVDD)
SVDD supply voltage
0.5
+4
VBUS
bus supply voltage
0.5
+5.5
500
mW
30
mA
0.5
+4
Ptot
total power dissipation
IDD(SVDD)
SVDD supply current
maximum current in VDDS
switch
Vi
input voltage
TX1, TX2, RX pins
VESD
electrostatic discharge voltage
HBM
[1]
2.0
kV
MM
[2]
200
CDM
[3]
1
kV
55
+150
C
C
storage temperature
Tstg
Tj
junction temperature
40
+125
Vi(dyn)(RX)
dynamic input voltage on pin RX
input signal at 13.56 MHz
0.7
VDD(AVDD) + 1.0 V
Vi(dyn)(TX1)
dynamic input voltage on pin TX1
input signal at 13.56 MHz
1.2
VDD(TVDD) + 1.3 V
Vi(dyn)(TX2)
dynamic input voltage on pin TX2
input signal at 13.56 MHz
1.2
VDD(TVDD) + 1.3 V
ITX1
current on pin TX1
output signal at 13.56 MHz
300
+300
mA
ITX2
current on pin TX2
output signal at 13.56 MHz
300
+300
mA
[1]
1500 , 100 pF; EIA/JESD22-A114-A
[2]
0.75 mH, 200 pF; EIA/JESD22-A115-A
[3]
Field induced model; EIA/JESC22-C101-C
PR533_SDS
Product short data sheet
COMPANY PUBLIC
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Rev. 3.6 — 27 October 2014
206436
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PR533
NXP Semiconductors
USB NFC integrated reader solution
8. Recommended operating conditions
Table 5.
Operating conditions
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VBUS
bus supply voltage
VSSA = VSSD = VSS(PVSS) = VSS(TVSS) = 0 V
4.02
5.25
supply voltage (non-USB mode); VBUS = VDDD;
VSSA = VSSD = VSS(PVSS) = VSS(TVSS) = 0 V
2.5
3.3
3.6
VDDA
analog supply voltage
VDDA = VDDD = VDD(TVDD) = VDD(PVDD);
VSSA = VSSD = VSS(PVSS) = VSS(TVSS) = 0 V
[1][2]
2.5
3.3
3.6
VDDD
digital supply voltage
VDDA = VDDD = VDD(TVDD) = VDD(PVDD);
VSSA = VSSD = VSS(PVSS) = VSS(TVSS) = 0 V
[1][2]
2.5
3.3
3.6
VDD(TVDD) TVDD supply voltage
VDDA = VDDD = VDD(TVDD) = VDD(PVDD);
VSSA = VSSD = VSS(PVSS) = VSS(TVSS) = 0 V
[1][2]
2.5
3.3
3.6
VDD(PVDD) PVDD supply voltage
supply pad for host interface;
VDDA = VDDD = VDD(TVDD) = VDD(PVDD);
VSSA = VSSD = VSS(PVSS) = VSS(TVSS) = 0 V
[2]
1.6
1.8 to 3.3 3.6
30
+25
C
Tamb
ambient temperature
[1]
VSSA, VDDD and VDD(TVDD) shall always be on the same voltage level.
[2]
Supply voltages below 3 V reduces the performance (e.g. the achievable operating distance).
+85
9. Thermal characteristics
Table 6.
Thermal characteristics
Symbol Parameter
Rth(j-a)
thermal resistance from
junction to ambient
Conditions
Min Typ Max Unit
in free air with exposed pad
soldered on a 4 layer Jedec
PCB-0.5
37
41.1 K/W
10. Characteristics
Unless otherwise specified, the limits are given for the full operating conditions. The
typical value is given for 25 C, VDDD = 3.4 V and VDD(PVDD) = 3 V in non-USB bus power
mode, VBUS = 5 V in USB power mode.
Timings are only given from characterization results.
10.1 Power management characteristics
10.1.1 Current consumption characteristics
Typical value using a complementary driver configuration and an antenna matched to
40  between TX1 and TX2 at 13.56 MHz.
PR533_SDS
Product short data sheet
COMPANY PUBLIC
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PR533
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USB NFC integrated reader solution
Table 7.
Current consumption characteristics
Symbol
Parameter
Conditions
Min
Ipd
power-down current
VDDA = VDDD = VDD(TVDD) = VDD(PVDD) = 3 V; not powered from USB
1.3
10
A
soft power-down current; not powered
from USB; RF level detector on
[1]
30
A
[1]
120
250
A
12
mA
mA
VBUS = 5 V; VDDA = VDDD = VDD(TVDD) =
VDD(PVDD) = 3 V; VDDS = 0 V; RF level
detector on (without resistor on pin DP
(D+))
IDDD
digital supply current
VDDA = VDDD = VDD(TVDD) = VDD(PVDD)
= 3 V; RF level detector on
IDDA
analog supply current
VDDA = VDDD = VDD(TVDD) = VDD(PVDD) = 3 V
RF level detector on
RF level detector off
IDD(SVDD)
SVDD supply current
sam_switch_en set to 1
TVDD supply current
IDD(TVDD)
Unit
[1]
suspended low-power device
supply current
PVDD supply current
Max
hard power-down current; not powered
from USB; RF level detector off
ICCSL
IDD(PVDD)
Typ
continuous wave; VDD(TVDD) = 3 V
[1]
Ipd is the total currents over all supplies.
[2]
IDD(PVDD) depends on the overall load at the digital pins.
[3]
IDD(SVDD) depends on the overall load on VDD(SVDD) pad.
[4]
IDD(TVDD) depends on VDD(TVDD) and the external circuitry connected to TX1 and TX2.
[5]
During operation with a typical circuitry the overall current is below 100 mA.
1.5
mA
[2]
30
mA
[3]
30
mA
[4][5]
60
100
mA
10.1.2 Voltage regulator characteristics
Table 8.
Voltage regulator characteristics[1]
Symbol
Parameter
Conditions
Min
VBUS
bus supply voltage
USB mode; VSS = 0 V
4.02 5
5.25 V
VDDD
digital supply voltage
after inrush current limitation (USB
mode); from IVDDD = 0 mA to
IVDDD = 150 mA
2.95 3.3
3.6
IBUS
bus supply current
USB mode; measure on VBUS
150
mA
Iinrush(lim)
inrush current limit
at power-up (curlimofff = 0)
100
mA
Vth(rst)reg
regulator reset threshold voltage
regulator reset
1.90 2.15 2.40 V
Vth(rst)reg(hys)
regulator reset threshold voltage
hysteresis
35
60
85
mV
VDDD decoupling capacitor
10
F
[1]
Typ
Max Unit
The internal regulator is only enabled when the USB interface is selected by I0 and I1.
10.2 Antenna presence self test thresholds
The values in Table 9 are guaranteed by design. Only functional is done in production for
cases andet_ithl[1:0] = 10b and for andet_ithh[2:0] = 011b.
PR533_SDS
Product short data sheet
COMPANY PUBLIC
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Rev. 3.6 — 27 October 2014
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PR533
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USB NFC integrated reader solution
Table 9.
Antenna presence detection
Parameter
Conditions
Min
Typ
Max
Unit
IVDDD lower current threshold for antenna presence detection
andet_ithl[1:0]
00b
mA
01b
15
mA
10b
25
mA
11b
35
mA
IVDDD upper current threshold for antenna presence detection
andet_ithh[2:0]
PR533_SDS
Product short data sheet
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000b
45
mA
001b
60
mA
010b
75
mA
011b
90
mA
100b
105
mA
101b
120
mA
110b
135
mA
111b
150
mA
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10.3 Typical 27.12 MHz Crystal requirements
Table 10.
Crystal requirements
Symbol Parameter
Conditions
Min
Typ
Max
Unit
fxtal
crystal frequency
27.107
27.12
27.133
MHz
ESR
equivalent series resistance
100

CL
load capacitance
10
pF
Pxtal
crystal power dissipation
100
W
10.4 Pin characteristics for 27.12 MHz XTAL Oscillator (OSCIN, OSCOUT)
Table 11.
Pin characteristics for 27.12 MHz XTAL Oscillator (OSCIN, OSCOUT)
Symbol
Parameter
Conditions
RSTPD_N = 0 V
Min
Typ
Max
Unit
ILI
input leakage current
1
+1
mA
VIH
HIGH-level input voltage
0.7  VDDA
VDDA
VIL
LOW-level input voltage
0.3  VDDA
VOH
HIGH-level output voltage
1.1
VOL
LOW-level output voltage
0.2
fclk
clock frequency
0.05 %
27.12
+0.05 %
MHz

duty cycle
n(th)
phase noise threshold
[1]
fn(th)
phase noise threshold fre- n(th) = 140dBc/Hz;
quency
20dB/decade slope
[1]
40
50
60
140
dBc/Hz
50
kHz
OSCIN
Vi
input voltage
DC
0.65
Ci
input capacitance
VDDA = 2.8 V; Vi (DC) = 0.65 V;
Vi (AC) = 1 V p-p
pF
pF
OSCOUT
Ci
[1]
input capacitance
n(th) and fn(th) define the mask for maximum acceptable phase noise of the clock signal at the OSCIN, OSCOUT inputs. See Figure 3
“27.12 MHz input clock phase noise spectrum mask”.
phase noise
(dBc/Hz)
-20 dB/decade
acceptable phase
noise area
φn(th)
fφn(th)
frequency (Hz)
001aao393
Fig 3.
PR533_SDS
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27.12 MHz input clock phase noise spectrum mask
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10.5 RSTPD_N input pin characteristics
Table 12.
RSTPD_N input pin characteristics
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VIH
HIGH-level input voltage
VDD(PVDD) 0.4 -
VDD(PVDD) V
VIL
LOW-level input voltage
0.4
IIH
HIGH-level input current
1
A
IIL
LOW-level input current VI = 0 V
1
A
Ci
input capacitance
2.5
pF
VI = VDD(PVDD)
10.6 Input pin characteristics for I0, I1 and TESTEN
PR533_SDS
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Table 13.
Input pin characteristics for I0, I1 and TESTEN
Symbol
Parameter
Conditions
Min
Typ Max
Unit
0.7  VDDD
VIH
HIGH-level input voltage
[1]
VIL
LOW-level input voltage
[2]
IIH
HIGH-level input current
I0 and I1;
VI = VDDD
[3]
1
IIL
LOW-level input current
VI = 0 V
Ci
input capacitance
VDDD
0.3  VDDD
A
1
A
2.5
pF
[1]
To minimize power consumption when in soft power-down mode, the limit is VDDD  0.4 V.
[2]
To minimize power consumption when in soft power-down mode, the limit is 0.4 V.
[3]
TESTEN should never be set to high level in the application. It is used for production test purpose only. It is
recommended to connect TESTEN to ground although there is a pull-down included.
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USB NFC integrated reader solution
10.7 RSTOUT_N output pin characteristics
Table 14.
RSTOUT_N output pin characteristics
Symbol Parameter
VOH
VOL
IOH
Conditions
Max
Unit
0.7  VDD(PVDD)
VDD(PVDD)
0.7  VDD(PVDD)
VDD(PVDD)
VDD(PVDD) = 3 V; IOH = 4 mA
LOW-level output
voltage
VDD(PVDD) = 3 V; IOL = 4 mA
0.3  VDD(PVDD) V
VDD(PVDD) = 1.8 V; IOL = 2 mA
[1]
0.3  VDD(PVDD) V
HIGH-level output
current
VDD(PVDD) = 3 V; VOH =
0.8  VDD(PVDD)
[2]
4
mA
2
mA
mA
mA
30
pF
LOW-level output
current
VDD(PVDD) = 1.8 V; IOH = 2 mA
VDD(PVDD) = 3 V; VOL =
0.2  VDD(PVDD)
VDD(PVDD) = 1.8 V; VOL =
0.3  VDD(PVDD)
CL
load capacitance
tr
rise time
tf
Typ
HIGH-level output
voltage
[1]
VDD(PVDD) = 1.8 V; VOH =
0.7  VDD(PVDD)
IOL
Min
fall time
[2]
VDD(PVDD) = 3 V;
VOH = 0.8  VDD(PVDD); CL = 30 pF
13.5
ns
VDDP = 1.8 V;
VOH = 0.7  VDD(PVDD); CL = 30 pF
10.8
ns
VDD(PVDD) = 3 V;
VOL = 0.2  VDD(PVDD); CL = 30 pF
13.5
ns
VDD(PVDD) = 1.8 V;
VOL = 0.3  VDD(PVDD); CL = 30 pF
10.8
ns
[1]
Data at VDD(PVDD) = 1.8V are only given from characterization results.
[2]
IOH and IOL give the output drive capability from which the rise and fall times may be calculated as a function of the load capacitance.
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10.8 Input/output characteristics for pin P70_IRQ
Table 15.
Input/output pin characteristics for pin P70_IRQ
Symbol Parameter
Conditions
VIH
HIGH-level input voltage
[1]
VIL
LOW-level input voltage
[2]
VOH
HIGH-level output voltage
push-pull mode;
VDD(PVDD) = 3 V; IOH = 4 mA
push-pull mode;
VDD(PVDD) = 1.8 V; IOH = -2 mA
VOL
LOW-level output voltage
[3]
push-pull mode;
VDD(PVDD) = 3 V; IOL = 4 mA
push-pull mode;
VDD(PVDD) = 1.8 V; IOL = 2 mA
IIH
HIGH-level input current input mode; VI = VDDD
IIL
LOW-level input current input mode; VI = 0 V
[3]
Min
Typ
Max
Unit
0.7  VDD(PVDD)
VDD(PVDD)
0.3  VDD(PVDD)
0.7  VDD(PVDD)
VDD(PVDD)
0.7  VDD(PVDD)
VDD(PVDD)
0.3  VDD(PVDD)
0.3  VDD(PVDD)
1
A
1
A
4
mA
mA
1
A
IOH
HIGH-level output current
VDD(PVDD) = 3 V;
VOH = 0.8  VDD(PVDD)
[5]
IOL
LOW-level output current
VDD(PVDD) = 3 V;
VOL = 0.2  VDD(PVDD)
[5]
ILI
input leakage current
RSTPD_N = 0.4 V
Ci
input capacitance
2.5
CL
load capacitance
30
pF
tr
rise time
VDD(PVDD) = 3 V;
VOH = 0.8  VDD(PVDD);
CL = 30 pF
13.5
ns
VDD(PVDD) = 1.8 V;
VOH = 0.7  VDD(PVDD);
CL = 30 pF
10.8
ns
VDD(PVDD) = 3 V;
VOL = 0.2  VDD(PVDD);
CL= 30 pF
13.5
ns
VDD(PVDD) = 1.8 V;
VOL = 0.3  VDD(PVDD);
CL = 30 pF
10.8
ns
tf
fall time
pF
[1]
To minimize power consumption when in soft power-down mode, the limit is VDD(PVDD)  0.4 V.
[2]
To minimize power consumption when in soft power-down mode, the limit is 0.4 V.
[3]
Data at VDD(PVDD) = 1.8 V are only given from characterization results.
[4]
The IOH and IOL give the output driving capability and allow to calculate directly the rise and fall time as function of the load capacitance.
PR533_SDS
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USB NFC integrated reader solution
10.9 Input/output pin characteristics for P30 / UART_RX, P31 / UART_TX,
P32_INT0, P33_INT1
Table 16.
Input/output pin characteristics for P30 / UART_RX, P31 / UART_TX, P32_INT0, P33_INT1
Symbol Parameter
Conditions
Min
VIH
HIGH-level input voltage
[1]
VIL
LOW-level input voltage
[2]
VOH
HIGH-level output voltage
push-pull mode;
VDD(PVDD) = 3 V;
IOH = 4 mA
VDD(PVDD) = 1.8 V;
IOH = 2 mA
LOW-level output voltage
VOL
[3]
push-pull mode;
VDD(PVDD) = 3 V;
IOL = 4 mA
VDD(PVDD) = 1.8 V;
IOL = 2 mA
IIH
HIGH-level input current
input mode;
VI = VDD(PVDD)
IIL
LOW-level input current
input mode; VI = 0 V
[3]
IOH
HIGH-level output current
VDD(PVDD) = 3 V;
VOH = 0.8  VDD(PVDD)
[4]
IOL
LOW-level output current VDD(PVDD) = 3 V;
VOL = 0.2  VDD(PVDD)
[4]
ILI
input leakage current
RSTPD_N = 0.4 V
Typ
Max
Unit
0.7  VDD(PVDD)
VDD(PVDD)
0.3  VDD(PVDD)
VDD(PVDD) 0.4
VDD(PVDD)
VDD(PVDD) 0.4
VDD(PVDD)
0.4
0.4
1
A
1
A
4
mA
mA
1
A
Ci
input capacitance
2.5
pF
CL
load capacitance
30
pF
tr
rise time
VDD(PVDD) = 3 V;
VOH = 0.8  VDD(PVDD);
CL = 30 pF
13.5
ns
VDD(PVDD) = 1.8 V;
VOH = 0.7  VDD(PVDD);
CL = 30 pF
10.8
ns
VDD(PVDD) = 3 V;
VOL = 0.2  VDD(PVDD);
CL= 30 pF
13.5
ns
VDD(PVDD) = 1.8 V;
VOL = 0.3  VDD(PVDD);
CL = 30 pF
10.8
ns
tf
fall time
[1]
To minimize power consumption when in soft power-down mode, the limit is VDD(PVDD)  0.4 V.
[2]
To minimize power consumption when in soft power-down mode, the limit is 0.4 V
[3]
Data at VDD(PVDD) = 1.8 V are only given from characterization results.
[4]
The IOH and IOL give the output driving capability and allow to calculate directly the rise and fall time as function of the load capacitance.
PR533_SDS
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10.10 Input/output pin characteristics for P35
Table 17.
Input/output pin characteristics for P35
Symbol Parameter
Min
Typ
Max
Unit
HIGH-level input voltage
[1]
0.7  VDDD
VDDD
VIL
LOW-level input voltage
[2]
0.3  VDDD
VOH
HIGH-level output voltage
VDDD  0.4
VDDD
VOL
LOW-level output voltage VDDD = 3 V; IOL = 4 mA
0.4
IIH
HIGH-level input current
VI = VDDD
1
A
IIL
LOW-level input current
VI = 0 V
1
A
IOH
HIGH-level output current VDDD = 3 V;
VOH = 0.8  VDD(PVDD)
[3]
4
mA
IOL
LOW-level output current VDDD = 3 V;
VOL = 0.2  VDD(PVDD)
[3]
mA
ILI
input leakage current
1
A
Ci
input capacitance
2.5
pF
CL
load capacitance
30
pF
tr
rise time
VDDD = 3 V; VOH = 0.8  VDDD;
CL = 30 pF
13.5
ns
VDDD = 1.8 V; VOH = 0.7  VDDD;
CL = 30 pF
10.8
ns
VDDD = 3 V; VOL = 0.2  VDDD;
CL= 30 pF
13.5
ns
VDDD = 1.8 V; VOL = 0.3  VDDD;
CL = 30 pF
10.8
ns
VIH
tf
fall time
Conditions
VDDD = 3 V; IOH = 4 mA
RSTPD_N = 0.4 V
[1]
To minimize power consumption when in soft power-down mode, the limit is VDDD  0.4 V.
[2]
To minimize power consumption when in soft power-down mode, the limit is 0.4 V.
[3]
The IOH and IOL give the output driving capability and allow to calculate directly the rise and fall time as function of the load capacitance.
PR533_SDS
Product short data sheet
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USB NFC integrated reader solution
10.11 Input/output pin characteristics for DP and DM
Table 18.
Input/output pin characteristics for DP and DM for USB interface
Symbol Parameter
Conditions
HIGH-level input voltage
VIH
VDD(PVDD) = 3.3 V
[1]
Min
Typ
Max
Unit
3.6
0.8
VIL
LOW-level input voltage
VOH
HIGH-level output voltage
VDD(PVDD) = 3.3 V;
RPD = 1.5  to VSS
2.8
VDD(PVDD) V
VOL
LOW-level output voltage
VDD(PVDD) = 3.3 V;
RPD = 1.5  to VDD(PVDD)
0.3
IOH
HIGH-level output current
VDD(PVDD) = 3.3 V;
VOH = 0.8  VDD(PVDD)
4
mA
2
mA
mA
mA
[2]
VDD(PVDD) = 1.8 V;
VOH = 0.7  VDD(PVDD)
LOW-level output current
IOL
VDD(PVDD) = 3.3 V;
VOL = 0.2  VDD(PVDD)
[2]
VDD(PVDD) = 1.8 V;
VOL = 0.3  VDD(PVDD)
IIH
HIGH-level input current
VI = VDD(PVDD)
A
IIL
LOW-level input current
VI = 0 V
A
ILI
input leakage current
RSTPD_N = 0 V
1
+1
A
Ci
input capacitance
2.5
3.5
pF
ZINP
input impedance exclusive of
pull-up/pull-down (for low-/full
speed)
300
k
ZDRV
driver output impedance for driver
which is not high-speed capable
28
44

tFDRATE
full-speed data rate for devices
which are not high-speed capable
11.97
12.03
Mb/s
tDJ1
source jitter total (including frequency tolerance) to next transition
3.5
+3.5
ns
tDJ2
source jitter total (including frequency tolerance) for paired transitions
4
+4
ns
tFDEOP
source jitter for differential transition
to SE0 transition
2
+5
ns
tJR1
receiver jitter to next transition
18.5
+18.5
ns
tJR2
receiver jitter for paired transitions
9
+9
ns
tFEOPT
source SE0 interval of EOP
160
175
ns
tFEOPR
receiver SE0 interval of EOP
82
ns
tFST
width of SE0 interval during differential transition
14
ns
[1]
The value does not guarantee the power-down consumptions. To reach the specified power-down consumptions, the limit is 0.4 V.
[2]
The IOH and IOL give the output driving capability and allow to calculate directly the rise and fall time as function of the load capacitance.
PR533_SDS
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USB NFC integrated reader solution
Table 19.
USB DP/DM differential receiver input levels
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDI
differential input sensitivity voltage
0.2
VCM
differential common
mode voltage range
0.8
2.5
Table 20.
USB DP/DM driver characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tr
rise time
CL = 50 pF;
10 % to 90 %
of (VOH - VOL)
20
ns
tf
fall time
CL = 50 pF;
10 % to 90 %
of (VOH - VOL)
20
ns
tFRFM
differential rise and
fall time matching
(tFR/tFF); excluding
the first transition
from Idle state
90
111.1
VCRS
output signal crossover voltage
excluding the first
transition from Idle
state
1.3
2.0
level 1
+400 mV differential
point 3
point 4
point 1
point 2
point 5
0 V differential
point 6
-400 mV differential
level 2
0%
unit interval
100 %
001aan914
Fig 4. Transmit waveform at DP/DM
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Table 21.
Input Pin characteristics for DP for HSU interface
Symbol
Parameter
VIH
Conditions
HIGH-level input voltage
[1]
[2]
Min
Typ
Max
Unit
0.7  VDD(PVDD)
VDD(PVDD)
VIL
LOW-level input voltage
0.3  VDD(PVDD) V
IIH
HIGH-level input current
Vi = VDD(PVDD)
mA
IIL
LOW-level input current
Vi = 0 V
mA
ILI
input leakage current
RSTPD_N = 0 V
1
mA
Ci
input capacitance
3.5
pF
2.5
[1]
The value does not guarantee the power-down consumptions. To reach the specified power-down consumptions, the limit is
VDD(PVDD)  0.4 V.
[2]
The value does not guarantee the power-down consumptions. To reach the specified power-down consumptions, the limit is 0.4 V.
Table 22.
Output Pin characteristics for DM for HSU interface
Symbol
Parameter
Conditions
Min
Max
Unit
VOH
HIGH-level output
voltage
VDD(PVDD) = 3 V; IOH = 4 mA
VDD(PVDD)  0.4 -
VDD(PVDD)
VDD(PVDD) = 1.8 V; IOH = 2 mA
VDD(PVDD)  0.4 -
VDD(PVDD)
0.4
VOL
LOW-level output volt- VDD(PVDD) = 3 V; IOL = 4 mA
age
VDD(PVDD) = 1.8 V; IOL = 2 mA
IOH
HIGH-level output
current
0.4
mA
2
mA
mA
VDD(PVDD) = 1.8 V;
VOL = 0.3  VDD(PVDD)
mA
RSTPD_N = 0 V
1
mA
30
pF
VDDP = 3 V;
VOH = 0.8  VDD(PVDD);
CL = 30 pF
13.5
ns
VDD(PVDD) = 1.8 V;
VOH = 0.7  VDD(PVDD);
CL = 30 pF
10.8
ns
VDD(PVDD) = 3 V;
VOL = 0.2  VDD(PVDD);
CL= 30 pF
13.5
ns
VDDP = 1.8 V;
VOL = 0.3  VDD(PVDD);
CL = 30 pF
10.8
ns
LOW-level output cur- VDD(PVDD) = 3.3 V;
rent
VOL = 0.2  VDD(PVDD)
ILI
input leakage current
CL
load capacitance
tr
rise time
fall time
tf
[1]
4
VDD(PVDD) = 3 V;
VOH = 0.8  VDD(PVDD)
[1]
VDD(PVDD) = 1.8 V;
VOH = 0.7  VDD(PVDD)
IOL
Typ
[1]
The IOH and IOL give the output driving capability and allow to calculate directly the rise and fall time as function of the load capacitance
PR533_SDS
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USB NFC integrated reader solution
10.12 Input pin characteristics for SCL
Table 23.
Input/output drain output pin characteristics for SCL I2C interface
Symbol Parameter
Conditions
Min
Max
Unit
0.7  VDD(PVDD) -
VDDD
0.3  VDDD V
VDDD = 3 V;
IOL = 4 mA
0.3
HIGH-level input current
VI = VDDD
1
A
LOW-level input current
VI = 0 V
1
A
RSTPD_N = 0.4 V
1
A
2.5
HIGH-level input voltage
[1]
VIL
LOW-level input voltage
[2]
VOL
LOW-level output voltage
IIH
IIL
VIH
ILI
input leakage current
Ci
input capacitance
CL
load capacitance
tr
tf
Typ
pF
30
pF
rise time of both SDA and SCL signals
[3]
20
300
ns
fall time of both SDA and SCL signals
[3]
20
300
ns
[1]
To minimize power consumption when in soft power-down mode, the limit is VDDD  0.4 V.
[2]
To minimize power consumption when in soft power-down mode, the limit is 0.4 V.
[3]
The PR533 has a slope control according to the I2C-bus specification for the Fast mode. The slope control is always present and not
dependent of the I2C-bus speed.
10.13 Input/output pin characteristics for SDA
Table 24.
Input/output drain output pin characteristics for SDA I2C interface
Symbol Parameter
VIH
Conditions
Min
HIGH-level input voltage
[1]
[2]
Typ
0.7  VDD(PVDD) -
Max
Unit
VDDD
VIL
LOW-level input voltage
0.3  VDDD V
VOL
LOW-level output voltage
VDDD = 3 V;
IOL = 4 mA
0.3
IIH
HIGH-level input current
VI = VDDD
1
A
IIL
LOW-level input current
VI = 0 V
1
A
ILI
input leakage current
RSTPD_N = 0.4 V
1
A
Ci
input capacitance
2.5
CL
load capacitance
tr
rise time of both SDA and SCL signals
[3]
tf
fall time of both SDA and SCL signals
[3]
[1]
pF
30
pF
20
300
ns
20
300
ns
To minimize power consumption when in soft power-down mode, the limit is VDDD  0.4 V.
[2]
To minimize power consumption when in soft power-down mode, the limit is 0.4 V.
[3]
The PR533 has a slope control according to the I2C-bus specification for the Fast mode. The slope control is always present and not
dependent of the I2C-bus speed.
PR533_SDS
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USB NFC integrated reader solution
10.14 Output pin characteristics for DELATT
Table 25.
Output pin characteristics for DELATT
Symbol Parameter
VOH
HIGH-level output voltage
VIL
LOW-level input voltage
Conditions
[1]
Min
Typ
Max
Unit
0.7  VDD(SVDD)
VDD(SVDD)
0.3  VDD(PVDD)
IIH
HIGH-level input current
input mode; VI = VDD(SVDD)
1
A
IIL
LOW-level input current
input mode; VI = 0 V
1
A
ILI
input leakage current
RSTPD_N = 0.4 V
1
A
Ci
input capacitance
2.5
pF
Typ
Max
Unit
[1]
To minimize power consumption when in soft power-down mode, the limit is VDD(PVDD)  0.4 V.
10.15 Input pin characteristics for SIGIN
Table 26.
Input/output pin characteristics for SIGIN
Symbol Parameter
Conditions
Min
0.7  VDD(SVDD)
VDD(SVDD)
0.3  VDD(SVDD)
VIH
HIGH-level input voltage
[1]
VIL
LOW-level input voltage
[2]
IIH
HIGH-level input current
VI = VDD(SVDD)
1
+1
A
IIL
LOW-level input current
VI = 0 V
1
+1
A
ILI
input leakage current
RSTPD_N = 0.4 V
1
+1
A
Ci
input capacitance
2.5
pF
[1]
To minimize power consumption when in soft power-down mode, the limit is VDD(SVDD)  0.4 V.
[2]
To minimize power consumption when in soft power-down mode, the limit is 0.4 V.
10.16 Output pin characteristics for SIGOUT
Table 27.
Output pin characteristics for SIGOUT
Symbol Parameter
Conditions
Min
Typ Max
Unit
VOH
HIGH-level output voltage
VDDD  0.1 < VDD(SVDD) < VDDD
IOH = 4 mA
VDD(SVDD)  0.4
VDD(SVDD)
VOL
LOW-level output voltage
VDDD  0.1 < VDD(SVDD) < VDDD
IOL = +4 mA
0.4
IOH
HIGH-level output current
VDDD  0.1 < VDD(SVDD) < VDDD
IOH = 4 mA
0.4
mA
IOL
LOW-level output current
VDDD  0.1 < VDD(SVDD) < VDDD
IOL = +4 mA
mA
RSTPD_N = 0.4 V
+1
ILI
input leakage current
1
Ci
input capacitance
2.5
CL
load capacitance
30
pF
tr
rise time
VDD(SVDD) = 3 V;
VOH = 0.8  VDD(SVDD); Cout = 30 pF
ns
tf
fall time
VDD(SVDD) = 3 V;
VOL = 0.2  VDD(SVDD); Cout = 30 pF
ns
PR533_SDS
Product short data sheet
COMPANY PUBLIC
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A
pF
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USB NFC integrated reader solution
10.17 Input/output pin characteristics for P34
Table 28.
Input/output pin characteristics for P34
Symbol Parameter
Conditions
Min
Typ
Max
Unit
0.7  VDD(SVDD) -
VDD(SVDD)
0.3  VDD(SVDD) V
HIGH-level input voltage
[1]
VIL
LOW-level input voltage
[2]
VOH
HIGH-level output voltage
push-pull;
VDDD  0.1 < VDD(SVDD) < VDDD
IOH = 4 mA
VDD(SVDD)  0.4 -
VDD(SVDD)
VOL
LOW-level output voltage
push-pull;
VDDD  0.1 < VDD(SVDD) < VDDD
IOH = +4 mA
0.4
IIH
HIGH-level input current input mode; VI = VDD(SVDD)
1
+1
A
IIL
LOW-level input current
input mode; VI = 0 V
1
+1
A
VOH
HIGH-level output voltage
VDDD  0.1 < VDD(SVDD) < VDDD
IOH = 4 mA
0.4
VOL
LOW-level output voltage
VDDD  0.1 < VDD(SVDD) < VDDD
IOL = +4 mA
ILI
input leakage current
RSTPD_N = 0.4 V
1
+1
A
Ci
input capacitance
2.5
CL
load capacitance
VIH
tr
rise time
VDDD = 0.1 < VDDD
VOH = 0.8  VDD(SVDD);
Cout = 30 pF
[3]
tf
fall time
VDDD = 0.1 < VDDD
VOL = 0.2  VDD(SVDD);
Cout = 30 pF
[3]
pF
30
pF
13.5
ns
13.5
ns
[1]
To minimize power consumption when in soft power-down mode, the limit is VDD(SVDD)  0.4 V.
[2]
To minimize power consumption when in soft power-down mode, the limit is 0.4 V.
[3]
IOH and IOL specify the output drive capability from which the rise and fall times may be calculated as a function of the load capacitance.
10.18 Output pin characteristics for LOADMOD
Table 29.
PR533_SDS
Product short data sheet
COMPANY PUBLIC
Output pin characteristics for LOADMOD
Symbol
Parameter
Conditions
Min
VOH
HIGH-level output voltage
VDDD = 3 V;
IOH = 4 mA
VDDD  0.4 -
VDDD
VOL
LOW-level output voltage
VDDD = 3 V;
IOL = 4 mA
0.4
CL
load capacitance
10
pF
tr
rise time
VDDD = 3 V;
VOH = 0.8  VDDD;
Cout = 10 pF
4.5
ns
tf
fall time
VDDD = 3 V;
VOL  = 0.2  VDDD;
Cout = 10 pF
4.5
ns
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Unit
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10.19 Input pin characteristics for RX
Miller coded signals
Vin, RX
AVDD +1 V
mRXmil =
VRX, IV, mil - Vmod
VRX, IV, mil + Vmod
VRX, IV, mil
Vmod
VMID
13.56 MHz
carrier
0V
Manchester coded signals
Vin, RX
AVDD +1 V
VRXMod, Man
VRX, IV, Man
Vmod
VMID
13.56 MHz
carrier
0V
aaa-002342
Fig 5.
Table 30.
RX input parameters
Input pin characteristics for RX
Symbol
Parameter
Conditions
Min
Vi
input voltage
dynamic; signal
frequency at
13.56 MHz
0.7
10
RX input;
VDDA = 3 V;
receiver active;
VRX(p-p) = 1 V;
1.5 V DC offset
315
350 385
Ci
input capacitance
Rs
series resistance
Typ Max
Unit
VDDA +1 V
14
pF

Minimum dynamic input voltage
PR533_SDS
Product short data sheet
COMPANY PUBLIC
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Table 30.
Input pin characteristics for RX …continued
Symbol
Parameter
Conditions
Min
Typ Max
Unit
VRX(p-p)
peak-to-peak receiver
voltage
Miller coded;
106 kbit/s
150 500
mV
Manchester
coded; 212 kbit/s
and 424 kbit/s
100 200
mV
Miller coded;
106 kbit/s
VDDA
Manchester
coded;
212 and 424 kbit/s
VDDA
Maximum dynamic input voltage
VRX(p-p)
peak-to-peak receiver
voltage
Minimum modulation voltage
Vmod
modulation voltage
RxGain = 6 and 7
[1]
mV
RxGain = 4 and 5
[1]
18
mV
RxGain = 0 to 3
[1]
120
mV
33
Minimum modulation index
[1]
modulation index
Miller coded;
106 kbit/s
VRX(p-p)= 1.5 V;
SensMiller = 3
The minimum modulation voltage is valid for all modulation schemes except Miller coded signals.
10.20 Output pin characteristics for AUX1/AUX2
Table 31.
PR533_SDS
Product short data sheet
COMPANY PUBLIC
Output pin characteristics for AUX1/AUX2
Symbol
Parameter
Conditions
Min
Typ Max
Unit
VOH
HIGH-level output voltage
VDDD = 3 V;
IOH = 4 mA
VDDD  0.4
VDDD
VOL
LOW-level output voltage
VDDD = 3 V;
IOL = 4 mA
VSSD
VSSD +0.4
IOH
HIGH-level output current
VDDD= 3 V; VOH =
VDDD 0.3
4
mA
IOL
LOW-level output current
VDDD= 3 V; VOL =
VDDD -0.3
mA
ILI
input leakage current
RSTPD_N = 0 V
1
+1
A
Ci
input capacitance
2.5
pF
CL
load capacitance
15
pF
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10.21 Output pin characteristics for TX1/TX2
Table 32.
Output pin characteristics for TX1/TX2
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VOH
HIGH-level output voltage
VDD(TVDD) = 3 V;
IO = 32 mA; CWGsN = Fh
150
mV
VDD(TVDD) = 3 V;
IO = 80 mA; CWGsN = Fh
400
mV
VDD(TVDD) = 2.5 V;
IO = 32 mA; CWGsN = Fh
240
mV
VDD(TVDD) = 2.5 V;
IO = 80 mA; CWGsN = Fh
640
mV
Typ
Max
Unit
VOL
Table 33.
LOW-level output voltage
Output resistance for TX1/TX2
Symbol Parameter
ROH
ROL
PR533_SDS
Product short data sheet
COMPANY PUBLIC
HIGH-level output resistance
Conditions1
CWGsP
VDD(TVDD) = 3 V; VO =
VDD(TVDD)  100 mV
01h
133
180
251

02h
67
90
125

04h
34
46
62

08h
17
23
31

LOW-level output
resistance
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Rev. 3.6 — 27 October 2014
206436
Min
10h
8.5
12
15.5

20h
4.7
7.8

3Fh
2.3
4.4

10h
34
46
62

20h
17
23
31

40h
8.5
12
15.5

80h
4.7
7.8

F0h
2.3
4.4

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10.22 System reset timing
Vth(rst)reg + Vth(rst)reg(hys)
VDD(PVDD)
Vth(rst)reg(hys)
RSTPD_N
trst
tw(rst)
tPOR
RSTOUT_N
001aao394
Fig 6. System reset overview
Table 34.
Reset duration time
Symbol
Parameter
tPOR
trst
tw(rst)
Min
Typ
Max
Unit
power-on reset time
[1]
0.1
0.4
ms
reset time
hard power-down time; user dependent
[2]
20
ns
reset time when RSTPD_N is released
[1]
0.1
0.4
ms
reset pulse width
Conditions
[1]
Dependent on the 27.12 MHz crystal oscillator startup time.
[2]
If the trst pulse is shorter than 20 ns, the device may be only partially reset.
PR533_SDS
Product short data sheet
COMPANY PUBLIC
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USB NFC integrated reader solution
10.23 Timing for the I2C-bus interface
SDA
tSU;DAT
tf
tSP
tf
tLOW
tr
tHD;STA
tBUF
SCL
tr
tHD;STA
tHIGH
tSU;STA
tHD;DAT
tSU;STO
Sr
001aaj635
Fig 7.
Table 35.
I2C-bus parameters
I2C-bus timing specification
Symbol
Parameter
fSCL
tHD;STA
Conditions
Min
Typ Max
Unit
SCL clock frequency
400
kHz
hold time (repeated) START condi- after this period, the
tion
first clock pulse is
generated
600
ns
tSU;STA
set-up time for a repeated START
condition
600
ns
tSU;STO
set-up time for STOP condition
600
ns
tLOW
LOW period of the SCL clock
P50_SCL
1300 -
ns
tHIGH
HIGH period of the SCL clock
P50_SCL
600
ns
tHD;DAT
data hold time
900
ns
tSU;DAT
data set-up time
tr
rise time of both SDA and SCL sig- P50_SCL
nals
[1]
tf
fall time of both SDA and SCL sig- P50_SCL
nals
[1]
tBUF
bus free time between a STOP
and START condition
tstretch
stretch time
stretching time on
P50_SCL when
woken-up on its
own address
th
hold time
internal for SDA
internal for SDA in
SPD mode
PR533_SDS
Product short data sheet
COMPANY PUBLIC
[2]
[3]
100
ns
20
300
ns
20
300
ns
1.3
ms
ms
330
590
ns
270 -
ns
[1]
The PR533 has a slope control according to the I2C-bus specification for the Fast mode. The slope control
is always present and not dependent of the I2C-bus speed.
[2]
27.12 MHz quartz starts in less than 800 s. For example, quartz like TAS-3225A, TAS-7 or KSS2F with
appropriate layout.
[3]
The PR533 has an internal hold time of around 270 ns for the SDA signal to bridge the undefined region of
the falling edge of P50_SCL.
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USB NFC integrated reader solution
10.24 Temperature sensor
Table 36.
Symbol
Tth(act)otp
[1]
PR533_SDS
Product short data sheet
COMPANY PUBLIC
Temperature sensor characteristics
Parameter
Conditions
overtemperature protection activation threshold temperature
CIU
[1]
Min
Typ Max
Unit
100
125 140
C
The temperature sensor embedded in the PR533 is not intended to monitor the temperature. Its purpose is
to prevent destruction of the IC due to excessive heat. The external application should include circuitry to
ensure that the ambient temperature does not exceed 85 C as specified in Table 5 “Operating conditions”.
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USB NFC integrated reader solution
11. Application information
interface supply
SVDD
RSDA
SIGOUT
RSCL
SDA
SECURE
CORE
SIGIN
l2C
MEMORY
P50_SCL
P34
CRX
RX
supply
R1
R2
VMID
VBUS
CVMID
DVDD
antenna
PR533
PVDD
HOST - PROCESSOR
TX1
C0
TVSS1
TVSS2
RTSPD_N
C1
L0
C0
host interface
TX2
P70_IRQ
L0
RQ
C2
C1
C2
RQ
TVDD
AVDD
DVSS
AVSS
OSCIN
OSCOUT
27.12 MHz
aaa-000042
Fig 8. Application diagram of PR533
12. Abbreviations
Table 37.
PR533_SDS
Product short data sheet
COMPANY PUBLIC
Abbreviations
Acronym
Description
CDM
Charge device Body Model
CRC
Cyclic Redundancy Check
EEPROM
Electrically Erasable Programmable Read-Only Memory
HBM
Human Body Model
HPD
Hard Power Down
MM
Machine Model
NFC
Near Field Communication
SPD
Soft Power Down mode
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13. Revision history
Table 38.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PR533_SDS v.3.6
20141027
Product short data sheet
PR533_SDS v.3.5
PR533_SDS v.3.4
PR533_SDS v.3.2
PR5331C3HN_SDS v.3.0
Modifications:
PR533_SDS
v.3.5[1]
Modifications:
PR533_SDS v.3.3
Modifications:
PR533_SDS v.3.2
Modifications:
•
Section 1.2 “Interfaces”: updated
20141003
•
•
•
Descriptive title updated.
Alternative descriptive title updated.
20121020
•
Product short data sheet
Section 4 “Ordering information”: updated
General update to comply full data sheet
PR5331C3HN_SDS v.3.0 20110803
[1]
Product short data sheet
Section 14.4 “Licenses”: updated
20120306
•
•
Product short data sheet
Template updated.
Product short data sheet
Revision 3.4 is not available.
PR533_SDS
Product short data sheet
COMPANY PUBLIC
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14. Legal information
14.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
14.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
14.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
PR533_SDS
Product short data sheet
COMPANY PUBLIC
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
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Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
14.4 Licenses
Purchase of NXP ICs with ISO/IEC 14443 type B functionality
This NXP Semiconductors IC is ISO/IEC 14443 Type B
software enabled and is licensed under Innovatron’s
Contactless Card patents license for ISO/IEC 14443 B.
The license includes the right to use the IC in systems
and/or end-user equipment.
RATP/Innovatron
Technology
Purchase of NXP ICs with NFC technology
Purchase of an NXP Semiconductors IC that complies with one of the Near
Field Communication (NFC) standards ISO/IEC 18092 and ISO/IEC 21481
does not convey an implied license under any patent right infringed by
implementation of any of those standards.
14.5 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
MIFARE — is a trademark of NXP Semiconductors N.V.
I2C-bus — logo is a trademark of NXP Semiconductors N.V.
15. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
PR533_SDS
Product short data sheet
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.6 — 27 October 2014
206436
© NXP Semiconductors N.V. 2014. All rights reserved.
32 of 36
PR533
NXP Semiconductors
USB NFC integrated reader solution
Notes
PR533_SDS
Product short data sheet
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.6 — 27 October 2014
206436
© NXP Semiconductors N.V. 2014. All rights reserved.
33 of 36
PR533
NXP Semiconductors
USB NFC integrated reader solution
16. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Quick reference data . . . . . . . . . . . . . . . . . . . . .3
Ordering information . . . . . . . . . . . . . . . . . . . . .4
PR533 pin description . . . . . . . . . . . . . . . . . . . .5
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . .7
Operating conditions . . . . . . . . . . . . . . . . . . . . .8
Thermal characteristics . . . . . . . . . . . . . . . . . . .8
Current consumption characteristics . . . . . . . . .9
Voltage regulator characteristics[1] . . . . . . . . . . .9
Antenna presence detection . . . . . . . . . . . . . . .10
Crystal requirements. . . . . . . . . . . . . . . . . . . . . 11
Pin characteristics for 27.12 MHz XTAL
Oscillator (OSCIN, OSCOUT). . . . . . . . . . . . . . 11
RSTPD_N input pin characteristics . . . . . . . . .12
Input pin characteristics for I0, I1 and
TESTEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
RSTOUT_N output pin characteristics . . . . . . .13
Input/output pin characteristics for
pin P70_IRQ . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Input/output pin characteristics for P30 /
UART_RX, P31 / UART_TX, P32_INT0,
P33_INT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Input/output pin characteristics for P35 . . . . . .16
Input/output pin characteristics for DP
and DM for USB interface. . . . . . . . . . . . . . . . .17
USB DP/DM differential receiver input levels . .18
USB DP/DM driver characteristics . . . . . . . . . .18
Input Pin characteristics for DP for HSU
interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Output Pin characteristics for DM for HSU
interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Input/output drain output pin characteristics
for SCL I2C interface. . . . . . . . . . . . . . . . . . . . .20
Input/output drain output pin characteristics
for SDA I2C interface . . . . . . . . . . . . . . . . . . . .20
Output pin characteristics for DELATT . . . . . . .21
Input/output pin characteristics for SIGIN . . . . .21
Output pin characteristics for SIGOUT . . . . . . .21
Input/output pin characteristics for P34 . . . . . .22
Output pin characteristics for LOADMOD . . . .22
Input pin characteristics for RX . . . . . . . . . . . .23
Output pin characteristics for AUX1/AUX2 . . .24
Output pin characteristics for TX1/TX2. . . . . . .25
Output resistance for TX1/TX2 . . . . . . . . . . . . .25
Reset duration time . . . . . . . . . . . . . . . . . . . . .26
I2C-bus timing specification . . . . . . . . . . . . . . .27
Temperature sensor characteristics . . . . . . . . .28
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .29
Revision history . . . . . . . . . . . . . . . . . . . . . . . .30
PR533_SDS
Product short data sheet
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.6 — 27 October 2014
206436
© NXP Semiconductors N.V. 2014. All rights reserved.
34 of 36
PR533
NXP Semiconductors
USB NFC integrated reader solution
17. Figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Pin configuration for HVQFN 40 (SOT618-1) . . . .5
27.12 MHz input clock phase noise spectrum
mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Transmit waveform at DP/DM . . . . . . . . . . . . . . .18
RX input parameters . . . . . . . . . . . . . . . . . . . . . .23
System reset overview. . . . . . . . . . . . . . . . . . . . .26
I2C-bus parameters . . . . . . . . . . . . . . . . . . . . . . .27
Application diagram of PR533 . . . . . . . . . . . . . . .29
PR533_SDS
Product short data sheet
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.6 — 27 October 2014
206436
© NXP Semiconductors N.V. 2014. All rights reserved.
35 of 36
PR533
NXP Semiconductors
USB NFC integrated reader solution
18. Contents
1.1
1.2
1.3
1.4
6.1
6.2
10
10.1
10.1.1
10.1.2
10.2
10.3
10.4
10.5
10.6
10.7
10.8
10.9
10.10
10.11
10.12
10.13
10.14
10.15
10.16
10.17
10.18
10.19
10.20
10.21
10.22
10.23
10.24
General description . . . . . . . . . . . . . . . . . . . . . . 1
RF protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Standards compliancy. . . . . . . . . . . . . . . . . . . . 1
Supported operating systems . . . . . . . . . . . . . . 2
Features and benefits . . . . . . . . . . . . . . . . . . . . 2
Quick reference data . . . . . . . . . . . . . . . . . . . . . 3
Ordering information . . . . . . . . . . . . . . . . . . . . . 4
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pinning information . . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7
Recommended operating conditions. . . . . . . . 8
Thermal characteristics . . . . . . . . . . . . . . . . . . 8
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power management characteristics . . . . . . . . . 8
Current consumption characteristics . . . . . . . . 8
Voltage regulator characteristics. . . . . . . . . . . . 9
Antenna presence self test thresholds . . . . . . . 9
Typical 27.12 MHz Crystal requirements . . . . 11
Pin characteristics for 27.12 MHz XTAL
Oscillator (OSCIN, OSCOUT). . . . . . . . . . . . . 11
RSTPD_N input pin characteristics . . . . . . . . 12
Input pin characteristics for I0, I1 and
TESTEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
RSTOUT_N output pin characteristics . . . . . . 13
Input/output characteristics for pin P70_IRQ . 14
Input/output pin characteristics for P30 /
UART_RX, P31 / UART_TX, P32_INT0,
P33_INT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Input/output pin characteristics for P35 . . . . . 16
Input/output pin characteristics for DP and DM 17
Input pin characteristics for SCL. . . . . . . . . . . 20
Input/output pin characteristics for SDA . . . . . 20
Output pin characteristics for DELATT . . . . . . 21
Input pin characteristics for SIGIN . . . . . . . . . 21
Output pin characteristics for SIGOUT . . . . . . 21
Input/output pin characteristics for P34 . . . . . 22
Output pin characteristics for LOADMOD. . . . 22
Input pin characteristics for RX. . . . . . . . . . . . 23
Output pin characteristics for AUX1/AUX2 . . . 24
Output pin characteristics for TX1/TX2. . . . . . 25
System reset timing . . . . . . . . . . . . . . . . . . . . 26
Timing for the I2C-bus interface . . . . . . . . . . . 27
Temperature sensor . . . . . . . . . . . . . . . . . . . . 28
11
12
13
14
14.1
14.2
14.3
14.4
14.5
15
16
17
18
Application information . . . . . . . . . . . . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
Licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29
29
30
31
31
31
31
32
32
32
34
35
36
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2014.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 27 October 2014
206436

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