Globalscale Technologies GTIMW302 GTI MW302 Module User Manual 88MW300 302 Datasheet

Globalscale Technologies INC GTI MW302 Module 88MW300 302 Datasheet

User manual

xam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & ConMARVELL CONFIDENTIAL, UNDER NDA# 12150208m1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & Control InMARVELL CONFIDENTIAL, UNDER NDA# 121502082fdrxam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global NetDoc. No. MV-S109936-00, Rev. AFebruary 3, 2015, 1.00CONFIDENTIALDocument Classification: ProprietaryCover88MW300/302WLAN MicrocontrollerIEEE 802.11n/g/bDatasheet
xam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & ConMARVELL CONFIDENTIAL, UNDER NDA# 12150208m1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & Control InMARVELL CONFIDENTIAL, UNDER NDA# 121502082fdrxam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Net Document Conventions Note: Provides related information or information of special importance. Caution: Indicates potential damage to hardware or software, or loss of data. Warning: Indicates a risk of personal injury.Document StatusDoc Status: 1.00 Technical Publication: 0.xx For more information, visit our website at: http://www.marvell.comDisclaimerNo part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, for any purpose, without the express written permission of Marvell. Marvell retains the right to make changes to this document at any time, without notice. Marvell makes no warranty of any kind, expressed or implied, with regard to any information contained in this document, including, but not limited to, the implied warranties of merchantability or fitness for any particular purpose. Further, Marvell does not warrant the accuracy or completeness of the information, text, graphics, or other items contained within this document. Marvell products are not designed for use in life-support equipment or applications that would cause a life-threatening situation if any such products failed. Do not use Marvell products in these types of equipment or applications. With respect to the products described herein, the user or recipient, in the absence of appropriate U.S. government authorization, agrees: 1) Not to re-export or release any such information consisting of technology, software or source code controlled for national security reasons by the U.S. Export Control Regulations ("EAR"), to a national of EAR Country Groups D:1 or E:2; 2) Not to export the direct product of such technology or such software, to EAR Country Groups D:1 or E:2, if such technology or software and direct products thereof are controlled for national security reasons by the EAR; and, 3) In the case of technology controlled for national security reasons under the EAR where the direct product of the technology is a complete plant or component of a plant, not to export to EAR Country Groups D:1 or E:2 the direct product of the plant or major component thereof, if such direct product is controlled for national security reasons by the EAR, or is subject to controls under the U.S. Munitions List ("USML"). At all times hereunder, the recipient of any such information agrees that they shall be deemed to have manually signed this document in connection with their receipt of any such information. Copyright © 1999–2015. Marvell International Ltd. All rights reserved. Alaska, ARMADA, Avanta, Avastar, CarrierSpan, Kinoma, Link Street, LinkCrypt, Marvell logo, Marvell, Moving Forward Faster, Marvell Smart, PISC, Prestera, Qdeo, QDEO logo, QuietVideo, Virtual Cable Tester, The World as YOU See It, Vmeta, Xelerated, and Yukon are registered trademarks of Marvell or its affiliates. G.now, HyperDuo, Kirkwood, and Wirespeed by Design are trademarks of Marvell or its affiliates.Patent(s) Pending—Products identified in this document may be covered by one or more Marvell patents and/or patent applications.88MW300/302 Datasheet Doc. No. MV-S109936-00 Rev. A CONFIDENTIAL Copyright © 2015 MarvellPage 2 Document Classification: Proprietary February 3, 2015, 1.00
xam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & ConMARVELL CONFIDENTIAL, UNDER NDA# 12150208m1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & Control InMARVELL CONFIDENTIAL, UNDER NDA# 121502082fdrxam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Net88MW300/302WLAN MicrocontrollerDatasheet Copyright © 2015 Marvell CONFIDENTIAL Doc. No. MV-S109936-00 Rev. AFebruary 3, 2015, 1.00 Document Classification: Proprietary Page 3 PRODUCT OVERVIEWThe Marvell® 88MW300/302 is a highly integrated, low-power WLAN Microcontroller System-on-Chip (SoC) solution designed for a broad array of smart devices for Internet of Things (IoT), wearables, accessories, Machine-to-Machine (M2M), home automation, and Smart Energy applicationsA high degree of integration enables very low system costs requiring only a single 3.3V power input, a 38.4 MHz crystal, and SPI Flash. The RF path needs only a lowpass filter for antenna connection.The SoC includes a full-featured W LAN subsystem powered by proven and mature IEEE 802.11n/g/b Marvell technology. The WLAN subsystem integrates a WLAN MAC, baseband, and direct-conversion RF radio with integrated PA, LNA, and transmit/receive switch. It also integrates a CPU subsystem with integrated memory to run Marvell WLAN firmware to handle real time WLAN protocol processing to off-load many WLAN functions from the main application CPU.The 88MW300/302 application subsystem is powered by an ARM Cortex-M4F CPU that operates up to 200 MHz. The device supports an integrated 512 KB SRAM, 128 KB mask ROM, and a QSPI interface to external Flash. An integrated Flash Controller with a 32 KB SRAM cache enables eXecute In Place (XIP) support for firmware from Flash. The SoC is designed for low-power operation and includes several low-power states and fast wake-up times. Multiple power domains and clocks can be individually shut down to save power. The SoC also has a high-efficiency internal PA that can be operated in low-power mode to save power. The microcontroller and WLAN subsystems can be placed into low-power states, independently, supporting a variety of application use cases. An internal DC-DC regulator provides the 1.8V rail for the WLAN subsystem. The SoC provides a full array of peripheral interfaces including SSP/SPI/I2S (3x), UART (3x), I2C (2x), General Purpose Timers and PWM, ADC, DAC, Analog Comparator, and GPIOs. It also includes a hardware cryptographic engine, RTC, and Watchdog Timer. The 88MW302 includes a high speed USB On-The-Go (OTG) interface to enable USB audio, video, and other applications.A complete set of digital and analog interfaces enable direct interfacing for I/O avoiding the need for external chips. The application CPU can be used to support custom application development avoiding the need for another microcontroller or processor.Figure 1 shows an overall block diagram of the device.
xam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & ConMARVELL CONFIDENTIAL, UNDER NDA# 12150208m1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & Control InMARVELL CONFIDENTIAL, UNDER NDA# 121502082fdrxam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Net88MW300/302 Datasheet Doc. No. MV-S109936-00 Rev. A CONFIDENTIAL Copyright © 2015 MarvellPage 4 Document Classification: Proprietary February 3, 2015, 1.00ApplicationsWhite goods/appliances—refrigerator, washer, dryer, oven range, microwave, dishwasher, water heater, air conditionerConsumer devices and accessories—toys, speakers, headset, alarm clock, gaming accessory, remote controlHome automation—smart outlet, light switch, security camera, thermostat, sprinkler controller, sensor, door lock, door bell, garage door, security systemPersonal health devices—weighing scale, glucometer, blood pressure monitor, fitness equipmentIoT/wearables—coffee pot, rice cooker, vacuum cleaner, air purifier, smart watch, fitness bracelet, pet monitorCommercial/industrial—lighting, building automation, asset management, Point of Sale (POS) salesGateways—Connecting IR, sub-Gig or Legacy RF, Bluetooth Smart, ZigBee, ZWave and other radios to Wi-Fi/IP networkKey FeaturesHighly integrated SoC requiring very few external components for a full system operationMultiple low-power modes and fast wake-up timesFull-featured, single stream 802.11n/g/b WLANHigh-efficiency PA with a low-power (10 dB) mode Cortex-M4F application CPU for applications with integrated 512 KB SRAM and 128 KB mask ROMFlash Controller with embedded 32 KB SRAM cache to support XIP from external SPI FlashSecure bootFull set of digital and analog I/O interfacesPower ManagementPower modes—active, idle, standby, sleep, shutoff, power-downIntegrated high efficiency buck DC-DC converterIndependent power domainsBrownout detectionIntegrated PORWake-up through dedicated GPIO, IRQ, and RTCFigure 1: Block Diagram WL_MCI_REFCLKDMA ControllerAHB Bus FabricI/O MultiplexerM0M1S0S1RTCPHYM2S2S3S4USB ControllerM3M4S7S5S6S84k SRAMJTAG SWDNVICCortex-M4MPU FPUCode RAM0Code RAM1Data RAM0Data RAM1Flash/CacheControllerUARTWDTPINMUXSSP/SPI/I2SI2CPMUAHBdecodeROMAES/CRC32 kHz GEN32 MHz GENPLLMicrocontroller88MW300/302WLAN32 KB SRAMAPB0APB1BUCK18Feroceon CPU SRAM/ROM JTAGV18LDO11V11...I2CQSPISSP/SPI/I2SADC/T-SensDACACOMPUARTGPIOTimer/PWMX2/12LDO12V12V18LDO18DigitalAnalogI/ODigitalAnalogI/ODigitalAnalogI/ODigitalAnalogI/ODigitalAnalogI/ODigitalAnalogI/O802.11 MAC Tx/Rx 1x1 SISO802.11 Baseband(DSSS/OFDM, 1x1 SISO)LNADirect ConversionWLAN RF1x1 SISOPAT/R Switch2.4 GHzSecurity/EncryptionVDD PowerManagement
xam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & ConMARVELL CONFIDENTIAL, UNDER NDA# 12150208m1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & Control InMARVELL CONFIDENTIAL, UNDER NDA# 121502082fdrxam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global NetPackageSignal Diagram Copyright © 2015 Marvell CONFIDENTIAL Doc. No. MV-S109936-00 Rev. AFebruary 3, 2015, 1.00 Document Classification: Proprietary Page 411Package1.1 Signal Diagram Figure 2: Signal Diagram1234 1. Signals are muxed on dedicated pins. See Section 1.4, Pin Description, on page 46 for dedicated pin / muxed signal descriptions.2. Some pins/signals are available on the 88-pin QFN only. See Section 1.4, Pin Description, on page 46.3. RF_TR, USB OTG, XTAL_IN/OUT, and RESETn pins are dedicated. Others are muxed on GPIOs.4. See Table 16, Power and Ground, on page 66 for power signals.88MW300/302GPIO InterfaceGPIO_0 to GPIO_49JTAG InterfaceTDITCKTDOTMSTRSTnWLAN RF InterfaceRF_TRUART Interface(UART0-UART2)UARTx_TXDUARTx_RXDUARTx_CTSnUARTx_RTSnSSP Interface(SSP0-SSP2)SSPx_FRMSSPx_CLKSSPx_TXDSSPx_RXDGPTx_CHx GPT Interface(GPT 0-GPT3, Ch0-5 each)GPT_CLKINClock/Control Interface WAKE_UP0WAKE_UP1XTAL32K_OUTXTAL32K_INXTAL_OUTXTAL_INRESETnAUDIO_CLKQSPI InterfaceQSPI_CLKQSPI_SSnQSPI_D0QSPI_D1QSPI_D2QSPI_D3WLAN RF Front End InterfaceRF_CNTL0_NRF_CNTL1_PVOICE_NVOICE_PVoiceTS_INPTS_INNTemperature Sensor InterfaceDACBDACADAC InterfaceI2Cx_SDA I2C Interface(I2C0-I2C1)I2Cx_SCLCOMP_IN_PCOMP_IN_NEXT_VREFADC/ACOMP Interface(ADC0, Ch0-7)ADC0_x / ACOMPxACOMP0_EDGE_PULSEACOMP1_EDGE_PULSEADC_DAC_TRIGGER0ADC_DAC_TRIGGER1ACOMP1_GPIO_OUTACOMP0_GPIO_OUTLDO18 Comparator InterfaceUSB OTG 2.0 InterfaceUSB_DPUSB_IDUSB_VBUSUSB_DMUSB_DRV_VBUS
xam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & ConMARVELL CONFIDENTIAL, UNDER NDA# 12150208m1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & Control InMARVELL CONFIDENTIAL, UNDER NDA# 121502082fdrxam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Net88MW300/302 Datasheet Doc. No. MV-S109936-00 Rev. A CONFIDENTIAL Copyright © 2015 MarvellPage 42 Document Classification: Proprietary February 3, 2015, 1.001.2 Pinout1.2.1 Pinout—68-Pin QFN Figure 3: Pinout—68-Pin QFN1 1. Connect pin 17 to ground.686766656463626160595857565554535288MW3001617123456789101112131415GPIO_27GPIO_39VDDIO_3GPIO_40GPIO_41GPIO_46GPIO_47GPIO_48GPIO_49FLY18VBAT_INFLY11VBAT_INBUCK18_VXLDO11_V18LDO11_VOUTGPIO_16VDDIO_1VDD11DNCDNCDNCDNCAVDD18XTAL_OUTXTAL_INAVDD18AVDD18AVDD181819202122232425262728293031323334GPIO_0GPIO_1GPIO_2GPIO_3VDDIO_0GPIO_4GPIO_5GPIO_6GPIO_7GPIO_8GPIO_9GPIO_10AVDD18AVDD18AVDD33RF_TRNC4140393851504948474645444342373635ISENSEVDDIO_2VDD11VDDIO_AONGPIO_26GPIO_25GPIO_24GPIO_23VTR_VDD33GPIO_22RES ETnGPIO_33GPIO_32GPIO_31GPIO_30GPIO_29GPIO_28VDDIO_3GPIO_42GPIO_43GPIO_44GPIO_45
xam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & ConMARVELL CONFIDENTIAL, UNDER NDA# 12150208m1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & Control InMARVELL CONFIDENTIAL, UNDER NDA# 121502082fdrxam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global NetPackagePinout Copyright © 2015 Marvell CONFIDENTIAL Doc. No. MV-S109936-00 Rev. AFebruary 3, 2015, 1.00 Document Classification: Proprietary Page 431.2.2 Pinout—88-Pin QFN Figure 4: Pinout—88-Pin QFN1 1. Connect pin 22 to ground.8887868584838281807978777675747372717069686788MW302515049486665646362616059585756555453524746452324252627282930313233343536373839404142434416171819123456789101112131415202122GPIO_0GPIO_1GPIO_2GPIO_3VDDIO_0GPIO_4GPIO_5GPIO_6GPIO_7GPIO_8GPIO_9GPIO_10GPIO_11GPIO_12GPIO_13GPIO_14GPIO_15AVDD18AVDD18AVDD33RF_TRNCUSB_DMUSB_DPUSB_AVDD33USB_IDUSB_VBUSISENSEVDDIO_2GPIO_33GPIO_32GPIO_31GPIO_30GPIO_29GPIO_28VDD11VDDIO_AONGPIO_26GPIO_25GPIO_24GPIO_23VTR_VDD33GPIO_22RESETnVBAT_INBUCK18_VXLDO11_V18LDO11_VOUTGPIO_21GPIO_20GPIO_19GPIO_18GPIO_17GPIO_16VDDIO_1VDD11DNCDNCDNCDNCAVDD18XTAL_OUTXTAL_INAVDD18AVDD18AVDD18GPIO_34GPIO_35GPIO_36GPIO_37GPIO_27GPIO_38GPIO_39VDDIO_3GPIO_40GPIO_41FLY18VBAT_INFLY11VDDIO_3GPIO_46GPIO_47GPIO_48GPIO_49GPIO_42GPIO_43GPIO_44GPIO_45
xam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * GMARVELL CONFIDENTIAL, UNDER NDA# 12m1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & Control Inc. MARVELL CONFIDENTIAL, UNDER NDA# 12150208MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY88MW300/302 Datasheet Doc. No. MV-S109936-00 Rev. A CONFIDENTIAL Copyright © 2015 MarvellPage 44 Document Classification: Proprietary February 3, 2015, 1.001.3 Mechanical Drawing1.3.1 Mechanical Drawing—68-Pin QFN Note: QFN package uses Epad size Option #3 only. See Section 22.4, Package Thermal Conditions, on page 315 for electrical specifications. See Section 23.2, Package Marking, on page 336 for package marking.Figure 5: Mechanical Drawing—68-Pin QFN
xam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * GMARVELL CONFIDENTIAL, UNDER NDA# 12m1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & Control Inc. MARVELL CONFIDENTIAL, UNDER NDA# 12150208MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLYPackageMechanical Drawing Copyright © 2015 Marvell CONFIDENTIAL Doc. No. MV-S109936-00 Rev. AFebruary 3, 2015, 1.00 Document Classification: Proprietary Page 451.3.2 Mechanical Drawing—88-Pin QFN Note: QFN package uses Epad size Option #3 only. See Section 22.4, Package Thermal Conditions, on page 315 for electrical specifications. See Section 23.2, Package Marking, on page 336 for package marking.Figure 6: Mechanical Drawing—88-Pin QFN
xam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & ConMARVELL CONFIDENTIAL, UNDER NDA# 12150208m1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & Control InMARVELL CONFIDENTIAL, UNDER NDA# 121502082fdrxam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Net88MW300/302 Datasheet Doc. No. MV-S109936-00 Rev. A CONFIDENTIAL Copyright © 2015 MarvellPage 46 Document Classification: Proprietary February 3, 2015, 1.001.4 Pin Description .Table 2: Pin TypesPin Type DescriptionI/O Digital input/outputI Digital inputO Digital outputA, I Analog inputA, O Analog outputNC No connectDNC Do not connectPWR PowerGround GroundTable 3: WLAN RF Interface88-Pin 68-Pin Pin Name Type Supply Description21 16 RF_TR A, I/O AVDD18 WLAN RF Interface (2.4 GHz Transmit/Receive)Baseband input/output dataTable 4: WLAN RF Front End Interface88-Pin 68-Pin Pin Name Type Supply DescriptionGPIO_44 RF_CNTL1_P A, O VDDIO_3 WLAN Radio Control 1Power-down output high signalGPIO_45 RF_CNTL0_N A, O VDDIO_3 WLAN Radio Control 0Power-down output low signal
xam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & ConMARVELL CONFIDENTIAL, UNDER NDA# 12150208m1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & Control InMARVELL CONFIDENTIAL, UNDER NDA# 121502082fdrxam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global NetPackagePin Description Copyright © 2015 Marvell CONFIDENTIAL Doc. No. MV-S109936-00 Rev. AFebruary 3, 2015, 1.00 Document Classification: Proprietary Page 47 Table 5: USB 2.0 OTG Interface1NOTE: Available on 88-pin package only (88MW302)88-Pin 68-Pin Pin Name Type Supply Description61 -- USB_VBUS A, I/O USB_AVDD33 USB VBUS Selection Input In Device Mode Unused in host mode; I/O for OTG mode to supply +5V@10mA during session negotiation.GPIO_27 -- USB_DRV_VBUS A, O VDDIO_3 Drive 5V on VBUS0 = do not drive VBUS1 = drive 5V on VBUSThe USB_DRV_VBUS port is connected to the SoC pad to drive an external power management chip to provide power for USB VBUS.62 -- USB_ID A, I USB_AVDD33 USB 2.0 OTG IDPIN63 -- USB_AVDD33 A, I -- USB 3.3V Analog Power SupplySee Table 16, Power and Ground, on page 66.64 -- USB_DP A, I/O USB_AVDD33 USB 2.0 Bus Data+65 -- USB_DM A, I/O USB_AVDD33 USB 2.0 Bus Data–1. After POR, if USB is in host mode, USB_DPUSB_DM will be SE0. If USB is in device mode, USB_DP/USB_DM will be High-z.Table 6: UART Interface188-Pin 68-Pin Signal Name Type Supply DescriptionGPIO_0 UART0_CTSn I VDDIO_0 UART 0 CTSn (active low)GPIO_1 UART0_RTSn O VDDIO_0 UART 0 RTSn (active low)GPIO_2 UART0_TXD O VDDIO_0 UART 0 TXD GPIO_3 UART0_RXD I VDDIO_0 UART 0 RXDGPIO_23 UART0_CTSn I VDDIO_AON UART 0 CTSn (active low)GPIO_24 UART0_RXD I VDDIO_AON UART 0 RXDGPIO_30 UART0_CTSn I VDDIO_2 UART 0 CTSn (active low)GPIO_31 UART0_RTSn O VDDIO_2 UART 0 RTSn (active low)GPIO_32 UART0_TXD O VDDIO_2 UART 0 TXDGPIO_33 UART0_RXD I VDDIO_2 UART 0 RXD
xam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & ConMARVELL CONFIDENTIAL, UNDER NDA# 12150208m1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & Control InMARVELL CONFIDENTIAL, UNDER NDA# 121502082fdrxam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Net88MW300/302 Datasheet Doc. No. MV-S109936-00 Rev. A CONFIDENTIAL Copyright © 2015 MarvellPage 48 Document Classification: Proprietary February 3, 2015, 1.00GPIO_37 -- UART0_RTSn O VDDIO_3 UART 0 RTSn (active low)GPIO_27 UART0_TXD O VDDIO_3 UART 0 TXDGPIO_11 -- UART1_CTSn I VDDIO_0 UART 1 CTSn (active low)GPIO_12 -- UART1_RTSn O VDDIO_0 UART 1 RTSn (active low)GPIO_13 -- UART1_TXD O VDDIO_0 UART 1 TXDGPIO_14 -- UART1_RXD I VDDIO_0 UART 1 RXDGPIO_35 -- UART1_CTSn I VDDIO_3 UART 1 CTSn (active low)GPIO_36 -- UART1_RTSn O VDDIO_3 UART 1 RTSn (active low)GPIO_38 -- UART1_TXD O VDDIO_3 UART 1 TXDGPIO_39 UART1_RXD I VDDIO_3 UART 1 RXDGPIO_42 UART1_CTSn I VDDIO_3 UART 1 CTSn (active low)GPIO_43 UART1_RTSn O VDDIO_3 UART 1 RTSn (active low)GPIO_44 UART1_TXD O VDDIO_3 UART 1 TXDGPIO_45 UART1_RXD I VDDIO_3 UART 1 RXDGPIO_7 UART2_CTSn I VDDIO_0 UART 2 CTSn (active low)GPIO_8 UART2_RTSn O VDDIO_0 UART 2 RTSn (active low)GPIO_9 UART2_TXD O VDDIO_0 UART 2 TXDGPIO_10 UART2_RXD I VDDIO_0 UART 2 RXDGPIO_46 UART2_CTSn I VDDIO_3 UART 2 CTSn (active low)GPIO_47 UART2_RTSn O VDDIO_3 UART 2 RTSn (active low)GPIO_48 UART2_TXD O VDDIO_3 UART 2 TXDGPIO_49 UART2_RXD I VDDIO_3 UART 2 RXD1. All UART signals are muxed on GPIO pins. See Table 11, GPIO Interface, on page 53 for GPIO muxing.Table 6: UART Interface188-Pin 68-Pin Signal Name Type Supply Description
xam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & ConMARVELL CONFIDENTIAL, UNDER NDA# 12150208m1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & Control InMARVELL CONFIDENTIAL, UNDER NDA# 121502082fdrxam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global NetPackagePin Description Copyright © 2015 Marvell CONFIDENTIAL Doc. No. MV-S109936-00 Rev. AFebruary 3, 2015, 1.00 Document Classification: Proprietary Page 49 Table 7: GPT Interface188-Pin 68-Pin Signal Name Type Supply DescriptionGPIO_0 GPT0_CH0 I/O VDDIO_0 General Purpose Timer 0, Channel 0GPIO_1 GPT0_CH1 I/O VDDIO_0 General Purpose Timer 0, Channel 1GPIO_2 GPT0_CH2 I/O VDDIO_0 General Purpose Timer 0, Channel 2GPIO_3 GPT0_CH3 I/O VDDIO_0 General Purpose Timer 0, Channel 3GPIO_4 GPT0_CH4 I/O VDDIO_0 General Purpose Timer 0, Channel 4GPIO_5 GPT0_CH5 I/O VDDIO_0 General Purpose Timer 0, Channel 5GPIO_35 -- GPT0_CLKIN I VDDIO_3 General Purpose Timer 0, Clock InputGPIO_28 GPT1_CH0 I/O VDDIO_2 General Purpose Timer 1, Channel 0GPIO_29 GPT1_CH1 I/O VDDIO_2 General Purpose Timer 1, Channel 1GPIO_30 GPT1_CH2 I/O VDDIO_2 General Purpose Timer 1, Channel 2GPIO_31 GPT1_CH3 I/O VDDIO_2 General Purpose Timer 1, Channel 3GPIO_32 GPT1_CH4 I/O VDDIO_2 General Purpose Timer 1, Channel 4GPIO_33 GPT1_CH5 I/O VDDIO_2 General Purpose Timer 1, Channel 5GPIO_24 GPT1_CH5 I/O VDDIO_AON General Purpose Timer 1, Channel 5GPIO_36 -- GPT1_CLKIN I VDDIO_3 General Purpose Timer 1, Clock InputGPIO_11 -- GPT2_CH0 I/O VDDIO_0 General Purpose Timer 2, Channel 0GPIO_12 -- GPT2_CH1 I/O VDDIO_0 General Purpose Timer 2, Channel 1GPIO_13 -- GPT2_CH2 I/O VDDIO_0 General Purpose Timer 2, Channel 2GPIO_14 -- GPT2_CH3 I/O VDDIO_0 General Purpose Timer 2, Channel 3GPIO_15 -- GPT2_CH4 I/O VDDIO_0 General Purpose Timer 2, Channel 4GPIO_37 -- GPT2_CH5 I/O VDDIO_3 General Purpose Timer 2, Channel 5GPIO_38 -- GPT2_CLKIN I VDDIO_3 General Purpose Timer 2, Clock InputGPIO_17 -- GPT3_CH0 I/O VDDIO_1 General Purpose Timer 3, Channel 0GPIO_18 -- GPT3_CH1 I/O VDDIO_1 General Purpose Timer 3, Channel 1GPIO_19 -- GPT3_CH2 I/O VDDIO_1 General Purpose Timer 3, Channel 2GPIO_20 -- GPT3_CH3 I/O VDDIO_1 General Purpose Timer 3, Channel 3
xam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & ConMARVELL CONFIDENTIAL, UNDER NDA# 12150208m1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & Control InMARVELL CONFIDENTIAL, UNDER NDA# 121502082fdrxam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Net88MW300/302 Datasheet Doc. No. MV-S109936-00 Rev. A CONFIDENTIAL Copyright © 2015 MarvellPage 50 Document Classification: Proprietary February 3, 2015, 1.00 GPIO_21 -- GPT3_CH4 I/O VDDIO_1 General Purpose Timer 3, Channel 4GPIO_34 -- GPT3_CH5 I/O VDDIO_3 General Purpose Timer 3, Channel 5GPIO_39 GPT3_CLKIN I VDDIO_3 General Purpose Timer 2, Clock Input1. All GPT signals are muxed on GPIO pins. See Table 11, GPIO Interface, on page 53 for GPIO muxing.Table 7: GPT Interface188-Pin 68-Pin Signal Name Type Supply DescriptionTable 8: SSP Interface188-Pin 68-Pin Pin Name Type Supply DescriptionGPIO_0 SSP0_CLK I/O VDDIO_0 SSP 0 Serial ClockGPIO_1 SSP0_FRM I/O VDDIO_0 SSP 0 Frame IndicatorGPIO_2 SSP0_TXD O VDDIO_0 SSP 0 TXDGPIO_3 SSP0_RXD I VDDIO_0 SSP 0 RXDGPIO_30 SSP0_CLK I/O VDDIO_2 SSP 0 Serial ClockGPIO_31 SSP0_FRM I/O VDDIO_2 SSP 0 Frame IndicatorGPIO_32 SSP0_TXD O VDDIO_2 SSP 0 TXDGPIO_33 SSP0_RXD I VDDIO_2 SSP 0 RXDGPIO_11 -- SSP1_CLK I/O VDDIO_0 SSP 1 Serial ClockGPIO_12 -- SSP1_FRM I/O VDDIO_0 SSP 1 Frame IndicatorGPIO_13 -- SSP1_TXD O VDDIO_0 SSP 1 TXDGPIO_14 -- SSP1_RXD I VDDIO_0 SSP 1 RXDGPIO_18 -- SSP1_CLK I/O VDDIO_1 SSP 1 Serial ClockGPIO_19 -- SSP1_FRM I/O VDDIO_1 SSP 1 Frame IndicatorGPIO_20 -- SSP1_TXD O VDDIO_1 SSP 1 TXDGPIO_21 -- SSP1_RXD I VDDIO_1 SSP 1 RXDGPIO_35 -- SSP1_CLK I/O VDDIO_3 SSP 1 Serial ClockGPIO_36 -- SSP1_FRM I/O VDDIO_3 SSP 1 Frame Indicator
xam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & ConMARVELL CONFIDENTIAL, UNDER NDA# 12150208m1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & Control InMARVELL CONFIDENTIAL, UNDER NDA# 121502082fdrxam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global NetPackagePin Description Copyright © 2015 Marvell CONFIDENTIAL Doc. No. MV-S109936-00 Rev. AFebruary 3, 2015, 1.00 Document Classification: Proprietary Page 51GPIO_38 -- SSP1_TXD O VDDIO_3 SSP 1 TXDGPIO_39 SSP1_RXD I VDDIO_3 SSP 1 RXDGPIO_42 SSP1_CLK I/O VDDIO_3 SSP 1 Serial ClockGPIO_43 SSP1_FRM I/O VDDIO_3 SSP 1 Frame IndicatorGPIO_44 SSP1_TXD O VDDIO_3 SSP 1 TXDGPIO_45 SSP1_RXD I VDDIO_3 SSP 1 RXDGPIO_7 SSP2_CLK I/O VDDIO_0 SSP 2 Serial ClockGPIO_8 SSP2_FRM I/O VDDIO_0 SSP 2 Frame IndicatorGPIO_9 SSP2_TXD O VDDIO_0 SSP 2 TXDGPIO_10 SSP2_RXD I VDDIO_0 SSP 2 RXDGPIO_46 SSP2_CLK I/O VDDIO_3 SSP 2 Serial ClockGPIO_47 SSP2_FRM I/O VDDIO_3 SSP 2 Frame IndicatorGPIO_48 SSP2_TXD O VDDIO_3 SSP 2 TXDGPIO_49 SSP2_RXD I VDDIO_3 SSP 2 RXD1. All SSP signals are muxed on GPIO pins. See Table 11, GPIO Interface, on page 53 for GPIO muxing.Table 8: SSP Interface1 (Continued)88-Pin 68-Pin Pin Name Type Supply Description
xam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & ConMARVELL CONFIDENTIAL, UNDER NDA# 12150208m1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & Control InMARVELL CONFIDENTIAL, UNDER NDA# 121502082fdrxam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Net88MW300/302 Datasheet Doc. No. MV-S109936-00 Rev. A CONFIDENTIAL Copyright © 2015 MarvellPage 52 Document Classification: Proprietary February 3, 2015, 1.00 Table 9: I2C Interface188-Pin 68-Pin Pin Name Type Supply DescriptionGPIO_4GPIO_7I2C0_SDA I/O VDDIO_0 I2C0 SDAGPIO_5GPIO_8I2C0_SCL I/O VDDIO_0 I2C0 SCLGPIO_6GPIO_9I2C1_SDA I/O VDDIO_0 I2C1 SDAGPIO_10 I2C1_SCL I/O VDDIO_0 I2C1 SCLGPIO_20 -- I2C0_SDA I/O VDDIO_1 I2C0 SDAGPIO_21 -- I2C0_SCL I/O VDDIO_1 I2C0 SCLGPIO_18 -- I2C1_SDA I/O VDDIO_1 I2C1 SDAGPIO_17GPIO_19-- I2C1_SCL I/O VDDIO_1 I2C1 SCLGPIO_25 I2C1_SDA I/O VDDIO_AON I2C1 SDAGPIO_26 I2C1_SCL I/O VDDIO_AON I2C1 SCLGPIO_28 I2C0_SDA I/O VDDIO_2 I2C1 SDAGPIO_29 I2C0_SCL I/O VDDIO_2 I2C1 SCL1. All I2C signals are muxed on GPIO pins. See Table 11, GPIO Interface, on page 53 for GPIO muxing.Table 10: QSPI Interface188-Pin 68-Pin Pin Name Type Supply DescriptionGPIO_28 QSPI_SSn O VDDIO_2 QSPI Chip Select (active low)GPIO_29 QSPI_CLK O VDDIO_2 QSPI ClockGPIO_30 QSPI_D0 I/O VDDIO_2 QSPI Data 0GPIO_31 QSPI_D1 I/O VDDIO_2 QSPI Data 1GPIO_32 QSPI_D2 I/O VDDIO_2 QSPI Data 2GPIO_33 QSPI_D3 I/O VDDIO_2 QSPI Data 31. QSPI signals are used for external Flash only. All QSPI signals are muxed on GPIO pins. See Table 11, GPIO Interface, on page 53 for GPIO muxing.
xam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & ConMARVELL CONFIDENTIAL, UNDER NDA# 12150208m1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & Control InMARVELL CONFIDENTIAL, UNDER NDA# 121502082fdrxam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global NetPackagePin Description Copyright © 2015 Marvell CONFIDENTIAL Doc. No. MV-S109936-00 Rev. AFebruary 3, 2015, 1.00 Document Classification: Proprietary Page 53Table 11: GPIO Interface 1288-Pin 68-Pin Pin/Signal Name Type Supply Description1 1 GPIO_0 I/O VDDIO_0 General Purpose I/O 0GPT0_CH0 I/O General Purpose Timer 0, Channel 0UART0_CTSn I UART 0 CTSn (active low)SSP0_CLK I/O SSP 0 Serial Clock2 2 GPIO_1 I/O VDDIO_0 General Purpose I/O 1GPT0_CH1 I/O General Purpose Timer 0, Channel 1UART0_RTSn O UART 0 RTSn (active low)SSP0_FRM I/O SSP 0 Frame Indicator3 3 GPIO_2 I/O VDDIO_0 General Purpose I/O 2GPT0_CH2 I/O General Purpose Timer 0, Channel 2UART0_TXD O UART 0 TXDSSP0_TXD O SSP 0 TXD4 4 GPIO_3 I/O VDDIO_0 General Purpose I/O 3GPT0_CH3 I/O General Purpose Timer 0, Channel 3UART0_RXD I UART 0 RXDSSP0_RXD I SSP 0 RXD6 6 GPIO_4 I/O VDDIO_0 General Purpose I/O 4GPT0_CH4 I/O General Purpose Timer 0, Channel 4I2C0_SDA I/O I2C0 SDAAUDIO_CLK O Audio ClockAUPLL Audio clock output provided by Audio PLL for external codec.7 7 GPIO_5 I/O VDDIO_0 General Purpose I/O 5GPT0_CH5 I/O General Purpose Timer 0, Channel 5I2C0_SCL I/O I2C0 SCL
xam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & ConMARVELL CONFIDENTIAL, UNDER NDA# 12150208m1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & Control InMARVELL CONFIDENTIAL, UNDER NDA# 121502082fdrxam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Net88MW300/302 Datasheet Doc. No. MV-S109936-00 Rev. A CONFIDENTIAL Copyright © 2015 MarvellPage 54 Document Classification: Proprietary February 3, 2015, 1.008 8 GPIO_6 I/O VDDIO_0 General Purpose I/O 6TDO O JTAG Test Data I2C1_SDA I/O I2C1 SDA9 9 GPIO_7 I/O VDDIO_0 General Purpose I/O 7TCK I JTAG Test Clock UART2_CTSn I UART 2 CTSn (active low)SSP2_CLK I/O SSP 2 Serial ClockI2C0_SDA I/O I2C0 SDA10 10 GPIO_8 I/O VDDIO_0 General Purpose I/O 8TMS I/O JTAG Controller Select UART2_RTSn O UART 2 RTSn (active low)SSP2_FRM I/O SSP_2 Frame IndicatorI2C0_SCL I/O I2C0 SCL11 11 GPIO_9 I/O VDDIO_0 General Purpose I/O 9TDI I JTAG Test Data UART2_TXD O UART 2 TXDSSP2_TXD O SSP 2 TXDI2C1_SDA I/O I2C1 SDA12 12 GPIO_10 I/O VDDIO_0 General Purpose I/O 10TRSTn I JTAG Test Reset (active low) UART2_RXD I UART 2 RXDSSP2_TXD O SSP 2 RXDI2C1_SCL I/O I2C1 SCLTable 11: GPIO Interface 1 (Continued)288-Pin 68-Pin Pin/Signal Name Type Supply Description
xam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & ConMARVELL CONFIDENTIAL, UNDER NDA# 12150208m1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & Control InMARVELL CONFIDENTIAL, UNDER NDA# 121502082fdrxam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global NetPackagePin Description Copyright © 2015 Marvell CONFIDENTIAL Doc. No. MV-S109936-00 Rev. AFebruary 3, 2015, 1.00 Document Classification: Proprietary Page 5513 -- GPIO_11 I/O VDDIO_0 General Purpose I/O 11GPT2_CH0 I/O General Purpose Timer 2, Channel 0UART1_CTSn I UART 1 CTSn (active low)SSP1_CLK I/O SSP 1 Serial Clock14 -- GPIO_12 I/O VDDIO_0 General Purpose I/O 12GPT2_CH1 I/O General Purpose Timer 2, Channel 1UART1_RTSn O UART 1 RTSn (active low)SSP1_FRM I/O SSP 1 Frame Indicator15 -- GPIO_13 I/O VDDIO_0 General Purpose I/O 13GPT2_CH2 I/O General Purpose Timer 2, Channel 2UART1_TXD O UART 1 TXDSSP1_TXD O SSP 1 TXD16 -- GPIO_14 I/O VDDIO_0 General Purpose I/O 14GPT2_CH3 I/O General Purpose Timer 2, Channel 3UART1_RXD I UART 1 RXDSSP1_RXD I SSP 1 RXD17 -- GPIO_15 I/O VDDIO_0 General Purpose I/O 15GPT2_CH4 I/O General Purpose Timer 2, Channel 435 30 GPIO_16 I/O VDDIO_1 General Purpose I/O 16CON[5] I/O Configuration BitSee Table 17, Configuration Pins, on page 67.AUDIO_CLK O Audio ClockAUPLL Audio clock output provided by Audio PLL for external codec.Table 11: GPIO Interface 1 (Continued)288-Pin 68-Pin Pin/Signal Name Type Supply Description
xam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & ConMARVELL CONFIDENTIAL, UNDER NDA# 12150208m1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & Control InMARVELL CONFIDENTIAL, UNDER NDA# 121502082fdrxam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Net88MW300/302 Datasheet Doc. No. MV-S109936-00 Rev. A CONFIDENTIAL Copyright © 2015 MarvellPage 56 Document Classification: Proprietary February 3, 2015, 1.0036 -- GPIO_17 I/O VDDIO_1 General Purpose I/O 17GPT3_CH0 I/O General Purpose Timer 3, Channel 0I2C1_SCL I/O I2C1 SCL37 -- GPIO_18 I/O VDDIO_1 General Purpose I/O 18GPT3_CH1 I/O General Purpose Timer 3, Channel 1I2C1_SDA I/O I2C1 SDASSP1_CLK I/O SSP 1 Serial Clock38 -- GPIO_19 I/O VDDIO_1 General Purpose I/O 19GPT3_CH2 I/O General Purpose Timer 3, Channel 2I2C1_SCL I/O I2C1 SDASSP1_FRM I/O SSP 1 Frame Indicator39 -- GPIO_20 I/O VDDIO_1 General Purpose I/O 20GPT3_CH3 I/O General Purpose Timer 3, Channel 3I2C0_SDA I/O I2C0 SDASSP1_TXD O SSP 1 TXD40 -- GPIO_21 I/O VDDIO_1 General Purpose I/O 21GPT3_CH4 I/O General Purpose Timer 3, Channel 4I2C0_SCL I/O I2C0 SCLSSP1_RXD I SSP 1 RXD46 36 GPIO_22 I/O VDDIO_AONGeneral Purpose I/O 22WAKE_UP0 I Wake-Up 0Table 11: GPIO Interface 1 (Continued)288-Pin 68-Pin Pin/Signal Name Type Supply Description
xam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & ConMARVELL CONFIDENTIAL, UNDER NDA# 12150208m1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & Control InMARVELL CONFIDENTIAL, UNDER NDA# 121502082fdrxam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global NetPackagePin Description Copyright © 2015 Marvell CONFIDENTIAL Doc. No. MV-S109936-00 Rev. AFebruary 3, 2015, 1.00 Document Classification: Proprietary Page 5747 37 GPIO_23 I/O VDDIO_AONGeneral Purpose I/O 23UART0_CTSn I UART 0 CTSn (active low)WAKE_UP1 I Wake-Up 1COMP_IN_P I LDO18 Comparator Input, PositivePositive input to LDO18 comparator.48 38 GPIO_24 I/O VDDIO_AONGeneral Purpose I/O 24UART0_RXD I UART 0 RXDGPT1_CH5 I/O General Purpose Timer 1, Channel 5COMP_IN_N I LDO18 Comparator Input, NegativeNegative input to LDO18 comparator.49 39 GPIO_25 I/O VDDIO_AONGeneral Purpose I/O 25XTAL32K_IN I 32.768 kHz Crystal InputI2C1_SDA I/O I2C1 SDA50 40 GPIO_26 I/O VDDIO_AONGeneral Purpose I/O 26XTAL32K_OUT O 32.768 kHz Crystal OutputI2C1_SCL I/O I2C1 SCL66 51 GPIO_27 I/O VDDIO_3 General Purpose I/O 27-- USB_DRV_VBUS O Drive 5V on VBUS51 UART0_TXD O UART 0 TXD51 CON[4] I/O Configuration BitSee Table 17, Configuration Pins, on page 67.52 42 GPIO_28 I/O VDDIO_2 General Purpose I/O 28QSPI_SSn O QSPI Chip Select (active low)I2C0_SDA I/O I2C0 SDAGPT1_CH0 I/O General Purpose Timer 1, Channel 0Table 11: GPIO Interface 1 (Continued)288-Pin 68-Pin Pin/Signal Name Type Supply Description
xam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & ConMARVELL CONFIDENTIAL, UNDER NDA# 12150208m1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & Control InMARVELL CONFIDENTIAL, UNDER NDA# 121502082fdrxam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Net88MW300/302 Datasheet Doc. No. MV-S109936-00 Rev. A CONFIDENTIAL Copyright © 2015 MarvellPage 58 Document Classification: Proprietary February 3, 2015, 1.0053 43 GPIO_29 I/O VDDIO_2 General Purpose I/O 29QSPI_CLK O QSPI ClockI2C0_SCL I/O I2C0 SCLGPT1_CH1 I/O General Purpose Timer 1, Channel 154 44 GPIO_30 I/O VDDIO_2 General Purpose I/O 30QSPI_D0 I/O QSPI Data 0UART0_CTSn I UART 0 CTSn (active low)SSP0_CLK I/O SSP 0 Serial ClockGPT1_CH2 I/O General Purpose Timer 1, Channel 255 45 GPIO_31 I/O VDDIO_2 General Purpose I/O 31QSPI_D1 I/O QSPI Data 1UART0_RTSn O UART 0 RTSn (active low)SSP0_FRM I/O SSP 0 Frame IndicatorGPT1_CH3 I/O General Purpose Timer 1, Channel 356 46 GPIO_32 I/O VDDIO_2 General Purpose I/O 32QSPI_D2 I/O QSPI Data 2UART0_TXD O UART 0 TXDSSP0_TXD O SSP 0 TXDGPT1_CH4 I/O General Purpose Timer 1, Channel 457 47 GPIO_33 I/O VDDIO_2 General Purpose I/O 33QSPI_D3 I/O QSPI Data 3UART0_RXD I UART 0 RXDSSP0_RXD I SSP 0 RXDGPT1_CH5 I/O General Purpose Timer 1, Channel 5Table 11: GPIO Interface 1 (Continued)288-Pin 68-Pin Pin/Signal Name Type Supply Description
xam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & ConMARVELL CONFIDENTIAL, UNDER NDA# 12150208m1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & Control InMARVELL CONFIDENTIAL, UNDER NDA# 121502082fdrxam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global NetPackagePin Description Copyright © 2015 Marvell CONFIDENTIAL Doc. No. MV-S109936-00 Rev. AFebruary 3, 2015, 1.00 Document Classification: Proprietary Page 5967 -- GPIO_34 I/O VDDIO_3 General Purpose I/O 34GPT3_CH5 I/O General Purpose Timer 3, Channel 568 -- GPIO_35 I/O VDDIO_3 General Purpose I/O 35GPT0_CLKIN I General Purpose Timer 0, Clock InputUART1_CTSn I UART 1 CTSn (active low)SSP1_CLK I/O SSP 1 Serial Clock69 -- GPIO_36 I/O VDDIO_3 General Purpose I/O 36GPT1_CLKIN I General Purpose Timer 1, Clock InputUART1_RTSn O UART 1 RTSn (active low)SSP1_FRM I/O SSP 1 Frame Indicator70 -- GPIO_37 I/O VDDIO_3 General Purpose I/O 37GPT2_CH5 I/O General Purpose Timer 2, Channel 5UART0_RTSn O UART 0 RTSn (active low)71 -- GPIO_38 I/O VDDIO_3 General Purpose I/O 38GPT2_CLKIN I General Purpose Timer 2, Clock InputUART1_TXD O UART 1 TXDSSP1_TXD O SSP 1 TXD72 52 GPIO_39 I/O VDDIO_3 General Purpose I/O 39GPT3_CLKIN I General Purpose Timer 2, Clock InputUART1_RXD I UART 1 RXDSSP1_RXD I SSP 1 RXDTable 11: GPIO Interface 1 (Continued)288-Pin 68-Pin Pin/Signal Name Type Supply Description
xam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & ConMARVELL CONFIDENTIAL, UNDER NDA# 12150208m1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & Control InMARVELL CONFIDENTIAL, UNDER NDA# 121502082fdrxam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Net88MW300/302 Datasheet Doc. No. MV-S109936-00 Rev. A CONFIDENTIAL Copyright © 2015 MarvellPage 60 Document Classification: Proprietary February 3, 2015, 1.0075 55 GPIO_40 I/O VDDIO_3 General Purpose I/O 40ADC_DAC_TRIGGER0 I ADC/DAC External Trigger 0ACOMP0_GPIO_OUT O ACOMP0 GPIO OutputACOMP0 output synchronous or asynchronous level signals.ACOMP1_GPIO_OUT O ACOMP1 GPIO OutputACOMP1 output synchronous or asynchronous level signals.76 56 GPIO_41 I/O VDDIO_3 General Purpose I/O 41ADC_DAC_TRIGGER1 I ADC/DAC External Trigger 1ACOMP0_EDGE_PULSEO ACOMP Edge Pulse 0Output pulse aligned with synchronized comparison result.ACOMP1_EDGE_PULSEO ACOMP Edge Pulse 1Output pulse aligned with synchronized comparison result.78 58 GPIO_42 I/O VDDIO_3 General Purpose I/O 42ADC0_0 / ACOMP0 / TS_INP / VOICE_PA, I ADC0 Channel 0ACOMP0 Channel 0ACOMP1 Channel 0Temperature sensor remote sensing positive inputVoice sensing positive inputUART1_CTSn I UART 1 CTSn (active low)SSP1_CLK I/O SSP 1 Serial ClockTable 11: GPIO Interface 1 (Continued)288-Pin 68-Pin Pin/Signal Name Type Supply Description
xam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & ConMARVELL CONFIDENTIAL, UNDER NDA# 12150208m1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & Control InMARVELL CONFIDENTIAL, UNDER NDA# 121502082fdrxam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global NetPackagePin Description Copyright © 2015 Marvell CONFIDENTIAL Doc. No. MV-S109936-00 Rev. AFebruary 3, 2015, 1.00 Document Classification: Proprietary Page 6179 59 GPIO_43 I/O VDDIO_3 General Purpose I/O 43ADC0_1 / ACOMP1 / TS_INN / DACB / VOICE_NA, I ADC0 Channel 1ACOMP0 Channel 1ACOMP1 Channel 1Temperature sensor remote sensing negative inputVoice sensing negative inputUART1_RTSn O UART 1 RTSn (active low)SSP1_FRM I/O SSP 1 Frame Indicator80 60 GPIO_44 I/O VDDIO_3 General Purpose I/O 44ADC0_2 / ACOMP2 / DACAA, I ADC0 Channel 2ACOMP0 Channel 2ACOMP1 Channel 2DAC Channel A outputUART1_TXD O UART 1 TXDSSP1_TXD O SSP 1 TXDRF_CNTL1_P O WLAN Radio Control 181 61 GPIO_45 I/O VDDIO_3 General Purpose I/O 45ADC0_3 / ACOMP3 / EXT_VREFA, I ADC0 Channel 3ACOMP0 Channel 3ACOMP1 Channel 3ADC or DAC external voltage reference inputUART1_RXD I UART 1 RXDSSP1_RXD I SSP 1 RXDRF_CNTL0_N O WLAN Radio Control 082 62 GPIO_46 I/O VDDIO_3 General Purpose I/O 46ADC0_4 / ACOMP4 A, I ADC0 Channel 4ACOMP0 Channel 4ACOMP1 Channel 4UART2_CTSn I UART 2 CTSn (active low)SSP2_CLK I/O SSP 2 Serial ClockTable 11: GPIO Interface 1 (Continued)288-Pin 68-Pin Pin/Signal Name Type Supply Description
xam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & ConMARVELL CONFIDENTIAL, UNDER NDA# 12150208m1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & Control InMARVELL CONFIDENTIAL, UNDER NDA# 121502082fdrxam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Net88MW300/302 Datasheet Doc. No. MV-S109936-00 Rev. A CONFIDENTIAL Copyright © 2015 MarvellPage 62 Document Classification: Proprietary February 3, 2015, 1.0083 63 GPIO_47 I/O VDDIO_3 General Purpose I/O 47ADC0_5 / ACOMP5 A, I ADC0 Channel 5ACOMP0 Channel 5ACOMP1 Channel 5UART2_RTSn O UART 2 RTSn (active low)SSP2_FRM I/O SSP 2 Frame Indicator84 64 GPIO_48 I/O VDDIO_3 General Purpose I/O 48ADC0_6 / ACOMP6 A, I ADC0 Channel 6ACOMP0 Channel 6ACOMP1 Channel 6UART2_TXD O UART 2 TXDSSP2_TXD O SSP 2 TXD85 65 GPIO_49 I/O VDDIO_3 General Purpose I/O 49ADC0_7 / ACOMP7 A, I ADC0 Channel 7ACOMP0 Channel 7ACOMP1 Channel 7UART2_RXD I UART 2 RXDSSP2_RXD I SSP 2 RXD1. GPIO_11 to GPIO_15, GPIO_17 to GPIO_21, GPIO_34 to GPIO_38 I/O and associated muxing available on 88-pin QFN only.2. All GPIO pins are pull-up high after POR.Table 11: GPIO Interface 1 (Continued)288-Pin 68-Pin Pin/Signal Name Type Supply Description
xam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & ConMARVELL CONFIDENTIAL, UNDER NDA# 12150208m1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & Control InMARVELL CONFIDENTIAL, UNDER NDA# 121502082fdrxam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global NetPackagePin Description Copyright © 2015 Marvell CONFIDENTIAL Doc. No. MV-S109936-00 Rev. AFebruary 3, 2015, 1.00 Document Classification: Proprietary Page 63 Table 12: Clock/Control Interface188-Pin 68-Pin Pin/Signal Name Type Supply Description26 21 XTAL_IN A, I AVDD18 Crystal Oscillator Input27 22 XTAL_OUT A, O AVDD18 Crystal Oscillator OutputConnect to ground when an external oscillator used.GPIO_25 XTAL32K_IN A, I VDDIO_AON 32.768 kHz Crystal InputGPIO_26 XTAL32K_OUT A, O VDDIO_AON 32.768 kHz Crystal OutputGPIO_22 WAKE_UP0 I VDDIO_AON Wake-Up 0GPIO_23 WAKE_UP1 I VDDIO_AON Wake-Up 1GPIO_4GPIO_16AUDIO_CLK VDDIO_0 Audio ClockAUPLL audio clock output provided by audio PLL for external codec.45 35 RESETn I VDDIO_AON Chip Reset (active low)1. The XTAL32K_IN/OUT and WAKE_UP0/1 signals are muxed on GPIO pins. See Table 11, GPIO Interface, on page 53 for GPIO muxing.
xam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & ConMARVELL CONFIDENTIAL, UNDER NDA# 12150208m1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & Control InMARVELL CONFIDENTIAL, UNDER NDA# 121502082fdrxam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Net88MW300/302 Datasheet Doc. No. MV-S109936-00 Rev. A CONFIDENTIAL Copyright © 2015 MarvellPage 64 Document Classification: Proprietary February 3, 2015, 1.00 Table 13: ADC/DAC/ACOMP Interface188-Pin 68-Pin Pin Name Type Supply DescriptionGPIO_40 ACOMP0_GPIO_OUT O VDDIO_3 ACOMP0 GPIO OutputACOMP0 output synchronous or asynchronous level signalsACOMP1_GPIO_OUT O VDDIO_3 ACOMP1 GPIO OutputACOMP1 output synchronous or asynchronous level signalsADC_DAC_TRIGGER0 I VDDIO_3 ADC/DAC External Trigger 0GPIO_41 ACOMP0_EDGE_PULSE O VDDIO_3 ACOMP Edge Pulse 0Output pulse aligned with synchronized comparison result.ACOMP1_EDGE_PULSE O VDDIO_3 ACOMP Edge Pulse 1Output pulse aligned with synchronized comparison result.ADC_DAC_TRIGGER1 I VDDIO_3 ADC/DAC External Trigger 1GPIO_49 ADC0_7 / ACOMP7 A, I VDDIO_3 ADC0 Channel 7ACOMP0 Channel 7ACOMP1 Channel 7GPIO_48 ADC0_6 / ACOMP6 A, I VDDIO_3 ADC0 Channel 6ACOMP0 Channel 6ACOMP1 Channel 6GPIO_47 ADC0_5 / ACOMP5 A, I VDDIO_3 ADC0 Channel 5ACOMP0 Channel 5ACOMP1 Channel 5GPIO_46 ADC0_4 / ACOMP4 A, I VDDIO_3 ADC0 Channel 4ACOMP0 Channel 4ACOMP1 Channel 4GPIO_45 ADC0_3 / ACOMP3 / EXT_VREFA, I VDDIO_3 ADC0 Channel 3ACOMP0 Channel 3ACOMP1 Channel 3ADC or DAC external voltage reference inputGPIO_44 ADC0_2 / ACOMP2 / DACAA, I VDDIO_3 ADC0 Channel 2ACOMP0 Channel 2ACOMP1 Channel 2DAC Channel A output
xam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & ConMARVELL CONFIDENTIAL, UNDER NDA# 12150208m1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & Control InMARVELL CONFIDENTIAL, UNDER NDA# 121502082fdrxam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global NetPackagePin Description Copyright © 2015 Marvell CONFIDENTIAL Doc. No. MV-S109936-00 Rev. AFebruary 3, 2015, 1.00 Document Classification: Proprietary Page 65 GPIO_43 ADC0_1 / ACOMP1 / TS_INN / DACB / VOICE_NA, I VDDIO_3 ADC0 Channel 1ACOMP0 Channel 1ACOMP1 Channel 1Temperature sensor remote sensing negative inputVoice sensing negative inputGPIO_42 ADC0_0 / ACOMP0 / TS_INP / VOICE_PA, I VDDIO_3 ADC0 Channel 0ACOMP0 Channel 0ACOMP1 Channel 0Temperature sensor remote sensing positive inputVoice sensing positive input1. All ADC/DAC/ACOMP signals are muxed on GPIO pins. See Table 11, GPIO Interface, on page 53 for GPIO muxing.Table 13: ADC/DAC/ACOMP Interface1 (Continued)88-Pin 68-Pin Pin Name Type Supply DescriptionTable 14: LDO18 Comparator Interface188-Pin 68-Pin Pin Name Type Supply DescriptionGPIO_23 COMP_IN_P A, I VDDIO_AON LDO18 Comparator Input, PositivePositive input to LDO18 comparator.GPIO_24 COMP_IN_N A, I VDDIO_AON LDO18 Comparator Input, NegativePositive input to LDO18 comparator.1. All COMP signals are muxed on GPIO pins. See Table 11, GPIO Interface, on page 53 for GPIO muxing.Table 15: JTAG Interface188-Pin 68-Pin Signal Name Type Supply DescriptionGPIO_6 TDO O VDDIO_0 JTAG Test Data GPIO_7 TCK I VDDIO_0 JTAG Test Clock GPIO_8 TMS I/O VDDIO_0 JTAG Controller Select GPIO_9 TDI I VDDIO_0 JTAG Test Data GPIO_10 TRSTn I VDDIO_0 JTAG Test Reset I/O (active low) 1. All JTAG signals are muxed on GPIO pins. See Table 11, GPIO Interface, on page 53 for GPIO muxing.
xam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & ConMARVELL CONFIDENTIAL, UNDER NDA# 12150208m1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & Control InMARVELL CONFIDENTIAL, UNDER NDA# 121502082fdrxam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Net88MW300/302 Datasheet Doc. No. MV-S109936-00 Rev. A CONFIDENTIAL Copyright © 2015 MarvellPage 66 Document Classification: Proprietary February 3, 2015, 1.00 Table 16: Power and GroundNOTE: See Section 22.2, Recommended Operating Conditions, on page 314 for ratings.88-Pin 68-Pin Pin Name Type Description33592849VDD11 PWR 1.1V Core Power Supply Input 5 5 VDDIO_0 PWR I/O Digital Power Supply 34 29 VDDIO_158 48 VDDIO_277 57 VDDIO_373 5351 41 VDDIO_AON60 50 VTR_VDD33 PWR 3.3V OTP Analog Power Supply63 -- USB_AVDD33 PWR 3.3V USB Analog Power Supply74 54 ISENSE -- USB Current SourceConnect pin to ground with resistance.20 15 AVDD33 PWR 3.3V Analog Power Supply181923242528131418192023AVDD18 PWR 1.8V Analog Power Supply41 31 LDO11_VOUT PWR 1.1V LV LDO Voltage Output42 32 LDO11_V18 -- BUCK18 Inductor Connection43 33 BUCK18_VX -- BUCK18 Inductor Connection44873467VBAT_IN PWR LDO VBAT Input This pin must be connected to VBAT/V33 input even if BUCK18 is not used. 86 66 FLY18 -- 1.8V LDO Fly Capacitor to Ground Connection 88 68 FLY11 -- 1.1V LDO Fly Capacitor to Ground Connection 22 17 NC NC No ConnectNOTE: CONNECT THESE PINS to GROUND.2930313224252627DNC DNC Do Not ConnectDo not connect these pins. Leave these pins floating.
xam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & ConMARVELL CONFIDENTIAL, UNDER NDA# 12150208m1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global Network Lighting & Control InMARVELL CONFIDENTIAL, UNDER NDA# 121502082fdrxam1uypvwincml8vcyp7azhga8189kcblgwl8g12a4v3hp-i72ogizr * Global NetPackageConfiguration Pins Copyright © 2015 Marvell CONFIDENTIAL Doc. No. MV-S109936-00 Rev. AFebruary 3, 2015, 1.00 Document Classification: Proprietary Page 671.5 Configuration PinsTable 17 shows the pins used as configuration inputs to set parameters following a reset. The definition of these pins changes immediately after reset to their usual function. To set a configuration bit to 0, attach a 100 kΩ resistor from the pin to ground. No external circuitry is required to set a configuration bit to 1. Table 17: Configuration PinsConfiguration Bits Pin Name Configuration FunctionCON[5] GPIO_16 Boot Options 00 = boot from UART01 = reserved 10 = boot from USB 11 = boot from Flash (default) CON[4] GPIO_27
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment. NOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures: -- Reorient or relocate the receiving antenna. -- Increase the separation between the equipment and receiver. -- Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. -- Consult the dealer or an experienced radio/TV technician for help. FCC Radiation Exposure Statement The modular can be installed or integrated in mobile or fix devices only. This modular cannot be installed in any portable device, for example, USB dongle like transmitters is forbidden. This modular complies with FCC RF radiation exposure limits set forth for an uncontrolled environment. This transmitter must not be co-located or operating in conjunction with any other antenna or transmitter. This modular must be installed and operated with a minimum distance of 20 cm between the radiator and user body. If the FCC identification number is not visible when the module is installed inside another device, then the outside of the device into which the module is installed must also display a label referring to the enclosed module. This exterior label can use wording such as the following: “Contains Transmitter Module FCC ID: YCJGTIMW302" or "Contains FCC ID: YCJGTIMW302” when the module is installed inside another device, the user manual of this device must contain below warning statements; 1. This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:(1) This device may not cause harmful interference. (2) This device must accept any interference received, including interference that may cause undesired operation. 2. Changes or modifications not expressly approved by the party responsible for compliance could void the user'sauthority to operate the equipment. This device must be installed and operated with a minimum distance of 20 cm between the radiator and user body.

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