Globalscale Technologies GTIMW302 GTI MW302 Module User Manual 88MW300 302 Datasheet
Globalscale Technologies INC GTI MW302 Module 88MW300 302 Datasheet
User manual
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| Document ID | 2777835 |
| Application ID | ye/KC/jDg/XQTO7VUNzSjQ== |
| Document Description | User manual |
| Short Term Confidential | No |
| Permanent Confidential | No |
| Supercede | No |
| Document Type | User Manual |
| Display Format | Adobe Acrobat PDF - pdf |
| Filesize | 35.46kB (443244 bits) |
| Date Submitted | 2015-10-11 00:00:00 |
| Date Available | 2015-10-11 00:00:00 |
| Creation Date | 2015-09-21 10:38:10 |
| Producing Software | Acrobat Distiller 7.0 (Windows) |
| Document Lastmod | 2015-10-11 09:55:20 |
| Document Title | 88MW300/302 Datasheet |
| Document Creator | PScript5.dll Version 5.2 |
| Document Author: | Marvell Technology Group |
Doc. No. MV-S109936-00, Rev. A
February 3, 2015, 1.00
CONFIDENTIAL
Document Classification: Proprietary
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Datasheet
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IEEE 802.11n/g/b
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WLAN Microcontroller
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88MW300/302
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Cover
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88MW300/302
Datasheet
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Document Conventions
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Note: Provides related information or information of special importance.
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Caution: Indicates potential damage to hardware or software, or loss of data.
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Warning: Indicates a risk of personal injury.
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Doc Status: 1.00
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Document Status
Technical Publication: 0.xx
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Disclaimer
No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, for any purpose,
without the express written permission of Marvell. Marvell retains the right to make changes to this document at any time, without notice. Marvell makes no warranty of any
kind, expressed or implied, with regard to any information contained in this document, including, but not limited to, the implied warranties of merchantability or fitness for any
particular purpose. Further, Marvell does not warrant the accuracy or completeness of the information, text, graphics, or other items contained within this document.
Marvell products are not designed for use in life-support equipment or applications that would cause a life-threatening situation if any such products failed. Do not use
Marvell products in these types of equipment or applications.
With respect to the products described herein, the user or recipient, in the absence of appropriate U.S. government authorization, agrees:
1) Not to re-export or release any such information consisting of technology, software or source code controlled for national security reasons by the U.S. Export Control
Regulations ("EAR"), to a national of EAR Country Groups D:1 or E:2;
2) Not to export the direct product of such technology or such software, to EAR Country Groups D:1 or E:2, if such technology or software and direct products thereof are
controlled for national security reasons by the EAR; and,
3) In the case of technology controlled for national security reasons under the EAR where the direct product of the technology is a complete plant or component of a plant,
not to export to EAR Country Groups D:1 or E:2 the direct product of the plant or major component thereof, if such direct product is controlled for national security reasons
by the EAR, or is subject to controls under the U.S. Munitions List ("USML").
At all times hereunder, the recipient of any such information agrees that they shall be deemed to have manually signed this document in connection with their receipt of any
such information.
Copyright © 1999–2015. Marvell International Ltd. All rights reserved. Alaska, ARMADA, Avanta, Avastar, CarrierSpan, Kinoma, Link Street, LinkCrypt, Marvell logo,
Marvell, Moving Forward Faster, Marvell Smart, PISC, Prestera, Qdeo, QDEO logo, QuietVideo, Virtual Cable Tester, The World as YOU See It, Vmeta, Xelerated, and
Yukon are registered trademarks of Marvell or its affiliates. G.now, HyperDuo, Kirkwood, and Wirespeed by Design are trademarks of Marvell or its affiliates.
Patent(s) Pending—Products identified in this document may be covered by one or more Marvell patents and/or patent applications.
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Doc. No. MV-S109936-00 Rev. A
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For more information, visit our website at: http://www.marvell.com
CONFIDENTIAL
Document Classification: Proprietary
Copyright © 2015 Marvell
February 3, 2015, 1.00
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88MW300/302
WLAN Microcontroller
Datasheet
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PRODUCT OVERVIEW
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The SoC provides a full array of peripheral interfaces
including SSP/SPI/I2S (3x), UART (3x), I2C (2x), General
Purpose Timers and PWM, ADC, DAC, Analog
Comparator, and GPIOs. It also includes a hardware
cryptographic engine, RTC, and Watchdog Timer. The
88MW302 includes a high speed USB On-The-Go
(OTG) interface to enable USB audio, video, and other
applications.
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The 88MW300/302 application subsystem is powered by
an ARM Cortex-M4F CPU that operates up to 200 MHz.
The device supports an integrated 512 KB SRAM,
128 KB mask ROM, and a QSPI interface to external
Flash. An integrated Flash Controller with a 32 KB
SRAM cache enables eXecute In Place (XIP) support for
firmware from Flash.
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A complete set of digital and analog interfaces enable
direct interfacing for I/O avoiding the need for external
chips. The application CPU can be used to support
custom application development avoiding the need for
another microcontroller or processor.
Figure 1 shows an overall block diagram of the device.
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The SoC includes a full-featured W LAN subsystem
powered by proven and mature IEEE 802.11n/g/b
Marvell technology. The WLAN subsystem integrates a
WLAN MAC, baseband, and direct-conversion RF radio
with integrated PA, LNA, and transmit/receive switch. It
also integrates a CPU subsystem with integrated
memory to run Marvell WLAN firmware to handle real
time WLAN protocol processing to off-load many WLAN
functions from the main application CPU.
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A high degree of integration enables very low system
costs requiring only a single 3.3V power input, a
38.4 MHz crystal, and SPI Flash. The RF path needs
only a lowpass filter for antenna connection.
The SoC is designed for low-power operation and
includes several low-power states and fast wake-up
times. Multiple power domains and clocks can be
individually shut down to save power. The SoC also has
a high-efficiency internal PA that can be operated in
low-power mode to save power. The microcontroller and
WLAN subsystems can be placed into low-power states,
independently, supporting a variety of application use
cases. An internal DC-DC regulator provides the 1.8V
rail for the WLAN subsystem.
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The Marvell® 88MW300/302 is a highly integrated,
low-power WLAN Microcontroller System-on-Chip (SoC)
solution designed for a broad array of smart devices for
Internet of Things (IoT), wearables, accessories,
Machine-to-Machine (M2M), home automation, and
Smart Energy applications
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Copyright © 2015 Marvell
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February 3, 2015, 1.00
CONFIDENTIAL
Document Classification: Proprietary
Doc. No. MV-S109936-00 Rev. A
Page 3
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88MW300/302
Datasheet
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Figure 1: Block Diagram
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88MW300/302
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Code RAM1
S1
Data RAM0
S2
Data RAM1
S3
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M4
DAC
I2C
ACOMP
PMU
4k SRAM
GPIO
Timer/PWM
X2/12
Digital
Analog
I/O
Direct
Conversion
WLAN RF
1x1 SISO
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802.11
Baseband
(DSSS/OFDM,
1x1 SISO)
PA
2.4 GHz
AES/CRC
T/R
Switch
LNA
Security/Encryption
Highly integrated SoC requiring very few external
components for a full system operation
Multiple low-power modes and fast wake-up times
Full-featured, single stream 802.11n/g/b WLAN
High-efficiency PA with a low-power (10 dB) mode
Cortex-M4F application CPU for applications with
integrated 512 KB SRAM and 128 KB mask ROM
Flash Controller with embedded 32 KB SRAM
cache to support XIP from external SPI Flash
Secure boot
Full set of digital and analog I/O interfaces
Power Management
Power modes—active, idle, standby, sleep, shutoff,
power-down
Integrated high efficiency buck DC-DC converter
Independent power domains
Brownout detection
Integrated POR
Wake-up through dedicated GPIO, IRQ, and RTC
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White goods/appliances—refrigerator, washer,
dryer, oven range, microwave, dishwasher, water
heater, air conditioner
Consumer devices and accessories—toys,
speakers, headset, alarm clock, gaming accessory,
remote control
Home automation—smart outlet, light switch,
security camera, thermostat, sprinkler controller,
sensor, door lock, door bell, garage door, security
system
Personal health devices—weighing scale,
glucometer, blood pressure monitor, fitness
equipment
IoT/wearables—coffee pot, rice cooker, vacuum
cleaner, air purifier, smart watch, fitness bracelet,
pet monitor
Commercial/industrial—lighting, building
automation, asset management, Point of Sale
(POS) sales
Gateways—Connecting IR, sub-Gig or Legacy RF,
Bluetooth Smart, ZigBee, ZWave and other radios to
Wi-Fi/IP network
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Doc. No. MV-S109936-00 Rev. A
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AHB
decode
802.11 MAC
Tx/Rx 1x1
SISO
Key Features
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Applications
S8
PHY
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UART
ROM
USB
Controller
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WDT
JTAG
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ADC/T-Sens
SRAM/
ROM
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I/O Multiplexer
SSP/SPI/I2S
Feroceon
CPU
DMA
Controller
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SSP/SPI/I2S
V11
PLL
M3
RTC
Digital
Analog
I/O
AHB Bus
Fabric
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Digital
Analog
I/O
UART
V18
32 kHz GEN
APB1
LDO11
32 MHz GEN
S5
PINMUX
WL_MCI_REFCLK
QSPI
BUCK18
FPU
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APB0
I2C
MPU
S4
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Flash/Cache
Controller
S6
NVIC
M2
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Digital
Analog
I/O
VDD Power
Management
Cortex-M4
M1
32 KB
SRAM
WLAN
JTAG SWD
M0
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V12
S0
2f
V18
hg
LDO12
Digital
Analog
I/O
Code RAM0
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LDO18
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Digital
Analog
I/O
Microcontroller
CONFIDENTIAL
Document Classification: Proprietary
Copyright © 2015 Marvell
February 3, 2015, 1.00
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Package
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Signal Diagram
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Package
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Signal Diagram
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Figure 2: Signal Diagram1 2 3 4
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88MW300/302
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ID 8g1
EN 2a
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COMP_IN_P
COMP_IN_N
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WAKE_UP0
WAKE_UP1
AUDIO_CLK
RESETn
LDO18
Comparator
Interface
UARTx_RXD
UARTx_TXD
UARTx_CTSn
UARTx_RTSn
UART Interface
(UART0-UART2)
GPTx_CHx
GPT_CLKIN
GPT Interface
(GPT 0-GPT3,
Ch0-5 each)
SSPx_CLK
SSPx_FRM
SSPx_TXD
SSPx_RXD
SSP Interface
(SSP0-SSP2)
I2Cx_SDA
I2Cx_SCL
I2C Interface
(I2C0-I2C1)
ADC/ACOMP Interface
(ADC0, Ch0-7)
DAC Interface
Temperature
Sensor Interface
Voice
QSPI_SSn
QSPI_CLK
QSPI_D0
QSPI_D1
QSPI_D2
QSPI_D3
QSPI Interface
GPIO_0 to GPIO_49
GPIO Interface
JTAG Interface
ACOMP0_GPIO_OUT
ACOMP1_GPIO_OUT
ACOMP0_EDGE_PULSE
ACOMP1_EDGE_PULSE
ADC_DAC_TRIGGER0
ADC_DAC_TRIGGER1
EXT_VREF
ADC0_x / ACOMPx
DACB
DACA
TS_INP
TS_INN
VOICE_N
VOICE_P
TDO
TCK
TMS
TDI
TRSTn
1. Signals are muxed on dedicated pins. See Section 1.4, Pin Description, on page 46 for dedicated pin / muxed signal descriptions.
2. Some pins/signals are available on the 88-pin QFN only. See Section 1.4, Pin Description, on page 46.
3. RF_TR, USB OTG, XTAL_IN/OUT, and RESETn pins are dedicated. Others are muxed on GPIOs.
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4. See Table 16, Power and Ground, on page 66 for power signals.
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Copyright © 2015 Marvell
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USB OTG 2.0 Interface
XTAL32K_IN
XTAL32K_OUT
Li
Clock/Control
Interface
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WLAN RF Front End
Interface
USB_VBUS
USB_DRV_VBUS
USB_ID
USB_DP
USB_DM
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RF_CNTL1_P
RF_CNTL0_N
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WLAN RF Interface
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RF_TR
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XTAL_IN
XTAL_OUT
CONFIDENTIAL
Document Classification: Proprietary
Doc. No. MV-S109936-00 Rev. A
Page 41
Doc. No. MV-S109936-00 Rev. A
GPIO_2
GPIO_3
VDDIO_0
GPIO_1
61
62
64
88MW300
66
20
67
68
19
18
1. Connect pin 17 to ground.
Document Classification: Proprietary
CONFIDENTIAL
17
58
16
57
15
14
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31
30
29
28
27
26
25
24
23
22
21
VDD11
DNC
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56
13
12
11
10
7a
GPIO_4
GPIO_5
M g
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GPIO_6
VE 18
GPIO_7
LL 9kc
GPIO_8
GPIO_9
CO blg
GPIO_10
NF l
ID 8g1 AVDD18
EN 2AVDD18
a4
TI AVDD33
v3
ALRF_TR
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65
GPIO_49
FLY18
VBAT_IN
FLY11
GPIO_0
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GPIO_47
GPIO_48
54
2f
51
45
46
18
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GPIO_24
GPIO_23
GPIO_22
RESETn
38
37
36
35
39
40
41
42
43
44
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BUCK18_VX
LDO11_V18
LDO11_VOUT
GPIO_16
VDDIO_1
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VBAT_IN
33
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34
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47
48
49
50
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Pinout
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60
53
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GPIO_27
ID 8g1
EN 2a
VTR_VDD33
TI 4v
VDD11
AL 3h
, U p- VDDIO_2
ND i72GPIO_33
og
ER GPIO_32
GPIO_31
NDizr *
GPIO_30
A# Gl
GPIO_29
GPIO_28 12 ba
1 lN
VDDIO_AON 5
02 e
GPIO_26
08 two
GPIO_25
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Figure 3: Pinout—68-Pin QFN1
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GPIO_44
GPIO_45
GPIO_46
59
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55
GPIO_40
GPIO_41
VDDIO_3
GPIO_42
GPIO_43
52
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GPIO_39
VDDIO_3
ISENSE
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88MW300/302
Datasheet
Pinout—68-Pin QFN
DNC
DNC
DNC
AVDD18
XTAL_OUT
XTAL_IN
AVDD18
AVDD18
AVDD18
Copyright © 2015 Marvell
February 3, 2015, 1.00
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February 3, 2015, 1.00
GPIO_4
GPIO_5
GPIO_6
GPIO_7
80
81
1. Connect pin 22 to ground.
77
82
88MW302
84
26
25
87
88
24
23
Document Classification: Proprietary
CONFIDENTIAL
22
21
20
76
19
18
17
16
73
15
42
41
pv
40
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39
am
38
37
36
35
31
34
GPIO_19
GPIO_18
GPIO_17
GPIO_16
VDDIO_1
33
VDD11
32
DNC
DNC
30
29
28
27
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VBAT_IN
BUCK18_VX
LDO11_V18
LDO11_VOUT
GPIO_21
GPIO_20
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72
14
13
71
12
11
10
7a
M zhg
GPIO_8
AR a8
GPIO_9
VE 18
GPIO_10
LL 9kc
GPIO_11
CO blg GPIO_12
NF wl GPIO_13
ID 8gGPIO_14
12
ENGPIO_15
a4
TAVDD18
AL v3h
AVDD18
AVDD33,
UN p-i7
RF_TR
DE 2o
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12 oba
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02 e
08 two
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70
2f
66
63
64
65
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
18
kc
GPIO_26
GPIO_25
GPIO_24
GPIO_23
GPIO_22
RESETn
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Pinout—88-Pin QFN
dr
69
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Copyright © 2015 Marvell
86
GPIO_3
VDDIO_0
85
FLY18
VBAT_IN
FLY11
GPIO_49
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83
GPIO_47
GPIO_48
GPIO_43
GPIO_44
GPIO_45
GPIO_46
79
GPIO_1
GPIO_2
78
GPIO_0
GPIO_42
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75
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M zhg
AR a8
VE 18
LL 9kc
CO blg
GPIO_27
NF wl
USB_DM
ID 8g1
USB_DP
EN 2a
USB_AVDD33
TI 4v
USB_ID
AL 3h
USB_VBUS
, U pVTR_VDD33
ND 72 VDD11
ER og VDDIO_2
NDizGPIO_33
r*
AGPIO_32
# Glo
GPIO_31
12 ba
GPIO_30
1 lN
GPIO_29 50
20 etw
GPIO_28
8 o
VDDIO_AON
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Figure 4: Pinout—88-Pin QFN1
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GPIO_40
GPIO_41
VDDIO_3
68
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ISENSE
67
blg
GPIO_34
GPIO_35
GPIO_36
GPIO_37
GPIO_38
GPIO_39
VDDIO_3
hg
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1.2.2
Package
Pinout
DNC
DNC
AVDD18
XTAL_OUT
XTAL_IN
AVDD18
AVDD18
AVDD18
Doc. No. MV-S109936-00 Rev. A
Page 43
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Copyright © 2015 Marvell
February 3, 2015, 1.00
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Note: QFN package uses Epad size Option #3 only. See Section 22.4, Package Thermal Conditions, on page 315 for electrical
specifications. See Section 23.2, Package Marking, on page 336 for package marking.
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Figure 5: Mechanical Drawing—68-Pin QFN
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Document Classification: Proprietary
Mechanical Drawing—68-Pin QFN
EN
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1.3.1
ID
cm
CONFIDENTIAL
cm
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Doc. No. MV-S109936-00 Rev. A
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Mechanical Drawing
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1.3
88MW300/302
Datasheet
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Doc. No. MV-S109936-00 Rev. A
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vw
l8
xa
In
nt
ro
Note: QFN package uses Epad size Option #3 only. See Section 22.4, Package Thermal Conditions, on page 315 for electrical
specifications. See Section 23.2, Package Marking, on page 336 for package marking.
-U
1u
AL
cm
CONFIDENTIAL
cm
Figure 6: Mechanical Drawing—88-Pin QFN
CO
NF
cy
February 3, 2015, 1.00
p7
M zh
AR ga8
E 189
L kcb
F l
DE8g1
TI a4v
L, 3hp
N -i72
E og
N izr
A * Gl
1 ob
15 al N
20 etw
rk
Copyright © 2015 Marvell
AR
VE
LL
vw
vc
7a
M zh
AR ga8
E 189
L kcb
F l
DE8g1
TI a4v
L, 3hp
N -i72
E og
N izr
A *
Mechanical Drawing—88-Pin QFN
ti
ig
Co
ng
1.3.2
Mechanical Drawing
Package
RI
ZE
ST
DI
RI
BU
US
RI
ST
TL
n
Co
lo
al
giz
Pin Description
7a
M zhg
AR a8
VE 18
LL 9kc
CO blg
NF wl
ID 8g1
EN 2a
TI 4v
AL 3h
, U pND i72
ER og
NDizr *
A# Gl
12 oba
15 l N
02 e
08 two
Pin Types
P i n Ty p e
Description
l8
blg
Digital input
kc
18
hg
A, I
Analog input
A, O
Analog output
NC
No connect
DNC
Do not connect
PWR
Power
Ground
Ground
tin
gh
am
dr
7a
M zhg
AR a8
VE 18
LL 9kc
CO blg
NF wl
ID 8g1
EN 2a
TI 4v
AL 3h
, U pND i72
ER og
NDizr *
A# Gl
12 oba
15 l N
02 e
08 two
rk
Li
2f
Pin Name
Ty p e
Supply
Description
21
16
RF_TR
A, I/O
AVDD18
WLAN RF Interface (2.4 GHz Transmit/Receive)
Baseband input/output data
vc
yp
8 8 -P in
l8
pv
6 8 -P in
nc
Co
WLAN RF Interface
8 8 -P in
Table 4:
WLAN RF Front End Interface
68-Pin
P in N a m e
Ty p e
Supply
D e s c r i p t io n
GPIO_44
RF_CNTL1_P
A, O
VDDIO_3
WLAN Radio Control 1
Power-down output high signal
GPIO_45
RF_CNTL0_N
A, O
VDDIO_3
WLAN Radio Control 0
Power-down output low signal
l8
cy
am
1u
yp
wi
nt
ro
az
yp
Table 3:
Digital output
1u
g1
Digital input/output
hp
4v
I/O
wi
nc
-i7
Table 2:
l8v
*G
1.4
rk
Li
gh
tin
88MW300/302
Datasheet
wi
nc
Doc. No. MV-S109936-00 Rev. A
1u
yp
Page 46
CONFIDENTIAL
Document Classification: Proprietary
Copyright © 2015 Marvell
February 3, 2015, 1.00
n
Co
lo
al
tin
Package
gh
Pin Description
giz
Li
rk
USB 2.0 OTG Interface1
*G
-i7
7a
M zhg
AR a8
VE 18
LL 9kc
CO blg
NF wl
ID 8g1
EN 2a
TI 4v
AL 3h
, U pND i72
ER og
NDizr *
A# Gl
12 oba
15 l N
02 e
08 two
Table 5:
hp
Ty p e
Supply
Description
USB_VBUS
A, I/O
USB_AVDD33
USB VBUS Selection Input In Device Mode
Unused in host mode; I/O for OTG mode to
supply +5V@10mA during session
negotiation.
A, O
VDDIO_3
Drive 5V on VBUS
0 = do not drive VBUS
1 = drive 5V on VBUS
The USB_DRV_VBUS port is connected to
the SoC pad to drive an external power
management chip to provide power for USB
VBUS.
kc
--
USB_ID
A, I
USB_AVDD33
--
USB_AVDD33
A, I
--
--
USB_DP
A, I/O
USB_AVDD33
--
USB_DM
hg
az
yp
l8v
pv
USB 3.3V Analog Power Supply
See Table 16, Power and Ground, on
page 66.
am
dr
2f
USB 2.0 Bus Data+
7a
M zhg
AR a8
VE 18
LL 9kc
CO blg
NF wl
ID 8g1
EN 2a
TI 4v
AL 3h
, U pND i72
ER og
NDizr *
A# Gl
12 oba
15 l N
02 e
08 two
65
1u
64
wi
nc
63
USB 2.0 OTG IDPIN
62
tin
USB_DRV_VBUS
gh
18
--
Li
l8
blg
GPIO_27
rk
--
Co
Pin Name
68-Pin
g1
61
4v
8 8 -P in
nt
ro
NOTE: Available on 88-pin package only (88MW302)
A, I/O
USB_AVDD33
USB 2.0 Bus Data–
1. After POR, if USB is in host mode, USB_DPUSB_DM will be SE0. If USB is in device mode, USB_DP/USB_DM will be High-z.
Table 6:
68-Pin
Signal Name
UART0_CTSn
GPIO_1
UART0_RTSn
GPIO_2
UART0_TXD
GPIO_3
UART0_RXD
GPIO_23
UART0_CTSn
GPIO_24
UART0_RXD
GPIO_30
UART0_CTSn
GPIO_31
UART0_RTSn
GPIO_32
UART0_TXD
GPIO_33
UART0_RXD
Ty p e
Supply
D e s c r i p t io n
VDDIO_0
UART 0 CTSn (active low)
VDDIO_0
UART 0 RTSn (active low)
VDDIO_0
UART 0 TXD
VDDIO_0
UART 0 RXD
VDDIO_AON
UART 0 CTSn (active low)
VDDIO_AON
UART 0 RXD
VDDIO_2
UART 0 CTSn (active low)
VDDIO_2
UART 0 RTSn (active low)
VDDIO_2
UART 0 TXD
VDDIO_2
UART 0 RXD
l8
cy
GPIO_0
wi
nc
Copyright © 2015 Marvell
1u
yp
February 3, 2015, 1.00
am
1u
yp
wi
nc
l8
vc
yp
8 8 -P in
UART Interface1
CONFIDENTIAL
Document Classification: Proprietary
Doc. No. MV-S109936-00 Rev. A
Page 47
n
Co
lo
al
giz
rk
Li
gh
tin
88MW300/302
Datasheet
UART Interface1
7a
M zhg
AR a8
VE 18
LL 9kc
CO blg
NF wl
ID 8g1
EN 2a
TI 4v
AL 3h
, U pND i72
ER og
NDizr *
A# Gl
12 oba
15 l N
02 e
08 two
Signal Name
Ty p e
Supply
D e s c r i p t io n
--
UART0_RTSn
VDDIO_3
UART 0 RTSn (active low)
UART0_TXD
VDDIO_3
UART 0 TXD
VDDIO_0
UART 1 CTSn (active low)
VDDIO_0
UART 1 RTSn (active low)
yp
VDDIO_0
UART 1 TXD
VDDIO_0
UART 1 RXD
GPIO_27
l8
blg
kc
18
hp
4v
GPIO_37
68-Pin
-i7
8 8 -P in
g1
--
UART1_CTSn
GPIO_12
--
UART1_RTSn
GPIO_13
--
UART1_TXD
GPIO_14
--
UART1_RXD
GPIO_35
--
UART1_CTSn
VDDIO_3
GPIO_36
--
UART1_RTSn
VDDIO_3
GPIO_38
--
UART1_TXD
VDDIO_3
UART 1 TXD
GPIO_39
UART1_RXD
VDDIO_3
UART 1 RXD
GPIO_42
UART1_CTSn
VDDIO_3
UART 1 CTSn (active low)
GPIO_43
UART1_RTSn
VDDIO_3
UART 1 RTSn (active low)
GPIO_44
UART1_TXD
VDDIO_3
UART 1 TXD
GPIO_45
UART1_RXD
VDDIO_3
UART 1 RXD
VDDIO_0
UART 2 CTSn (active low)
VDDIO_0
UART 2 RTSn (active low)
VDDIO_0
UART 2 TXD
VDDIO_0
UART 2 RXD
VDDIO_3
UART 2 CTSn (active low)
VDDIO_3
UART 2 RTSn (active low)
VDDIO_3
UART 2 TXD
VDDIO_3
UART 2 RXD
Co
nt
ro
GPIO_11
l8v
hg
az
*G
Table 6:
UART2_RXD
GPIO_46
UART2_CTSn
GPIO_47
UART2_RTSn
GPIO_48
UART2_TXD
GPIO_49
UART2_RXD
tin
gh
Li
rk
7a
M zhg
AR a8
VE 18
LL 9kc
CO blg
NF wl
ID 8g1
EN 2a
TI 4v
AL 3h
, U pND i72
ER og
NDizr *
A# Gl
12 oba
15 l N
02 e
08 two
l8
l8
cy
1. All UART signals are muxed on GPIO pins. See Table 11, GPIO Interface, on page 53 for GPIO muxing.
wi
nc
Doc. No. MV-S109936-00 Rev. A
1u
yp
Page 48
nc
wi
am
1u
yp
GPIO_10
2f
UART2_TXD
am
GPIO_9
UART 1 RTSn (active low)
dr
UART2_RTSn
pv
GPIO_8
1u
vc
yp
UART2_CTSn
wi
nc
GPIO_7
UART 1 CTSn (active low)
CONFIDENTIAL
Document Classification: Proprietary
Copyright © 2015 Marvell
February 3, 2015, 1.00
n
Co
gh
tin
lo
al
giz
Li
D e s c ri p ti o n
GPT0_CH0
I/O
VDDIO_0
General Purpose Timer 0, Channel 0
GPT0_CH1
I/O
VDDIO_0
General Purpose Timer 0, Channel 1
GPT0_CH2
I/O
VDDIO_0
General Purpose Timer 0, Channel 2
I/O
VDDIO_0
General Purpose Timer 0, Channel 3
I/O
VDDIO_0
General Purpose Timer 0, Channel 4
VDDIO_0
General Purpose Timer 0, Channel 5
VDDIO_3
General Purpose Timer 0, Clock Input
GPT0_CH5
az
GPT0_CLKIN
GPIO_28
GPT1_CH0
I/O
VDDIO_2
GPIO_29
GPT1_CH1
I/O
VDDIO_2
GPIO_30
GPT1_CH2
I/O
VDDIO_2
GPIO_31
GPT1_CH3
I/O
VDDIO_2
General Purpose Timer 1, Channel 3
GPIO_32
GPT1_CH4
I/O
VDDIO_2
General Purpose Timer 1, Channel 4
GPIO_33
GPT1_CH5
I/O
VDDIO_2
General Purpose Timer 1, Channel 5
GPIO_24
GPT1_CH5
I/O
VDDIO_AON
General Purpose Timer 1, Channel 5
VDDIO_3
General Purpose Timer 1, Clock Input
I/O
VDDIO_0
General Purpose Timer 2, Channel 0
I/O
VDDIO_0
General Purpose Timer 2, Channel 1
I/O
VDDIO_0
General Purpose Timer 2, Channel 2
I/O
VDDIO_0
General Purpose Timer 2, Channel 3
I/O
VDDIO_0
General Purpose Timer 2, Channel 4
I/O
VDDIO_3
General Purpose Timer 2, Channel 5
VDDIO_3
General Purpose Timer 2, Clock Input
I/O
VDDIO_1
General Purpose Timer 3, Channel 0
I/O
VDDIO_1
General Purpose Timer 3, Channel 1
I/O
VDDIO_1
General Purpose Timer 3, Channel 2
I/O
VDDIO_1
General Purpose Timer 3, Channel 3
GPIO_13
--
GPT2_CH2
GPIO_14
--
GPT2_CH3
GPIO_15
--
GPT2_CH4
GPIO_37
--
GPT2_CH5
GPIO_38
--
GPT2_CLKIN
GPIO_17
--
GPT3_CH0
GPIO_18
--
GPT3_CH1
GPIO_19
--
GPT3_CH2
GPIO_20
--
GPT3_CH3
cy
rk
l8
l8
wi
nc
Copyright © 2015 Marvell
1u
yp
February 3, 2015, 1.00
nc
wi
General Purpose Timer 1, Channel 2
7a
M zhg
AR a8
VE 18
LL 9kc
CO blg
NF wl
ID 8g1
EN 2a
TI 4v
AL 3h
, U pND i72
ER og
NDizr *
A# Gl
12 oba
15 l N
02 e
08 two
GPT2_CH1
vc
yp
--
General Purpose Timer 1, Channel 1
2f
GPIO_12
am
GPT2_CH0
General Purpose Timer 1, Channel 0
dr
--
pv
GPIO_11
1u
GPT1_CLKIN
--
wi
nc
GPIO_36
--
hg
GPIO_35
I/O
GPIO_5
tin
GPT0_CH4
gh
GPIO_4
Li
GPT0_CH3
kc
18
GPIO_3
Co
7a
M zhg
AR a8
VE 18
LL 9kc
CO blg
NF wl
ID 8g1
EN 2a
TI 4v
AL 3h
, U pND i72
ER og
NDizr *
A# Gl
12 oba
15 l N
02 e
08 two
Supply
l8v
GPIO_2
Ty p e
yp
l8
GPIO_1
Signal Name
blg
hp
4v
-i7
GPIO_0
68-Pin
g1
*G
8 8 -P in
nt
ro
rk
GPT Interface1
Table 7:
am
1u
yp
Package
Pin Description
CONFIDENTIAL
Document Classification: Proprietary
Doc. No. MV-S109936-00 Rev. A
Page 49
n
Co
lo
al
giz
rk
Li
gh
tin
88MW300/302
Datasheet
GPT Interface1
7a
M zhg
AR a8
VE 18
LL 9kc
CO blg
NF wl
ID 8g1
EN 2a
TI 4v
AL 3h
, U pND i72
ER og
NDizr *
A# Gl
12 oba
15 l N
02 e
08 two
68-Pin
Signal Name
Ty p e
Supply
D e s c ri p ti o n
--
GPT3_CH4
I/O
VDDIO_1
General Purpose Timer 3, Channel 4
GPT3_CH5
I/O
VDDIO_3
General Purpose Timer 3, Channel 5
VDDIO_3
General Purpose Timer 2, Clock Input
4v
GPIO_34
--
l8
hp
GPIO_21
GPIO_39
blg
-i7
8 8 -P in
g1
*G
Table 7:
GPT3_CLKIN
kc
18
1. All GPT signals are muxed on GPIO pins. See Table 11, GPIO Interface, on page 53 for GPIO muxing.
hg
VDDIO_0
GPIO_2
SSP0_TXD
VDDIO_0
GPIO_3
SSP0_RXD
VDDIO_0
GPIO_30
SSP0_CLK
GPIO_31
SSP0_FRM
GPIO_32
SSP0_TXD
GPIO_33
SSP0_RXD
--
SSP1_RXD
GPIO_18
--
SSP1_CLK
GPIO_19
--
SSP1_FRM
GPIO_20
--
SSP1_TXD
GPIO_21
--
SSP1_RXD
GPIO_35
--
SSP1_CLK
GPIO_36
--
SSP1_FRM
7a
M zhg
AR a8
VE 18
LL 9kc
CO blg
NF wl
ID 8g1
EN 2a
TI 4v
AL 3h
, U pND i72
ER og
NDizr *
A# Gl
12 oba
15 l N
02 e
08 two
vc
yp
GPIO_14
VDDIO_2
SSP 0 Serial Clock
I/O
VDDIO_2
SSP 0 Frame Indicator
VDDIO_2
SSP 0 TXD
VDDIO_2
SSP 0 RXD
I/O
VDDIO_0
SSP 1 Serial Clock
I/O
VDDIO_0
SSP 1 Frame Indicator
VDDIO_0
SSP 1 TXD
VDDIO_0
SSP 1 RXD
I/O
VDDIO_1
SSP 1 Serial Clock
I/O
VDDIO_1
SSP 1 Frame Indicator
VDDIO_1
SSP 1 TXD
VDDIO_1
SSP 1 RXD
I/O
VDDIO_3
SSP 1 Serial Clock
I/O
VDDIO_3
SSP 1 Frame Indicator
cy
I/O
l8
wi
nc
Doc. No. MV-S109936-00 Rev. A
1u
yp
Page 50
am
1u
yp
wi
nc
l8
SSP1_TXD
SSP 0 RXD
2f
--
SSP 0 TXD
am
GPIO_13
SSP 0 Frame Indicator
dr
SSP1_FRM
pv
--
GPIO_12
wi
nc
SSP1_CLK
--
l8v
GPIO_11
Co
I/O
SSP0_FRM
SSP 0 Serial Clock
VDDIO_0
GPIO_1
Description
tin
I/O
Supply
gh
SSP0_CLK
Ty p e
Li
yp
GPIO_0
6 8 -P i n
rk
Pin Name
8 8 -P in
1u
SSP Interface1
nt
ro
az
Table 8:
CONFIDENTIAL
Document Classification: Proprietary
Copyright © 2015 Marvell
February 3, 2015, 1.00
n
Co
lo
al
tin
Package
gh
Pin Description
giz
Li
rk
SSP Interface1 (Continued)
7a
M zhg
AR a8
VE 18
LL 9kc
CO blg
NF wl
ID 8g1
EN 2a
TI 4v
AL 3h
, U pND i72
ER og
NDizr *
A# Gl
12 oba
15 l N
02 e
08 two
Ty p e
Supply
Description
--
SSP1_TXD
VDDIO_3
SSP 1 TXD
SSP1_RXD
VDDIO_3
SSP 1 RXD
I/O
VDDIO_3
SSP 1 Serial Clock
I/O
VDDIO_3
SSP 1 Frame Indicator
yp
VDDIO_3
SSP 1 TXD
VDDIO_3
SSP 1 RXD
l8
blg
kc
18
hp
GPIO_39
Pin Name
4v
GPIO_38
6 8 -P i n
-i7
8 8 -P in
g1
SSP1_CLK
GPIO_43
SSP1_FRM
GPIO_44
SSP1_TXD
GPIO_45
SSP1_RXD
GPIO_7
SSP2_CLK
I/O
VDDIO_0
GPIO_8
SSP2_FRM
I/O
VDDIO_0
GPIO_9
SSP2_TXD
VDDIO_0
SSP 2 TXD
GPIO_10
SSP2_RXD
VDDIO_0
SSP 2 RXD
GPIO_46
SSP2_CLK
I/O
VDDIO_3
SSP 2 Serial Clock
GPIO_47
SSP2_FRM
I/O
VDDIO_3
SSP 2 Frame Indicator
GPIO_48
SSP2_TXD
VDDIO_3
SSP 2 TXD
VDDIO_3
SSP 2 RXD
Co
nt
ro
GPIO_42
l8v
hg
az
*G
Table 8:
tin
gh
7a
M zhg
AR a8
VE 18
LL 9kc
CO blg
NF wl
ID 8g1
EN 2a
TI 4v
AL 3h
, U pND i72
ER og
NDizr *
A# Gl
12 oba
15 l N
02 e
08 two
rk
Li
2f
SSP2_RXD
1. All SSP signals are muxed on GPIO pins. See Table 11, GPIO Interface, on page 53 for GPIO muxing.
l8
cy
am
1u
yp
wi
nc
l8
am
SSP 2 Frame Indicator
dr
pv
1u
vc
yp
wi
nc
GPIO_49
SSP 2 Serial Clock
wi
nc
Copyright © 2015 Marvell
1u
yp
February 3, 2015, 1.00
CONFIDENTIAL
Document Classification: Proprietary
Doc. No. MV-S109936-00 Rev. A
Page 51
n
Co
lo
al
giz
rk
Li
gh
tin
88MW300/302
Datasheet
I2C Interface1
7a
M zhg
AR a8
VE 18
LL 9kc
CO blg
NF wl
ID 8g1
EN 2a
TI 4v
AL 3h
, U pND i72
ER og
NDizr *
A# Gl
12 oba
15 l N
02 e
08 two
Pin Name
Ty p e
Supply
D e s c r i p t io n
I2C0_SDA
I/O
VDDIO_0
I2C 0 SDA
I/O
VDDIO_0
I2C 0 SCL
I/O
VDDIO_0
I2C 1 SDA
I/O
VDDIO_0
I2C 1 SCL
l8
GPIO_5
GPIO_8
blg
I2C0_SCL
I2C1_SDA
GPIO_10
I2C1_SCL
nt
ro
kc
18
GPIO_6
GPIO_9
hg
az
yp
hp
4v
GPIO_4
GPIO_7
68-Pin
-i7
8 8 -P in
g1
*G
Table 9:
I2C1_SCL
GPIO_28
I2C0_SDA
GPIO_29
I2C0_SCL
vc
yp
GPIO_26
I2C1_SCL
--
I2C 1 SCL
Li
GPIO_17
GPIO_19
rk
I2C1_SDA
7a
M zhg
AR a8
VE 18
LL 9kc
CO blg
NF wl
ID 8g1
EN 2a
TI 4v
AL 3h
, U pND i72
ER og
NDizr *
A# Gl
12 oba
15 l N
02 e
08 two
--
tin
VDDIO_1
GPIO_18
gh
I/O
I/O
2f
l8
I2C 1 SDA
I2C0_SCL
am
I/O
VDDIO_AON
I2C 1 SDA
I/O
VDDIO_AON
I2C 1 SCL
I/O
VDDIO_2
I2C 1 SDA
I/O
VDDIO_2
I2C 1 SCL
1. All I2C signals are muxed on GPIO pins. See Table 11, GPIO Interface, on page 53 for GPIO muxing.
Table 10: QSPI Interface1
8 8 -P in
6 8 -P in
Pin Name
Ty p e
Supply
D e s c ri p ti o n
GPIO_28
QSPI_SSn
VDDIO_2
QSPI Chip Select (active low)
GPIO_29
QSPI_CLK
VDDIO_2
QSPI Clock
GPIO_30
QSPI_D0
I/O
VDDIO_2
QSPI Data 0
GPIO_31
QSPI_D1
I/O
VDDIO_2
QSPI Data 1
GPIO_32
QSPI_D2
I/O
VDDIO_2
QSPI Data 2
GPIO_33
QSPI_D3
I/O
VDDIO_2
QSPI Data 3
l8
cy
1. QSPI signals are used for external Flash only. All QSPI signals are muxed on GPIO pins. See Table 11, GPIO Interface, on page 53 for
GPIO muxing.
wi
nc
Doc. No. MV-S109936-00 Rev. A
1u
yp
Page 52
nc
VDDIO_1
--
dr
wi
I/O
GPIO_21
1u
am
1u
yp
pv
I2C 0 SCL
I/O
I2C1_SDA
VDDIO_1
I2C0_SDA
GPIO_25
wi
nc
I2C 0 SDA
--
Co
l8v
VDDIO_1
GPIO_20
CONFIDENTIAL
Document Classification: Proprietary
Copyright © 2015 Marvell
February 3, 2015, 1.00
n
Co
lo
al
tin
Package
gh
Pin Description
rk
Li
giz
*G
Table 11: GPIO Interface 1 2
7a
M zhg
AR a8
VE 18
LL 9kc
CO blg
NF wl
ID 8g1
EN 2a
TI 4v
AL 3h
, U pND i72
ER og
NDizr *
A# Gl
12 oba
15 l N
02 e
08 two
-i7
P i n /S ig n a l N a m e
Type
S u p p ly
D e s c ri p ti o n
GPIO_0
I/O
VDDIO_0
General Purpose I/O 0
GPT0_CH0
I/O
General Purpose Timer 0, Channel 0
UART 0 CTSn (active low)
I/O
SSP 0 Serial Clock
g1
hp
68-Pin
4v
8 8 -P in
l8
blg
UART0_CTSn
kc
18
SSP0_CLK
nt
ro
General Purpose I/O 1
l8v
GPT0_CH1
I/O
General Purpose Timer 0, Channel 1
UART0_RTSn
SSP0_FRM
I/O
GPIO_2
I/O
GPT0_CH2
I/O
General Purpose Timer 0, Channel 2
UART 0 TXD
SSP 0 TXD
Co
VDDIO_0
UART 0 RTSn (active low)
I/O
GPIO_1
SSP 0 Frame Indicator
tin
az
yp
wi
nc
pv
1u
hg
GPIO_3
vc
yp
I/O
GPT0_CH3
nc
l8
UART0_RXD
GPIO_4
I2C0_SDA
AUDIO_CLK
GPIO_5
UART 0 RXD
SSP 0 RXD
VDDIO_0
Li
rk
General Purpose I/O 4
I/O
General Purpose Timer 0, Channel 4
I/O
I2C 0 SDA
Audio Clock
AUPLL Audio clock output provided by Audio
PLL for external codec.
VDDIO_0
General Purpose I/O 5
I/O
General Purpose Timer 0, Channel 5
I/O
I2C 0 SCL
l8
cy
I2C0_SCL
General Purpose I/O 3
General Purpose Timer 0, Channel 3
I/O
GPT0_CH5
VDDIO_0
I/O
I/O
GPT0_CH4
wi
nc
Copyright © 2015 Marvell
1u
yp
February 3, 2015, 1.00
am
1u
yp
wi
SSP0_RXD
General Purpose I/O 2
7a
M zhg
AR a8
VE 18
LL 9kc
CO blg
NF wl
ID 8g1
EN 2a
TI 4v
AL 3h
, U pND i72
ER og
NDizr *
A# Gl
12 oba
15 l N
02 e
08 two
SSP0_TXD
2f
UART0_TXD
VDDIO_0
gh
am
dr
CONFIDENTIAL
Document Classification: Proprietary
Doc. No. MV-S109936-00 Rev. A
Page 53
n
Co
lo
al
giz
rk
Li
gh
tin
88MW300/302
Datasheet
*G
Table 11: GPIO Interface 1 (Continued)2
7a
M zhg
AR a8
VE 18
LL 9kc
CO blg
NF wl
ID 8g1
EN 2a
TI 4v
AL 3h
, U pND i72
ER og
NDizr *
A# Gl
12 oba
15 l N
02 e
08 two
-i7
68-Pin
hp
4v
8 8 -P in
P i n /S ig n a l N a m e
Type
S u p p ly
D e s c ri p ti o n
GPIO_6
I/O
VDDIO_0
General Purpose I/O 6
l8
blg
TDO
kc
g1
18
I2C1_SDA
JTAG Test Data
I/O
I2C 1 SDA
GPIO_8
I/O
SSP2_TXD
I2C1_SDA
12
12
GPIO_10
UART2_RXD
SSP2_TXD
UART 2 RTSn (active low)
I/O
SSP_2 Frame Indicator
I/O
I2C 0 SCL
VDDIO_0
General Purpose I/O 9
JTAG Test Data
UART 2 TXD
SSP 2 TXD
I/O
I2C 1 SDA
VDDIO_0
General Purpose I/O 10
JTAG Test Reset (active low)
UART 2 RXD
SSP 2 RXD
I/O
I2C 1 SCL
l8
cy
I2C1_SCL
General Purpose I/O 8
JTAG Controller Select
I/O
TRSTn
VDDIO_0
7a
M zhg
AR a8
VE 18
LL 9kc
CO blg
NF wl
ID 8g1
EN 2a
TI 4v
AL 3h
, U pND i72
ER og
NDizr *
A# Gl
12 oba
15 l N
02 e
08 two
vc
yp
l8
nc
wi
am
1u
yp
UART2_TXD
I2C 0 SDA
I/O
I/O
TDI
SSP 2 Serial Clock
am
GPIO_9
pv
11
1u
I2C0_SCL
SSP2_FRM
wi
nc
UART2_RTSn
nt
ro
I/O
Co
I2C0_SDA
I/O
SSP2_CLK
UART 2 CTSn (active low)
gh
Li
UART2_CTSn
JTAG Test Clock
rk
General Purpose I/O 7
tin
TCK
TMS
11
VDDIO_0
l8v
10
I/O
2f
GPIO_7
dr
az
yp
10
hg
wi
nc
Doc. No. MV-S109936-00 Rev. A
1u
yp
Page 54
CONFIDENTIAL
Document Classification: Proprietary
Copyright © 2015 Marvell
February 3, 2015, 1.00
n
Co
lo
al
tin
Package
gh
Pin Description
rk
Li
giz
*G
Table 11: GPIO Interface 1 (Continued)2
7a
M zhg
AR a8
VE 18
LL 9kc
CO blg
NF wl
ID 8g1
EN 2a
TI 4v
AL 3h
, U pND i72
ER og
NDizr *
A# Gl
12 oba
15 l N
02 e
08 two
-i7
P i n /S ig n a l N a m e
Type
S u p p ly
D e s c ri p ti o n
--
GPIO_11
I/O
VDDIO_0
General Purpose I/O 11
GPT2_CH0
I/O
General Purpose Timer 2, Channel 0
UART 1 CTSn (active low)
I/O
SSP 1 Serial Clock
g1
hp
13
68-Pin
4v
8 8 -P in
l8
blg
UART1_CTSn
kc
18
SSP1_CLK
nt
ro
General Purpose I/O 12
l8v
GPT2_CH1
I/O
General Purpose Timer 2, Channel 1
UART1_RTSn
SSP1_FRM
I/O
GPIO_13
I/O
GPT2_CH2
I/O
General Purpose Timer 2, Channel 2
UART 1 TXD
SSP 1 TXD
Co
VDDIO_0
UART 1 RTSn (active low)
I/O
GPIO_12
SSP 1 Frame Indicator
tin
az
yp
wi
nc
pv
1u
--
hg
14
--
GPIO_14
vc
yp
16
I/O
GPT2_CH3
nc
l8
UART1_RXD
17
--
GPIO_15
35
30
VDDIO_0
General Purpose Timer 2, Channel 3
UART 1 RXD
SSP 1 RXD
VDDIO_0
I/O
GPIO_16
I/O
CON[5]
Li
rk
General Purpose I/O 15
General Purpose Timer 2, Channel 4
VDDIO_1
General Purpose I/O 16
I/O
Configuration Bit
See Table 17, Configuration Pins, on
page 67.
Audio Clock
AUPLL Audio clock output provided by Audio
PLL for external codec.
l8
cy
AUDIO_CLK
General Purpose I/O 14
I/O
I/O
GPT2_CH4
wi
nc
Copyright © 2015 Marvell
1u
yp
February 3, 2015, 1.00
am
1u
yp
wi
SSP1_RXD
General Purpose I/O 13
7a
M zhg
AR a8
VE 18
LL 9kc
CO blg
NF wl
ID 8g1
EN 2a
TI 4v
AL 3h
, U pND i72
ER og
NDizr *
A# Gl
12 oba
15 l N
02 e
08 two
SSP1_TXD
2f
UART1_TXD
VDDIO_0
gh
am
--
dr
15
CONFIDENTIAL
Document Classification: Proprietary
Doc. No. MV-S109936-00 Rev. A
Page 55
n
Co
lo
al
giz
rk
Li
gh
tin
88MW300/302
Datasheet
Type
S u p p ly
D e s c ri p ti o n
--
GPIO_17
I/O
VDDIO_1
General Purpose I/O 17
GPT3_CH0
I/O
General Purpose Timer 3, Channel 0
I/O
I2C 1 SCL
kc
18
I/O
az
yp
GPIO_18
hg
GPT3_CH1
VDDIO_1
General Purpose I/O 18
I/O
General Purpose Timer 3, Channel 1
I2C 1 SDA
I2C1_SDA
I/O
SSP1_CLK
I/O
GPIO_19
I/O
GPT3_CH2
I/O
General Purpose Timer 3, Channel 2
I2C1_SCL
I/O
I2C 1 SDA
I/O
SSP 1 Frame Indicator
wi
nc
--
l8
blg
37
l8v
g1
hp
I2C1_SCL
nt
ro
7a
M zhg
AR a8
VE 18
LL 9kc
CO blg
NF wl
ID 8g1
EN 2a
TI 4v
AL 3h
, U pND i72
ER og
NDizr *
A# Gl
12 oba
15 l N
02 e
08 two
P i n /S ig n a l N a m e
4v
36
68-Pin
Co
-i7
8 8 -P in
SSP 1 Serial Clock
*G
Table 11: GPIO Interface 1 (Continued)2
vc
yp
GPIO_21
am
1u
yp
I2C0_SCL
SSP1_RXD
36
GPIO_22
tin
gh
Li
General Purpose I/O 20
General Purpose Timer 3, Channel 3
I/O
I2C 0 SDA
SSP 1 TXD
VDDIO_1
General Purpose I/O 21
I/O
General Purpose Timer 3, Channel 4
I/O
I2C 0 SCL
SSP 1 RXD
I/O
VDDIO_
AON
General Purpose I/O 22
Wake-Up 0
l8
cy
WAKE_UP0
VDDIO_1
I/O
I/O
wi
nc
l8
SSP1_TXD
GPT3_CH4
46
rk
7a
M zhg
AR a8
VE 18
LL 9kc
CO blg
NF wl
ID 8g1
EN 2a
TI 4v
AL 3h
, U pND i72
ER og
NDizr *
A# Gl
12 oba
15 l N
02 e
08 two
I/O
I2C0_SDA
--
2f
GPIO_20
GPT3_CH3
40
am
--
General Purpose I/O 19
dr
SSP1_FRM
39
VDDIO_1
pv
--
1u
38
wi
nc
Doc. No. MV-S109936-00 Rev. A
1u
yp
Page 56
CONFIDENTIAL
Document Classification: Proprietary
Copyright © 2015 Marvell
February 3, 2015, 1.00
n
Co
lo
al
tin
Package
gh
Pin Description
rk
Li
giz
*G
Table 11: GPIO Interface 1 (Continued)2
7a
M zhg
AR a8
VE 18
LL 9kc
CO blg
NF wl
ID 8g1
EN 2a
TI 4v
AL 3h
, U pND i72
ER og
NDizr *
A# Gl
12 oba
15 l N
02 e
08 two
-i7
P i n /S ig n a l N a m e
Type
S u p p ly
D e s c ri p ti o n
37
GPIO_23
I/O
VDDIO_
AON
General Purpose I/O 23
UART0_CTSn
UART 0 CTSn (active low)
Wake-Up 1
LDO18 Comparator Input, Positive
Positive input to LDO18 comparator.
g1
hp
47
68-Pin
4v
8 8 -P in
l8
blg
WAKE_UP1
kc
18
COMP_IN_P
hg
I/O
GPIO_27
--
USB_DRV_VBUS
51
UART0_TXD
51
CON[4]
42
GPIO_28
I/O
I2C 1 SDA
gh
rk
General Purpose I/O 26
32.768 kHz Crystal Output
I/O
I2C 1 SCL
VDDIO_3
General Purpose I/O 27
Drive 5V on VBUS
UART 0 TXD
I/O
Configuration Bit
See Table 17, Configuration Pins, on
page 67.
VDDIO_2
General Purpose I/O 28
QSPI Chip Select (active low)
I/O
I2C 0 SDA
I/O
General Purpose Timer 1, Channel 0
l8
cy
GPT1_CH0
VDDIO_
AON
I/O
I2C0_SDA
Li
32.768 kHz Crystal Input
I/O
QSPI_SSn
General Purpose I/O 25
7a
M zhg
AR a8
VE 18
LL 9kc
CO blg
NF wl
ID 8g1
EN 2a
TI 4v
AL 3h
, U pND i72
ER og
NDizr *
A# Gl
12 oba
15 l N
02 e
08 two
vc
yp
l8
nc
wi
nc
Copyright © 2015 Marvell
1u
yp
February 3, 2015, 1.00
wi
am
1u
yp
51
VDDIO_
AON
2f
52
am
I2C1_SCL
LDO18 Comparator Input, Negative
Negative input to LDO18 comparator.
I/O
XTAL32K_OUT
General Purpose Timer 1, Channel 5
dr
GPIO_26
Co
GPIO_25
UART 0 RXD
COMP_IN_N
General Purpose I/O 24
tin
I/O
1u
66
GPT1_CH5
wi
nc
I2C1_SDA
40
VDDIO_
AON
UART0_RXD
XTAL32K_IN
50
l8v
39
I/O
pv
GPIO_24
nt
ro
az
49
38
yp
48
CONFIDENTIAL
Document Classification: Proprietary
Doc. No. MV-S109936-00 Rev. A
Page 57
n
Co
lo
al
giz
rk
Li
gh
tin
88MW300/302
Datasheet
*G
Table 11: GPIO Interface 1 (Continued)2
7a
M zhg
AR a8
VE 18
LL 9kc
CO blg
NF wl
ID 8g1
EN 2a
TI 4v
AL 3h
, U pND i72
ER og
NDizr *
A# Gl
12 oba
15 l N
02 e
08 two
-i7
68-Pin
hp
4v
8 8 -P in
P i n /S ig n a l N a m e
Type
S u p p ly
D e s c ri p ti o n
GPIO_29
I/O
VDDIO_2
General Purpose I/O 29
I2C 0 SCL
I/O
General Purpose Timer 1, Channel 1
GPT1_CH2
I/O
UART0_RTSn
vc
yp
SSP0_FRM
46
GPIO_32
wi
am
1u
yp
QSPI_D2
UART0_TXD
SSP0_TXD
GPT1_CH4
57
47
GPIO_33
UART0_RXD
SSP0_RXD
VDDIO_2
General Purpose I/O 31
UART 0 RTSn (active low)
I/O
SSP 0 Frame Indicator
I/O
General Purpose Timer 1, Channel 3
VDDIO_2
General Purpose I/O 32
I/O
QSPI Data 2
UART 0 TXD
SSP 0 TXD
I/O
General Purpose Timer 1, Channel 4
VDDIO_2
General Purpose I/O 33
I/O
QSPI Data 3
UART 0 RXD
SSP 0 RXD
I/O
General Purpose Timer 1, Channel 5
l8
cy
GPT1_CH5
General Purpose Timer 1, Channel 2
QSPI Data 1
I/O
QSPI_D3
SSP 0 Serial Clock
I/O
I/O
nc
l8
GPT1_CH3
UART 0 CTSn (active low)
7a
M zhg
AR a8
VE 18
LL 9kc
CO blg
NF wl
ID 8g1
EN 2a
TI 4v
AL 3h
, U pND i72
ER og
NDizr *
A# Gl
12 oba
15 l N
02 e
08 two
I/O
QSPI_D1
56
pv
GPIO_31
Co
I/O
SSP0_CLK
tin
UART0_CTSn
QSPI Data 0
gh
I/O
General Purpose I/O 30
Li
QSPI_D0
VDDIO_2
rk
I/O
GPIO_30
wi
nc
45
55
44
2f
az
yp
54
nt
ro
I/O
am
hg
GPT1_CH1
QSPI Clock
dr
kc
18
I2C0_SCL
1u
QSPI_CLK
l8v
l8
blg
43
g1
53
wi
nc
Doc. No. MV-S109936-00 Rev. A
1u
yp
Page 58
CONFIDENTIAL
Document Classification: Proprietary
Copyright © 2015 Marvell
February 3, 2015, 1.00
n
Co
lo
al
tin
Package
gh
Pin Description
rk
Li
giz
*G
Table 11: GPIO Interface 1 (Continued)2
7a
M zhg
AR a8
VE 18
LL 9kc
CO blg
NF wl
ID 8g1
EN 2a
TI 4v
AL 3h
, U pND i72
ER og
NDizr *
A# Gl
12 oba
15 l N
02 e
08 two
-i7
68-Pin
hp
4v
8 8 -P in
P i n /S ig n a l N a m e
Type
S u p p ly
D e s c ri p ti o n
GPIO_34
I/O
VDDIO_3
General Purpose I/O 34
I/O
kc
18
I/O
az
GPIO_35
yp
GPT0_CLKIN
VDDIO_3
General Purpose I/O 35
General Purpose Timer 0, Clock Input
UART 1 CTSn (active low)
SSP1_CLK
I/O
GPIO_36
I/O
GPT1_CLKIN
General Purpose Timer 1, Clock Input
UART1_RTSn
UART 1 RTSn (active low)
I/O
SSP 1 Frame Indicator
Co
UART1_CTSn
SSP 1 Serial Clock
wi
nc
--
hg
68
General Purpose Timer 3, Channel 5
nt
ro
GPT3_CH5
l8v
l8
blg
--
g1
67
I/O
vc
yp
GPT2_CH5
nc
l8
UART0_RTSn
--
GPIO_38
wi
71
am
1u
yp
UART1_TXD
SSP1_TXD
52
GPIO_39
UART1_RXD
UART 0 RTSn (active low)
VDDIO_3
tin
gh
Li
rk
General Purpose I/O 38
General Purpose Timer 2, Clock Input
UART 1 TXD
SSP 1 TXD
VDDIO_3
General Purpose I/O 39
General Purpose Timer 2, Clock Input
UART 1 RXD
SSP 1 RXD
l8
cy
SSP1_RXD
General Purpose I/O 37
General Purpose Timer 2, Channel 5
I/O
GPT3_CLKIN
VDDIO_3
I/O
I/O
GPT2_CLKIN
72
7a
M zhg
AR a8
VE 18
LL 9kc
CO blg
NF wl
ID 8g1
EN 2a
TI 4v
AL 3h
, U pND i72
ER og
NDizr *
A# Gl
12 oba
15 l N
02 e
08 two
GPIO_37
2f
--
am
70
General Purpose I/O 36
dr
SSP1_FRM
VDDIO_3
pv
--
1u
69
wi
nc
Copyright © 2015 Marvell
1u
yp
February 3, 2015, 1.00
CONFIDENTIAL
Document Classification: Proprietary
Doc. No. MV-S109936-00 Rev. A
Page 59
n
Co
lo
al
giz
7a
M zhg
AR a8
VE 18
LL 9kc
CO blg
NF wl
ID 8g1
EN 2a
TI 4v
AL 3h
, U pND i72
ER og
NDizr *
A# Gl
12 oba
15 l N
02 e
08 two
-i7
P i n /S ig n a l N a m e
Type
S u p p ly
D e s c ri p ti o n
55
GPIO_40
I/O
VDDIO_3
General Purpose I/O 40
ADC_DAC_TRIGGER0
ADC/DAC External Trigger 0
ACOMP0 GPIO Output
ACOMP0 output synchronous or
asynchronous level signals.
ACOMP1 GPIO Output
ACOMP1 output synchronous or
asynchronous level signals.
g1
hp
75
68-Pin
4v
8 8 -P in
l8
blg
kc
ACOMP0_GPIO_OUT
18
hg
az
yp
ACOMP1_GPIO_OUT
Co
*G
Table 11: GPIO Interface 1 (Continued)2
nt
ro
rk
Li
gh
tin
88MW300/302
Datasheet
l8v
ACOMP0_EDGE_
PULSE
UART1_CTSn
VDDIO_3
gh
Li
rk
ACOMP Edge Pulse 1
Output pulse aligned with synchronized
comparison result.
General Purpose I/O 42
A, I
ADC0 Channel 0
ACOMP0 Channel 0
ACOMP1 Channel 0
Temperature sensor remote sensing positive
input
Voice sensing positive input
UART 1 CTSn (active low)
I/O
SSP 1 Serial Clock
l8
cy
SSP1_CLK
ACOMP Edge Pulse 0
Output pulse aligned with synchronized
comparison result.
7a
M zhg
AR a8
VE 18
LL 9kc
CO blg
NF wl
ID 8g1
EN 2a
TI 4v
AL 3h
, U pND i72
ER og
NDizr *
A# Gl
12 oba
15 l N
02 e
08 two
nc
wi
am
1u
yp
I/O
ADC0_0 / ACOMP0 /
TS_INP / VOICE_P
l8
vc
yp
GPIO_42
2f
58
am
78
ADC/DAC External Trigger 1
dr
ACOMP1_EDGE_
PULSE
General Purpose I/O 41
VDDIO_3
tin
ADC_DAC_TRIGGER1
pv
I/O
1u
GPIO_41
56
wi
nc
76
wi
nc
Doc. No. MV-S109936-00 Rev. A
1u
yp
Page 60
CONFIDENTIAL
Document Classification: Proprietary
Copyright © 2015 Marvell
February 3, 2015, 1.00
n
Co
lo
al
tin
Package
gh
Pin Description
7a
M zhg
AR a8
VE 18
LL 9kc
CO blg
NF wl
ID 8g1
EN 2a
TI 4v
AL 3h
, U pND i72
ER og
NDizr *
A# Gl
12 oba
15 l N
02 e
08 two
-i7
P i n /S ig n a l N a m e
Type
S u p p ly
D e s c ri p ti o n
59
GPIO_43
I/O
VDDIO_3
General Purpose I/O 43
ADC0_1 / ACOMP1 /
TS_INN / DACB /
VOICE_N
A, I
ADC0 Channel 1
ACOMP0 Channel 1
ACOMP1 Channel 1
Temperature sensor remote sensing
negative input
Voice sensing negative input
UART 1 RTSn (active low)
SSP 1 Frame Indicator
g1
hp
4v
79
68-Pin
l8
blg
kc
18
hg
az
yp
UART1_RTSn
I/O
l8v
SSP1_FRM
Co
*G
8 8 -P in
nt
ro
rk
Li
giz
Table 11: GPIO Interface 1 (Continued)2
vc
yp
RF_CNTL1_P
61
GPIO_45
nc
wi
am
1u
yp
UART1_RXD
SSP1_RXD
RF_CNTL0_N
82
62
UART 1 TXD
SSP 1 TXD
WLAN Radio Control 1
I/O
ADC0_3 / ACOMP3 /
EXT_VREF
l8
81
GPIO_46
UART2_CTSn
tin
gh
Li
General Purpose I/O 45
ADC0 Channel 3
ACOMP0 Channel 3
ACOMP1 Channel 3
ADC or DAC external voltage reference input
UART 1 RXD
SSP 1 RXD
WLAN Radio Control 0
VDDIO_3
General Purpose I/O 46
A, I
ADC0 Channel 4
ACOMP0 Channel 4
ACOMP1 Channel 4
UART 2 CTSn (active low)
I/O
SSP 2 Serial Clock
l8
cy
SSP2_CLK
VDDIO_3
A, I
I/O
ADC0_4 / ACOMP4
rk
7a
M zhg
AR a8
VE 18
LL 9kc
CO blg
NF wl
ID 8g1
EN 2a
TI 4v
AL 3h
, U pND i72
ER og
NDizr *
A# Gl
12 oba
15 l N
02 e
08 two
SSP1_TXD
ADC0 Channel 2
ACOMP0 Channel 2
ACOMP1 Channel 2
DAC Channel A output
2f
UART1_TXD
General Purpose I/O 44
am
A, I
VDDIO_3
dr
ADC0_2 / ACOMP2 /
DACA
pv
I/O
1u
GPIO_44
60
wi
nc
80
wi
nc
Copyright © 2015 Marvell
1u
yp
February 3, 2015, 1.00
CONFIDENTIAL
Document Classification: Proprietary
Doc. No. MV-S109936-00 Rev. A
Page 61
n
Co
lo
al
giz
rk
Li
gh
tin
88MW300/302
Datasheet
7a
M zhg
AR a8
VE 18
LL 9kc
CO blg
NF wl
ID 8g1
EN 2a
TI 4v
AL 3h
, U pND i72
ER og
NDizr *
A# Gl
12 oba
15 l N
02 e
08 two
Type
S u p p ly
D e s c ri p ti o n
63
GPIO_47
I/O
VDDIO_3
General Purpose I/O 47
ADC0_5 / ACOMP5
A, I
ADC0 Channel 5
ACOMP0 Channel 5
ACOMP1 Channel 5
UART 2 RTSn (active low)
I/O
SSP 2 Frame Indicator
SSP2_TXD
pv
I/O
ADC0_7 / ACOMP7
SSP2_RXD
SSP 2 TXD
VDDIO_3
General Purpose I/O 49
A, I
ADC0 Channel 7
ACOMP0 Channel 7
ACOMP1 Channel 7
UART 2 RXD
SSP 2 RXD
1. GPIO_11 to GPIO_15, GPIO_17 to GPIO_21, GPIO_34 to GPIO_38 I/O and associated muxing available on 88-pin QFN only.
2. All GPIO pins are pull-up high after POR.
l8
cy
am
1u
yp
wi
nc
l8
vc
yp
UART2_RXD
UART 2 TXD
7a
M zhg
AR a8
VE 18
LL 9kc
CO blg
NF wl
ID 8g1
EN 2a
TI 4v
AL 3h
, U pND i72
ER og
NDizr *
A# Gl
12 oba
15 l N
02 e
08 two
GPIO_49
ADC0 Channel 6
ACOMP0 Channel 6
ACOMP1 Channel 6
am
65
1u
85
Co
UART2_TXD
wi
nc
A, I
General Purpose I/O 48
ADC0_6 / ACOMP6
VDDIO_3
az
yp
I/O
tin
hg
GPIO_48
gh
kc
18
64
Li
l8
blg
84
rk
g1
SSP2_FRM
l8v
hp
UART2_RTSn
nt
ro
P i n /S ig n a l N a m e
4v
83
68-Pin
2f
-i7
8 8 -P in
dr
*G
Table 11: GPIO Interface 1 (Continued)2
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nc
Doc. No. MV-S109936-00 Rev. A
1u
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Page 62
CONFIDENTIAL
Document Classification: Proprietary
Copyright © 2015 Marvell
February 3, 2015, 1.00
n
Co
lo
al
tin
Package
gh
Pin Description
rk
Li
giz
7a
M zhg
AR a8
VE 18
LL 9kc
CO blg
NF wl
ID 8g1
EN 2a
TI 4v
AL 3h
, U pND i72
ER og
NDizr *
A# Gl
12 oba
15 l N
02 e
08 two
D e s c ri p t i o n
XTAL_IN
A, I
AVDD18
Crystal Oscillator Input
A, O
AVDD18
Crystal Oscillator Output
Connect to ground when an external oscillator used.
A, I
VDDIO_AON
32.768 kHz Crystal Input
A, O
VDDIO_AON
32.768 kHz Crystal Output
VDDIO_AON
Wake-Up 0
GPIO_22
WAKE_UP0
GPIO_23
WAKE_UP1
GPIO_4
GPIO_16
AUDIO_CLK
hg
az
yp
Wake-Up 1
VDDIO_0
Audio Clock
AUPLL audio clock output provided by audio PLL for
external codec.
1u
VDDIO_AON
gh
RESETn
Chip Reset (active low)
Li
35
rk
45
VDDIO_AON
pv
XTAL32K_OUT
wi
nc
GPIO_26
l8v
XTAL32K_IN
Co
kc
18
GPIO_25
XTAL_OUT
l8
22
nt
ro
Supply
tin
g1
27
21
Ty p e
2f
hp
4v
26
Pin/Signal
Name
blg
6 8 -P in
am
-i7
8 8 -P in
dr
*G
Table 12: Clock/Control Interface1
l8
cy
am
1u
yp
wi
nc
l8
vc
yp
7a
M zhg
AR a8
VE 18
LL 9kc
CO blg
NF wl
ID 8g1
EN 2a
TI 4v
AL 3h
, U pND i72
ER og
NDizr *
A# Gl
12 oba
15 l N
02 e
08 two
1. The XTAL32K_IN/OUT and WAKE_UP0/1 signals are muxed on GPIO pins. See Table 11, GPIO Interface, on page 53 for GPIO muxing.
wi
nc
Copyright © 2015 Marvell
1u
yp
February 3, 2015, 1.00
CONFIDENTIAL
Document Classification: Proprietary
Doc. No. MV-S109936-00 Rev. A
Page 63
n
Co
lo
al
giz
ACOMP0_GPIO_OUT
VDDIO_3
blg
ACOMP0 GPIO Output
ACOMP0 output synchronous or
asynchronous level signals
VDDIO_3
ACOMP1 GPIO Output
ACOMP1 output synchronous or
asynchronous level signals
VDDIO_3
ADC/DAC External Trigger 0
VDDIO_3
ACOMP Edge Pulse 0
Output pulse aligned with synchronized
comparison result.
l8
hg
ACOMP0_EDGE_PULSE
l8v
az
yp
GPIO_41
1u
ADC0_6 / ACOMP6
ADC0_5 / ACOMP5
GPIO_46
ADC0_4 / ACOMP4
GPIO_45
ADC0_3 / ACOMP3 /
EXT_VREF
GPIO_44
ADC0_2 / ACOMP2 /
DACA
VDDIO_3
ADC0 Channel 7
ACOMP0 Channel 7
ACOMP1 Channel 7
A, I
VDDIO_3
ADC0 Channel 6
ACOMP0 Channel 6
ACOMP1 Channel 6
A, I
VDDIO_3
ADC0 Channel 5
ACOMP0 Channel 5
ACOMP1 Channel 5
A, I
VDDIO_3
ADC0 Channel 4
ACOMP0 Channel 4
ACOMP1 Channel 4
A, I
VDDIO_3
ADC0 Channel 3
ACOMP0 Channel 3
ACOMP1 Channel 3
ADC or DAC external voltage reference
input
A, I
VDDIO_3
ADC0 Channel 2
ACOMP0 Channel 2
ACOMP1 Channel 2
DAC Channel A output
cy
A, I
l8
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Doc. No. MV-S109936-00 Rev. A
1u
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Page 64
am
1u
yp
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l8
GPIO_47
ADC/DAC External Trigger 1
7a
M zhg
AR a8
VE 18
LL 9kc
CO blg
NF wl
ID 8g1
EN 2a
TI 4v
AL 3h
, U pND i72
ER og
NDizr *
A# Gl
12 oba
15 l N
02 e
08 two
GPIO_48
vc
yp
ADC0_7 / ACOMP7
VDDIO_3
am
GPIO_49
ACOMP Edge Pulse 1
Output pulse aligned with synchronized
comparison result.
dr
ADC_DAC_TRIGGER1
VDDIO_3
pv
wi
nc
ACOMP1_EDGE_PULSE
gh
18
ADC_DAC_TRIGGER0
Li
kc
ACOMP1_GPIO_OUT
Co
Description
S u p p ly
Type
tin
7a
M zhg
AR a8
VE 18
LL 9kc
CO blg
NF wl
ID 8g1
EN 2a
TI 4v
AL 3h
, U pND i72
ER og
NDizr *
A# Gl
12 oba
15 l N
02 e
08 two
Pin Name
g1
hp
4v
GPIO_40
68-Pin
rk
-i7
8 8 -P in
2f
*G
Table 13: ADC/DAC/ACOMP Interface1
nt
ro
rk
Li
gh
tin
88MW300/302
Datasheet
CONFIDENTIAL
Document Classification: Proprietary
Copyright © 2015 Marvell
February 3, 2015, 1.00
n
Co
lo
al
tin
Package
gh
Pin Description
7a
M zhg
AR a8
VE 18
LL 9kc
CO blg
NF wl
ID 8g1
EN 2a
TI 4v
AL 3h
, U pND i72
ER og
NDizr *
A# Gl
12 oba
15 l N
02 e
08 two
Pin Name
Type
S u p p ly
Description
ADC0_1 / ACOMP1 /
TS_INN / DACB /
VOICE_N
A, I
VDDIO_3
ADC0 Channel 1
ACOMP0 Channel 1
ACOMP1 Channel 1
Temperature sensor remote sensing
negative input
Voice sensing negative input
g1
hp
4v
A, I
VDDIO_3
ADC0 Channel 0
ACOMP0 Channel 0
ACOMP1 Channel 0
Temperature sensor remote sensing
positive input
Voice sensing positive input
l8
blg
kc
18
hg
GPIO_42
ADC0_0 / ACOMP0 /
TS_INP / VOICE_P
Co
-i7
GPIO_43
68-Pin
*G
8 8 -P in
nt
ro
rk
Li
giz
Table 13: ADC/DAC/ACOMP Interface1 (Continued)
az
yp
l8v
wi
nc
1. All ADC/DAC/ACOMP signals are muxed on GPIO pins. See Table 11, GPIO Interface, on page 53 for GPIO muxing.
tin
gh
am
Li
2f
Type
S u p p ly
Description
GPIO_23
COMP_IN_P
A, I
VDDIO_AON
LDO18 Comparator Input, Positive
Positive input to LDO18 comparator.
GPIO_24
COMP_IN_N
A, I
VDDIO_AON
LDO18 Comparator Input, Negative
Positive input to LDO18 comparator.
rk
Pin Name
7a
M zhg
AR a8
VE 18
LL 9kc
CO blg
NF wl
ID 8g1
EN 2a
TI 4v
AL 3h
, U pND i72
ER og
NDizr *
A# Gl
12 oba
15 l N
02 e
08 two
68-Pin
dr
8 8 -P in
pv
1u
Table 14: LDO18 Comparator Interface1
vc
yp
1. All COMP signals are muxed on GPIO pins. See Table 11, GPIO Interface, on page 53 for GPIO muxing.
8 8 -P in
6 8 -P in
Signal Name
Ty p e
Supply
D e s c r ip ti o n
GPIO_6
TDO
VDDIO_0
JTAG Test Data
GPIO_7
TCK
VDDIO_0
JTAG Test Clock
GPIO_8
TMS
I/O
VDDIO_0
JTAG Controller Select
GPIO_9
TDI
VDDIO_0
JTAG Test Data
GPIO_10
TRSTn
VDDIO_0
JTAG Test Reset I/O (active low)
l8
cy
1. All JTAG signals are muxed on GPIO pins. See Table 11, GPIO Interface, on page 53 for GPIO muxing.
wi
nc
Copyright © 2015 Marvell
1u
yp
February 3, 2015, 1.00
am
1u
yp
wi
nc
l8
Table 15: JTAG Interface1
CONFIDENTIAL
Document Classification: Proprietary
Doc. No. MV-S109936-00 Rev. A
Page 65
n
Co
lo
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giz
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Li
gh
tin
88MW300/302
Datasheet
*G
Table 16: Power and Ground
7a
M zhg
AR a8
VE 18
LL 9kc
CO blg
NF wl
ID 8g1
EN 2a
TI 4v
AL 3h
, U pND i72
ER og
NDizr *
A# Gl
12 oba
15 l N
02 e
08 two
-i7
NOTE: See Section 22.2, Recommended Operating Conditions, on page 314 for ratings.
29
VDDIO_1
48
VDDIO_2
57
VDDIO_3
nt
ro
az
yp
Co
l8v
53
wi
nc
PWR
3.3V OTP Analog Power Supply
--
USB_AVDD33
PWR
3.3V USB Analog Power Supply
54
ISENSE
--
USB Current Source
Connect pin to ground with resistance.
15
AVDD33
13
14
18
19
20
23
AVDD18
41
31
LDO11_VOUT
42
32
LDO11_V18
43
33
BUCK18_VX
44
87
34
67
VBAT_IN
86
66
FLY18
88
68
FLY11
22
17
NC
29
30
31
32
24
25
26
27
DNC
tin
gh
am
dr
7a
M zhg
AR a8
VE 18
LL 9kc
CO blg
NF wl
ID 8g1
EN 2a
TI 4v
AL 3h
, U pND i72
ER og
NDizr *
A# Gl
12 oba
15 l N
02 e
08 two
rk
Li
2f
vc
yp
pv
1u
18
19
23
24
25
28
VTR_VDD33
20
PWR
3.3V Analog Power Supply
PWR
1.8V Analog Power Supply
PWR
1.1V LV LDO Voltage Output
--
BUCK18 Inductor Connection
--
BUCK18 Inductor Connection
PWR
LDO VBAT Input
This pin must be connected to VBAT/V33 input even if
BUCK18 is not used.
--
1.8V LDO Fly Capacitor to Ground Connection
--
1.1V LDO Fly Capacitor to Ground Connection
NC
No Connect
NOTE: CONNECT THESE PINS to GROUND.
DNC
Do Not Connect
Do not connect these pins. Leave these pins floating.
l8
cy
l8
I/O Digital Power Supply
50
74
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nc
Doc. No. MV-S109936-00 Rev. A
1u
yp
Page 66
nc
PWR
VDDIO_0
VDDIO_AON
63
wi
1.1V Core Power Supply Input
41
60
am
1u
yp
PWR
hg
51
VDD11
kc
73
D e s c r i p t io n
18
77
Ty p e
l8
58
28
49
Pin Name
blg
34
6 8 -P in
g1
hp
33
59
4v
8 8 -P in
CONFIDENTIAL
Document Classification: Proprietary
Copyright © 2015 Marvell
February 3, 2015, 1.00
n
Co
tin
lo
al
gh
Package
giz
*G
1.5
rk
Li
Configuration Pins
Configuration Pins
-i7
7a
M zhg
AR a8
VE 18
LL 9kc
CO blg
NF wl
ID 8g1
EN 2a
TI 4v
AL 3h
, U pND i72
ER og
NDizr *
A# Gl
12 oba
15 l N
02 e
08 two
Table 17 shows the pins used as configuration inputs to set parameters following a reset. The
definition of these pins changes immediately after reset to their usual function. To set a configuration
bit to 0, attach a 100 kΩ resistor from the pin to ground. No external circuitry is required to set a
configuration bit to 1.
hp
4v
g1
l8
blg
Table 17: Configuration Pins
kc
18
C o n fi g u r a t io n
B i ts
Pin Name
C o n f i g u r a ti o n F u n c t io n
nt
ro
Co
l8v
GPIO_27
az
CON[4]
Boot Options
00 = boot from UART
01 = reserved
10 = boot from USB
11 = boot from Flash (default)
yp
GPIO_16
hg
CON[5]
wi
nc
pv
tin
1u
gh
am
2f
l8
cy
am
1u
yp
wi
nc
l8
vc
yp
7a
M zhg
AR a8
VE 18
LL 9kc
CO blg
NF wl
ID 8g1
EN 2a
TI 4v
AL 3h
, U pND i72
ER og
NDizr *
A# Gl
12 oba
15 l N
02 e
08 two
rk
Li
dr
wi
nc
Copyright © 2015 Marvell
1u
yp
February 3, 2015, 1.00
CONFIDENTIAL
Document Classification: Proprietary
Doc. No. MV-S109936-00 Rev. A
Page 67
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This
device may not cause harmful interference, and (2) this device must accept any interference received, including
interference that may cause undesired operation.
Changes or modifications not expressly approved by the party responsible for compliance could void the user's
authority to operate the equipment.
NOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant
to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful
interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and,
if not installed and used in accordance with the instructions, may cause harmful interference to radio
communications. However, there is no guarantee that interference will not occur in a particular installation. If this
equipment does cause harmful interference to radio or television reception, which can be determined by turning the
equipment off and on, the user is encouraged to try to correct the interference by one or more of the following
measures:
-- Reorient or relocate the receiving antenna.
-- Increase the separation between the equipment and receiver.
-- Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
-- Consult the dealer or an experienced radio/TV technician for help.
FCC Radiation Exposure Statement
The modular can be installed or integrated in mobile or fix devices only. This modular cannot be installed in any
portable device, for example, USB dongle like transmitters is forbidden.
This modular complies with FCC RF radiation exposure limits set forth for an uncontrolled environment. This
transmitter must not be co-located or operating in conjunction with any other antenna or transmitter. This modular
must be installed and operated with a minimum distance of 20 cm between the radiator and user body.
If the FCC identification number is not visible when the module is installed inside another device, then the outside
of the device into which the module is installed must also display a label referring to the enclosed module. This
exterior label can use wording such as the following: “Contains Transmitter Module FCC ID: YCJGTIMW302"
or "Contains FCC ID: YCJGTIMW302”
when the module is installed inside another device, the user manual of this device must contain below warning
statements;
1. This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:
(1) This device may not cause harmful interference.
(2) This device must accept any interference received, including interference that may cause undesired operation.
2. Changes or modifications not expressly approved by the party responsible for compliance could void the user's
authority to operate the equipment.
This device must be installed and operated with a minimum distance of 20 cm between the radiator and user body.
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