Microchip Technology BM57SPPSYC2A Bluetooth Module User Manual Manual

Microchip Technology Inc. Bluetooth Module Manual

Manual

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Document DescriptionManual
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Document TypeUser Manual
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Filesize101.06kB (1263224 bits)
Date Submitted2012-03-25 00:00:00
Date Available2012-04-16 00:00:00
Creation Date2012-03-13 17:01:53
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Document Lastmod2012-03-13 17:01:53
Document TitleMicrosoft Word - Datasheet_BM57SPPSy_120308_FCC.doc
Document CreatorPScript5.dll Version 5.2
Document Author: Anthony

Datasheet of Bluetooth
BM57SPPSyC2 Module
iSSC Technologies Corp.
Revision History
Date
2012/03/08
Revision Content
Preliminary Draft Version
Version
0.2
Content
1.
Introduction ...................................................................................................................... 3
1.1.
Major Components ....................................................................................................................................... 3
1.2.
Features........................................................................................................................................................ 3
1.3.
Application .................................................................................................................................................... 4
1.4.
Certifications ................................................................................................................................................. 4
2.
Product Specification ...................................................................................................... 5
2.1.
Chipset.......................................................................................................................................................... 5
2.2.
Interfaces ...................................................................................................................................................... 5
2.3.
Hardware Design Considerations ................................................................................................................. 5
3.
Hardware Architecture ................................................................................................... 10
4.
Compatibility Requirements.......................................................................................... 10
5.
Environmental Requirements ....................................................................................... 11
5.1.
Temperature ............................................................................................................................................... 11
5.2.
Humidity ...................................................................................................................................................... 11
Appendix A: Dimension and Foot Print ................................................................................. 12
Appendix B: Product Image .................................................................................................... 13
Appendix C: PIN Assignment ................................................................................................. 14
Appendix D: Reflow Profile ..................................................................................................... 16
Appendix E: Schematic ........................................................................................................... 17
Appendix F: Reference Schematic ......................................................................................... 18
Appendix G: Test Board Layout Information ......................................................................... 19
Appendix H: Test Board Layout Information ......................................................................... 19
Appendix H: Label Information ............................................................................................... 19
Appendix I: Packaging Information ........................................................................................ 20
Appendix I: Reversion History ................................................................................................ 21
CONFIDENTIAL
© 2000~2011 iSSC Technologies Corp.
1. Introduction
Part Name: iSSC BM57SPPSyC2 Bluetooth module
Part Number: BM57SPPSyC2-xxxxxx
The iSSC BM57SPPSyC2 Bluetooth module is design for MFi (The Made for iPod, Made for iPhone and Made for
iPad logos) electronic accessory via Bluetooth connectivity. It is available in the 2.4GHz ISM band Class 2 Radio,
compatible with Bluetooth Core Specification Version 3.0 + EDR.
iSSC IS1657NM single chip solution combines transceiver and baseband function to decrease the external
components. It narrows down the module size and minimizes its cost. The optimized power designs minimize power
consumption to keep low battery.
The module is integrated with shielding case and 2.4GHz RF Chip antenna. It has passed the Bluetooth SIG and
FCC Part 15 certification.
*Notice:
1. Changes or modifications made to this equipment not expressly approved by the Grantee of the FCC
ID may void the FCC authorization to operate this equipment.
2. LABEL OF THE END PRODUCT: The final end product must be labeled in a visible area with the following
" Contains FCC ID: A8TBM57SPPSYC2A”.
1.1. Major Components
- iSSC IS1657NM (48 pin QFN, single-chip Bluetooth transceiver and baseband processor)
- Serial EEPROM 8K (1024*8) TSSOP 8P
1.2. Features
- Bluetooth 3.0 EDR compliant
- Low power 1.8V RF operation
- RF transmitter output power Class 2
- RF receiver GFSK typical -90dBm, π/4 PSK typical -90dBm, 8DPSK typical -83dBm
- Internal ROM and 4Mibts of flash
- HCI over UART
- I2C for external EEPROM and authentication chip (to enable functionality between your electronic accessory and
the iPod, iPhone and iPad)
- 1 LED driver
- 2.4GHz ceramic chip antenna
CONFIDENTIAL
© 2000~2011 iSSC Technologies Corp.
1.3. Application
- GPS
- Printers
- Electric Scale
- Blood Pressure Monitors
- Bar code Scanner
- Industrial Applications (CNC, PLC, RFID)
- Embedded systems
1.4. Certifications
- Bluetooth SIG: QDID B017511
http://www.bluetooth.org/tpg/QLI_viewQDL.cfm?qid=17511
- FCC ID: A8TBM57SPPSYC2A
CONFIDENTIAL
© 2000~2011 iSSC Technologies Corp.
2. Product Specification
2.1. Chipset
7x7 mm2 48 pin QFN IS1657NM
2.2. Interfaces
- Multi function GPIO interface
- Bluetooth RF interface
- HCI over URAT up to 921600 bps
- I2C for external EEPROM and authentication chip
- 2/4 wires SPI interface (master/slave) for external peripherals control. (Optional)
2.3. Hardware Design Considerations
- Power
The module requires either a 3.3V or 5V supply voltage. (3.3V was suggested)
- Power ramp-up timing restriction
1) BAT_IN : ramp-up (0 to 1.6V) < 200ms
2) PMULDO_O : PMU-logic ramp-up (0 to 1.6V) <60ms
3) VCC_RF (1.8V power domain) : RF BPOR ramp-up (0 to 1.6V) < 20ms
- Power on sequence
1) BAT_IN/ BAT_IN_5V: must be first!
2) 3.3V power domain: VDD_IO/ VDD_FIO must power-up early than 1.8V power.
3) 1.8V power domain: 1V8/ VCC_RF/ VDD_XO/ 1V8_U_P
4) RST_N: digital reset released from 0 to 1.6V must be the last one.
- Recommended operating conditions
Rating
Min
Typ
Max
VDD_IO_x,
3.2V
3.63V
SW_BTN
3.2V
4.3V
BAT_IN
3.2V
4.3V
- Clock Sources
A high accuracy crystal with ±10ppm tolerance is connected to the BM57SPPSyC2 clock input pins.
- Serial Flash and Firmware Version
Firmware code is stored on chip internal flash.
- Radio Characteristics
Bluetooth V3.0 + EDR
Frequency Band: 2402-2480 GHz
Number of Channels: 79 1MHz channels
CONFIDENTIAL
© 2000~2011 iSSC Technologies Corp.
- Current Consumption
Operation Mode
Peak
AVG
current
current
Unit
Peak current at TX mode
50.357
mA
Peak current at RX mode
49.413
mA
Standby mode (Discoverable &
Note
2.382
mA
Deep power down mode
0.276
mA
Connected + Sniff, Master (No data)
2.723
mA
Connected + Sniff, Master (No data)
0.673
mA
Connected + Sniff, Slave (No data)
0.745
mA
Data, Master
17.641
mA
Data transmitted at 115200bps
Data, Slave
18.025
mA
Data transmitted at 115200bps
connectable mode
No data was transmitted
Sniff (40 20 4 0)
No data was transmitted
Sniff (500 20 4 0)
No data was transmitted
Sniff (500 20 3 3) iPhone parameters
- Terminal characteristics
Condition :
VDD_IO=3.3V
Min
Typ
Max
Unit
I/O voltage levels
VIL input logic levels low
-0.3
0.8
VIH input logic levels high
2.0
3.6
0.4
VOL output logic levels low
VOH output logic levels
2.4
high
Reset terminal
VTH,res threshold voltage
1.6
65
Kohm
Input and tri-state current with
Pull-up Resistor
Leakage current
-10
+10
μA
TX mode
70
mA
RX mode
70
mA
Vdd supply current
CONFIDENTIAL
© 2000~2011 iSSC Technologies Corp.
- Baud Rate
Desired baud rate
Clock
Div
Actual Baud rate
Error Rate %
921600
48000000
13
3.50641026
923077
0.16
460800
48000000
13
7.51282051
461538
0.16
230400
48000000
13
15.525641
230769
0.16
115200
16000000
13
10.1837607
111888
-2.87
57600
16000000
13
20.8675214
58608
1.75
38400
16000000
13
31.5512821
38462
0.16
28800
16000000
13
42.2350427
28623
-0.62
19200
16000000
13
63.6025641
19231
0.16
14400
16000000
13
84.9700855
14480
0.55
9600
16000000
13
127.705128
9615
0.16
4800
16000000
13
255.910256
4808
0.16
2400
16000000
13
512.320513
2399
-0.03
- Testing Criterion
NO.
Testing Item Name
Spec.
Device Initialization
System Verify
System Power>1.6V
PMU LDO trim
1.8~2.1
Calibration LDO18
1.81~1.93V
Calibration LDO33
3.1~3.4V
RF frequency calibration
< 10k Hz
RF TX power verify
> -5 dBm
8852 output power
-2dbm~+4dbm
Initial carrier test
+/- 30KHz
10
Single slot sensitivity
> -70dbm
11
Multi slot sensitivity
> -70dbm
‘140KHz ≦ f1avg ≦ 175KHz
12
Modulation index test
f2max ≧ 115KHz
f2/f1avg ≧ 0.8
CONFIDENTIAL
© 2000~2011 iSSC Technologies Corp.
- Timing Sequence
Timing Sequence for Mode selection Pin (P20, P24) under APP mode
Pin No.
I/O
Name
Description
BAT_IN
3.3V power input
VDD_IO
Main power supply
17
P20
System configuration, refer to P2_4, MCU do NOT drive under APP Mode
Boot mode selection (MCU NOT drive under APP Mode)
18
P2_0/ P2_4: HH Æ Application
P24
LL Æ Boot mode
LH Æ HCI UART mode for testing and system configuration.
7.28ms
41.1ms
P20
P24
VDDIO
Power
P20, P24 Mode Selection Timing Diagram
CONFIDENTIAL
© 2000~2011 iSSC Technologies Corp.
Timing Sequence for Rest Pin (RST_N) under different mode
22
RST_N
External reset input (Low Active), clock period 62.5n at least.
60 ms
External Rest
400 ms
1 ms
Write Flash Mode
Ready
for MCU
Test Mode
Ready
for MCU
APP Mode
Ready
for MCU
5 ms
RST_N Timing Diagram
CONFIDENTIAL
© 2000~2011 iSSC Technologies Corp.
3. Hardware Architecture
Block Diagram
32 mm
IS1657NM
I2C
Antenna
RTX
(Class 2)
UART/ HCI Interface
GPIO Control
EEPROM
16M XTAL
12.6 mm
Power Tree
BM57 Module
IS1657NM
2V8 ~ 3V3
LDO33_O
VDD_FIO
USB_VDD
LDO18_I
BAT_IN_5V
BAT_IN
5V
3V~4V2
Either One
BAT_IN is
recommended
BAT_IN_5V
VDD_IO
2V8 ~ 3V3
VDD_IO
LDO18_O
BAT_IN
1V8
VDD_XO
VCC_RF
AVDD_SAR
1V8_U_P
1V8
EEPROM
4. Compatibility Requirements
The BM57SPPSyC2 Bluetooth module shall pass the standard test plan, which includes hardware compatibility and
reliability, and software compatibility test.
CONFIDENTIAL
© 2000~2011 iSSC Technologies Corp.
10
5. Environmental Requirements
5.1. Temperature
Conditions
Operating Temperature
Non-Operating Temperature
Minimum
-10 ℃
-40℃
Maximum
+70 ℃
+80 ℃
Conditions
Operating Humidity
Non-Operating Humidity
Minimum
10%
5%
Maximum
90%
95%
5.2. Humidity
CONFIDENTIAL
© 2000~2011 iSSC Technologies Corp.
11
Appendix A: Dimension and Foot Print
1. Dimension
•
32mm* 12.6mm* 1.86mm (Length* Width* Height)
•
board thickness: 0.8mm (4 layers PCB)
2. Module Foot Print
3. The mandatory layout under the module.
4. The solder stop mask
CONFIDENTIAL
© 2000~2011 iSSC Technologies Corp.
12
Appendix B: Product Image
CONFIDENTIAL
© 2000~2011 iSSC Technologies Corp.
13
Appendix C: PIN Assignment
Chip Antenna
10
11
12
13
14
15
16
GND
SAR_BAT
BAT_IN_5V
BAT_IN
SW_BTN
LDO33_O
VDD_IO
LDO18_O
WAKEUP
PMULDO_O
P04
P12 / SCL
P13 / SDA
P16
USB_DP
USB_DM
32
BT_RF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
GND
LED1
P07
P25
P23
P27
P26
HCI_TXD
HCI_RXD
RST_N
EAN
P22
P21
P24
P20
BM57_V2
Pin #
I/O
Name
Description
GND
Ground
SAR_BAT
Reserved
BAT_IN_5V
5V power input
BAT_IN
3.3V power input
SW_BTN
Reserved
LDO33_O
3V3 LDO output
VDD_IO
Main power supply
LDO18_O
LDO18 output
WAKEUP
10
PMULDO_O
Wakeup BM57 from Shutdown State. (Low Active)
It is only valid while BM57 into Shutdown State.
Output of PMULDO
UART_TX_IND:
H: BM57 indicate UART data will be transmitted out after a certain timing
11
P04
(setting by EEPROM, default 5 ms)
L: Otherwise.
STATUS_IND_2: BM57 State indication , refer to P22
12
I/O
P12/ SCL
I2C_SCL, for Authentication Coprocessor 2.0B
13
I/O
P13/ SDA
I2C_SDA, for Authentication Coprocessor 2.0B
14
I/O
P16
EEPROM WP
CONFIDENTIAL
© 2000~2011 iSSC Technologies Corp.
14
15
I/O
USB_DP
Reserved
16
I/O
USB_DM
Reserved
17
P20
System configuration, refer to P2_4, No drive under APP Mode
Boot mode selection (No drive under APP Mode)
18
P24
P2_0/ P2_4: HH Æ Application
LL Æ Boot mode
LH Æ HCI UART mode for testing and system configuration.
19
P21
CP_RST:
Reset Authentication Coprocessor 2.0B
STATUS_IND:
Bluetooth link status indication,
20
P22
P22/P04: HH Æ Power default value and Shutdown State.
P22/P04: HL Æ Access State.
P22/P04: LL Æ Link State w/o UART_TXD.
P22/P04: LH Æ Link State with UART_TXD.
ROM/ Flash selection. (No drive under APP Mode)
21
EAN
22
RST_N
External reset input (Low Active), clock period 62.5n at least.
23
HCI_RXD
UART_RXD
24
HCI_TXD
UART_TXD
25
P26
H: ROM code; L: Flash code
UART_CTS:
UART Flow Control- set HIGH to disable TX transmitter.
UART_RTS:
26
P27
UART Flow Control- go HIGH to disable host transmitter.
Open data session indication- go LOW when APP session is ready.
LINK_DROP:
27
P23
Host_MCU ask to drop SPP link under Link State;
One low pulse with 10 ms duration low signal to trigger SPP disconnection.
Otherwise it will be set as high always.
28
P25
Pairing Key:
Device will enter Standby Mode after pull low over 240ms.
UART_RX_IND:
29
P07
L: Inform BM57 that UART data will be transmitted out after 1 ms
H: Otherwise.
30
LED1
LED1 driver
31
GND
Ground
32
RI/O
BT_RF
RF Port
CONFIDENTIAL
© 2000~2011 iSSC Technologies Corp.
15
Appendix D: Reflow Profile
1.) Follow: IPC/JEDEC J-STD-020 C
2.) Condition:
Average ramp-up rate (217℃ to peak): 1~2℃/sec max.
Preheat:150~200C、60~180 seconds
Temperature maintained above 217℃ : 60~150 seconds
Time within 5℃ of actual peak temperature: 20 ~ 40 sec.
Peak temperature:250+0/-5℃ or 260+0/-5℃
Ramp-down rate : 3℃/sec. max.
Time 25℃ to peak temperature : 8 minutes max.
Cycle interval:5 minus
Slope: 1~2℃/ sec max.
(217℃ to peak)
Peak: 250+0/-5℃
Or 260+0/-5℃
Ramp down rate:
Max. 3℃/sec.
217℃
Preheat: 150~200℃
20~40 sec.
60~180 sec.
60~150 sec.
25℃
Time (sec)
CONFIDENTIAL
© 2000~2011 iSSC Technologies Corp.
16
Appendix E: Schematic
5V_IN
C3
10u/6.3V
L1
C4
1.8p/50V
LDO33_O
4.7nH
BT_RF1
C6
1.2p/50V
LDO18_O
LDO18_O
C5
10u/6.3V
2.7nH
C7
CAN4311851042453K
NP-0402
VBAT_IN
ANT1
L2
SAR_BAT
C8
10u/6.3V
C9
SW_BTN
1u/16V
C11
9p/50V
C14
1u/10V
48
47
46
45
44
43
42
41
40
39
38
37
EP
LDO18_O 1
WAKEUP
PMULDO_O 3
P04
P16
P12
P13
10
11
12
LDO18_O
XO_N
WAKEUP
XO_P
VDD_XO
PMULDO_O
VDD_FIO
NC
P0_4
P0_7
P1_4/TX_CLS1
P2_5/SCLK
P1_5/RX_CLS1
P2_3/MOSI
P2_7/MISO
P1_6/WP
P1_2/SCL
P2_6/NCS
P1_3/SDA QFN48-SPP Bridge
VDD_IO
GND
1V8
HCI_TXD
1V8
IS1657NM
9p/50V
36
35
34
33
32
31
30
29
28
27
26
25
P07
P25
P23
P27
P26
LDO33_O
1u/10V
C16
LDO33_O
LDO18_O
1u/10V
C15
LDO18_O
13
14
15
16
17
18
19
20
21
22
23
24
HCI_TXD
LDO18_O
C13
X1
VDD_IO
USB_DP
USB_DM
USB_VDD
1V8_U_P
P2_0
P2_4
P2_1
P2_2
EAN
RST_N
HCI_RXD
LDO18_O
C12
10u/6.3V
X4P-16MHZ-HLT
1V8_GND
LDO18_IN
LDO33_O
SW_BTN
BAT_IN
BAT_IN_5V
SAR_BAT
AVDD_SAR
RTX
RX
VCC_RF
LED1
49
LED1
HCI_RXD
P20
P24
P21
P22
EAN
LDO33_O
USB_DP
USB_DM
RST_N
R3
4K7
LDO33_O
LDO18_O
1u/10V
C17
1u/10V
C19
5V_IN
GND
BT_RF
32
VBAT_IN
LDO33_O
LDO18_O
SAR_BAT 2
SW_BTN 5
WAKEUP 9
PMULDO_O
10
P04
11
P12
12
P13
13
P16
14
USB_DP 15
USB_DM 16
SAR_BAT
BAT_IN_5V
BAT_IN
SW_BTN
LDO33_O
VDD_IO
LDO18_O
WAKEUP
PMULDO_O
P04
P12 / SCL
P13 / SDA
P16
USB_DP
USB_DM
GND
LED1
P07
P25
P23
P27
P26
HCI_TXD
HCI_RXD
RST_N
EAN
P22
P21
P24
P20
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
LED1
P07
P25
P23
P27
P26
HCI_TXD
HCI_RXD
RST_N
EAN
P22
P21
P24
P20
BM57_V2
CONFIDENTIAL
© 2000~2011 iSSC Technologies Corp.
17
VDD_IO
A0
A1
A2
GND
VCC
WP
SCL
SDA
P16
P12/SCL
P13/SDA
U4
IS24C08A
VDD_IO
R6
10K
Appendix F: Reference Schematic
GND
BT_RF
32
3V3
LED1
4V2~3V2
WAKEUP (option)
10
UART_TX_IND (option) 11
CP_SCL (option) 12
CP_SDA (option) 13
14
15
16
SAR_BAT
BAT_IN_5V
BAT_IN
SW_BTN
LDO33_O
VDD_IO
LDO18_O
WAKEUP
PMULDO_O
P04
P12 / SCL
P13 / SDA
P16
USB_DP
USB_DM
GND
LED1
P07
P25
P23
P27
P26
HCI_TXD
HCI_RXD
RST_N
EAN
P22
P21
P24
P20
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
LED1
UART_RX_IND (option)
Pairing Key (option)
LINK_DROP (option)
LED-B
UART_RTS (option)
UART_CTS (option)
HCI_TXD
HCI_RXD
RST_N (option)
ROM/ Flash selection (reserv e test point)
STATUS_IND (recommend)
TP1
CP_RST (option)
Boot mode selection (reserv e test point)
Sy stem conf iguration (reserv e test point)
TP2
TP3
BM57_V2
Test Point: TP1, TP2, TP3 are recommended for future firmware, EEPROM table update if the module are welded
on load board.
CONFIDENTIAL
© 2000~2011 iSSC Technologies Corp.
18
Appendix G: Test Board Layout Information
1. The CN1 is reserved for SMA Connector, It’s will be used only if user would like to check
module RF performance.
2. The C4 components must be removed under general condition. The RF trace will output from
the chip antenna on the module.
Appendix H: Test Board Layout Information
Top
Bottom
Appendix H: Label Information
TBA
CONFIDENTIAL
© 2000~2011 iSSC Technologies Corp.
19
Appendix I: Packaging Information
TBA
CONFIDENTIAL
© 2000~2011 iSSC Technologies Corp.
20
Appendix I: Reversion History
Version
0.1
Date
History
2011/12/11
Preliminary Draft Version
CONFIDENTIAL
© 2000~2011 iSSC Technologies Corp.
21

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