Motorola Coldfire Mcf5281 Users Manual 5282UM

2015-01-23

• About This Book
  • Audience
  • Organization
  • Suggested Reading
    • General Information
    • ColdFire Documentation
  • Conventions
  • Acronyms and Abbreviations
  • Terminology Conventions
  • Revision History
• Chapter 1 Overview
  • 1.1 MCF5282 Key Features
    • Figure 1-1. MCF5282 Block Diagram
    • 1.1.1 Version 2 ColdFire Core
      • 1.1.1.1 Cache
        • Table 1-1. Cache Configuration
      • 1.1.1.2 SRAM
      • 1.1.1.3 Flash
      • 1.1.1.4 Debug Module
    • 1.1.2 System Control Module
    • 1.1.3 External Interface Module (EIM)
    • 1.1.4 Chip Select
    • 1.1.5 Power Management
    • 1.1.6 General Input/Output Ports
    • 1.1.7 Interrupt Controllers (INTC0/INTC1)
    • 1.1.8 SDRAM Controller
    • 1.1.9 Test Access Port
    • 1.1.10 UART Modules
    • 1.1.11 DMA Timers (DTIM0-DTIM3)
    • 1.1.12 General-Purpose Timers (GPTA/GPTB)
    • 1.1.13 Periodic Interrupt Timers (PIT0-PIT3)
    • 1.1.14 Software Watchdog Timer
    • 1.1.15 Phase Locked Loop (PLL)
    • 1.1.16 DMA Controller
    • 1.1.17 Reset
  • 1.2 MCF5282-Specific Features
    • 1.2.1 Fast Ethernet Controller (FEC)
    • 1.2.2 FlexCAN
    • 1.2.3 I2C Bus
    • 1.2.4 Queued Serial Peripheral Interface (QSPI)
    • 1.2.5 Queued Analog-to-Digital Converter (QADC)
• Chapter 2 ColdFire Core
  • 2.1 Processor Pipelines
    • Figure 2-1. ColdFire Processor Core Pipelines
  • 2.2 Processor Register Description
    • 2.2.1 User Programming Model
      • 2.2.1.1 Data Registers (D0-D7)
      • 2.2.1.2 Address Registers (A0-A6)
      • 2.2.1.3 Stack Pointer (A7)
      • 2.2.1.4 Program Counter (PC)
        • Figure 2-2. User Programming Model
      • 2.2.1.5 Condition Code Register (CCR)
        • Figure 2-3. Condition Code Register (CCR)
        • Table 2-1. CCR Field Descriptions
    • 2.2.2 EMAC Programming Model
      • Figure 2-4. EMAC Register Set
    • 2.2.3 Supervisor Programming Model
      • Figure 2-5. Supervisor Programming Model
      • 2.2.3.1 Status Register (SR)
        • Figure 2-6. Status Register
        • Table 2-2. SR Field Descriptions (continued)
      • 2.2.3.2 Supervisor/User Stack Pointers (A7 and OTHER_A7)
      • 2.2.3.3 Vector Base Register (VBR)
      • 2.2.3.4 Cache Control Register (CACR)
      • 2.2.3.5 Access Control Registers (ACR0, ACR1)
      • 2.2.3.6 Memory Base Address Registers (RAMBAR, FLASHBAR)
  • 2.3 Programming Model
    • Table 2-3. ColdFire CPU Registers (continued)
  • 2.4 Additions to the Instruction Set Architecture
    • Table 2-4. ISA Revision A+ New Instructions
  • 2.5 Exception Processing Overview
    • Table 2-5. Exception Vector Assignments (continued)
  • 2.6 Exception Stack Frame Definition
    • Figure 2-7. Exception Stack Frame Form
    • Table 2-6. Format Field Encodings
    • Table 2-7. Fault Status Encodings
  • 2.7 Processor Exceptions
    • 2.7.1 Access Error Exception
    • 2.7.2 Address Error Exception
    • 2.7.3 Illegal Instruction Exception
    • 2.7.4 Divide-By-Zero
    • 2.7.5 Privilege Violation
    • 2.7.6 Trace Exception
    • 2.7.7 Unimplemented Line-A Opcode
    • 2.7.8 Unimplemented Line-F Opcode
    • 2.7.9 Debug Interrupt
    • 2.7.10 RTE and Format Error Exception
    • 2.7.11 TRAP Instruction Exception
    • 2.7.12 Interrupt Exception
    • 2.7.13 Fault-on-Fault Halt
    • 2.7.14 Reset Exception
      • Figure 2-8. D0 Hardware Configuration Info
      • Table 2-8. D0 Hardware Configuration Info Field Description
      • Figure 2-9. D1 Hardware Configuration Info
      • Table 2-9. D1 Local Memory Hardware Configuration Information Field Description (continued)
  • 2.8 Instruction Execution Timing
    • 2.8.1 Timing Assumptions
      • Table 2-10. Misaligned Operand References
    • 2.8.2 MOVE Instruction Execution Times
      • Table 2-11. Move Byte and Word Execution Times
      • Table 2-12. Move Long Execution Times
  • 2.9 Standard One Operand Instruction Execution Times
    • Table 2-13. One Operand Instruction Execution Times
  • 2.10 Standard Two Operand Instruction Execution Times
    • Table 2-14. Two Operand Instruction Execution Times (continued)
  • 2.11 Miscellaneous Instruction Execution Times
    • Table 2-15. Miscellaneous Instruction Execution Times
  • 2.12 EMAC Instruction Execution Times
    • Table 2-16. EMAC Instruction Execution Times
  • 2.13 Branch Instruction Execution Times
    • Table 2-17. General Branch Instruction Execution Times
    • Table 2-18. BRA, Bcc Instruction Execution Times
  • 2.14 ColdFire Instruction Set Architecture Enhancements
• Chapter 3 Enhanced Multiply-Accumulate Unit (EMAC)
  • 3.1 Multiply-Accumulate Unit
    • Figure 3-1. Multiply-Accumulate Functionality Diagram
  • 3.2 Introduction to the MAC
    • Figure 3-2. Infinite Impulse Response (IIR) Filter
    • Figure 3-3. Four-Tap FIR Filter
  • 3.3 General Operation
    • Figure 3-4. Fractional Alignment
    • Figure 3-5. Signed and Unsigned Integer Alignment
  • 3.4 Memory Map/Register Set
    • Figure 3-6. EMAC Register Set
    • 3.4.1 MAC Status Register (MACSR)
      • Figure 3-7. MAC Status Register (MACSR)
      • Table 3-1. MACSR Field Descriptions (continued)
      • Table 3-2. Summary of S/U, F/I, and R/T Control Bits
      • 3.4.1.1 Fractional Operation Mode
    • 3.4.2 Mask Register (MASK)
  • 3.5 EMAC Instruction Set Summary
    • Table 3-3. EMAC Instruction Summary
    • 3.5.1 EMAC Instruction Execution Times
      • Figure 3-8. EMAC-Specific OEP Sequence Stall
    • 3.5.2 Data Representation
      • Figure 3-9. Two’s Complement, Signed Fractional Equation
    • 3.5.3 MAC Opcodes
• Chapter 4 Cache
  • 4.1 Cache Features
  • 4.2 Cache Physical Organization
    • Figure 4-1. Cache Block Diagram
  • 4.3 Cache Operation
    • 4.3.1 Interaction with Other Modules
    • 4.3.2 Memory Reference Attributes
    • 4.3.3 Cache Coherency and Invalidation
    • 4.3.4 Reset
    • 4.3.5 Cache Miss Fetch Algorithm/Line Fills
      • Table 4-1. Initial Fetch Offset vs. CLNF Bits
      • Table 4-2. Instruction Cache Operation as Defined by CACR[31, 10]
  • 4.4 Cache Programming Model
    • 4.4.1 Cache Registers Memory Map
      • Table 4-3. Memory Map of Cache Registers
    • 4.4.2 Cache Registers
      • 4.4.2.1 Cache Control Register (CACR)
        • Figure 4-2. Cache Control Register (CACR)
        • Table 4-4. CACR Field Descriptions (continued)
        • Table 4-5. Cache Configuration as Defined by CACR[31, 23, 22]
        • Table 4-6. Cache Invalidate All as Defined by CACR[23, 22, 21, 20]
        • Table 4-7. External Fetch Size Based on Miss Address and CLNF
      • 4.4.2.2 Access Control Registers (ACR0, ACR1)
        • Figure 4-3. Access Control Registers (ACR0, ACR1)
        • Table 4-8. ACR Field Descriptions (continued)
• Chapter 5 Static RAM (SRAM)
  • 5.1 SRAM Features
  • 5.2 SRAM Operation
  • 5.3 SRAM Programming Model
    • 5.3.1 SRAM Base Address Register (RAMBAR)
      • Figure 5-1. SRAM Base Address Register (RAMBAR)
      • Table 5-1. SRAM Base Address Register (continued)
    • 5.3.2 SRAM Initialization
    • 5.3.3 SRAM Initialization Code
    • 5.3.4 Power Management
      • Table 5-2. Typical RAMBAR Setting Examples
• Chapter 6 ColdFire Flash Module (CFM)
  • 6.1 Features
  • 6.2 Block Diagram
    • Figure 6-1. CFM Block Diagram
  • 6.3 Memory Map
    • Figure 6-2. CFM Array Memory Map
    • 6.3.1 CFM Configuration Field
      • Table 6-1. CFM Configuration Field
    • 6.3.2 Flash Base Address Register (FLASHBAR)
      • Figure 6-3. Flash Base Address Register (FLASHBAR)
      • Table 6-2. FLASHBAR Field Descriptions
    • 6.3.3 CFM Registers
      • Table 6-3. CFM Register Address Map
    • 6.3.4 Register Descriptions
      • 6.3.4.1 CFM Configuration Register (CFMCR)
        • Figure 6-4. CFM Module Configuration Register (CFMCR)
        • Table 6-4. CFMCR Field Descriptions
      • 6.3.4.2 CFM Clock Divider Register (CFMCLKD)
        • Figure 6-5. CFM Clock Divider Register (CFMCLKD)
        • Table 6-5. CFMCLKD Field Descriptions
      • 6.3.4.3 CFM Security Register (CFMSEC)
        • Figure 6-6. CFM Security Register (CFMSEC)
        • Table 6-6. CFMSEC Field Descriptions
      • 6.3.4.4 CFM Protection Register (CFMPROT)
        • Figure 6-7. CFM Protection Register (CFMPROT)
        • Table 6-7. CFMPROT Field Descriptions
        • Figure 6-8. CFMPROT Protection Diagram
      • 6.3.4.5 CFM Supervisor Access Register (CFMSACC)
        • Figure 6-9. CFM Supervisor Access Register (CFMSACC)
        • Table 6-8. CFMSACC Field Descriptions
      • 6.3.4.6 CFM Data Access Register (CFMDACC)
        • Figure 6-10. CFM Data Access Register (CFMDACC)
        • Table 6-9. CFMDACC Field Descriptions
      • 6.3.4.7 CFM User Status Register (CFMUSTAT)
        • Figure 6-11. CFM User Status Register (CFMUSTAT)
        • Table 6-10. CFMUSTAT Field Descriptions
      • 6.3.4.8 CFM Command Register (CFMCMD)
        • Figure 6-12. CFM Command Register (CFMCMD)
        • Table 6-11. CFMCMD Field Descriptions
        • Table 6-12. CFMCMD User Mode Commands
  • 6.4 CFM Operation
    • 6.4.1 Read Operations
    • 6.4.2 Write Operations
    • 6.4.3 Program and Erase Operations
      • 6.4.3.1 Setting the CFMCLKD Register
      • 6.4.3.2 Program, Erase, and Verify Sequences
      • 6.4.3.3 Flash Valid Commands
        • Table 6-13. Flash User Commands
        • Figure 6-13. Example Program Algorithm
      • 6.4.3.4 Flash User Mode Illegal Operations
    • 6.4.4 Stop Mode
    • 6.4.5 Master Mode
  • 6.5 Flash Security Operation
    • 6.5.1 Back Door Access
    • 6.5.2 Erase Verify Check
  • 6.6 Reset
  • 6.7 Interrupts
    • Table 6-14. CFM Interrupt Sources
• Chapter 7 Power Management
  • 7.1 Features
  • 7.2 Memory Map and Registers
    • 7.2.1 Programming Model
    • 7.2.2 Memory Map
      • Table 7-1. Chip Configuration Module Memory Map
    • 7.2.3 Register Descriptions
      • 7.2.3.1 Low-Power Interrupt Control Register (LPICR)
        • Figure 7-1. Low-Power Interrupt Control Register (LPICR)
        • Table 7-2. LPICR Field Description
        • Table 7-3. XLPM_IPL Settings
      • 7.2.3.2 Low-Power Control Register (LPCR)
        • Figure 7-2. Low-Power Control Register (LPCR)
        • Table 7-4. LPCR Field Descriptions
        • Table 7-5. Low-Power Modes
        • Table 7-6. PLL/CLKOUT Stop Mode Operation
  • 7.3 Functional Description
    • 7.3.1 Low-Power Modes
      • 7.3.1.1 Run Mode
      • 7.3.1.2 Wait Mode
      • 7.3.1.3 Doze Mode
      • 7.3.1.4 Stop Mode
      • 7.3.1.5 Peripheral Shut Down
    • 7.3.2 Peripheral Behavior in Low-Power Modes
      • 7.3.2.1 ColdFire Core
      • 7.3.2.2 Static Random-Access Memory (SRAM)
      • 7.3.2.3 Flash
      • 7.3.2.4 System Control Module (SCM)
      • 7.3.2.5 SDRAM Controller (SDRAMC)
      • 7.3.2.6 Chip Select Module
      • 7.3.2.7 DMA Controller (DMAC0-DMA3)
      • 7.3.2.8 UART Modules (UART0, UART1, and UART2)
      • 7.3.2.9 I2C Module
      • 7.3.2.10 Queued Serial Peripheral Interface (QSPI)
      • 7.3.2.11 DMA Timers (DMAT0-DMAT3)
      • 7.3.2.12 Interrupt Controllers (INTC0, INTC1)
      • 7.3.2.13 Fast Ethernet Controller (FEC)
      • 7.3.2.14 I/O Ports
      • 7.3.2.15 Reset Controller
      • 7.3.2.16 Chip Configuration Module
      • 7.3.2.17 Clock Module
      • 7.3.2.18 Edge Port
      • 7.3.2.19 Watchdog Timer
      • 7.3.2.20 Programmable Interrupt Timers (PIT0, PIT1, PIT2 and PIT3)
      • 7.3.2.21 Queued Analog-to-Digital Converter (QADC)
      • 7.3.2.22 General Purpose Timers (GPTA and GPTB)
      • 7.3.2.23 FlexCAN
      • 7.3.2.24 ColdFire Flash Module
      • 7.3.2.25 BDM
      • 7.3.2.26 JTAG
    • 7.3.3 Summary of Peripheral State During Low-Power Modes
      • Table 7-7. CPU and Peripherals in Low-Power Modes (continued)
• Chapter 8 System Control Module (SCM)
  • 8.1 Overview
  • 8.2 Features
  • 8.3 Memory Map and Register Definition
    • Table 8-1. SCM Register Map
  • 8.4 Register Descriptions
    • 8.4.1 Internal Peripheral System Base Address Register (IPSBAR)
      • Figure 8-1. IPS Base Address Register (IPSBAR)
      • Table 8-2. IPSBAR Field Description
    • 8.4.2 Memory Base Address Register (RAMBAR)
      • Figure 8-2. Memory Base Address Register (RAMBAR)
      • Table 8-3. RAMBAR Field Description
    • 8.4.3 Core Reset Status Register (CRSR)
      • Figure 8-3. Core Reset Status Register (CRSR)
      • Table 8-4. CRSR Field Descriptions
    • 8.4.4 Core Watchdog Control Register (CWCR)
      • Figure 8-4. Core Watchdog Control Register (CWCR)
      • Table 8-5. CWCR Field Description
      • Table 8-6. Core Watchdog Timer Delay
    • 8.4.5 Core Watchdog Service Register (CWSR)
      • Figure 8-5. Core Watchdog Service Register (CWSR)
  • 8.5 Internal Bus Arbitration
    • Figure 8-6. Arbiter Module Functions
    • 8.5.1 Overview
    • 8.5.2 Arbitration Algorithms
      • 8.5.2.1 Round-Robin Mode
      • 8.5.2.2 Fixed Mode
    • 8.5.3 Bus Master Park Register (MPARK)
      • Figure 8-7. Default Bus Master Park Register (MPARK)
      • Table 8-7. MPARK Field Description
  • 8.6 System Access Control Unit (SACU)
    • 8.6.1 Overview
    • 8.6.2 Features
    • 8.6.3 Memory Map/Register Definition
      • Table 8-8. SACU Register Memory Map (continued)
      • 8.6.3.1 Master Privilege Register (MPR)
        • Figure 8-8. Master Privilege Register (MPR)
        • Table 8-9. MPR[n] Field Descriptions
      • 8.6.3.2 Peripheral Access Control Registers (PACR 0-PACR8)
        • Figure 8-9. Peripheral Access Control Register (PACRn)
        • Table 8-10. PACR Field Descriptions
        • Table 8-11. PACR ACCESSCTRL Bit Encodings
        • Table 8-12. Peripheral Access Control Registers (PACRs) (continued)
      • 8.6.3.3 Grouped Peripheral Access Control Registers (GPACR0 and GPACR1)
        • Figure 8-10. GPACR Register
        • Table 8-13. Grouped PeripheralAccess Control Register (GPACR) Field Descriptions
        • Table 8-14. GPACR ACCESS_CTRL Bit Encodings
        • Table 8-15. GPACR Address Space
• Chapter 9 Clock Module
  • 9.1 Features
  • 9.2 Modes of Operation
    • 9.2.1 Normal PLL Mode
    • 9.2.2 1:1 PLL Mode
    • 9.2.3 External Clock Mode
  • 9.3 Low-power Mode Operation
    • Table 9-1. Clock Module Operation in Low-power Modes
  • 9.4 Block Diagram
    • Figure 9-1. Clock Module Block Diagram
    • Figure 9-2. PLL Block Diagram
  • 9.5 Signal Descriptions
    • Table 9-2. Signal Properties
    • 9.5.1 EXTAL
    • 9.5.2 XTAL
    • 9.5.3 CLKOUT
    • 9.5.4 CLKMOD[1:0]
    • 9.5.5 RSTOUT
  • 9.6 Memory Map and Registers
    • 9.6.1 Module Memory Map
      • Table 9-3. Clock Module Memory Map
    • 9.6.2 Register Descriptions
      • 9.6.2.1 Synthesizer Control Register (SYNCR)
        • Figure 9-3. Synthesizer Control Register (SYNCR)
        • Table 9-4. SYNCR Field Descriptions (continued)
      • 9.6.2.2 Synthesizer Status Register (SYNSR)
        • Figure 9-4. Synthesizer Status Register (SYNSR)
        • Table 9-5. SYNSR Field Descriptions (continued)
        • Table 9-6. System Clock Modes
  • 9.7 Functional Description
    • 9.7.1 System Clock Modes
      • Table 9-7. Clock Out and Clock In Relationships
    • 9.7.2 Clock Operation During Reset
    • 9.7.3 System Clock Generation
    • 9.7.4 PLL Operation
      • Figure 9-5. Crystal Oscillator Example
      • 9.7.4.1 Phase and Frequency Detector (PFD)
      • 9.7.4.2 Charge Pump/Loop Filter
        • Table 9-8. Charge Pump Current and MFD in Normal Mode Operation
      • 9.7.4.3 Voltage Control Output (VCO)
      • 9.7.4.4 Multiplication Factor Divider (MFD)
      • 9.7.4.5 PLL Lock Detection
        • Figure 9-6. Lock Detect Sequence
      • 9.7.4.6 PLL Loss of Lock Conditions
      • 9.7.4.7 PLL Loss of Lock Reset
      • 9.7.4.8 Loss of Clock Detection
      • 9.7.4.9 Loss of Clock Reset
      • 9.7.4.10 Alternate Clock Selection
        • Table 9-9. Loss of Clock Summary
      • 9.7.4.11 Loss of Clock in Stop Mode
        • Table 9-10. Stop Mode Operation (Sheet 5 of 5)
• Chapter 10 Interrupt Controller Modules
  • 10.1 68K/ColdFire Interrupt Architecture Overview
    • 10.1.1 Interrupt Controller Theory of Operation
      • Table 10-1. Interrupt Priority Within a Level
      • 10.1.1.1 Interrupt Recognition
      • 10.1.1.2 Interrupt Prioritization
      • 10.1.1.3 Interrupt Vector Determination
  • 10.2 Memory Map
    • Table 10-2. Interrupt Controller Base Addresses
    • Table 10-3. Interrupt Controller Memory Map (continued)
  • 10.3 Register Descriptions
    • 10.3.1 Interrupt Pending Registers (IPRHn, IPRLn)
      • Figure 10-1. Interrupt Pending Register High (IPRHn)
      • Table 10-4. IPRHn Field Descriptions
      • Figure 10-2. Interrupt Pending Register Low (IPRLn)
      • Table 10-5. IPRLn Field Descriptions
    • 10.3.2 Interrupt Mask Register (IMRHn, IMRLn)
      • Figure 10-3. Interrupt Mask Register High (IMRHn)
      • Table 10-6. IMRHn Field Descriptions
      • Figure 10-4. Interrupt Mask Register Low (IMRLn)
      • Table 10-7. IMRLn Field Descriptions
    • 10.3.3 Interrupt Force Registers (INTFRCHn, INTFRCLn)
      • Figure 10-5. Interrupt Force Register High (INTFRCHn)
      • Table 10-8. INTFRCHn Field Descriptions
      • Figure 10-6. Interrupt Force Register Low (INTFRCLn)
      • Table 10-9. INTFRCLn Field Descriptions
    • 10.3.4 Interrupt Request Level Register (IRLRn)
      • Figure 10-7. Interrupt RequestLevel Register (IRLRn)
      • Table 10-10. IRQn Field Descriptions
    • 10.3.5 Interrupt Acknowledge Level and Priority Register (IACKLPRn)
      • Figure 10-8. IACK Level and Priority Register (IACKLPRn)
      • Table 10-11. IACKLPRn Field Descriptions
    • 10.3.6 Interrupt Control Register (ICRnx, (x = 1, 2,..., 63))
      • Figure 10-9. Interrupt Control Register (ICRnx)
      • Table 10-12. ICRnx Field Descriptions
      • 10.3.6.1 Interrupt Sources
        • Table 10-13. Interrupt Source Assignment for INTC0 (continued)
        • Table 10-14. Interrupt Source Assignment for INTC1
    • 10.3.7 Software and Level n IACK Registers (SWIACKR, L1IACK-L7IACK)
      • Figure 10-10. Software and Level n IACK Registers (SWIACKR, L1IACK-L7IACK)
      • Table 10-15. SWIACK and L1IACK-L7IACK Field Descriptions
  • 10.4 Prioritization Between Interrupt Controllers
  • 10.5 Low-Power Wakeup Operation
• Chapter 11 Edge Port Module (EPORT)
  • 11.1 Introduction
    • Figure 11-1. EPORT Block Diagram
  • 11.2 Low-Power Mode Operation
    • Table 11-1. Edge Port Module Operation in Low-power Modes
  • 11.3 Interrupt/General-Purpose I/O Pin Descriptions
  • 11.4 Memory Map and Registers
    • 11.4.1 Memory Map
      • Table 11-2. Edge Port Module Memory Map
    • 11.4.2 Registers
      • 11.4.2.1 EPORT Pin Assignment Register (EPPAR)
        • Figure 11-2. EPORT Pin Assignment Register (EPPAR)
        • Table 11-3. EPPAR Field Descriptions
      • 11.4.2.2 EPORT Data Direction Register (EPDDR)
        • Figure 11-3. EPORT Data Direction Register (EPDDR)
        • Table 11-4. EPDD Field Descriptions
      • 11.4.2.3 Edge Port Interrupt Enable Register (EPIER)
        • Figure 11-4. EPORT Port Interrupt Enable Register (EPIER)
        • Table 11-5. EPIER Field Descriptions
      • 11.4.2.4 Edge Port Data Register (EPDR)
        • Figure 11-5. EPORT Port Data Register (EPDR)
        • Table 11-6. EPDR Field Descriptions
      • 11.4.2.5 Edge Port Pin Data Register (EPPDR)
        • Figure 11-6. EPORT Port Pin Data Register (EPPDR)
        • Table 11-7. EPPDR Field Descriptions
      • 11.4.2.6 Edge Port Flag Register (EPFR)
        • Figure 11-7. EPORT Port Flag Register (EPFR)
        • Table 11-8. EPFR Field Descriptions
• Chapter 12 Chip Select Module
  • 12.1 Overview
  • 12.2 Chip Select Module Signals
    • Table 12-1. Chip Select Module Signals
    • Table 12-2. Byte Enables/Byte Write Enable Signal Settings
  • 12.3 Chip Select Operation
    • 12.3.1 General Chip Select Operation
      • Table 12-3. Accesses by Matches in CSARs and DACRs
      • 12.3.1.1 8-, 16-, and 32-Bit Port Sizing
        • Figure 12-1. Connections for External Memory Port Sizes
      • 12.3.1.2 External Boot Chip Select Operation
        • Table 12-4. D[19:18] External Boot Chip Select Configuration
  • 12.4 Chip Select Registers
    • Table 12-5. Chip Select Registers (continued)
    • 12.4.1 Chip Select Module Registers
      • 12.4.1.1 Chip Select Address Registers (CSAR0-CSAR6)
        • Figure 12-2. Chip Select Address Registers (CSARn)
        • Table 12-6. CSARn Field Description
      • 12.4.1.2 Chip Select Mask Registers (CSMR0-CSMR6)
        • Figure 12-3. Chip Select Mask Registers (CSMRn)
        • Table 12-7. CSMRn Field Descriptions (continued)
      • 12.4.1.3 Chip Select Control Registers (CSCR0-CSCR6)
        • Figure 12-4. Chip Select Control Registers (CSCRn)
        • Table 12-8. CSCRn Field Descriptions
• Chapter 13 External Interface Module (EIM)
  • 13.1 Features
  • 13.2 Bus and Control Signals
    • Table 13-1. ColdFire Bus Signal Summary (Continued)
  • 13.3 Bus Characteristics
    • Figure 13-1. Signal Relationship to CLKOUT for Non-DRAM Access
  • 13.4 Data Transfer Operation
    • Figure 13-2. Connections for External Memory Port Sizes
    • Figure 13-3. Chip-Select Module Output Timing Diagram
    • 13.4.1 Bus Cycle Execution
      • Table 13-2. Accesses by Matches in CSCRs and DACRs
    • 13.4.2 Data Transfer Cycle States
      • Figure 13-4. Data Transfer State Transition Diagram
      • Table 13-3. Bus Cycle States (Continued)
    • 13.4.3 Read Cycle
      • Figure 13-5. Read Cycle Flowchart
      • Figure 13-6. Basic Read Bus Cycle
    • 13.4.4 Write Cycle
      • Figure 13-7. Write Cycle Flowchart
      • Figure 13-8. Basic Write Bus Cycle
    • 13.4.5 Fast Termination Cycles
      • Figure 13-9. Read Cycle with Fast Termination
      • Figure 13-10. Write Cycle with Fast Termination
    • 13.4.6 Back-to-Back Bus Cycles
      • Figure 13-11. Back-to-Back Bus Cycles
    • 13.4.7 Burst Cycles
      • 13.4.7.1 Line Transfers
        • Table 13-4. Allowable Line Access Patterns
      • 13.4.7.2 Line Read Bus Cycles
        • Figure 13-12. Line Read Burst (2-1-1-1), External Termination
        • Figure 13-13. Line Read Burst (2-1-1-1), Internal Termination
        • Figure 13-14. Line Read Burst (3-2-2-2), External Termination
        • Figure 13-15. Line Read Burst-Inhibited, Fast Termination, External Termination
      • 13.4.7.3 Line Write Bus Cycles
        • Figure 13-16. Line Write Burst (2-1-1-1), Internal/External Termination
        • Figure 13-17. Line Write Burst (3-2-2-2) with One Wait State
        • Figure 13-18. Line Write Burst-Inhibited
  • 13.5 Misaligned Operands
    • Figure 13-19. Example of a Misaligned Longword Transfer (32-Bit Port)
    • Figure 13-20. Example of a Misaligned Word Transfer (32-Bit Port)
• Chapter 14 Signal Descriptions
  • 14.1 Overview
    • Figure 14-1. MCF5282 Block Diagram with Signal Interfaces
    • Table 14-1. MCF5282 Signal Description (Continued)
    • Table 14-2. MCF5282 Alphabetical Signal Index (Continued)
    • Table 14-3. MCF5282 Signals and Pin Numbers Sorted by Function (Continued)
    • 14.1.1 Single-Chip Mode
      • Table 14-4. Pin Reset States at Reset (Single-Chip Mode)
    • 14.1.2 External Boot Mode
      • Table 14-5. Default Signal Functions After System Reset (External Boot Mode) (Continued)
  • 14.2 MCF5282 External Signals
    • 14.2.1 External Interface Module (EIM) Signals
      • 14.2.1.1 Address Bus (A[23:0])
      • 14.2.1.2 Data Bus (D[31:0])
      • 14.2.1.3 Byte Strobes (BS[3:0])
      • 14.2.1.4 Output Enable (OE)
      • 14.2.1.5 Transfer Acknowledge (TA)
      • 14.2.1.6 Transfer Error Acknowledge (TEA)
      • 14.2.1.7 Read/Write (R/W)
      • 14.2.1.8 Transfer Size(SIZ[1:0])
        • Table 14-6. Transfer Size Encoding
      • 14.2.1.9 Transfer Start (TS)
      • 14.2.1.10 Transfer In Progress (TIP)
      • 14.2.1.11 Chip Selects (CS[6:0])
    • 14.2.2 SDRAM Controller Signals
      • 14.2.2.1 SDRAM Row Address Strobe (SRAS)
      • 14.2.2.2 SDRAM Column Address Strobe (SCAS)
      • 14.2.2.3 SDRAM Write Enable (DRAMW)
      • 14.2.2.4 SDRAM Bank Selects (SDRAM_CS[1:0])
      • 14.2.2.5 SDRAM Clock Enable (SCKE)
    • 14.2.3 Clock and Reset Signals
      • 14.2.3.1 Reset In (RSTI)
      • 14.2.3.2 Reset Out (RSTO)
      • 14.2.3.3 EXTAL
      • 14.2.3.4 XTAL
      • 14.2.3.5 Clock Output (CLKOUT)
    • 14.2.4 Chip Configuration Signals
      • 14.2.4.1 RCON
      • 14.2.4.2 CLKMOD[1:0]
    • 14.2.5 External Interrupt Signals
      • 14.2.5.1 External Interrupts (IRQ[7:1])
    • 14.2.6 Ethernet Module Signals
      • 14.2.6.1 Management Data (EMDIO)
      • 14.2.6.2 Management Data Clock (EMDC)
      • 14.2.6.3 Transmit Clock (ETXCLK)
      • 14.2.6.4 Transmit Enable (ETXEN)
      • 14.2.6.5 Transmit Data 0 (ETXD0)
      • 14.2.6.6 Collision (ECOL)
      • 14.2.6.7 Receive Clock (ERXCLK)
      • 14.2.6.8 Receive Data Valid (ERXDV)
      • 14.2.6.9 Receive Data 0 (ERXD0)
      • 14.2.6.10 Carrier Receive Sense (ECRS)
      • 14.2.6.11 Transmit Data 1-3 (ETXD[3:1])
      • 14.2.6.12 Transmit Error (ETXER)
      • 14.2.6.13 Receive Data 1-3 (ERXD[3:1])
      • 14.2.6.14 Receive Error (ERXER)
    • 14.2.7 Queued Serial Peripheral Interface (QSPI) Signals
      • 14.2.7.1 QSPI Synchronous Serial Output (QSPI_DOUT)
      • 14.2.7.2 QSPI Synchronous Serial Data Input (QSPI_DIN)
      • 14.2.7.3 QSPI Serial Clock (QSPI_CLK)
      • 14.2.7.4 QSPI Chip Selects (QSPI_CS[3:0])
    • 14.2.8 FlexCAN Signals
      • 14.2.8.1 FlexCAN Transmit (CANTX)
      • 14.2.8.2 FlexCAN Receive (CANRX)
    • 14.2.9 I2C Signals
      • 14.2.9.1 Serial Clock (SCL)
      • 14.2.9.2 Serial Data (SDA)
    • 14.2.10 UART Module Signals
      • 14.2.10.1 Transmit Serial Data Output (UTXD[2:0])
      • 14.2.10.2 Receive Serial Data Input (URXD[2:0])
      • 14.2.10.3 Clear-to-Send (UCTS[1:0])
      • 14.2.10.4 Request-to-Send (URTS[1:0])
    • 14.2.11 General Purpose Timer Signals
      • 14.2.11.1 GPTA[3:0]
      • 14.2.11.2 GPTB[3:0]
      • 14.2.11.3 External Clock Input (SYNCA/SYNCB)
    • 14.2.12 DMA Timer Signals
      • 14.2.12.1 DMA Timer 0 Input (DTIN0)
      • 14.2.12.2 DMA Timer 0 Output (DTOUT0)
      • 14.2.12.3 DMA Timer 1 Input (DTIN1)
      • 14.2.12.4 DMA Timer 1 Output (DTOUT1)
      • 14.2.12.5 DMA Timer 2 Input (DTIN2)
      • 14.2.12.6 DMA Timer 2 Output (DTOUT2)
      • 14.2.12.7 DMA Timer 3 Input (DTIN3)
      • 14.2.12.8 DMA Timer 3 Output (DTOUT3)
    • 14.2.13 Analog-to-Digital Converter Signals
      • 14.2.13.1 QADC Analog Input (AN0/ANW)
      • 14.2.13.2 QADC Analog Input (AN1/ANX)
      • 14.2.13.3 QADC Analog Input (AN2/ANY)
      • 14.2.13.4 QADC Analog Input (AN3/ANZ)
      • 14.2.13.5 QADC Analog Input (AN52/MA0)
      • 14.2.13.6 QADC Analog Input (AN53/MA1)
      • 14.2.13.7 QADC Analog Input (AN55/TRIG1)
      • 14.2.13.8 QADC Analog Input (AN56/TRIG2)
    • 14.2.14 Debug Support Signals
      • 14.2.14.1 JTAG_EN
      • 14.2.14.2 Development Serial Clock/Test Reset (DSCLK/TRST)
      • 14.2.14.3 Breakpoint/Test Mode Select (BKPT/TMS)
      • 14.2.14.4 Development Serial Input/Test Data (DSI/TDI)
      • 14.2.14.5 Development Serial Output/Test Data (DSO/TDO)
      • 14.2.14.6 Test Clock (TCLK)
      • 14.2.14.7 Debug Data (DDATA[3:0])
      • 14.2.14.8 Processor Status Outputs (PST[3:0])
        • Table 14-7. Processor Status Encoding
    • 14.2.15 Test Signals
      • 14.2.15.1 Test (TEST)
    • 14.2.16 Power and Reference Signals
      • 14.2.16.1 QADC Analog Reference (VRH, VRL)
      • 14.2.16.2 QADC Analog Supply (VDDA, VSSA)
      • 14.2.16.3 PLL Analog Supply (VDDPLL, VSSPLL)
      • 14.2.16.4 QADC Positive Supply (VDDH)
      • 14.2.16.5 Power for Flash Erase/Program (VPP)
      • 14.2.16.6 Power and Ground for Flash Array (VDDF, VSSF)
      • 14.2.16.7 Standby Power (VSTBY)
      • 14.2.16.8 Positive Supply (VDD)
      • 14.2.16.9 Ground (VSS)
• Chapter 15 Synchronous DRAM Controller Module
  • 15.1 Overview
    • 15.1.1 Definitions
    • 15.1.2 Block Diagram and Major Components
      • Figure 15-1. Synchronous DRAM Controller Block Diagram
  • 15.2 SDRAM Controller Operation
    • Table 15-1. SDRAM Commands
    • 15.2.1 DRAM Controller Signals
      • Table 15-2. Synchronous DRAM Signal Connections
    • 15.2.2 Memory Map for SDRAMC Registers
      • Table 15-3. DRAM Controller Registers
      • 15.2.2.1 DRAM Control Register (DCR)
        • Figure 15-2. DRAM Control Register (DCR)
        • Table 15-4. DCR Field Descriptions
      • 15.2.2.2 DRAM Address and Control Registers (DACR0/DACR1)
        • Figure 15-3. DRAM Address and Control Register (DACRn)
        • Table 15-5. DACRn Field Descriptions (continued)
      • 15.2.2.3 DRAM Controller Mask Registers (DMR0/DMR1)
        • Figure 15-4. DRAM Controller Mask Registers (DMRn)
        • Table 15-6. DMRn Field Descriptions
    • 15.2.3 General Synchronous Operation Guidelines
      • 15.2.3.1 Address Multiplexing
        • Table 15-7. Generic Address Multiplexing Scheme
        • Table 15-8. MCF5282 to SDRAM Interface (8-Bit Port, 9-Column Address Lines)
        • Table 15-9. MCF5282 to SDRAM Interface (8-Bit Port,10-Column Address Lines)
        • Table 15-10. MCF5282 to SDRAM Interface (8-Bit Port,11-Column Address Lines)
        • Table 15-11. MCF5282 to SDRAM Interface (8-Bit Port,12-Column Address Lines)
        • Table 15-12. MCF5282 to SDRAM Interface (8-Bit Port,13-Column Address Lines)
        • Table 15-13. MCF5282 to SDRAM Interface (16-Bit Port, 8-Column Address Lines)
        • Table 15-14. MCF5282 to SDRAM Interface (16-Bit Port, 9-Column Address Lines)
        • Table 15-15. MCF5282 to SDRAM Interface (16-Bit Port, 10-Column Address Lines)
        • Table 15-16. MCF5282 to SDRAM Interface (16-Bit Port, 11-Column Address Lines)
        • Table 15-17. MCF5282 to SDRAM Interface (16-Bit Port, 12-Column Address Lines)
        • Table 15-18. MCF5282 to SDRAM Interface (16-Bit Port, 13-Column-Address Lines)
        • Table 15-19. MCF5282 to SDRAM Interface (32-Bit Port, 8-Column Address Lines)
        • Table 15-20. MCF5282 to SDRAM Interface (32-Bit Port, 9-Column Address Lines)
        • Table 15-21. MCF5282 to SDRAM Interface (32-Bit Port, 10-Column Address Lines)
        • Table 15-22. MCF5282 to SDRAM Interface (32-Bit Port, 11-Column Address Lines)
        • Table 15-23. MCF5282 to SDRAM Interface (32-Bit Port, 12-Column Address Lines)
      • 15.2.3.2 SDRAM Byte Strobe Connections
        • Figure 15-5. Connections for External Memory Port Sizes
      • 15.2.3.3 Interfacing Example
        • Table 15-24. SDRAM Hardware Connections
      • 15.2.3.4 Burst Page Mode
        • Figure 15-6. Burst Read SDRAM Access
        • Figure 15-7. Burst Write SDRAM Access
      • 15.2.3.5 Auto-Refresh Operation
        • Figure 15-8. Auto-Refresh Operation
      • 15.2.3.6 Self-Refresh Operation
        • Figure 15-9. Self-Refresh Operation
    • 15.2.4 Initialization Sequence
      • 15.2.4.1 Mode Register Settings
        • Figure 15-10. Mode Register Set (mrs) Command
  • 15.3 SDRAM Example
    • Table 15-25. SDRAM Example Specifications
    • 15.3.1 SDRAM Interface Configuration
      • Table 15-26. SDRAM Hardware Connections
    • 15.3.2 DCR Initialization
      • Figure 15-11. Initialization Values for DCR
      • Table 15-27. DCR Initialization Values
    • 15.3.3 DACR Initialization
      • Figure 15-12. SDRAM Configuration
      • Figure 15-13. DACR Register Configuration
      • Table 15-28. DACR Initialization Values (continued)
    • 15.3.4 DMR Initialization
      • Figure 15-14. DMR0 Register
      • Table 15-29. DMR0 Initialization Values (continued)
    • 15.3.5 Mode Register Initialization
      • Table 15-30. Mode Register Initialization
      • Table 15-31. Mode Register Mapping to MCF5282 A[31:0]
    • 15.3.6 Initialization Code
• Chapter 16 DMA Controller Module
  • 16.1 Overview
    • Figure 16-1. DMA Signal Diagram
    • 16.1.1 DMA Module Features
  • 16.2 DMA Request Control (DMAREQC)
    • Figure 16-2. DMA Request Control Register (DMAREQC)
    • Table 16-1. DMAREQC Field Description
  • 16.3 DMA Transfer Overview
    • Figure 16-3. Dual-Address Transfer
  • 16.4 DMA Controller Module Programming Model
    • Table 16-2. Memory Map for DMA Controller Module Registers
    • 16.4.1 Source Address Registers (SAR0-SAR3)
      • Figure 16-4. Source Address Registers (SARn)
    • 16.4.2 Destination Address Registers (DAR0-DAR3)
      • Figure 16-5. Destination Address Registers (DARn)
    • 16.4.3 Byte Count Registers (BCR0-BCR3)
      • Figure 16-6. Byte Count Registers (BCRn)-BCR24BIT = 1
      • Figure 16-7. Byte Count Registers (BCRn)-BCR24BIT = 0
    • 16.4.4 DMA Control Registers (DCR0-DCR3)
      • Figure 16-8. DMA Control Registers (DCRn)
      • Table 16-3. DCRn Field Descriptions (continued)
    • 16.4.5 DMA Status Registers (DSR0-DSR3)
      • Figure 16-9. DMA Status Registers (DSRn)
      • Table 16-4. DSRn Field Descriptions (continued)
  • 16.5 DMA Controller Module Functional Description
    • 16.5.1 Transfer Requests (Cycle-Steal and Continuous Modes)
    • 16.5.2 Data Transfer Modes
      • 16.5.2.1 Dual-Address Transfers
    • 16.5.3 Channel Initialization and Startup
      • 16.5.3.1 Channel Prioritization
      • 16.5.3.2 Programming the DMA Controller Module
    • 16.5.4 Data Transfer
      • 16.5.4.1 Auto-Alignment
      • 16.5.4.2 Bandwidth Control
    • 16.5.5 Termination
• Chapter 17 Fast Ethernet Controller (FEC)
  • 17.1 Overview
    • 17.1.1 Features
  • 17.2 Modes of Operation
    • 17.2.1 Full and Half Duplex Operation
    • 17.2.2 Interface Options
      • 17.2.2.1 10 Mbps and 100 Mbps MII Interface
      • 17.2.2.2 10 Mpbs 7-Wire Interface Operation
    • 17.2.3 Address Recognition Options
    • 17.2.4 Internal Loopback
  • 17.3 FEC Top-Level Functional Diagram
    • Figure 17-1. FEC Block Diagram
  • 17.4 Functional Description
    • 17.4.1 Initialization Sequence
      • 17.4.1.1 Hardware Controlled Initialization
        • Table 17-1. ECR[ETHER_EN] De-Assertion Effect on FEC
    • 17.4.2 User Initialization (Prior to Asserting ECR[ETHER_EN])
      • Table 17-2. User Initialization (Before ECR[ETHER_EN]) (continued)
      • Table 17-3. FEC User Initialization (Before ECR[ETHER_EN])
    • 17.4.3 Microcontroller Initialization
      • Table 17-4. Microcontroller Initialization
    • 17.4.4 User Initialization (After Asserting ECR[ETHER_EN])
    • 17.4.5 Network Interface Options
      • Table 17-5. MII Mode
      • Table 17-6. 7-Wire Mode Configuration
    • 17.4.6 FEC Frame Transmission
    • 17.4.7 FEC Frame Reception
    • 17.4.8 Ethernet Address Recognition
      • Figure 17-2. Ethernet Address Recognition-Receive Block Decisions
      • Figure 17-3. Ethernet Address Recognitionq-Microcode Decisions
    • 17.4.9 Hash Algorithm
      • Table 17-7. Destination Address to 6-Bit Hash (continued)
    • 17.4.10 Full Duplex Flow Control
      • Table 17-8. PAUSE Frame Field Specification
    • 17.4.11 Inter-Packet Gap (IPG) Time
    • 17.4.12 Collision Handling
    • 17.4.13 Internal and External Loopback
    • 17.4.14 Ethernet Error-Handling Procedure
      • 17.4.14.1 Transmission Errors
      • 17.4.14.2 Reception Errors
  • 17.5 Programming Model
    • 17.5.1 Top Level Module Memory Map
      • Table 17-9. Module Memory Map
    • 17.5.2 Detailed Memory Map (Control/Status Registers)
      • Table 17-10. FEC Register Memory Map (continued)
    • 17.5.3 MIB Block Counters Memory Map
      • Table 17-11. MIB Counters Memory Map (continued)
    • 17.5.4 Registers
      • 17.5.4.1 Ethernet Interrupt Event Register (EIR)
        • Figure 17-4. Ethernet Interrupt Event Register (EIR)
        • Table 17-12. EIR Field Descriptions (continued)
      • 17.5.4.2 Interrupt Mask Register (EIMR)
        • Figure 17-5. Interrupt Mask Register (EIMR)
        • Table 17-13. EIMR Field Descriptions
      • 17.5.4.3 Receive Descriptor Active Register (RDAR)
        • Figure 17-6. Receive Descriptor Active Register (RDAR)
        • Table 17-14. RDAR Field Descriptions
      • 17.5.4.4 Transmit Descriptor Active Register (TDAR)
        • Figure 17-7. Transmit Descriptor Active Register (TDAR)
        • Table 17-15. TDAR Field Descriptions
      • 17.5.4.5 Ethernet Control Register (ECR)
        • Figure 17-8. Ethernet Control Register (ECR)
        • Table 17-16. ECR Field Descriptions
      • 17.5.4.6 MII Management Frame Register (MMFR)
        • Figure 17-9. MII Management Frame Register (MMFR)
        • Table 17-17. MMFR Field Descriptions
      • 17.5.4.7 MII Speed Control Register (MSCR)
        • Figure 17-10. MII Speed Control Register (MSCR)
        • Table 17-18. MSCR Field Descriptions
        • Table 17-19. Programming Examples for MSCR
      • 17.5.4.8 MIB Control Register (MIBC)
        • Figure 17-11. MIB Control Register (MIBC)
        • Table 17-20. MIBC Field Descriptions
      • 17.5.4.9 Receive Control Register (RCR)
        • Figure 17-12. Receive Control Register (RCR)
        • Table 17-21. RCR Field Descriptions (continued)
      • 17.5.4.10 Transmit Control Register (TCR)
        • Figure 17-13. Transmit Control Register (TCR)
        • Table 17-22. TCR Field Descriptions
      • 17.5.4.11 Physical Address Low Register (PALR)
        • Figure 17-14. Physical Address Low Register (PALR)
        • Table 17-23. PALR Field Descriptions
      • 17.5.4.12 Physical Address High Register (PAUR)
        • Figure 17-15. Physical Address High Register (PAUR)
        • Table 17-24. PAUR Field Descriptions
      • 17.5.4.13 Opcode/Pause Duration Register (OPD)
        • Figure 17-16. Opcode/Pause Duration Register (OPD)
        • Table 17-25. OPD Field Descriptions
      • 17.5.4.14 Descriptor Individual Upper Address Register (IAUR)
        • Figure 17-17. Descriptor Individual Upper Address Register (IAUR)
        • Table 17-26. IAUR Field Descriptions
      • 17.5.4.15 Descriptor Individual Lower Address (IALR)
        • Figure 17-18. Descriptor Individual Lower Address Register (IALR)
        • Table 17-27. IALR Field Descriptions
      • 17.5.4.16 Descriptor Group Upper Address (GAUR)
        • Figure 17-19. Descriptor Group Upper Address Register (GAUR)
        • Table 17-28. GAUR Field Descriptions
      • 17.5.4.17 Descriptor Group Lower Address (GALR)
        • Figure 17-20. Descriptor Group Lower Address Register (GALR)
        • Table 17-29. GALR Field Descriptions
      • 17.5.4.18 FIFO Transmit FIFO Watermark Register (TFWR)
        • Figure 17-21. FIFO Transmit FIFO Watermark Register (TFWR)
        • Table 17-30. TFWR Field Descriptions
      • 17.5.4.19 FIFO Receive Bound Register (FRBR)
        • Figure 17-22. FIFO Receive Bound Register (FRBR)
        • Table 17-31. FRBR Field Descriptions
      • 17.5.4.20 FIFO Receive Start Register (FRSR)
        • Figure 17-23. FIFO Receive Start Register (FRSR)
        • Table 17-32. FRSR Field Descriptions
      • 17.5.4.21 Receive Descriptor Ring Start (ERDSR)
        • Figure 17-24. Receive Descriptor Ring Start Register (ERDSR)
        • Table 17-33. ERDSR Field Descriptions
      • 17.5.4.22 Transmit Buffer Descriptor Ring Start (ETSDR)
        • Figure 17-25. Transmit Buffer Descriptor Ring Start Register (ETDSR)
        • Table 17-34. ETDSR Field Descriptions
      • 17.5.4.23 Receive Buffer Size Register (EMRBR)
        • Figure 17-26. Receive Buffer Size Register (EMRBR)
        • Table 17-35. EMRBR Field Descriptions
  • 17.6 Buffer Descriptors
    • 17.6.1 Driver/DMA Operation with Buffer Descriptors
      • 17.6.1.1 Driver/DMA Operation with Transmit BDs
      • 17.6.1.2 Driver/DMA Operation with Receive BDs
    • 17.6.2 Ethernet Receive Buffer Descriptor (RxBD)
      • Figure 17-27. Receive Buffer Descriptor (RxBD)
      • Table 17-36. Receive Buffer Descriptor Field Definitions (continued)
    • 17.6.3 Ethernet Transmit Buffer Descriptor (TxBD)
      • Figure 17-28. Transmit Buffer Descriptor (TxBD)
      • Table 17-37. Transmit Buffer Descriptor Field Definitions (continued)
• Chapter 18 Watchdog Timer Module
  • 18.1 Introduction
  • 18.2 Low-Power Mode Operation
    • Table 18-1. Watchdog Module Operation in Low-power Modes
  • 18.3 Block Diagram
    • Figure 18-1. Watchdog Timer Block Diagram
  • 18.4 Signals
  • 18.5 Memory Map and Registers
    • 18.5.1 Memory Map
      • Table 18-2. Watchdog Timer Module Memory Map
    • 18.5.2 Registers
      • 18.5.2.1 Watchdog Control Register (WCR)
        • Figure 18-2. Watchdog Control Register (WCR)
        • Table 18-3. WCR Field Descriptions
      • 18.5.2.2 Watchdog Modulus Register (WMR)
        • Figure 18-3. Watchdog Modulus Register (WMR)
        • Table 18-4. WMR Field Descriptions
      • 18.5.2.3 Watchdog Count Register (WCNTR)
        • Figure 18-4. Watchdog Count Register (WCNTR)
        • Table 18-5. WCNTR Field Descriptions
      • 18.5.2.4 Watchdog Service Register (WSR)
        • Figure 18-5. Watchdog Service Register (WSR)
• Chapter 19 Programmable Interrupt Timer Modules (PIT0-PIT3)
  • 19.1 Overview
  • 19.2 Block Diagram
    • Figure 19-1. PIT Block Diagram
  • 19.3 Low-Power Mode Operation
    • Table 19-1. PIT Module Operation in Low-power Modes
  • 19.4 Signals
  • 19.5 Memory Map and Registers
    • 19.5.1 Memory Map
      • Table 19-2. Programmable Interrupt Timer Modules Memory Map
    • 19.5.2 Registers
      • 19.5.2.1 PIT Control and Status Register (PCSR)
        • Figure 19-2. PIT Control and Status Register (PCSR)
        • Table 19-3. PCSR Field Descriptions (continued)
      • 19.5.2.2 PIT Modulus Register (PMR)
        • Figure 19-3. PIT Modulus Register (PMR)
      • 19.5.2.3 PIT Count Register (PCNTR)
        • Figure 19-4. PIT Count Register (PCNTR)
  • 19.6 Functional Description
    • 19.6.1 Set-and-Forget Timer Operation
      • Figure 19-5. Counter Reloading from the Modulus Latch
    • 19.6.2 Free-Running Timer Operation
      • Figure 19-6. Counter in Free-Running Mode
    • 19.6.3 Timeout Specifications
  • 19.7 Interrupt Operation
    • Table 19-4. PIT Interrupt Requests
• Chapter 20 General Purpose Timer Modules (GPTA and GPTB)
  • 20.1 Features
  • 20.2 Block Diagram
    • Figure 20-1. GPT Block Diagram
  • 20.3 Low-Power Mode Operation
    • Table 20-1. Watchdog Module Operation in Low-power Modes
  • 20.4 Signal Description
    • Table 20-2. Signal Properties
    • 20.4.1 GPTn[2:0]
    • 20.4.2 GPTn3
    • 20.4.3 SYNCn
  • 20.5 Memory Map and Registers
    • Table 20-3. GPT Modules Memory Map (continued)
    • 20.5.1 GPT Input Capture/Output Compare Select Register (GPTIOS)
      • Figure 20-2. GPT Input Capture/Output Compare Select Register (GPTIOS)
      • Table 20-4. GPTIOS Field Descriptions
    • 20.5.2 GPT Compare Force Register (GPCFORC)
      • Figure 20-3. GPT Input Compare Force Register (GPCFORC)
      • Table 20-5. GPTCFORC Field Descriptions
    • 20.5.3 GPT Output Compare 3 Mask Register (GPTOC3M)
      • Figure 20-4. GPT Output Compare 3 Mask Register (GPTOC3M)
      • Table 20-6. GPTOC3M Field Descriptions
    • 20.5.4 GPT Output Compare 3 Data Register (GPTOC3D)
      • Figure 20-5. GPT Output Compare 3 Data Register (GPTOC3D)
      • Table 20-7. GPTOC3D Field Descriptions
    • 20.5.5 GPT Counter Register (GPTCNT)
      • Figure 20-6. GPT Counter Register (GPTCNT)
      • Table 20-8. GPTCNT Field Descriptions
    • 20.5.6 GPT System Control Register 1 (GPTSCR1)
      • Figure 20-7. GPT System Control Register 1 (GPTSCR1)
      • Table 20-9. GPTSCR1 Field Descriptions
      • Figure 20-8. Fast Clear Flag Logic
    • 20.5.7 GPT Toggle-On-Overflow Register (GPTTOV)
      • Figure 20-9. GPT Toggle-On-Overflow Register (GPTTOV)
      • Table 20-10. GPTTOV Field Description
    • 20.5.8 GPT Control Register 1 (GPTCTL1)
      • Figure 20-10. GPT Control Register 1 (GPTCTL1)
      • Table 20-11. GPTCL1 Field Descriptions
    • 20.5.9 GPT Control Register 2 (GPTCTL2)
      • Figure 20-11. GPT Control Register 2 (GPTCTL2)
      • Table 20-12. GPTLCTL2 Field Descriptions
    • 20.5.10 GPT Interrupt Enable Register (GPTIE)
      • Figure 20-12. GPT Interrupt Enable Register (GPTIE)
      • Table 20-13. GPTIE Field Descriptions
    • 20.5.11 GPT System Control Register 2 (GPTSCR2)
      • Figure 20-13. GPT System Control Register 2 (GPTSCR2)
      • Table 20-14. GPTSCR2 Field Descriptions
    • 20.5.12 GPT Flag Register 1 (GPTFLG1)
      • Figure 20-14. GPT Flag Register 1 (GPTFLG1)
      • Table 20-15. GPTFLG1 Field Descriptions
    • 20.5.13 GPT Flag Register 2 (GPTFLG2)
      • Figure 20-15. GPT Flag Register 2 (GPTFLG2)
      • Table 20-16. GPTFLG2 Field Descriptions
    • 20.5.14 GPT Channel Registers (GPTCn)
      • Figure 20-16. GPT Channel[0:3] Register (GPTCn)
      • Table 20-17. GPTCn Field Descriptions
    • 20.5.15 Pulse Accumulator Control Register (GPTPACTL)
      • Figure 20-17. Pulse Accumulator Control Register (GPTPACTL)
      • Table 20-18. GPTPACTL Field Descriptions (continued)
    • 20.5.16 Pulse Accumulator Flag Register (GPTPAFLG)
      • Figure 20-18. Pulse Accumulator Flag Register (GPTPAFLG)
      • Table 20-19. GPTPAFLG Field Descriptions
    • 20.5.17 Pulse Accumulator Counter Register (GPTPACNT)
      • Figure 20-19. Pulse Accumulator Counter Register (GPTPACNT)
      • Table 20-20. GPTPACR Field Descriptions
    • 20.5.18 GPT Port Data Register (GPTPORT)
      • Figure 20-20. GPT Port Data Register (GPTPORT)
      • Table 20-21. GPTPORT Field Descriptions
    • 20.5.19 GPT Port Data Direction Register (GPTDDR)
      • Figure 20-21. GPT Port Data Direction Register (GPTDDR)
      • Table 20-22. GPTDDR Field Descriptions
  • 20.6 Functional Description
    • 20.6.1 Prescaler
    • 20.6.2 Input Capture
    • 20.6.3 Output Compare
    • 20.6.4 Pulse Accumulator
    • 20.6.5 Event Counter Mode
    • 20.6.6 Gated Time Accumulation Mode
      • Figure 20-22. Channel 3 Output Compare/Pulse Accumulator Logic
    • 20.6.7 General-Purpose I/O Ports
      • Table 20-23. GPT Settings and Pin Functions (continued)
  • 20.7 Reset
  • 20.8 Interrupts
    • Table 20-24. GPT Interrupt Requests
    • 20.8.1 GPT Channel Interrupts (CnF)
    • 20.8.2 Pulse Accumulator Overflow (PAOVF)
    • 20.8.3 Pulse Accumulator Input (PAIF)
    • 20.8.4 Timer Overflow (TOF)
• Chapter 21 DMA Timers (DTIM0-DTIM3)
  • 21.1 Overview
    • Figure 21-1. DMA Timer Block Diagram
    • 21.1.1 Key Features
  • 21.2 DMA Timer Programming Model
    • 21.2.1 Prescaler
    • 21.2.2 Capture Mode
    • 21.2.3 Reference Compare
    • 21.2.4 Output Mode
    • 21.2.5 Memory Map
      • Table 21-1. DMA Timer Module Memory Map (continued)
    • 21.2.6 DMA Timer Mode Registers (DTMRn)
      • Figure 21-2. DTMRn Bit Definitions
      • Table 21-2. DTMRn Field Descriptions
    • 21.2.7 DMA Timer Extended Mode Registers (DTXMRn)
      • Figure 21-3. DTXMRn Bit Definitions
      • Table 21-3. DTXMRn Field Descriptions
    • 21.2.8 DMA Timer Event Registers (DTERn)
      • Figure 21-4. DTERn Bit Definitions
      • Table 21-4. DTERn Field Descriptions
    • 21.2.9 DMA Timer Reference Registers (DTRRn)
      • Figure 21-5. DTRRn Bit Definitions
    • 21.2.10 DMA Timer Capture Registers (DTCRn)
      • Figure 21-6. DTCRn Bit Definitions
    • 21.2.11 DMA Timer Counters (DTCNn)
      • Figure 21-7. DTCNn Bit Definitions
  • 21.3 Using the DMA Timer Modules
    • 21.3.1 Code Example
    • 21.3.2 Calculating Time-Out Values
• Chapter 22 Queued Serial Peripheral Interface (QSPI) Module
  • 22.1 Overview
  • 22.2 Features
  • 22.3 Module Description
    • 22.3.1 Interface and Signals
      • Figure 22-1. QSPI Block Diagram
      • Table 22-1. QSPI Input and Output Signals and Functions
    • 22.3.2 Internal Bus Interface
  • 22.4 Operation
    • 22.4.1 QSPI RAM
      • Figure 22-2. QSPI RAM Model
      • 22.4.1.1 Receive RAM
      • 22.4.1.2 Transmit RAM
      • 22.4.1.3 Command RAM
    • 22.4.2 Baud Rate Selection
      • Table 22-2. QSPI_CLK Frequency as Function of System Clock and Baud Rate
    • 22.4.3 Transfer Delays
    • 22.4.4 Transfer Length
    • 22.4.5 Data Transfer
  • 22.5 Programming Model
    • Table 22-3. QSPI Registers
    • 22.5.1 QSPI Mode Register (QMR)
      • Figure 22-3. QSPI Mode Register (QMR)
      • Table 22-4. QMR Field Descriptions (continued)
      • Figure 22-4. QSPI Clocking and Data Transfer Example
    • 22.5.2 QSPI Delay Register (QDLYR)
      • Figure 22-5. QSPI Delay Register (QDLYR)
      • Table 22-5. QDLYR Field Descriptions
    • 22.5.3 QSPI Wrap Register (QWR)
      • Figure 22-6. QSPI Wrap Register (QWR)
      • Table 22-6. QWR Field Descriptions
    • 22.5.4 QSPI Interrupt Register (QIR)
      • Figure 22-7. QSPI Interrupt Register (QIR)
      • Table 22-7. QIR Field Descriptions
    • 22.5.5 QSPI Address Register (QAR)
      • Figure 22-8. QSPI Address Register
    • 22.5.6 QSPI Data Register (QDR)
      • Figure 22-9. QSPI Data Register (QDR)
    • 22.5.7 Command RAM Registers (QCR0-QCR15)
      • Figure 22-10. Command RAM Registers (QCR0-QCR15)
      • Table 22-8. QCR0-QCR15 Field Descriptions
      • Figure 22-11. QSPI Timing
    • 22.5.8 Programming Example
• Chapter 23 UART Modules
  • 23.1 Overview
    • Figure 23-1. Simplified Block Diagram
  • 23.2 Serial Module Overview
  • 23.3 Register Descriptions
    • Table 23-1. UART Module Memory Map (continued)
    • 23.3.1 UART Mode Registers 1 (UMR1n)
      • Figure 23-2. UART Mode Registers 1 (UMR1n)
      • Table 23-2. UMR1n Field Descriptions
    • 23.3.2 UART Mode Register 2 (UMR2n)
      • Figure 23-3. UART Mode Register 2 (UMR2n)
      • Table 23-3. UMR2n Field Descriptions (continued)
    • 23.3.3 UART Status Registers (USRn)
      • Figure 23-4. UART Status Register (USRn)
      • Table 23-4. USRn Field Descriptions (continued)
    • 23.3.4 UART Clock Select Registers (UCSRn)
      • Figure 23-5. UART Clock Select Register (UCSRn)
      • Table 23-5. UCSRn Field Descriptions
    • 23.3.5 UART Command Registers (UCRn)
      • Figure 23-6. UART Command Register (UCRn)
      • Table 23-6. UCRn Field Descriptions (continued)
    • 23.3.6 UART Receive Buffers (URBn)
      • Figure 23-7. UART Receive Buffer (URBn)
    • 23.3.7 UART Transmit Buffers (UTBn)
      • Figure 23-8. UART Transmit Buffer (UTBn)
    • 23.3.8 UART Input Port Change Registers (UIPCRn)
      • Figure 23-9. UART Input Port Change Register (UIPCRn)
      • Table 23-7. UIPCRn Field Descriptions
    • 23.3.9 UART Auxiliary Control Register (UACRn)
      • Figure 23-10. UART Auxiliary Control Register (UACRn)
      • Table 23-8. UACRn Field Descriptions
    • 23.3.10 UART Interrupt Status/Mask Registers (UISRn/UIMRn)
      • Figure 23-11. UART Interrupt Status/Mask Registers (UISRn/UIMRn)
      • Table 23-9. UISRn/UIMRn Field Descriptions
    • 23.3.11 UART Baud Rate Generator Registers (UBG1n/UBG2n)
      • Figure 23-12. UART Baud Rate Generator Register (UBG1n)
      • Figure 23-13. UART Baud Rate Generator Register (UBG2n)
    • 23.3.12 UART Input Port Register (UIPn)
      • Figure 23-14. UART Input Port Register (UIPn)
      • Table 23-10. UIPn Field Descriptions
    • 23.3.13 UART Output Port Command Registers (UOP1n/UOP0n)
      • Figure 23-15. UART Output Port Command Registers (UOP1n/UOP0n)
      • Table 23-11. UOP1/UOP0 Field Descriptions
  • 23.4 UART Module Signal Definitions
    • Figure 23-16. UART Block Diagram Showing External and Internal Interface Signals
    • Table 23-12. UART Module Signals
    • Figure 23-17. UART/RS-232 Interface
  • 23.5 Operation
    • 23.5.1 Transmitter/Receiver Clock Source
      • 23.5.1.1 Programmable Divider
        • Figure 23-18. Clocking Source Diagram
      • 23.5.1.2 Calculating Baud Rates
    • 23.5.2 Transmitter and Receiver Operating Modes
      • Figure 23-19. Transmitter and Receiver Functional Diagram
      • 23.5.2.1 Transmitter
        • Figure 23-20. Transmitter Timing Diagram
      • 23.5.2.2 Receiver
        • Figure 23-21. Receiver Timing
      • 23.5.2.3 FIFO Stack
    • 23.5.3 Looping Modes
      • 23.5.3.1 Automatic Echo Mode
        • Figure 23-22. Automatic Echo
      • 23.5.3.2 Local Loop-Back Mode
        • Figure 23-23. Local Loop-Back
      • 23.5.3.3 Remote Loop-Back Mode
        • Figure 23-24. Remote Loop-Back
    • 23.5.4 Multidrop Mode
      • Figure 23-25. Multidrop Mode Timing Diagram
    • 23.5.5 Bus Operation
      • 23.5.5.1 Read Cycles
      • 23.5.5.2 Write Cycles
    • 23.5.6 Programming
      • 23.5.6.1 Interrupt and DMA Request Initialization
        • Table 23-13. UART Interrupts
        • Table 23-14. UART DMA Requests
      • 23.5.6.2 UART Module Initialization Sequence
        • Table 23-15. UART Module Initialization Sequence
        • Figure 23-26. UART Mode Programming Flowchart (Sheet 5 of 5)
• Chapter 24 I2C Interface
  • 24.1 Overview
  • 24.2 Interface Features
    • Figure 24-1. I2C Module Block Diagram
  • 24.3 I2C System Configuration
  • 24.4 I2C Protocol
    • Figure 24-2. I2C Standard Communication Protocol
    • Figure 24-3. Repeated START
    • 24.4.1 Arbitration Procedure
    • 24.4.2 Clock Synchronization
      • Figure 24-4. Synchronized Clock SCL
    • 24.4.3 Handshaking
    • 24.4.4 Clock Stretching
  • 24.5 Programming Model
    • Table 24-1. I2C Interface Memory Map
    • 24.5.1 I2C Address Register (I2ADR)
      • Figure 24-5. I2C Address Register (I2ADR)
      • Table 24-2. I2ADR Field Descriptions
    • 24.5.2 I2C Frequency Divider Register (I2FDR)
      • Figure 24-6. I2C Frequency Divider Register (I2FDR)
      • Table 24-3. I2FDR Field Descriptions
    • 24.5.3 I2C Control Register (I2CR)
      • Figure 24-7. I2C Control Register (I2CR)
      • Table 24-4. I2CR Field Descriptions
    • 24.5.4 I2C Status Register (I2SR)
      • Figure 24-8. I2CR Status Register (I2SR)
      • Table 24-5. I2SR Field Descriptions (continued)
    • 24.5.5 I2C Data I/O Register (I2DR)
      • Figure 24-9. I2C Data I/O Register (I2DR)
  • 24.6 I2C Programming Examples
    • 24.6.1 Initialization Sequence
    • 24.6.2 Generation of START
    • 24.6.3 Post-Transfer Software Response
    • 24.6.4 Generation of STOP
    • 24.6.5 Generation of Repeated START
    • 24.6.6 Slave Mode
    • 24.6.7 Arbitration Lost
      • Figure 24-10. Flow-Chart of Typical I2C Interrupt Routine
• Chapter 25 FlexCAN
  • 25.1 Features
    • Figure 25-1. FlexCAN Block Diagram and Pinout
    • 25.1.1 FlexCAN Memory Map
      • Table 25-1. FlexCAN Memory Map
    • 25.1.2 External Signals
  • 25.2 The CAN System
    • Figure 25-2. Typical CAN system
  • 25.3 Message Buffers
    • 25.3.1 Message Buffer Structure
      • Figure 25-3. Extended ID Message Buffer Structure
      • Figure 25-4. Standard ID Message Buffer Structure
      • 25.3.1.1 Common Fields for Extended and Standard Format Frames
        • Table 25-2. Common Extended/Standard Format Frames
        • Table 25-3. Message Buffer Codes for Receive Buffers
        • Table 25-4. Message Buffer Codes for Transmit Buffers
      • 25.3.1.2 Fields for Extended Format Frames
        • Table 25-5. Extended Format Frames
      • 25.3.1.3 Fields for Standard Format Frames
        • Table 25-6. Standard Format Frames
    • 25.3.2 Message Buffer Memory Map
      • Figure 25-5. FlexCAN Memory Map
  • 25.4 Functional Overview
    • 25.4.1 Transmit Process
    • 25.4.2 Receive Process
      • 25.4.2.1 Self-Received Frames
    • 25.4.3 Message Buffer Handling
      • 25.4.3.1 Serial Message Buffers (SMBs)
      • 25.4.3.2 Transmit Message Buffer Deactivation
      • 25.4.3.3 Receive Message Buffer Deactivation
      • 25.4.3.4 Locking and Releasing Message Buffers
    • 25.4.4 Remote Frames
    • 25.4.5 Overload Frames
    • 25.4.6 Time Stamp
    • 25.4.7 Listen-Only Mode
    • 25.4.8 Bit Timing
      • Table 25-7. Examples of System Clock/CAN Bit-Rate/S-Clock
      • 25.4.8.1 Configuring the FlexCAN Bit Timing
    • 25.4.9 FlexCAN Error Counters
    • 25.4.10 FlexCAN Initialization Sequence
    • 25.4.11 Special Operating Modes
      • 25.4.11.1 Debug Mode
      • 25.4.11.2 Low-Power Stop Mode for Power Saving
      • 25.4.11.3 Auto-Power Save Mode
    • 25.4.12 Interrupts
  • 25.5 Programmer’s Model
    • 25.5.1 CAN Module Configuration Register (CANMCR)
      • Figure 25-6. CAN Module Configuration Register (CANMCR)
      • Table 25-8. CANMCR Field Descriptions (continued)
    • 25.5.2 FlexCAN Control Register 0 (CANCTRL0)
      • Figure 25-7. FlexCAN Control Register 0 (CANCTRL0)
      • Table 25-9. CANCTRL0 Field Descriptions
      • Table 25-10. Transmit Pin Configuration
    • 25.5.3 FlexCAN Control Register 1 (CANCTRL1)
      • Figure 25-8. FlexCAN Control Register 1 (CANCTRL1)
      • Table 25-11. CANCTRL1 Field Descriptions
    • 25.5.4 Prescaler Divide Register (PRESDIV)
      • Figure 25-9. Prescaler Divide Register (PRESDIV)
      • Table 25-12. PRESDIV Field Descriptions
    • 25.5.5 FlexCAN Control Register 2 (CANCTRL2)
      • Figure 25-10. FlexCAN Control Register 2 (CANCTRL2)
      • Table 25-13. CANCTRL2 Field Descriptions
    • 25.5.6 Free Running Timer (TIMER)
      • Figure 25-11. Free Running Timer (TIMER)
      • Table 25-14. TIMER Field Descriptions
    • 25.5.7 Rx Mask Registers
      • Table 25-15. Mask examples for Normal/Extended Messages (continued)
      • 25.5.7.1 Receive Mask Registers (RXGMASK, RX14MASK, RX15MASK)
        • Figure 25-12. Rx Mask Registers (RXGMASK, RX14MASK, and RX15MASK)
        • Table 25-16. RXGMASK, RX14MASK, and RX15MASK Field Descriptions
    • 25.5.8 FlexCAN Error and Status Register (ESTAT)
      • Figure 25-13. FlexCAN Error and Status Register (ESTAT)
      • Table 25-17. ESTAT Field Descriptions (continued)
    • 25.5.9 Interrupt Mask Register (IMASK)
      • Figure 25-14. Interrupt Mask Register (IMASK)
      • Table 25-18. IMASK Field Descriptions
    • 25.5.10 Interrupt Flag Register (IFLAG)
      • Figure 25-15. Interrupt Flag Register (IFLAG)
      • Table 25-19. IFLAG Field Descriptions
    • 25.5.11 FlexCAN Receive Error Counter (RXECTR)
      • Figure 25-16. FlexCAN Receive Error Counter (RXECTR)
      • Table 25-20. RXECTR Field Descriptions
    • 25.5.12 FlexCAN Transmit Error Counter (TXECTR)
      • Figure 25-17. FlexCAN Transmit Error Counter (TXECTR)
      • Table 25-21. TXECTR Field Descriptions
• Chapter 26 General Purpose I/O Module
  • 26.1 Introduction
    • Figure 26-1. MCF5282 Ports Module Block Diagram
    • 26.1.1 Overview
    • 26.1.2 Features
    • 26.1.3 Modes of Operation
  • 26.2 External Signal Description
    • Table 26-1. MCF5282 Ports External Signals (continued)
  • 26.3 Memory Map/Register Definition
    • 26.3.1 Register Overview
      • Table 26-2. MCF5282 Ports Module Memory Map (continued)
    • 26.3.2 Register Descriptions
      • 26.3.2.1 Port Output Data Registers (PORTn)
        • Figure 26-2. Port Output Data Registers (8-bit)
        • Figure 26-3. Port Output Data Register (7-bit)
        • Figure 26-4. Port Output Data Registers (6-bit)
        • Figure 26-5. Port Output Data Registers (4-bit)
        • Table 26-3. PORTn (8-bit, 7-bit, 6-bit, and 4-bit) Field Descriptions
      • 26.3.2.2 Port Data Direction Registers (DDRn)
        • Figure 26-6. Port Data Direction Registers (8-bit)
        • Figure 26-7. Port Data Direction Register (7-bit)
        • Figure 26-8. Port Data Direction Registers (6-bit)
        • Figure 26-9. Port Data Direction Registers (4-bit)
        • Table 26-4. DDRn (8-bit, 6-bit, and 4-bit) Field Descriptions
      • 26.3.2.3 Port Pin Data/Set Data Registers (PORTnP/SETn)
        • Figure 26-10. Port Pin Data/Set Data Registers (8-bit)
        • Figure 26-11. Port Pin Data/Set Data Register (7-bit)
        • Figure 26-12. Port Pin Data/Set Data Registers (6-bit)
        • Figure 26-13. Port Pin Data/Set Data Registers (4-bit)
        • Table 26-5. PORTnP/SETn (8-bit, 6-bit, and 4-bit) Field Descriptions
      • 26.3.2.4 Port Clear Output Data Registers (CLRn)
        • Figure 26-14. Port Clear Output Data Registers (8-bit)
        • Figure 26-15. Port Clear Output Data Register (7-bit)
        • Figure 26-16. Port Clear Output Data Registers (6-bit)
        • Figure 26-17. Port Clear Output Data Registers (4-bit)
        • Table 26-6. CLRn (8-bit,7-bit, 6-bit, and 4-bit) Field Descriptions
      • 26.3.2.5 Port B/C/D Pin Assignment Register (PBCDPAR)
        • Figure 26-18. Port B/C/D Pin Assignment Register (PBCDPAR)
        • Table 26-7. PBCDPAR Field Descriptions
        • Table 26-8. Reset Values for PBCDPAR Bits
      • 26.3.2.6 Port E Pin Assignment Register (PEPAR)
        • Figure 26-19. Port E Pin Assignment Register (PEPAR)
        • Table 26-9. PEPAR Field Descriptions (continued)
        • Table 26-10. Reset Values for PEPAR Bits and Fields
      • 26.3.2.7 Port F Pin Assignment Register (PFPAR)
        • Figure 26-20. Port F Pin Assignment Register (PFPAR)
        • Table 26-11. PFPAR Field Descriptions
      • 26.3.2.8 Port J Pin Assignment Register (PJPAR)
        • Figure 26-21. Port J Pin Assignment Register (PJPAR)
        • Table 26-12. PJPAR Field Descriptions
      • 26.3.2.9 Port SD Pin Assignment Register (PSDPAR)
        • Figure 26-22. Port SD Pin Assignment Register (PSDPAR)
        • Table 26-13. PSDPAR Field Descriptions
      • 26.3.2.10 Port AS Pin Assignment Register (PASPAR)
        • Figure 26-23. Port AS Pin Assignment Register (PASPAR)
        • Table 26-14. PASPAR Field Descriptions
      • 26.3.2.11 Port EH/EL Pin Assignment Register (PEHLPAR)
        • Figure 26-24. Port EH/EL Pin Assignment Register (PEHLPAR)
        • Table 26-15. PEHLPAR Field Descriptions
      • 26.3.2.12 Port QS Pin Assignment Register (PQSPAR)
        • Figure 26-25. Port QS Pin Assignment Register (PQSPAR)
        • Table 26-16. PQSPAR Field Description (continued)
      • 26.3.2.13 Port TC Pin Assignment Register (PTCPAR)
        • Figure 26-26. Port TC Pin Assignment Register (PTCPAR)
        • Table 26-17. PTCPAR Field Descriptions (continued)
      • 26.3.2.14 Port TD Pin Assignment Register (PTDPAR)
        • Figure 26-27. Port TD Pin Assignment Register (PTDPAR)
        • Table 26-18. PTDPAR Field Descriptions (continued)
      • 26.3.2.15 Port UA Pin Assignment Register (PUAPAR)
        • Figure 26-28. Port UA Pin Assignment Register (PUAPAR)
        • Table 26-19. PUAPAR Field Descriptions
  • 26.4 Functional Description
    • 26.4.1 Overview
    • 26.4.2 Port Digital I/O Timing
      • Figure 26-29. Digital Input Timing
      • Figure 26-30. Digital Output Timing
  • 26.5 Initialization/Application Information
• Chapter 27 Queued Analog-to-Digital Converter (QADC)
  • 27.1 Features
  • 27.2 Block Diagram
    • Figure 27-1. QADC Block Diagram
  • 27.3 Modes of Operation
    • 27.3.1 Debug Mode
    • 27.3.2 Stop Mode
  • 27.4 Signals
    • 27.4.1 Port QA Signal Functions
      • 27.4.1.1 Port QA Analog Input Signals
        • Figure 27-2. QADC Input and Output Signals
      • 27.4.1.2 Port QA Digital Input/Output Signals
    • 27.4.2 Port QB Signal Functions
      • 27.4.2.1 Port QB Analog Input Signals
      • 27.4.2.2 Port QB Digital I/O Signals
    • 27.4.3 External Trigger Input Signals
    • 27.4.4 Multiplexed Address Output Signals
    • 27.4.5 Multiplexed Analog Input Signals
      • Table 27-1. Multiplexed Analog Input Channels
    • 27.4.6 Voltage Reference Signals
    • 27.4.7 Dedicated Analog Supply Signals
    • 27.4.8 Dedicated Digital I/O Port Supply Signal
  • 27.5 Memory Map
    • Table 27-2. QADC Memory Map
  • 27.6 Register Descriptions
    • 27.6.1 QADC Module Configuration Register (QADCMCR)
      • Figure 27-3. QADC Module Configuration Register (QADCMCR)
      • Table 27-3. QADCMCR Field Descriptions
    • 27.6.2 QADC Test Register (QADCTEST)
    • 27.6.3 Port Data Registers (PORTQA and PORTQB)
      • Figure 27-4. QADC Port QA Data Register (PORTQA)
      • Figure 27-5. QADC Port QB Data Register (PORTQB)
    • 27.6.4 Port QA and QB Data Direction Register (DDRQA and DDRQB)
      • Figure 27-6. QADC Port QA Data Direction Register (DDRQA)
      • Figure 27-7. Port QB Data Direction Register (DDRQB)
    • 27.6.5 Control Registers
      • 27.6.5.1 QADC Control Register 0 (QACR0)
        • Figure 27-8. QADC Control Register 0 (QACR0)
        • Table 27-4. QACR0 Field Descriptions
        • Table 27-5. Prescaler fSYS Divide-by Values
      • 27.6.5.2 QADC Control Register 1 (QACR1)
        • Figure 27-9. QADC Control Register 1 (QACR1)
        • Table 27-6. QACR1 Field Descriptions
        • Table 27-7. Queue 1 Operating Modes
      • 27.6.5.3 QADC Control Register 2 (QACR2)
        • Figure 27-10. QADC Control Register 2 (QACR2)
        • Table 27-8. QACR2 Field Descriptions
        • Table 27-9. Queue 2 Operating Modes (continued)
    • 27.6.6 Status Registers
      • 27.6.6.1 QADC Status Register 0 (QASR0)
        • Figure 27-11. QADC Status Register 0 (QASR0)
        • Table 27-10. QASR0 Field Descriptions
        • Table 27-11. CCW Pause Bit Response
        • Table 27-12. Queue Status
        • Figure 27-12. Queue Status Transition
      • 27.6.6.2 QADC Status Register 1 (QASR1)
        • Figure 27-13. QADC Status Register 1 (QASR1)
        • Table 27-13. QASR1 Field Descriptions
    • 27.6.7 Conversion Command Word Table (CCW)
      • Figure 27-14. Conversion Command Word Table (CCW)
      • Table 27-14. CCW Field Descriptions (continued)
      • Table 27-15. Input Sample Times
      • Table 27-16. Non-Multiplexed Channel Assignments and Signal Designations
      • Table 27-17. Multiplexed Channel Assignments and Signal Designations
    • 27.6.8 Result Registers
      • 27.6.8.1 Right-Justified Unsigned Result Register (RJURR)
        • Figure 27-15. Right-Justified Unsigned Result Register (RJURR)
        • Table 27-18. RJURR Field Descriptions
      • 27.6.8.2 Left-Justified Signed Result Register (LJSRR)
        • Figure 27-16. Left-Justified Signed Result Register (LJSRR)
        • Table 27-19. LJSRR Field Descriptions
      • 27.6.8.3 Left-Justified Unsigned Result Register (LJURR)
        • Figure 27-17. Left-Justified Unsigned Result Register (LJURR)
        • Table 27-20. LJURR Field Descriptions
  • 27.7 Functional Description
    • 27.7.1 Result Coherency
    • 27.7.2 External Multiplexing
      • 27.7.2.1 External Multiplexing Operation
        • Figure 27-18. External Multiplexing Configuration
      • 27.7.2.2 Module Version Options
        • Table 27-21. Analog Input Channels
    • 27.7.3 Analog Subsystem
      • 27.7.3.1 Analog-to-Digital Converter Operation
        • Figure 27-19. QADC Analog Subsystem Block Diagram
      • 27.7.3.2 Conversion Cycle Times
        • Figure 27-20. Conversion Timing
        • Figure 27-21. Bypass Mode Conversion Timing
      • 27.7.3.3 Channel Decode and Multiplexer
      • 27.7.3.4 Sample Buffer
      • 27.7.3.5 Comparator
      • 27.7.3.6 Bias
      • 27.7.3.7 Successive Approximation Register (SAR)
      • 27.7.3.8 State Machine
  • 27.8 Digital Control Subsystem
    • 27.8.1 Queue Priority Timing Examples
      • 27.8.1.1 Queue Priority
        • Figure 27-22. QADC Queue Operation with Pause
      • 27.8.1.2 Queue Priority Schemes
        • Table 27-22. Trigger Events
        • Table 27-23. Status Bits
        • Figure 27-23. CCW Priority Situation 1
        • Figure 27-24. CCW Priority Situation 2
        • Figure 27-25. CCW Priority Situation 3
        • Figure 27-26. CCW Priority Situation 4
        • Figure 27-27. CCW Priority Situation 5
        • Figure 27-28. CCW Priority Situation 6
        • Figure 27-29. CCW Priority Situation 7
        • Figure 27-30. CCW Priority Situation 8
        • Figure 27-31. CCW Priority Situation 9
        • Figure 27-32. CCW Priority Situation 10
        • Figure 27-33. CCW Priority Situation 11
        • Figure 27-34. CCW Freeze Situation 12
        • Figure 27-35. CCW Freeze Situation 13
        • Figure 27-36. CCW Freeze Situation 14
        • Figure 27-37. . CCW Freeze Situation 15
        • Figure 27-38. CCW Freeze Situation 16
        • Figure 27-39. CCW Freeze Situation 17
        • Figure 27-40. CCW Freeze Situation 18
        • Figure 27-41. CCW Freeze Situation 19
    • 27.8.2 Boundary Conditions
    • 27.8.3 Scan Modes
    • 27.8.4 Disabled Mode
    • 27.8.5 Reserved Mode
    • 27.8.6 Single-Scan Modes
      • 27.8.6.1 Software-Initiated Single-Scan Mode
      • 27.8.6.2 Externally Triggered Single-Scan Mode
      • 27.8.6.3 Externally Gated Single-Scan Mode
      • 27.8.6.4 Interval Timer Single-Scan Mode
    • 27.8.7 Continuous-Scan Modes
      • 27.8.7.1 Software-Initiated Continuous-Scan Mode
      • 27.8.7.2 Externally Triggered Continuous-Scan Mode
      • 27.8.7.3 Externally Gated Continuous-Scan Mode
      • 27.8.7.4 Periodic Timer Continuous-Scan Mode
    • 27.8.8 QADC Clock (QCLK) Generation
      • Figure 27-42. QADC Clock Subsystem Functions
    • 27.8.9 Periodic/Interval Timer
    • 27.8.10 Conversion Command Word Table
      • Figure 27-43. QADC Conversion Queue Operation
    • 27.8.11 Result Word Table
  • 27.9 Signal Connection Considerations
    • 27.9.1 Analog Reference Signals
    • 27.9.2 Analog Power Signals
      • Figure 27-44. Equivalent Analog Input Circuitry
      • Figure 27-45. Errors Resulting from Clipping
    • 27.9.3 Conversion Timing Schemes
      • Figure 27-46. External Positive Edge Trigger Mode Timing with Pause
      • Figure 27-47. Gated Mode, Single Scan Timing
      • Figure 27-48. Gated Mode, Continuous Scan Timing
    • 27.9.4 Analog Supply Filtering and Grounding
      • Figure 27-49. Star-Ground at the Point of Power Supply Origin
    • 27.9.5 Accommodating Positive/Negative Stress Conditions
      • Figure 27-50. Input Signal Subjected to Negative Stress
      • Figure 27-51. Input Signal Subjected to Positive Stress
    • 27.9.6 Analog Input Considerations
      • Figure 27-52. External Multiplexing of Analog Signal Sources
    • 27.9.7 Analog Input Pins
      • Figure 27-53. Electrical Model of an A/D Input Signal
      • 27.9.7.1 Settling Time for the External Circuit
        • Table 27-24. External Circuit Settling Time to 1/2 LSB
      • 27.9.7.2 Error Resulting from Leakage
        • Table 27-25. Error Resulting from Input Leakage (IOff)
  • 27.10 Interrupts
    • 27.10.1 Interrupt Operation
      • Table 27-26. QADC Status Flags and Interrupt Sources
    • 27.10.2 Interrupt Sources
• Chapter 28 Reset Controller Module
  • 28.1 Features
  • 28.2 Block Diagram
    • Figure 28-1. Reset Controller Block Diagram
  • 28.3 Signals
    • Table 28-1. Reset Controller Signal Properties
    • 28.3.1 RSTI
    • 28.3.2 RSTO
  • 28.4 Memory Map and Registers
    • Table 28-2. Reset Controller Memory Map
    • 28.4.1 Reset Control Register (RCR)
      • Figure 28-2. Reset Control Register (RCR)
      • Table 28-3. RCR Field Descriptions (continued)
    • 28.4.2 Reset Status Register (RSR)
      • Figure 28-3. Reset Status Register (RSR)
      • Table 28-4. RSR Field Descriptions
  • 28.5 Functional Description
    • 28.5.1 Reset Sources
      • Table 28-5. Reset Source Summary
      • 28.5.1.1 Power-On Reset
      • 28.5.1.2 External Reset
      • 28.5.1.3 Watchdog Timer Reset
      • 28.5.1.4 Loss-of-Clock Reset
      • 28.5.1.5 Loss-of-Lock Reset
      • 28.5.1.6 Software Reset
      • 28.5.1.7 LVD Reset
    • 28.5.2 Reset Control Flow
      • Figure 28-4. Reset Control Flow
      • 28.5.2.1 Synchronous Reset Requests
      • 28.5.2.2 Internal Reset Request
      • 28.5.2.3 Power-On Reset/Low-Voltage Detect Reset
    • 28.5.3 Concurrent Resets
      • 28.5.3.1 Reset Flow
      • 28.5.3.2 Reset Status Flags
• Chapter 29 Debug Support
  • 29.1 Overview
    • Figure 29-1. Processor/Debug Module Interface
  • 29.2 Signal Description
    • Table 29-1. Debug Module Signals
    • Figure 29-2. CLKOUT Timing
  • 29.3 Real-Time Trace Support
    • Table 29-2. Processor Status Encoding (continued)
    • 29.3.1 Begin Execution of Taken Branch (PST = 0x5)
      • Figure 29-3. Example JMP Instruction Output on PST/DDATA
  • 29.4 Programming Model
    • Figure 29-4. Debug Programming Model
    • Table 29-3. BDM/Breakpoint Registers
    • 29.4.1 Revision A Shared Debug Resources
      • Table 29-4. Rev. A Shared BDM/Breakpoint Hardware
    • 29.4.2 Address Attribute Trigger Register (AATR)
      • Figure 29-5. Address Attribute Trigger Register (AATR)
      • Table 29-5. AATR Field Descriptions (continued)
    • 29.4.3 Address Breakpoint Registers (ABLR, ABHR)
      • Figure 29-6. Address Breakpoint Registers (ABLR, ABHR)
      • Table 29-6. ABLR Field Description
      • Table 29-7. ABHR Field Description
    • 29.4.4 Configuration/Status Register (CSR)
      • Figure 29-7. Configuration/Status Register (CSR)
      • Table 29-8. CSR Field Descriptions (continued)
    • 29.4.5 Data Breakpoint/Mask Registers (DBR, DBMR)
      • Figure 29-8. Data Breakpoint/Mask Registers (DBR/DBMR)
      • Table 29-9. DBR Field Descriptions
      • Table 29-10. DBMR Field Descriptions
      • Table 29-11. Access Size and Operand Data Location
    • 29.4.6 Program Counter Breakpoint/Mask Registers (PBR, PBMR)
      • Figure 29-9. Program Counter Breakpoint Register (PBR)
      • Table 29-12. PBR Field Descriptions
      • Figure 29-10. Program Counter Breakpoint Mask Register (PBMR)
      • Table 29-13. PBMR Field Descriptions
    • 29.4.7 Trigger Definition Register (TDR)
      • Figure 29-11. Trigger Definition Register (TDR)
      • Table 29-14. TDR Field Descriptions (continued)
  • 29.5 Background Debug Mode (BDM)
    • 29.5.1 CPU Halt
    • 29.5.2 BDM Serial Interface
      • Figure 29-12. BDM Serial Interface Timing
      • 29.5.2.1 Receive Packet Format
        • Figure 29-13. Receive BDM Packet
        • Table 29-15. Receive BDM Packet Field Description
      • 29.5.2.2 Transmit Packet Format
        • Figure 29-14. Transmit BDM Packet
        • Table 29-16. Transmit BDM Packet Field Description
    • 29.5.3 BDM Command Set
      • Table 29-17. BDM Command Summary
      • 29.5.3.1 ColdFire BDM Command Format
        • Figure 29-15. BDM Command Format
        • Table 29-18. BDM Field Descriptions
      • 29.5.3.2 Command Sequence Diagrams
        • Figure 29-16. Command Sequence Diagram
      • 29.5.3.3 Command Set Descriptions
        • Figure 29-17. rareg/rdreg Command Format
        • Figure 29-18. rareg/rdreg Command Sequence
        • Figure 29-19. wareg/wdreg Command Format
        • Figure 29-20. wareg/wdreg Command Sequence
        • Figure 29-21. read Command/Result Formats
        • Figure 29-22. read Command Sequence
        • Figure 29-23. write Command Format
        • Figure 29-24. write Command Sequence
        • Figure 29-25. dump Command/Result Formats
        • Figure 29-26. dump Command Sequence
        • Figure 29-27. fill Command Format
        • Figure 29-28. fill Command Sequence
        • Figure 29-29. go Command Format
        • Figure 29-30. go Command Sequence
        • Figure 29-31. nop Command Format
        • Figure 29-32. nop Command Sequence
        • Figure 29-33. rcreg Command/Result Formats
        • Table 29-19. Control Register Map
        • Figure 29-34. rcreg Command Sequence
        • Figure 29-35. wcreg Command/Result Formats
        • Figure 29-36. wcreg Command Sequence
        • Figure 29-37. rdmreg Command/Result Formats
        • Table 29-20. Definition of DRc Encoding-Read
        • Figure 29-38. rdmreg Command Sequence
        • Figure 29-39. wdmreg BDM Command Format
        • Figure 29-40. wdmreg Command Sequence
  • 29.6 Real-Time Debug Support
    • 29.6.1 Theory of Operation
      • Table 29-21. DDATA[3:0]/CSR[BSTAT] Breakpoint Response
      • 29.6.1.1 Emulator Mode
    • 29.6.2 Concurrent BDM and Processor Operation
  • 29.7 Processor Status, DDATA Definition
    • 29.7.1 User Instruction Set
      • Table 29-22. PST/DDATA Specification for User-Mode Instructions (continued)
      • Table 29-23. PST/DDATA Specification for MAC Instructions (continued)
    • 29.7.2 Supervisor Instruction Set
      • Table 29-24. PST/DDATA Specification for Supervisor-Mode Instructions
  • 29.8 Motorola-Recommended BDM Pinout
    • Figure 29-41. Recommended BDM Connector
• Chapter 30 Chip Configuration Module (CCM)
  • 30.1 Features
  • 30.2 Modes of Operation
    • 30.2.1 Master Mode
    • 30.2.2 Single-Chip Mode
  • 30.3 Block Diagram
    • Figure 30-1. Chip Configuration Module Block Diagram
  • 30.4 Signal Descriptions
    • Table 30-1. Signal Properties
    • 30.4.1 RCON
    • 30.4.2 CLKMOD[1:0]
    • 30.4.3 D[26:24, 21, 19:16] (Reset Configuration Override)
  • 30.5 Memory Map and Registers
    • 30.5.1 Programming Model
      • Table 30-2. Write-Once Bits Read/Write Accessibility
    • 30.5.2 Memory Map
      • Table 30-3. Chip Configuration Module Memory Map
    • 30.5.3 Register Descriptions
      • 30.5.3.1 Chip Configuration Register (CCR)
        • Figure 30-2. Chip Configuration Register (CCR)
        • Table 30-4. CCR Field Descriptions (continued)
      • 30.5.3.2 Reset Configuration Register (RCON)
        • Figure 30-3. Reset Configuration Register (RCON)
        • Table 30-5. RCON Field Descriptions (continued)
        • Table 30-6. RCSC Chip Select Configuration
        • Table 30-7. BOOTPS Port Size Configuration
      • 30.5.3.3 Chip Identification Register (CIR)
        • Figure 30-4. Chip Identification Register (CIR)
        • Table 30-8. CIR Field Description
  • 30.6 Functional Description
    • 30.6.1 Reset Configuration
      • Table 30-9. Reset Configuration Pin States During Reset
      • Table 30-10. Configuration During Reset (continued)
    • 30.6.2 Chip Mode Selection
      • Table 30-11. Chip Configuration Mode Selection
    • 30.6.3 Boot Device Selection
    • 30.6.4 Output Pad Strength Configuration
      • Table 30-12. Output Pad Driver Strength Selection
    • 30.6.5 Clock Mode Selection
      • Table 30-13. Clock Mode Selection
    • 30.6.6 Chip Select Configuration
  • 30.7 Reset
  • 30.8 Interrupts
• Chapter 31 IEEE 1149.1 Test Access Port (JTAG)
  • Figure 31-1. JTAG Block Diagram
  • 31.1 Features
  • 31.2 Modes of Operation
  • 31.3 External Signal Description
    • 31.3.1 Detailed Signal Description
      • Table 31-1. Signal Properties
      • 31.3.1.1 JTAG_EN - JTAG Enable
        • Table 31-2. Pin Function Selected
        • Table 31-3. Signal State to the Disable Module
      • 31.3.1.2 TCLK - Test Clock Input
      • 31.3.1.3 TMS/BKPT - Test Mode Select / Breakpoint
      • 31.3.1.4 TDI/DSI - Test Data Input / Development Serial Input
      • 31.3.1.5 TRST/DSCLK - Test Reset / Development Serial Clock
      • 31.3.1.6 TDO/DSO - Test Data Output / Development Serial Output
  • 31.4 Memory Map/Register Definition
    • 31.4.1 Memory Map
    • 31.4.2 Register Descriptions
      • 31.4.2.1 Instruction Shift Register (IR)
      • 31.4.2.2 IDCODE Register
        • Figure 31-2. IDCODE Register
        • Table 31-4. IDCODE Register Field Descriptions
      • 31.4.2.3 Bypass Register
      • 31.4.2.4 JTAG_CFM_CLKDIV Register
      • 31.4.2.5 TEST_CTRL Register
      • 31.4.2.6 Boundary Scan Register
  • 31.5 Functional Description
    • 31.5.1 JTAG Module
    • 31.5.2 TAP Controller
      • Figure 31-3. TAP Controller State Machine Flow
    • 31.5.3 JTAG Instructions
      • Table 31-5. JTAG Instructions (continued)
      • 31.5.3.1 External Test Instruction (EXTEST)
      • 31.5.3.2 IDCODE Instruction
      • 31.5.3.3 SAMPLE/PRELOAD Instruction
      • 31.5.3.4 TEST_LEAKAGE Instruction
      • 31.5.3.5 ENABLE_TEST_CTRL Instruction
      • 31.5.3.6 HIGHZ Instruction
      • 31.5.3.7 LOCKOUT_RECOVERY Instruction
      • 31.5.3.8 CLAMP Instruction
      • 31.5.3.9 BYPASS Instruction
  • 31.6 Initialization/Application Information
    • 31.6.1 Restrictions
    • 31.6.2 Nonscan Chain Operation
• Chapter 32 Mechanical Data
  • 32.1 Pinout
    • Figure 32-1. MCF5282 Pinout (256 MAPBGA)
    • Table 32-1. MCF5282 Signal Description by Pin Number (Continued)
    • Figure 32-2. 256 MAPBGA Package Dimensions
  • 32.2 Ordering Information
    • Table 32-2. Orderable Part Numbers
• Chapter 33 Electrical Characteristics
  • 33.1 Maximum Ratings
    • Table 33-1. Absolute Maximum Ratings, (Continued)
  • 33.2 Thermal Characteristics
    • Table 33-2. Thermal Characteristics
  • 33.3 DC Electrical Specifications
    • Table 33-3. DC Electrical Specifications (Continued)
  • 33.4 Phase Lock Loop Electrical Specifications
    • Table 33-4. PLL Electrical Specifications
  • 33.5 QADC Electrical Characteristics
    • Table 33-5. QADC Absolute Maximum Ratings
    • Table 33-6. QADC Electrical Specifications (Operating) (Continued)
    • Table 33-7. QADC Conversion Specifications (Operating)
  • 33.6 Flash Memory Characteristics
    • Table 33-8. SGFM Flash Program and Erase Characteristics
    • Table 33-9. SGFM Flash Module Life Characteristics
  • 33.7 External Interface Timing Characteristics
    • Table 33-10. Processor Bus Input Timing Specifications
    • Figure 33-1. General Input Timing Requirements
  • 33.8 Processor Bus Output Timing Specifications
    • Table 33-11. External Bus Output Timing Specifications (Continued)
    • Figure 33-2. Read/Write (Internally Terminated) Timing
    • Figure 33-3. Read Bus Cycle Terminated by TA
    • Figure 33-4. Read Bus Cycle Terminated by TEA
    • Figure 33-5. SDRAM Read Cycle
    • Table 33-12. SDRAM Timing
    • Figure 33-6. SDRAM Write Cycle
  • 33.9 General Purpose I/O Timing
    • Table 33-13. GPIO Timing, (Continued)
    • (VDD = 2.7 to 3.6 V, VSS = 0 V, VDDH = 5 V)
    • Figure 33-7. GPIO Timing
  • 33.10 Reset and Configuration Override Timing
    • Table 33-14. Reset and Configuration Override Timing (Continued)
    • Figure 33-8. RSTI and Configuration Override Timing
  • 33.11 I2C Input/Output Timing Specifications
    • Table 33-15. I2C Input Timing Specifications between SCL and SDA
    • Table 33-16. I2C Output Timing Specifications between SCL and SDA
    • Figure 33-9. I2C Input/Output Timings
  • 33.12 Fast Ethernet AC Timing Specifications
    • 33.12.1 MII Receive Signal Timing (ERXD[3:0], ERXDV, ERXER, and ERXCLK)
      • Table 33-17. MII Receive Signal Timing
      • Figure 33-10. MII Receive Signal Timing Diagram
    • 33.12.2 MII Transmit Signal Timing (ETXD[3:0], ETXEN, ETXER, ETXCLK)
      • Table 33-18. MII Transmit Signal Timing
      • Figure 33-11. MII Transmit Signal Timing Diagram
    • 33.12.3 MII Async Inputs Signal Timing (ECRS and ECOL)
      • Table 33-19. MII Async Inputs Signal Timing
      • Figure 33-12. MII Async Inputs Timing Diagram
    • 33.12.4 MII Serial Management Channel Timing (EMDIO and EMDC)
      • Table 33-20. MII Serial Management Channel Timing
      • Figure 33-13. MII Serial Management Channel Timing Diagram
  • 33.13 DMA Timer Module AC Timing Specifications
    • Table 33-21. Timer Module AC Timing Specifications
  • 33.14 QSPI Electrical Specifications
    • Table 33-22. QSPI Modules AC Timing Specifications
    • Figure 33-14. QSPI Timing
  • 33.15 JTAG and Boundary Scan Timing
    • Table 33-23. JTAG and Boundary Scan Timing
    • Figure 33-15. Test Clock Input Timing
    • Figure 33-16. Boundary Scan (JTAG) Timing
    • Figure 33-17. Test Access Port Timing
    • Figure 33-18. TRST Timing
    • Figure 33-19. BKPT Timing
  • 33.16 Debug AC Timing Specifications
    • Table 33-24. Debug AC Timing Specification
    • Figure 33-20. Real-Time Trace AC Timing
    • Figure 33-21. BDM Serial Port AC Timing
• Appendix A Register Memory Map
  • Table A-1. CPU Space Register Memory Map
  • Table A-2. Module Memory Map Overview
  • Table A-3. Register Memory Map (Continued)