Motorola Coldfire Mcf5281 Users Manual 5282UM

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MCF5282UM/D
Rev. 2
1/2004

MCF5282 ColdFire®
Microcontroller User’s Manual
Devices Supported:
MCF5281

HOW TO REACH US:
USA/EUROPE/LOCATIONS NOT LISTED:
Motorola Literature Distribution;
P.O. Box 5405
Denver, Colorado 80217
1-800-521-6274 or 480-768-2130
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Motorola Japan Ltd.;
SPS, Technical Information Center,
3-20-1, Minami-Azabu Minato-ku,
Tokyo 106-8573 Japan
81-3-3440-3569

Information in this document is provided solely to enable system and software implementers to use
Motorola products. There are no express or implied copyright licenses granted hereunder to design

ASIA/PACIFIC:

or fabricate any integrated circuits or integrated circuits based on the information in this document.

Motorola Semiconductors H.K. Ltd.;
Silicon Harbour Centre
2 Dai King Street,
Tai Po Industrial Estate
Tai Po, N.T., Hong Kong
852-26668334

Motorola reserves the right to make changes without further notice to any products herein.

HOME PAGE:
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for any particular purpose, nor does Motorola assume any liability arising out of the application or
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performance may vary over time. All operating parameters, including “Typicals” must be validated
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© Motorola, Inc. 2004

Overview

1

ColdFire Core

2

Enhanced Multiply-Accumulate Unit (EMAC)

3

Cache

4

Static RAM (SRAM)

5

ColdFire Flash Module (CFM)

6

Power Management

7

System Control Module (SCM)

8

Clock Module

9

Interrupt Controller Modules

10

Edge Port Module (EPORT)

11

Chip Select Module

12

External Interface Module (EIM)

13

Signal Descriptions

14

Synchronous DRAM Controller Module

15

DMA Controller Module

16

Fast Ethernet Controller (FEC)

17

Watchdog Timer Module

18

Programmable Interrupt Timer (PIT) Modules

19

General Purpose Timer (GPT) Modules

20

DMA Timers

21

Queued Serial Peripheral Interface Module (QSPI)

22

UART Modules

23

I2C Module
FlexCAN Module

24

General Purpose I/O Module

26

Chip Configuration Module (CCM)

27

Queued Analog-to-Digital Converter (QADC)

28

Reset Controller Module

29

Debug Support

30

IEEE 1149.1 Test Access Port (JTAG)

31

Mechanical Data

32

Electrical Characteristics

33

Appendix A: List of Memory Maps

A

Index

25

IND

1

Overview

2

ColdFire Core

3

Enhanced Multiply-Accumulate Unit (EMAC)

4

Cache

5

Static RAM (SRAM)

6

ColdFire Flash Module (CFM)

7

Power Management

8

System Control Module (SCM)

9

Clock Module

10

Interrupt Controller Modules

11

Edge Port Module (EPORT)

12

Chip Select Module

13

External Interface Module (EIM)

14

Signal Descriptions

15

Synchronous DRAM Controller Module

16

DMA Controller Module

17

Fast Ethernet Controller (FEC)

18

Watchdog Timer Module

19

Programmable Interrupt Timer (PIT) Modules

20

General Purpose Timer (GPT) Modules

21

DMA Timers

22

Queued Serial Peripheral Interface Module (QSPI)

23

UART Modules

24
25

I2C Module
FlexCAN Module

26

General Purpose I/O Module

27

Chip Configuration Module (CCM)

28

Queued Analog-to-Digital Converter (QADC)

29

Reset Controller Module

30

Debug Support

31

IEEE 1149.1 Test Access Port (JTAG)

32

Mechanical Data

33

Electrical Characteristics

A

Appendix A: List of Memory Maps

IND

Index

CONTENTS
Paragraph
Number

Title

Page
Number

Chapter 1
Overview
1.1
1.1.1
1.1.2
1.1.3
1.1.4
1.1.5
1.1.6
1.1.7
1.1.8
1.1.9
1.1.10
1.1.11
1.1.12
1.1.13
1.1.14
1.1.15
1.1.16
1.1.17
1.2
1.2.1
1.2.2
1.2.3
1.2.4
1.2.5

MCF5282 Key Features...................................................................................... 1-1
Version 2 ColdFire Core................................................................................. 1-8
System Control Module ................................................................................ 1-10
External Interface Module (EIM) ................................................................. 1-10
Chip Select.................................................................................................... 1-11
Power Management ...................................................................................... 1-11
General Input/Output Ports........................................................................... 1-11
Interrupt Controllers (INTC0/INTC1) .......................................................... 1-11
SDRAM Controller....................................................................................... 1-11
Test Access Port............................................................................................ 1-12
UART Modules............................................................................................. 1-12
DMA Timers (DTIM0-DTIM3) ................................................................... 1-13
General-Purpose Timers (GPTA/GPTB)...................................................... 1-13
Periodic Interrupt Timers (PIT0-PIT3)......................................................... 1-13
Software Watchdog Timer............................................................................ 1-14
Phase Locked Loop (PLL)............................................................................ 1-14
DMA Controller............................................................................................ 1-14
Reset.............................................................................................................. 1-14
MCF5282-Specific Features ............................................................................. 1-15
Fast Ethernet Controller (FEC)..................................................................... 1-15
FlexCAN....................................................................................................... 1-15
I2C Bus.......................................................................................................... 1-15
Queued Serial Peripheral Interface (QSPI)................................................... 1-15
Queued Analog-to-Digital Converter (QADC) ............................................ 1-15

Chapter 2
ColdFire Core
2.1
2.2
2.2.1
2.2.2
2.2.3

MOTOROLA

Processor Pipelines .............................................................................................
Processor Register Description ...........................................................................
User Programming Model ..............................................................................
EMAC Programming Model .........................................................................
Supervisor Programming Model.....................................................................

Contents

2-1
2-2
2-2
2-5
2-5

v

CONTENTS
Paragraph
Number
2.3
2.4
2.5
2.6
2.7
2.7.1
2.7.2
2.7.3
2.7.4
2.7.5
2.7.6
2.7.7
2.7.8
2.7.9
2.7.10
2.7.11
2.7.12
2.7.13
2.7.14
2.8
2.8.1
2.8.2
2.9
2.10
2.11
2.12
2.13
2.14

Page
Number
Programming Model ........................................................................................... 2-8
Additions to the Instruction Set Architecture ..................................................... 2-9
Exception Processing Overview ....................................................................... 2-10
Exception Stack Frame Definition.................................................................... 2-12
Processor Exceptions ........................................................................................ 2-13
Access Error Exception ................................................................................ 2-13
Address Error Exception............................................................................... 2-14
Illegal Instruction Exception......................................................................... 2-14
Divide-By-Zero............................................................................................. 2-14
Privilege Violation........................................................................................ 2-14
Trace Exception ............................................................................................ 2-14
Unimplemented Line-A Opcode................................................................... 2-15
Unimplemented Line-F Opcode ................................................................... 2-15
Debug Interrupt............................................................................................. 2-15
RTE and Format Error Exception................................................................. 2-16
TRAP Instruction Exception......................................................................... 2-16
Interrupt Exception ....................................................................................... 2-16
Fault-on-Fault Halt ....................................................................................... 2-16
Reset Exception ............................................................................................ 2-16
Instruction Execution Timing ........................................................................... 2-21
Timing Assumptions..................................................................................... 2-21
MOVE Instruction Execution Times ............................................................ 2-22
Standard One Operand Instruction Execution Times ....................................... 2-24
Standard Two Operand Instruction Execution Times....................................... 2-24
Miscellaneous Instruction Execution Times..................................................... 2-26
EMAC Instruction Execution Times ................................................................ 2-27
Branch Instruction Execution Times ................................................................ 2-28
ColdFire Instruction Set Architecture Enhancements ...................................... 2-28
Title

Chapter 3
Enhanced Multiply-Accumulate Unit (EMAC)
3.1
3.2
3.3
3.4
3.4.1
3.4.2
3.5
3.5.1
3.5.2
3.5.3

vi

Multiply-Accumulate Unit.................................................................................. 3-1
Introduction to the MAC..................................................................................... 3-2
General Operation............................................................................................... 3-3
Memory Map/Register Set.................................................................................. 3-6
MAC Status Register (MACSR) .................................................................... 3-6
Mask Register (MASK) ................................................................................ 3-11
EMAC Instruction Set Summary ...................................................................... 3-12
EMAC Instruction Execution Times ............................................................ 3-12
Data Representation...................................................................................... 3-13
MAC Opcodes .............................................................................................. 3-14

MCF5282 User’s Manual

MOTOROLA

CONTENTS
Paragraph
Number

Title

Page
Number

Chapter 4
Cache
4.1
4.2
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.4
4.4.1
4.4.2

Cache Features ....................................................................................................
Cache Physical Organization ..............................................................................
Cache Operation .................................................................................................
Interaction with Other Modules......................................................................
Memory Reference Attributes ........................................................................
Cache Coherency and Invalidation .................................................................
Reset................................................................................................................
Cache Miss Fetch Algorithm/Line Fills .........................................................
Cache Programming Model ................................................................................
Cache Registers Memory Map .......................................................................
Cache Registers...............................................................................................

4-1
4-1
4-3
4-3
4-4
4-4
4-5
4-5
4-7
4-7
4-7

Chapter 5
Static RAM (SRAM)
5.1
5.2
5.3
5.3.1
5.3.2
5.3.3
5.3.4

SRAM Features...................................................................................................
SRAM Operation ................................................................................................
SRAM Programming Model...............................................................................
SRAM Base Address Register (RAMBAR)...................................................
SRAM Initialization........................................................................................
SRAM Initialization Code ..............................................................................
Power Management ........................................................................................

5-1
5-1
5-1
5-2
5-3
5-4
5-4

Chapter 6
ColdFire Flash Module (CFM)
6.1
6.2
6.3
6.3.1
6.3.2
6.3.3
6.3.4
6.4
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5

MOTOROLA

Features ............................................................................................................... 6-1
Block Diagram .................................................................................................... 6-2
Memory Map ...................................................................................................... 6-4
CFM Configuration Field ............................................................................... 6-5
Flash Base Address Register (FLASHBAR) .................................................. 6-5
CFM Registers ................................................................................................ 6-8
Register Descriptions...................................................................................... 6-9
CFM Operation ................................................................................................. 6-17
Read Operations............................................................................................ 6-17
Write Operations........................................................................................... 6-17
Program and Erase Operations ..................................................................... 6-17
Stop Mode..................................................................................................... 6-22
Master Mode ................................................................................................. 6-23

Contents

vii

CONTENTS
Paragraph
Number
6.5
6.5.1
6.5.2
6.6
6.7

Page
Number
Flash Security Operation .................................................................................. 6-23
Back Door Access......................................................................................... 6-24
Erase Verify Check....................................................................................... 6-24
Reset.................................................................................................................. 6-24
Interrupts ........................................................................................................... 6-25
Title

Chapter 7
Power Management
7.1
7.2
7.2.1
7.2.2
7.2.3
7.3
7.3.1
7.3.2
7.3.3

Features ............................................................................................................... 7-1
Memory Map and Registers................................................................................ 7-1
Programming Model ....................................................................................... 7-1
Memory Map .................................................................................................. 7-2
Register Descriptions...................................................................................... 7-2
Functional Description........................................................................................ 7-5
Low-Power Modes.......................................................................................... 7-5
Peripheral Behavior in Low-Power Modes .................................................... 7-7
Summary of Peripheral State During Low-Power Modes ............................ 7-16

Chapter 8
System Control Module (SCM)
8.1
8.2
8.3
8.4
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
8.5
8.5.1
8.5.2
8.5.3
8.6
8.6.1
8.6.2
8.6.3

viii

Overview............................................................................................................. 8-1
Features ............................................................................................................... 8-1
Memory Map and Register Definition................................................................ 8-2
Register Descriptions .......................................................................................... 8-3
Internal Peripheral System Base Address Register (IPSBAR)....................... 8-3
Memory Base Address Register (RAMBAR) ................................................ 8-4
Core Reset Status Register (CRSR)................................................................ 8-6
Core Watchdog Control Register (CWCR) .................................................... 8-6
Core Watchdog Service Register (CWSR)..................................................... 8-9
Internal Bus Arbitration ...................................................................................... 8-9
Overview....................................................................................................... 8-11
Arbitration Algorithms ................................................................................. 8-11
Bus Master Park Register (MPARK)............................................................ 8-12
System Access Control Unit (SACU)............................................................... 8-14
Overview....................................................................................................... 8-14
Features......................................................................................................... 8-14
Memory Map/Register Definition ................................................................ 8-15

MCF5282 User’s Manual

MOTOROLA

CONTENTS
Paragraph
Number

Title

Page
Number

Chapter 9
Clock Module
9.1
9.2
9.2.1
9.2.2
9.2.3
9.3
9.4
9.5
9.5.1
9.5.2
9.5.3
9.5.4
9.5.5
9.6
9.6.1
9.6.2
9.7
9.7.1
9.7.2
9.7.3
9.7.4

Features ............................................................................................................... 9-1
Modes of Operation ............................................................................................ 9-1
Normal PLL Mode.......................................................................................... 9-1
1:1 PLL Mode................................................................................................. 9-2
External Clock Mode ...................................................................................... 9-2
Low-power Mode Operation .............................................................................. 9-2
Block Diagram .................................................................................................... 9-3
Signal Descriptions ............................................................................................. 9-4
EXTAL ........................................................................................................... 9-4
XTAL.............................................................................................................. 9-5
CLKOUT ........................................................................................................ 9-5
CLKMOD[1:0] ............................................................................................... 9-5
RSTOUT......................................................................................................... 9-5
Memory Map and Registers................................................................................ 9-5
Module Memory Map..................................................................................... 9-5
Register Descriptions...................................................................................... 9-6
Functional Description...................................................................................... 9-10
System Clock Modes .................................................................................... 9-10
Clock Operation During Reset...................................................................... 9-11
System Clock Generation ............................................................................. 9-11
PLL Operation .............................................................................................. 9-12

Chapter 10
Interrupt Controller Modules
10.1
10.1.1
10.2
10.3
10.3.1
10.3.2
10.3.3
10.3.4
10.3.5
10.3.6
10.3.7
10.4
10.5

MOTOROLA

68K/ColdFire Interrupt Architecture Overview ............................................... 10-1
Interrupt Controller Theory of Operation ..................................................... 10-3
Memory Map .................................................................................................... 10-5
Register Descriptions ........................................................................................ 10-6
Interrupt Pending Registers (IPRHn, IPRLn) ............................................... 10-6
Interrupt Mask Register (IMRHn, IMRLn) .................................................. 10-8
Interrupt Force Registers (INTFRCHn, INTFRCLn) ................................... 10-9
Interrupt Request Level Register (IRLRn) ................................................. 10-10
Interrupt Acknowledge Level and Priority Register (IACKLPRn) ............ 10-11
Interrupt Control Register (ICRnx, (x = 1, 2,..., 63)).................................. 10-11
Software and Level n IACK Registers (SWIACKR, L1IACK–L7IACK). 10-15
Prioritization Between Interrupt Controllers .................................................. 10-16
Low-Power Wakeup Operation ...................................................................... 10-17

Contents

ix

CONTENTS
Paragraph
Number

Title

Page
Number

Chapter 11
Edge Port Module (EPORT)
11.1
11.2
11.3
11.4
11.4.1
11.4.2

Introduction.......................................................................................................
Low-Power Mode Operation ............................................................................
Interrupt/General-Purpose I/O Pin Descriptions...............................................
Memory Map and Registers..............................................................................
Memory Map ................................................................................................
Registers........................................................................................................

11-1
11-1
11-2
11-3
11-3
11-3

Chapter 12
Chip Select Module
12.1
12.2
12.3
12.3.1
12.4
12.4.1

Overview...........................................................................................................
Chip Select Module Signals..............................................................................
Chip Select Operation .......................................................................................
General Chip Select Operation .....................................................................
Chip Select Registers ........................................................................................
Chip Select Module Registers.......................................................................

12-1
12-1
12-3
12-3
12-5
12-6

Chapter 13
External Interface Module (EIM)
13.1
13.2
13.3
13.4
13.4.1
13.4.2
13.4.3
13.4.4
13.4.5
13.4.6
13.4.7
13.5

Features ............................................................................................................. 13-1
Bus and Control Signals ................................................................................... 13-1
Bus Characteristics ........................................................................................... 13-2
Data Transfer Operation ................................................................................... 13-2
Bus Cycle Execution..................................................................................... 13-3
Data Transfer Cycle States ........................................................................... 13-5
Read Cycle.................................................................................................... 13-6
Write Cycle ................................................................................................... 13-8
Fast Termination Cycles ............................................................................... 13-9
Back-to-Back Bus Cycles ........................................................................... 13-10
Burst Cycles................................................................................................ 13-10
Misaligned Operands ...................................................................................... 13-14

Chapter 14
Signal Descriptions
14.1
14.1.1
14.1.2

x

Overview........................................................................................................... 14-1
Single-Chip Mode....................................................................................... 14-17
External Boot Mode.................................................................................... 14-17

MCF5282 User’s Manual

MOTOROLA

CONTENTS
Paragraph
Number
14.2
14.2.1
14.2.2
14.2.3
14.2.4
14.2.5
14.2.6
14.2.7
14.2.8
14.2.9
14.2.10
14.2.11
14.2.12
14.2.13
14.2.14
14.2.15
14.2.16

Title

Page
Number

MCF5282 External Signals.............................................................................
External Interface Module (EIM) Signals ..................................................
SDRAM Controller Signals ........................................................................
Clock and Reset Signals .............................................................................
Chip Configuration Signals ........................................................................
External Interrupt Signals ...........................................................................
Ethernet Module Signals.............................................................................
Queued Serial Peripheral Interface (QSPI) Signals....................................
FlexCAN Signals ........................................................................................
I2C Signals ..................................................................................................
UART Module Signals ...............................................................................
General Purpose Timer Signals ..................................................................
DMA Timer Signals....................................................................................
Analog-to-Digital Converter Signals ..........................................................
Debug Support Signals ...............................................................................
Test Signals.................................................................................................
Power and Reference Signals .....................................................................

14-18
14-18
14-21
14-22
14-22
14-23
14-23
14-25
14-26
14-26
14-26
14-27
14-28
14-29
14-30
14-32
14-33

Chapter 15
Synchronous DRAM Controller Module
15.1
15.1.1
15.1.2
15.2
15.2.1
15.2.2
15.2.3
15.2.4
15.3
15.3.1
15.3.2
15.3.3
15.3.4
15.3.5
15.3.6

Overview........................................................................................................... 15-1
Definitions .................................................................................................... 15-1
Block Diagram and Major Components ....................................................... 15-2
SDRAM Controller Operation.......................................................................... 15-3
DRAM Controller Signals ............................................................................ 15-4
Memory Map for SDRAMC Registers......................................................... 15-4
General Synchronous Operation Guidelines................................................. 15-9
Initialization Sequence................................................................................ 15-17
SDRAM Example ........................................................................................... 15-19
SDRAM Interface Configuration................................................................ 15-20
DCR Initialization....................................................................................... 15-20
DACR Initialization.................................................................................... 15-21
DMR Initialization...................................................................................... 15-22
Mode Register Initialization ....................................................................... 15-23
Initialization Code....................................................................................... 15-24

Chapter 16
DMA Controller Module
16.1
16.1.1

MOTOROLA

Overview........................................................................................................... 16-1
DMA Module Features ................................................................................. 16-2

Contents

xi

CONTENTS
Paragraph
Number
16.2
16.3
16.4
16.4.1
16.4.2
16.4.3
16.4.4
16.4.5
16.5
16.5.1
16.5.2
16.5.3
16.5.4
16.5.5

Page
Number
DMA Request Control (DMAREQC) .............................................................. 16-3
DMA Transfer Overview.................................................................................. 16-4
DMA Controller Module Programming Model................................................ 16-5
Source Address Registers (SAR0–SAR3) .................................................... 16-6
Destination Address Registers (DAR0–DAR3) ........................................... 16-6
Byte Count Registers (BCR0–BCR3) .......................................................... 16-7
DMA Control Registers (DCR0–DCR3)...................................................... 16-8
DMA Status Registers (DSR0–DSR3) ....................................................... 16-10
DMA Controller Module Functional Description .......................................... 16-11
Transfer Requests (Cycle-Steal and Continuous Modes) ........................... 16-11
Data Transfer Modes .................................................................................. 16-12
Channel Initialization and Startup .............................................................. 16-13
Data Transfer .............................................................................................. 16-14
Termination................................................................................................. 16-15
Title

Chapter 17
Fast Ethernet Controller (FEC)
17.1
17.1.1
17.2
17.2.1
17.2.2
17.2.3
17.2.4
17.3
17.4
17.4.1
17.4.2
17.4.3
17.4.4
17.4.5
17.4.6
17.4.7
17.4.8
17.4.9
17.4.10
17.4.11
17.4.12
17.4.13
17.4.14
17.5

xii

Overview........................................................................................................... 17-1
Features......................................................................................................... 17-1
Modes of Operation .......................................................................................... 17-2
Full and Half Duplex Operation ................................................................... 17-2
Interface Options........................................................................................... 17-2
Address Recognition Options ....................................................................... 17-3
Internal Loopback ......................................................................................... 17-3
FEC Top-Level Functional Diagram ................................................................ 17-4
Functional Description...................................................................................... 17-5
Initialization Sequence.................................................................................. 17-6
User Initialization (Prior to Asserting ECR[ETHER_EN]).......................... 17-6
Microcontroller Initialization........................................................................ 17-7
User Initialization (After Asserting ECR[ETHER_EN]) ............................. 17-7
Network Interface Options............................................................................ 17-8
FEC Frame Transmission ............................................................................. 17-9
FEC Frame Reception................................................................................. 17-10
Ethernet Address Recognition .................................................................... 17-11
Hash Algorithm........................................................................................... 17-13
Full Duplex Flow Control........................................................................... 17-16
Inter-Packet Gap (IPG) Time...................................................................... 17-17
Collision Handling...................................................................................... 17-17
Internal and External Loopback.................................................................. 17-17
Ethernet Error-Handling Procedure ............................................................ 17-18
Programming Model ....................................................................................... 17-20

MCF5282 User’s Manual

MOTOROLA

CONTENTS
Paragraph
Number
17.5.1
17.5.2
17.5.3
17.5.4
17.6
17.6.1
17.6.2
17.6.3

Title

Page
Number

Top Level Module Memory Map ...............................................................
Detailed Memory Map (Control/Status Registers) .....................................
MIB Block Counters Memory Map............................................................
Registers......................................................................................................
Buffer Descriptors...........................................................................................
Driver/DMA Operation with Buffer Descriptors........................................
Ethernet Receive Buffer Descriptor (RxBD)..............................................
Ethernet Transmit Buffer Descriptor (TxBD) ............................................

17-20
17-20
17-21
17-23
17-45
17-45
17-47
17-49

Chapter 18
Watchdog Timer Module
18.1
18.2
18.3
18.4
18.5
18.5.1
18.5.2

Introduction.......................................................................................................
Low-Power Mode Operation ............................................................................
Block Diagram ..................................................................................................
Signals...............................................................................................................
Memory Map and Registers..............................................................................
Memory Map ................................................................................................
Registers........................................................................................................

18-1
18-1
18-2
18-2
18-2
18-2
18-3

Chapter 19
Programmable Interrupt Timer Modules (PIT0–PIT3)
19.1
19.2
19.3
19.4
19.5
19.5.1
19.5.2
19.6
19.6.1
19.6.2
19.6.3
19.7

Overview...........................................................................................................
Block Diagram ..................................................................................................
Low-Power Mode Operation ............................................................................
Signals...............................................................................................................
Memory Map and Registers..............................................................................
Memory Map ................................................................................................
Registers........................................................................................................
Functional Description......................................................................................
Set-and-Forget Timer Operation...................................................................
Free-Running Timer Operation ....................................................................
Timeout Specifications .................................................................................
Interrupt Operation ...........................................................................................

19-1
19-1
19-2
19-2
19-3
19-3
19-3
19-6
19-6
19-7
19-7
19-8

Chapter 20
General Purpose Timer Modules
(GPTA and GPTB)
20.1
20.2
MOTOROLA

Features ............................................................................................................. 20-1
Block Diagram .................................................................................................. 20-2
Contents

xiii

CONTENTS
Paragraph
Number
20.3
20.4
20.4.1
20.4.2
20.4.3
20.5
20.5.1
20.5.2
20.5.3
20.5.4
20.5.5
20.5.6
20.5.7
20.5.8
20.5.9
20.5.10
20.5.11
20.5.12
20.5.13
20.5.14
20.5.15
20.5.16
20.5.17
20.5.18
20.5.19
20.6
20.6.1
20.6.2
20.6.3
20.6.4
20.6.5
20.6.6
20.6.7
20.7
20.8
20.8.1
20.8.2
20.8.3
20.8.4

xiv

Page
Number
Low-Power Mode Operation ............................................................................ 20-3
Signal Description............................................................................................. 20-3
GPTn[2:0] ..................................................................................................... 20-3
GPTn3........................................................................................................... 20-4
SYNCn.......................................................................................................... 20-4
Memory Map and Registers.............................................................................. 20-4
GPT Input Capture/Output Compare Select Register (GPTIOS) ................. 20-5
GPT Compare Force Register (GPCFORC)................................................. 20-6
GPT Output Compare 3 Mask Register (GPTOC3M).................................. 20-6
GPT Output Compare 3 Data Register (GPTOC3D).................................... 20-7
GPT Counter Register (GPTCNT) ............................................................... 20-7
GPT System Control Register 1 (GPTSCR1)............................................... 20-8
GPT Toggle-On-Overflow Register (GPTTOV).......................................... 20-9
GPT Control Register 1 (GPTCTL1)............................................................ 20-9
GPT Control Register 2 (GPTCTL2).......................................................... 20-10
GPT Interrupt Enable Register (GPTIE) .................................................... 20-10
GPT System Control Register 2 (GPTSCR2)............................................. 20-11
GPT Flag Register 1 (GPTFLG1)............................................................... 20-12
GPT Flag Register 2 (GPTFLG2)............................................................... 20-12
GPT Channel Registers (GPTCn)............................................................... 20-13
Pulse Accumulator Control Register (GPTPACTL) .................................. 20-13
Pulse Accumulator Flag Register (GPTPAFLG)........................................ 20-14
Pulse Accumulator Counter Register (GPTPACNT) ................................. 20-15
GPT Port Data Register (GPTPORT)......................................................... 20-16
GPT Port Data Direction Register (GPTDDR)........................................... 20-16
Functional Description.................................................................................... 20-17
Prescaler...................................................................................................... 20-17
Input Capture .............................................................................................. 20-17
Output Compare.......................................................................................... 20-17
Pulse Accumulator...................................................................................... 20-18
Event Counter Mode................................................................................... 20-18
Gated Time Accumulation Mode ............................................................... 20-19
General-Purpose I/O Ports .......................................................................... 20-19
Reset................................................................................................................ 20-21
Interrupts ......................................................................................................... 20-21
GPT Channel Interrupts (CnF) ................................................................... 20-22
Pulse Accumulator Overflow (PAOVF)..................................................... 20-22
Pulse Accumulator Input (PAIF) ................................................................ 20-22
Timer Overflow (TOF) ............................................................................... 20-22
Title

MCF5282 User’s Manual

MOTOROLA

CONTENTS
Paragraph
Number

Title

Page
Number

Chapter 21
DMA Timers (DTIM0–DTIM3)
21.1
21.1.1
21.2
21.2.1
21.2.2
21.2.3
21.2.4
21.2.5
21.2.6
21.2.7
21.2.8
21.2.9
21.2.10
21.2.11
21.3
21.3.1
21.3.2

Overview........................................................................................................... 21-1
Key Features ................................................................................................. 21-2
DMA Timer Programming Model .................................................................... 21-2
Prescaler........................................................................................................ 21-2
Capture Mode ............................................................................................... 21-3
Reference Compare....................................................................................... 21-3
Output Mode ................................................................................................. 21-3
Memory Map ................................................................................................ 21-3
DMA Timer Mode Registers (DTMRn)....................................................... 21-4
DMA Timer Extended Mode Registers (DTXMRn).................................... 21-5
DMA Timer Event Registers (DTERn) ........................................................ 21-6
DMA Timer Reference Registers (DTRRn)................................................. 21-7
DMA Timer Capture Registers (DTCRn) .................................................... 21-7
DMA Timer Counters (DTCNn) .................................................................. 21-8
Using the DMA Timer Modules ....................................................................... 21-8
Code Example............................................................................................... 21-9
Calculating Time-Out Values ..................................................................... 21-10

Chapter 22
Queued Serial Peripheral Interface
(QSPI) Module
22.1
22.2
22.3
22.3.1
22.3.2
22.4
22.4.1
22.4.2
22.4.3
22.4.4
22.4.5
22.5
22.5.1
22.5.2
22.5.3
22.5.4
22.5.5

MOTOROLA

Overview........................................................................................................... 22-1
Features ............................................................................................................. 22-1
Module Description .......................................................................................... 22-1
Interface and Signals..................................................................................... 22-2
Internal Bus Interface.................................................................................... 22-3
Operation .......................................................................................................... 22-3
QSPI RAM.................................................................................................... 22-4
Baud Rate Selection...................................................................................... 22-6
Transfer Delays............................................................................................. 22-7
Transfer Length............................................................................................. 22-8
Data Transfer ................................................................................................ 22-8
Programming Model ......................................................................................... 22-9
QSPI Mode Register (QMR) ...................................................................... 22-10
QSPI Delay Register (QDLYR) ................................................................. 22-11
QSPI Wrap Register (QWR)....................................................................... 22-12
QSPI Interrupt Register (QIR).................................................................... 22-13
QSPI Address Register (QAR) ................................................................... 22-14

Contents

xv

CONTENTS
Paragraph
Number
22.5.6
22.5.7
22.5.8

Page
Number
QSPI Data Register (QDR)......................................................................... 22-14
Command RAM Registers (QCR0–QCR15).............................................. 22-15
Programming Example ............................................................................... 22-16
Title

Chapter 23
UART Modules
23.1
23.2
23.3
23.3.1
23.3.2
23.3.3
23.3.4
23.3.5
23.3.6
23.3.7
23.3.8
23.3.9
23.3.10
23.3.11
23.3.12
23.3.13
23.4
23.5
23.5.1
23.5.2
23.5.3
23.5.4
23.5.5
23.5.6

Overview........................................................................................................... 23-1
Serial Module Overview ................................................................................... 23-2
Register Descriptions ........................................................................................ 23-3
UART Mode Registers 1 (UMR1n).............................................................. 23-4
UART Mode Register 2 (UMR2n) ............................................................... 23-6
UART Status Registers (USRn) ................................................................... 23-7
UART Clock Select Registers (UCSRn) ...................................................... 23-8
UART Command Registers (UCRn) ............................................................ 23-9
UART Receive Buffers (URBn)................................................................. 23-11
UART Transmit Buffers (UTBn) ............................................................... 23-11
UART Input Port Change Registers (UIPCRn).......................................... 23-12
UART Auxiliary Control Register (UACRn)............................................. 23-13
UART Interrupt Status/Mask Registers (UISRn/UIMRn).......................... 23-13
UART Baud Rate Generator Registers (UBG1n/UBG2n) ......................... 23-14
UART Input Port Register (UIPn) .............................................................. 23-15
UART Output Port Command Registers (UOP1n/UOP0n) ....................... 23-15
UART Module Signal Definitions .................................................................. 23-17
Operation ........................................................................................................ 23-18
Transmitter/Receiver Clock Source............................................................ 23-18
Transmitter and Receiver Operating Modes............................................... 23-20
Looping Modes ........................................................................................... 23-25
Multidrop Mode.......................................................................................... 23-26
Bus Operation ............................................................................................. 23-28
Programming .............................................................................................. 23-28

Chapter 24
Interface

I2C
24.1
24.2
24.3
24.4
24.4.1
24.4.2
24.4.3

xvi

Overview...........................................................................................................
Interface Features..............................................................................................
I2C System Configuration.................................................................................
I2C Protocol ......................................................................................................
Arbitration Procedure ...................................................................................
Clock Synchronization..................................................................................
Handshaking .................................................................................................

MCF5282 User’s Manual

24-1
24-1
24-3
24-3
24-4
24-5
24-5

MOTOROLA

CONTENTS
Paragraph
Number
24.4.4
24.5
24.5.1
24.5.2
24.5.3
24.5.4
24.5.5
24.6
24.6.1
24.6.2
24.6.3
24.6.4
24.6.5
24.6.6
24.6.7

Title

Page
Number

Clock Stretching ........................................................................................... 24-5
Programming Model ......................................................................................... 24-6
I2C Address Register (I2ADR) ..................................................................... 24-6
I2C Frequency Divider Register (I2FDR)..................................................... 24-7
I2C Control Register (I2CR)......................................................................... 24-8
I2C Status Register (I2SR)............................................................................ 24-9
I2C Data I/O Register (I2DR) ..................................................................... 24-10
2
I C Programming Examples ........................................................................... 24-10
Initialization Sequence................................................................................ 24-10
Generation of START................................................................................. 24-11
Post-Transfer Software Response............................................................... 24-11
Generation of STOP.................................................................................... 24-12
Generation of Repeated START................................................................. 24-13
Slave Mode ................................................................................................. 24-13
Arbitration Lost........................................................................................... 24-14

Chapter 25
FlexCAN
25.1
25.1.1
25.1.2
25.2
25.3
25.3.1
25.3.2
25.4
25.4.1
25.4.2
25.4.3
25.4.4
25.4.5
25.4.6
25.4.7
25.4.8
25.4.9
25.4.10
25.4.11
25.4.12
25.5
25.5.1
25.5.2

MOTOROLA

Features ............................................................................................................. 25-1
FlexCAN Memory Map................................................................................ 25-3
External Signals ............................................................................................ 25-3
The CAN System .............................................................................................. 25-4
Message Buffers ............................................................................................... 25-4
Message Buffer Structure ............................................................................. 25-4
Message Buffer Memory Map...................................................................... 25-7
Functional Overview......................................................................................... 25-8
Transmit Process........................................................................................... 25-9
Receive Process ............................................................................................ 25-9
Message Buffer Handling ........................................................................... 25-10
Remote Frames ........................................................................................... 25-12
Overload Frames......................................................................................... 25-13
Time Stamp................................................................................................. 25-13
Listen-Only Mode....................................................................................... 25-13
Bit Timing................................................................................................... 25-14
FlexCAN Error Counters ............................................................................ 25-15
FlexCAN Initialization Sequence ............................................................... 25-16
Special Operating Modes............................................................................ 25-17
Interrupts..................................................................................................... 25-19
Programmer’s Model ...................................................................................... 25-20
CAN Module Configuration Register (CANMCR).................................... 25-20
FlexCAN Control Register 0 (CANCTRL0) .............................................. 25-22

Contents

xvii

CONTENTS
Paragraph
Number
25.5.3
25.5.4
25.5.5
25.5.6
25.5.7
25.5.8
25.5.9
25.5.10
25.5.11
25.5.12

Page
Number
FlexCAN Control Register 1 (CANCTRL1) .............................................. 25-23
Prescaler Divide Register (PRESDIV) ....................................................... 25-24
FlexCAN Control Register 2 (CANCTRL2) .............................................. 25-25
Free Running Timer (TIMER).................................................................... 25-26
Rx Mask Registers ...................................................................................... 25-26
FlexCAN Error and Status Register (ESTAT) ........................................... 25-28
Interrupt Mask Register (IMASK).............................................................. 25-30
Interrupt Flag Register (IFLAG)................................................................. 25-31
FlexCAN Receive Error Counter (RXECTR) ............................................ 25-32
FlexCAN Transmit Error Counter (TXECTR)........................................... 25-32
Title

Chapter 26
General Purpose I/O Module
26.1
26.1.1
26.1.2
26.1.3
26.2
26.3
26.3.1
26.3.2
26.4
26.4.1
26.4.2
26.5

Introduction....................................................................................................... 26-1
Overview....................................................................................................... 26-3
Features......................................................................................................... 26-3
Modes of Operation ...................................................................................... 26-3
External Signal Description .............................................................................. 26-4
Memory Map/Register Definition .................................................................... 26-6
Register Overview ........................................................................................ 26-6
Register Descriptions.................................................................................... 26-8
Functional Description.................................................................................... 26-25
Overview..................................................................................................... 26-25
Port Digital I/O Timing .............................................................................. 26-25
Initialization/Application Information ............................................................ 26-26

Chapter 27
Queued Analog-to-Digital Converter (QADC)
27.1
27.2
27.3
27.3.1
27.3.2
27.4
27.4.1
27.4.2
27.4.3
27.4.4
27.4.5
27.4.6

xviii

Features .............................................................................................................
Block Diagram ..................................................................................................
Modes of Operation ..........................................................................................
Debug Mode .................................................................................................
Stop Mode.....................................................................................................
Signals...............................................................................................................
Port QA Signal Functions .............................................................................
Port QB Signal Functions .............................................................................
External Trigger Input Signals......................................................................
Multiplexed Address Output Signals............................................................
Multiplexed Analog Input Signals................................................................
Voltage Reference Signals............................................................................

MCF5282 User’s Manual

27-1
27-2
27-3
27-3
27-3
27-4
27-4
27-5
27-6
27-6
27-6
27-7

MOTOROLA

CONTENTS
Paragraph
Number
27.4.7
27.4.8
27.5
27.6
27.6.1
27.6.2
27.6.3
27.6.4
27.6.5
27.6.6
27.6.7
27.6.8
27.7
27.7.1
27.7.2
27.7.3
27.8
27.8.1
27.8.2
27.8.3
27.8.4
27.8.5
27.8.6
27.8.7
27.8.8
27.8.9
27.8.10
27.8.11
27.9
27.9.1
27.9.2
27.9.3
27.9.4
27.9.5
27.9.6
27.9.7
27.10
27.10.1
27.10.2

MOTOROLA

Title

Page
Number

Dedicated Analog Supply Signals ................................................................ 27-7
Dedicated Digital I/O Port Supply Signal..................................................... 27-7
Memory Map .................................................................................................... 27-7
Register Descriptions ........................................................................................ 27-8
QADC Module Configuration Register (QADCMCR) ................................ 27-8
QADC Test Register (QADCTEST) ............................................................ 27-9
Port Data Registers (PORTQA and PORTQB) ............................................ 27-9
Port QA and QB Data Direction Register (DDRQA and DDRQB) ........... 27-10
Control Registers ........................................................................................ 27-11
Status Registers........................................................................................... 27-19
Conversion Command Word Table (CCW) ............................................... 27-26
Result Registers .......................................................................................... 27-29
Functional Description.................................................................................... 27-31
Result Coherency........................................................................................ 27-31
External Multiplexing ................................................................................. 27-31
Analog Subsystem ...................................................................................... 27-34
Digital Control Subsystem.............................................................................. 27-37
Queue Priority Timing Examples ............................................................... 27-38
Boundary Conditions .................................................................................. 27-49
Scan Modes................................................................................................. 27-50
Disabled Mode............................................................................................ 27-50
Reserved Mode ........................................................................................... 27-50
Single-Scan Modes ..................................................................................... 27-50
Continuous-Scan Modes ............................................................................. 27-54
QADC Clock (QCLK) Generation ............................................................. 27-57
Periodic/Interval Timer............................................................................... 27-58
Conversion Command Word Table ............................................................ 27-59
Result Word Table ...................................................................................... 27-62
Signal Connection Considerations.................................................................. 27-62
Analog Reference Signals........................................................................... 27-63
Analog Power Signals................................................................................. 27-63
Conversion Timing Schemes ...................................................................... 27-64
Analog Supply Filtering and Grounding .................................................... 27-67
Accommodating Positive/Negative Stress Conditions ............................... 27-69
Analog Input Considerations ...................................................................... 27-71
Analog Input Pins ....................................................................................... 27-73
Interrupts ......................................................................................................... 27-75
Interrupt Operation ..................................................................................... 27-75
Interrupt Sources......................................................................................... 27-76

Contents

xix

CONTENTS
Paragraph
Number

Title

Page
Number

Chapter 28
Reset Controller Module
28.1
28.2
28.3
28.3.1
28.3.2
28.4
28.4.1
28.4.2
28.5
28.5.1
28.5.2
28.5.3

Features ............................................................................................................. 28-1
Block Diagram .................................................................................................. 28-2
Signals............................................................................................................... 28-2
RSTI............................................................................................................. 28-2
RSTO ........................................................................................................... 28-2
Memory Map and Registers.............................................................................. 28-3
Reset Control Register (RCR) ...................................................................... 28-3
Reset Status Register (RSR) ......................................................................... 28-4
Functional Description...................................................................................... 28-6
Reset Sources................................................................................................ 28-6
Reset Control Flow ....................................................................................... 28-8
Concurrent Resets ....................................................................................... 28-10

Chapter 29
Debug Support
29.1
29.2
29.3
29.3.1
29.4
29.4.1
29.4.2
29.4.3
29.4.4
29.4.5
29.4.6
29.4.7
29.5
29.5.1
29.5.2
29.5.3
29.6
29.6.1
29.6.2
29.7
29.7.1
29.7.2
29.8

xx

Overview........................................................................................................... 29-1
Signal Description............................................................................................. 29-2
Real-Time Trace Support.................................................................................. 29-3
Begin Execution of Taken Branch (PST = 0x5) ........................................... 29-4
Programming Model ......................................................................................... 29-5
Revision A Shared Debug Resources ........................................................... 29-7
Address Attribute Trigger Register (AATR) ................................................ 29-8
Address Breakpoint Registers (ABLR, ABHR) ........................................... 29-9
Configuration/Status Register (CSR) ......................................................... 29-10
Data Breakpoint/Mask Registers (DBR, DBMR)....................................... 29-12
Program Counter Breakpoint/Mask Registers (PBR, PBMR).................... 29-13
Trigger Definition Register (TDR) ............................................................. 29-14
Background Debug Mode (BDM) .................................................................. 29-16
CPU Halt..................................................................................................... 29-16
BDM Serial Interface.................................................................................. 29-18
BDM Command Set ................................................................................... 29-20
Real-Time Debug Support .............................................................................. 29-37
Theory of Operation.................................................................................... 29-37
Concurrent BDM and Processor Operation ................................................ 29-39
Processor Status, DDATA Definition............................................................. 29-40
User Instruction Set .................................................................................... 29-40
Supervisor Instruction Set........................................................................... 29-44
Motorola-Recommended BDM Pinout........................................................... 29-46

MCF5282 User’s Manual

MOTOROLA

CONTENTS
Paragraph
Number

Title

Page
Number

Chapter 30
Chip Configuration Module (CCM)
30.1
30.2
30.2.1
30.2.2
30.3
30.4
30.4.1
30.4.2
30.4.3
30.5
30.5.1
30.5.2
30.5.3
30.6
30.6.1
30.6.2
30.6.3
30.6.4
30.6.5
30.6.6
30.7
30.8

Features ............................................................................................................. 30-1
Modes of Operation .......................................................................................... 30-1
Master Mode ................................................................................................. 30-2
Single-Chip Mode......................................................................................... 30-2
Block Diagram .................................................................................................. 30-2
Signal Descriptions ........................................................................................... 30-3
RCON ........................................................................................................... 30-3
CLKMOD[1:0] ............................................................................................. 30-3
D[26:24, 21, 19:16] (Reset Configuration Override) ................................... 30-3
Memory Map and Registers.............................................................................. 30-3
Programming Model ..................................................................................... 30-3
Memory Map ................................................................................................ 30-4
Register Descriptions.................................................................................... 30-5
Functional Description...................................................................................... 30-8
Reset Configuration ...................................................................................... 30-8
Chip Mode Selection .................................................................................. 30-10
Boot Device Selection ................................................................................ 30-11
Output Pad Strength Configuration ............................................................ 30-11
Clock Mode Selection................................................................................. 30-11
Chip Select Configuration .......................................................................... 30-12
Reset................................................................................................................ 30-12
Interrupts ......................................................................................................... 30-12

Chapter 31
IEEE 1149.1 Test Access Port (JTAG)
31.1
31.2
31.3
31.3.1
31.4
31.4.1
31.4.2
31.5
31.5.1
31.5.2
31.5.3
31.6
31.6.1

MOTOROLA

Features ............................................................................................................. 31-2
Modes of Operation .......................................................................................... 31-3
External Signal Description .............................................................................. 31-3
Detailed Signal Description .......................................................................... 31-3
Memory Map/Register Definition .................................................................... 31-5
Memory Map ................................................................................................ 31-5
Register Descriptions.................................................................................... 31-5
Functional Description...................................................................................... 31-7
JTAG Module ............................................................................................... 31-7
TAP Controller ............................................................................................. 31-7
JTAG Instructions......................................................................................... 31-8
Initialization/Application Information ............................................................ 31-11
Restrictions ................................................................................................. 31-11

Contents

xxi

CONTENTS
Paragraph
Number
31.6.2

Page
Number
Nonscan Chain Operation........................................................................... 31-12
Title

Chapter 32
Mechanical Data
32.1
32.2

Pinout ................................................................................................................ 32-2
Ordering Information ........................................................................................ 32-7

Chapter 33
Electrical Characteristics
33.1
33.2
33.3
33.4
33.5
33.6
33.7
33.8
33.9
33.10
33.11
33.12
33.12.1
33.12.2
33.12.3
33.12.4
33.13
33.14
33.15
33.16

Maximum Ratings............................................................................................. 33-1
Thermal Characteristics .................................................................................... 33-3
DC Electrical Specifications ............................................................................. 33-4
Phase Lock Loop Electrical Specifications ...................................................... 33-6
QADC Electrical Characteristics ...................................................................... 33-7
Flash Memory Characteristics .......................................................................... 33-9
External Interface Timing Characteristics ...................................................... 33-10
Processor Bus Output Timing Specifications ................................................. 33-11
General Purpose I/O Timing........................................................................... 33-17
Reset and Configuration Override Timing ..................................................... 33-18
I2C Input/Output Timing Specifications......................................................... 33-19
Fast Ethernet AC Timing Specifications ........................................................ 33-20
MII Receive Signal Timing (ERXD[3:0], ERXDV, ERXER,
and ERXCLK) ........................................................................................ 33-21
MII Transmit Signal Timing (ETXD[3:0], ETXEN, ETXER, ETXCLK). 33-21
MII Async Inputs Signal Timing (ECRS and ECOL) ................................ 33-22
MII Serial Management Channel Timing (EMDIO and EMDC)............... 33-23
DMA Timer Module AC Timing Specifications ............................................ 33-24
QSPI Electrical Specifications........................................................................ 33-24
JTAG and Boundary Scan Timing.................................................................. 33-25
Debug AC Timing Specifications................................................................... 33-27

Appendix A
Register Memory Map

xxii

MCF5282 User’s Manual

MOTOROLA

ILLUSTRATIONS
Figure
Number

1-1
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
4-1
4-2
4-3
5-1
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13

Title

Page
Number

MCF5282 Block Diagram ............................................................................................ 1-7
ColdFire Processor Core Pipelines ............................................................................... 2-1
User Programming Model ............................................................................................ 2-4
Condition Code Register (CCR) ................................................................................... 2-4
EMAC Register Set ...................................................................................................... 2-5
Supervisor Programming Model................................................................................... 2-6
Status Register .............................................................................................................. 2-6
Exception Stack Frame Form ..................................................................................... 2-12
D0 Hardware Configuration Info................................................................................ 2-17
D1 Hardware Configuration Info................................................................................ 2-19
Multiply-Accumulate Functionality Diagram .............................................................. 3-2
Infinite Impulse Response (IIR) Filter.......................................................................... 3-3
Four-Tap FIR Filter ...................................................................................................... 3-3
Fractional Alignment .................................................................................................... 3-4
Signed and Unsigned Integer Alignment...................................................................... 3-4
EMAC Register Set ...................................................................................................... 3-6
MAC Status Register (MACSR)................................................................................... 3-6
EMAC-Specific OEP Sequence Stall ......................................................................... 3-13
Two’s Complement, Signed Fractional Equation....................................................... 3-14
Cache Block Diagram ................................................................................................... 4-3
Cache Control Register (CACR) .................................................................................. 4-8
Access Control Registers (ACR0, ACR1) .................................................................. 4-11
SRAM Base Address Register (RAMBAR) ................................................................. 5-2
CFM Block Diagram .................................................................................................... 6-3
CFM Array Memory Map............................................................................................. 6-4
Flash Base Address Register (FLASHBAR) ................................................................ 6-7
CFM Module Configuration Register (CFMCR) ......................................................... 6-9
CFM Clock Divider Register (CFMCLKD) ............................................................... 6-10
CFM Security Register (CFMSEC)............................................................................ 6-11
CFM Protection Register (CFMPROT) ...................................................................... 6-12
CFMPROT Protection Diagram ................................................................................. 6-13
CFM Supervisor Access Register (CFMSACC) ........................................................ 6-13
CFM Data Access Register (CFMDACC).................................................................. 6-14
CFM User Status Register (CFMUSTAT) ................................................................. 6-15
CFM Command Register (CFMCMD)....................................................................... 6-16
Example Program Algorithm...................................................................................... 6-21

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ILLUSTRATIONS
Figure
Number
7-1
7-2
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Low-Power Interrupt Control Register (LPICR) ......................................................... 7-3
Low-Power Control Register (LPCR) ......................................................................... 7-4
IPS Base Address Register (IPSBAR).......................................................................... 8-4
Memory Base Address Register (RAMBAR) .............................................................. 8-5
Core Reset Status Register (CRSR)............................................................................. 8-6
Core Watchdog Control Register (CWCR) ................................................................. 8-8
Core Watchdog Service Register (CWSR) .................................................................. 8-9
Arbiter Module Functions........................................................................................... 8-10
Default Bus Master Park Register (MPARK)............................................................. 8-12
Master Privilege Register (MPR) .............................................................................. 8-16
Peripheral Access Control Register (PACRn) ............................................................ 8-17
GPACR Register......................................................................................................... 8-18
Clock Module Block Diagram ...................................................................................... 9-3
PLL Block Diagram...................................................................................................... 9-4
Synthesizer Control Register (SYNCR) ....................................................................... 9-6
Synthesizer Status Register (SYNSR) .......................................................................... 9-8
Crystal Oscillator Example ......................................................................................... 9-12
Lock Detect Sequence ................................................................................................ 9-15
Interrupt Pending Register High (IPRHn) .................................................................. 10-7
Interrupt Pending Register Low (IPRLn) ................................................................... 10-7
Interrupt Mask Register High (IMRHn) ..................................................................... 10-8
Interrupt Mask Register Low (IMRLn) ...................................................................... 10-8
Interrupt Force Register High (INTFRCHn) .............................................................. 10-9
Interrupt Force Register Low (INTFRCLn) ............................................................. 10-10
Interrupt RequestLevel Register (IRLRn) ................................................................ 10-10
IACK Level and Priority Register (IACKLPRn) ..................................................... 10-11
Interrupt Control Register (ICRnx)........................................................................... 10-12
Software and Level n IACK Registers (SWIACKR, L1IACK–L7IACK) ............... 10-16
EPORT Block Diagram .............................................................................................. 11-1
EPORT Pin Assignment Register (EPPAR) ............................................................... 11-4
EPORT Data Direction Register (EPDDR) ................................................................ 11-4
EPORT Port Interrupt Enable Register (EPIER) ........................................................ 11-5
EPORT Port Data Register (EPDR) ........................................................................... 11-5
EPORT Port Pin Data Register (EPPDR)................................................................... 11-6
EPORT Port Flag Register (EPFR) ............................................................................ 11-6
Connections for External Memory Port Sizes ............................................................ 12-4
Chip Select Address Registers (CSARn)................................................................... 12-6
Chip Select Mask Registers (CSMRn) ...................................................................... 12-7
Chip Select Control Registers (CSCRn) ..................................................................... 12-8
Signal Relationship to CLKOUT for Non-DRAM Access ........................................ 13-2
Connections for External Memory Port Sizes ............................................................ 13-3
Chip-Select Module Output Timing Diagram ............................................................ 13-3

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Data Transfer State Transition Diagram ..................................................................... 13-5
Read Cycle Flowchart................................................................................................. 13-7
Basic Read Bus Cycle................................................................................................. 13-7
Write Cycle Flowchart................................................................................................ 13-8
Basic Write Bus Cycle ................................................................................................ 13-8
Read Cycle with Fast Termination ............................................................................. 13-9
Write Cycle with Fast Termination ............................................................................ 13-9
Back-to-Back Bus Cycles ......................................................................................... 13-10
Line Read Burst (2-1-1-1), External Termination .................................................... 13-11
Line Read Burst (2-1-1-1), Internal Termination ..................................................... 13-12
Line Read Burst (3-2-2-2), External Termination .................................................... 13-12
Line Read Burst-Inhibited, Fast Termination, External Termination....................... 13-13
Line Write Burst (2-1-1-1), Internal/External Termination...................................... 13-13
Line Write Burst (3-2-2-2) with One Wait State ...................................................... 13-14
Line Write Burst-Inhibited........................................................................................ 13-14
Example of a Misaligned Longword Transfer (32-Bit Port) .................................... 13-15
Example of a Misaligned Word Transfer (32-Bit Port) ............................................ 13-15
MCF5282 Block Diagram with Signal Interfaces ...................................................... 14-2
Synchronous DRAM Controller Block Diagram........................................................ 15-2
DRAM Control Register (DCR) ................................................................................. 15-5
DRAM Address and Control Register (DACRn) ....................................................... 15-6
DRAM Controller Mask Registers (DMRn) .............................................................. 15-8
Connections for External Memory Port Sizes .......................................................... 15-13
Burst Read SDRAM Access ..................................................................................... 15-14
Burst Write SDRAM Access .................................................................................... 15-15
Auto-Refresh Operation............................................................................................ 15-16
Self-Refresh Operation ............................................................................................. 15-17
Mode Register Set (mrs) Command ......................................................................... 15-19
Initialization Values for DCR ................................................................................... 15-20
SDRAM Configuration............................................................................................. 15-21
DACR Register Configuration.................................................................................. 15-21
DMR0 Register ......................................................................................................... 15-22
DMA Signal Diagram ................................................................................................. 16-2
DMA Request Control Register (DMAREQC) .......................................................... 16-3
Dual-Address Transfer................................................................................................ 16-4
Source Address Registers (SARn) .............................................................................. 16-6
Destination Address Registers (DARn) ...................................................................... 16-6
Byte Count Registers (BCRn)—BCR24BIT = 1........................................................ 16-7
Byte Count Registers (BCRn)—BCR24BIT = 0........................................................ 16-7
DMA Control Registers (DCRn) ................................................................................ 16-8
DMA Status Registers (DSRn) ................................................................................ 16-10
FEC Block Diagram.................................................................................................... 17-4
Ethernet Address Recognition—Receive Block Decisions ...................................... 17-12

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ILLUSTRATIONS
Figure
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17-3
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Ethernet Address Recognitionq—Microcode Decisions .......................................... 17-13
Ethernet Interrupt Event Register (EIR) ................................................................... 17-24
Interrupt Mask Register (EIMR)............................................................................... 17-26
Receive Descriptor Active Register (RDAR) ........................................................... 17-27
Transmit Descriptor Active Register (TDAR).......................................................... 17-28
Ethernet Control Register (ECR) ............................................................................. 17-28
MII Management Frame Register (MMFR) ............................................................. 17-29
MII Speed Control Register (MSCR) ....................................................................... 17-31
MIB Control Register (MIBC) ................................................................................. 17-32
Receive Control Register (RCR) .............................................................................. 17-33
Transmit Control Register (TCR) ............................................................................. 17-34
Physical Address Low Register (PALR) .................................................................. 17-36
Physical Address High Register (PAUR) ................................................................. 17-36
Opcode/Pause Duration Register (OPD) .................................................................. 17-37
Descriptor Individual Upper Address Register (IAUR) ........................................... 17-38
Descriptor Individual Lower Address Register (IALR) ........................................... 17-38
Descriptor Group Upper Address Register (GAUR) ................................................ 17-39
Descriptor Group Lower Address Register (GALR) ................................................ 17-40
FIFO Transmit FIFO Watermark Register (TFWR)................................................. 17-40
FIFO Receive Bound Register (FRBR) .................................................................... 17-41
FIFO Receive Start Register (FRSR)........................................................................ 17-42
Receive Descriptor Ring Start Register (ERDSR) ................................................... 17-43
Transmit Buffer Descriptor Ring Start Register (ETDSR)....................................... 17-43
Receive Buffer Size Register (EMRBR) .................................................................. 17-44
Receive Buffer Descriptor (RxBD) .......................................................................... 17-47
Transmit Buffer Descriptor (TxBD) ......................................................................... 17-50
Watchdog Timer Block Diagram................................................................................ 18-2
Watchdog Control Register (WCR)............................................................................ 18-3
Watchdog Modulus Register (WMR)......................................................................... 18-4
Watchdog Count Register (WCNTR)......................................................................... 18-5
Watchdog Service Register (WSR) ............................................................................ 18-6
PIT Block Diagram ..................................................................................................... 19-1
PIT Control and Status Register (PCSR) .................................................................... 19-4
PIT Modulus Register (PMR)..................................................................................... 19-6
PIT Count Register (PCNTR)..................................................................................... 19-6
Counter Reloading from the Modulus Latch .............................................................. 19-7
Counter in Free-Running Mode .................................................................................. 19-7
GPT Block Diagram ................................................................................................... 20-2
GPT Input Capture/Output Compare Select Register (GPTIOS) ............................... 20-5
GPT Input Compare Force Register (GPCFORC) ..................................................... 20-6
GPT Output Compare 3 Mask Register (GPTOC3M)................................................ 20-6
GPT Output Compare 3 Data Register (GPTOC3D).................................................. 20-7

MCF5282 User’s Manual

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GPT Counter Register (GPTCNT) ............................................................................. 20-7
GPT System Control Register 1 (GPTSCR1)............................................................. 20-8
Fast Clear Flag Logic.................................................................................................. 20-9
GPT Toggle-On-Overflow Register (GPTTOV) ........................................................ 20-9
GPT Control Register 1 (GPTCTL1).......................................................................... 20-9
GPT Control Register 2 (GPTCTL2)........................................................................ 20-10
GPT Interrupt Enable Register (GPTIE) .................................................................. 20-10
GPT System Control Register 2 (GPTSCR2)........................................................... 20-11
GPT Flag Register 1 (GPTFLG1)............................................................................. 20-12
GPT Flag Register 2 (GPTFLG2)............................................................................. 20-12
GPT Channel[0:3] Register (GPTCn)....................................................................... 20-13
Pulse Accumulator Control Register (GPTPACTL) ................................................ 20-13
Pulse Accumulator Flag Register (GPTPAFLG)...................................................... 20-14
Pulse Accumulator Counter Register (GPTPACNT) ............................................... 20-15
GPT Port Data Register (GPTPORT) ....................................................................... 20-16
GPT Port Data Direction Register (GPTDDR)......................................................... 20-16
Channel 3 Output Compare/Pulse Accumulator Logic ............................................ 20-19
DMA Timer Block Diagram....................................................................................... 21-2
DTMRn Bit Definitions .............................................................................................. 21-4
DTXMRn Bit Definitions ........................................................................................... 21-5
DTERn Bit Definitions ............................................................................................... 21-6
DTRRn Bit Definitions ............................................................................................... 21-7
DTCRn Bit Definitions ............................................................................................... 21-8
DTCNn Bit Definitions............................................................................................... 21-8
QSPI Block Diagram .................................................................................................. 22-2
QSPI RAM Model ...................................................................................................... 22-5
QSPI Mode Register (QMR) .................................................................................... 22-10
QSPI Clocking and Data Transfer Example ............................................................. 22-11
QSPI Delay Register (QDLYR) ............................................................................... 22-11
QSPI Wrap Register (QWR)..................................................................................... 22-12
QSPI Interrupt Register (QIR) .................................................................................. 22-13
QSPI Address Register ............................................................................................. 22-14
QSPI Data Register (QDR)....................................................................................... 22-14
Command RAM Registers (QCR0–QCR15)............................................................ 22-15
QSPI Timing ............................................................................................................. 22-16
Simplified Block Diagram .......................................................................................... 23-1
UART Mode Registers 1 (UMR1n)............................................................................ 23-4
UART Mode Register 2 (UMR2n) ............................................................................. 23-6
UART Status Register (USRn) ................................................................................... 23-7
UART Clock Select Register (UCSRn)...................................................................... 23-8
UART Command Register (UCRn)............................................................................ 23-9
UART Receive Buffer (URBn) ................................................................................ 23-11
UART Transmit Buffer (UTBn) ............................................................................... 23-12

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ILLUSTRATIONS
Figure
Number
23-9
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UART Input Port Change Register (UIPCRn) ......................................................... 23-12
UART Auxiliary Control Register (UACRn) ........................................................... 23-13
UART Interrupt Status/Mask Registers (UISRn/UIMRn)........................................ 23-13
UART Baud Rate Generator Register (UBG1n) ...................................................... 23-14
UART Baud Rate Generator Register (UBG2n) ...................................................... 23-14
UART Input Port Register (UIPn) ............................................................................ 23-15
UART Output Port Command Registers (UOP1n/UOP0n) ..................................... 23-15
UART Block Diagram Showing External and Internal Interface Signals ................ 23-17
UART/RS-232 Interface ........................................................................................... 23-18
Clocking Source Diagram......................................................................................... 23-19
Transmitter and Receiver Functional Diagram......................................................... 23-20
Transmitter Timing Diagram ................................................................................... 23-22
Receiver Timing ....................................................................................................... 23-23
Automatic Echo ........................................................................................................ 23-25
Local Loop-Back ...................................................................................................... 23-25
Remote Loop-Back ................................................................................................... 23-26
Multidrop Mode Timing Diagram ............................................................................ 23-27
UART Mode Programming Flowchart ..................................................................... 23-31
I2C Module Block Diagram ....................................................................................... 24-2
I2C Standard Communication Protocol ...................................................................... 24-3
Repeated START ........................................................................................................ 24-4
Synchronized Clock SCL............................................................................................ 24-5
I2C Address Register (I2ADR)................................................................................... 24-6
I2C Frequency Divider Register (I2FDR) ................................................................. 24-7
I2C Control Register (I2CR) ....................................................................................... 24-8
I2CR Status Register (I2SR) ...................................................................................... 24-9
I2C Data I/O Register (I2DR) .................................................................................. 24-10
Flow-Chart of Typical I2C Interrupt Routine........................................................... 24-15
FlexCAN Block Diagram and Pinout ........................................................................ 25-2
Typical CAN system................................................................................................... 25-4
Extended ID Message Buffer Structure ...................................................................... 25-5
Standard ID Message Buffer Structure ....................................................................... 25-5
FlexCAN Memory Map.............................................................................................. 25-8
CAN Module Configuration Register (CANMCR).................................................. 25-20
FlexCAN Control Register 0 (CANCTRL0) ............................................................ 25-22
FlexCAN Control Register 1 (CANCTRL1) ............................................................ 25-23
Prescaler Divide Register (PRESDIV) ..................................................................... 25-24
FlexCAN Control Register 2 (CANCTRL2) ............................................................ 25-25
Free Running Timer (TIMER).................................................................................. 25-26
Rx Mask Registers (RXGMASK, RX14MASK, and RX15MASK) ....................... 25-27
FlexCAN Error and Status Register (ESTAT) ......................................................... 25-28
Interrupt Mask Register (IMASK)............................................................................ 25-30

MCF5282 User’s Manual

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Interrupt Flag Register (IFLAG)............................................................................... 25-31
FlexCAN Receive Error Counter (RXECTR) .......................................................... 25-32
FlexCAN Transmit Error Counter (TXECTR) ......................................................... 25-32
MCF5282 Ports Module Block Diagram.................................................................... 26-2
Port Output Data Registers (8-bit) .............................................................................. 26-8
Port Output Data Register (7-bit)................................................................................ 26-8
Port Output Data Registers (6-bit) .............................................................................. 26-8
Port Output Data Registers (4-bit) .............................................................................. 26-9
Port Data Direction Registers (8-bit) .......................................................................... 26-9
Port Data Direction Register (7-bit).......................................................................... 26-10
Port Data Direction Registers (6-bit) ........................................................................ 26-10
Port Data Direction Registers (4-bit) ........................................................................ 26-10
Port Pin Data/Set Data Registers (8-bit) .................................................................. 26-11
Port Pin Data/Set Data Register (7-bit)..................................................................... 26-11
Port Pin Data/Set Data Registers (6-bit) ................................................................... 26-11
Port Pin Data/Set Data Registers (4-bit) ................................................................... 26-12
Port Clear Output Data Registers (8-bit) .................................................................. 26-12
Port Clear Output Data Register (7-bit) .................................................................... 26-13
Port Clear Output Data Registers (6-bit) .................................................................. 26-13
Port Clear Output Data Registers (4-bit) .................................................................. 26-13
Port B/C/D Pin Assignment Register (PBCDPAR).................................................. 26-14
Port E Pin Assignment Register (PEPAR) ............................................................... 26-15
Port F Pin Assignment Register (PFPAR) ................................................................ 26-17
Port J Pin Assignment Register (PJPAR) ................................................................ 26-18
Port SD Pin Assignment Register (PSDPAR) .......................................................... 26-19
Port AS Pin Assignment Register (PASPAR) .......................................................... 26-19
Port EH/EL Pin Assignment Register (PEHLPAR) ................................................ 26-20
Port QS Pin Assignment Register (PQSPAR) .......................................................... 26-21
Port TC Pin Assignment Register (PTCPAR) ......................................................... 26-22
Port TD Pin Assignment Register (PTDPAR)......................................................... 26-23
Port UA Pin Assignment Register (PUAPAR)........................................................ 26-24
Digital Input Timing ................................................................................................. 26-25
Digital Output Timing .............................................................................................. 26-26
QADC Block Diagram................................................................................................ 27-2
QADC Input and Output Signals ................................................................................ 27-5
QADC Module Configuration Register (QADCMCR) .............................................. 27-9
QADC Port QA Data Register (PORTQA) .............................................................. 27-10
QADC Port QB Data Register (PORTQB)............................................................... 27-10
QADC Port QA Data Direction Register (DDRQA)................................................ 27-11
Port QB Data Direction Register (DDRQB)............................................................. 27-11
QADC Control Register 0 (QACR0)........................................................................ 27-12
QADC Control Register 1 (QACR1)........................................................................ 27-14
QADC Control Register 2 (QACR2)........................................................................ 27-17

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ILLUSTRATIONS
Figure
Number
27-11
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QADC Status Register 0 (QASR0)........................................................................... 27-22
Queue Status Transition............................................................................................ 27-25
QADC Status Register 1 (QASR1)........................................................................... 27-26
Conversion Command Word Table (CCW) ............................................................. 27-27
Right-Justified Unsigned Result Register (RJURR)................................................. 27-29
Left-Justified Signed Result Register (LJSRR) ........................................................ 27-30
Left-Justified Unsigned Result Register (LJURR) ................................................... 27-31
External Multiplexing Configuration........................................................................ 27-33
QADC Analog Subsystem Block Diagram .............................................................. 27-35
Conversion Timing ................................................................................................... 27-36
Bypass Mode Conversion Timing ............................................................................ 27-36
QADC Queue Operation with Pause ........................................................................ 27-39
CCW Priority Situation 1.......................................................................................... 27-41
CCW Priority Situation 2.......................................................................................... 27-42
CCW Priority Situation 3.......................................................................................... 27-42
CCW Priority Situation 4.......................................................................................... 27-43
CCW Priority Situation 5.......................................................................................... 27-43
CCW Priority Situation 6.......................................................................................... 27-44
CCW Priority Situation 7.......................................................................................... 27-44
CCW Priority Situation 8.......................................................................................... 27-45
CCW Priority Situation 9.......................................................................................... 27-45
CCW Priority Situation 10........................................................................................ 27-46
CCW Priority Situation 11........................................................................................ 27-46
CCW Freeze Situation 12 ......................................................................................... 27-47
CCW Freeze Situation 13 ......................................................................................... 27-47
CCW Freeze Situation 14 ......................................................................................... 27-47
. CCW Freeze Situation 15 ....................................................................................... 27-47
CCW Freeze Situation 16 ......................................................................................... 27-48
CCW Freeze Situation 17 ......................................................................................... 27-48
CCW Freeze Situation 18 ......................................................................................... 27-48
CCW Freeze Situation 19 ......................................................................................... 27-48
QADC Clock Subsystem Functions ......................................................................... 27-58
QADC Conversion Queue Operation ....................................................................... 27-60
Equivalent Analog Input Circuitry ........................................................................... 27-63
Errors Resulting from Clipping ................................................................................ 27-64
External Positive Edge Trigger Mode Timing with Pause ....................................... 27-65
Gated Mode, Single Scan Timing............................................................................. 27-66
Gated Mode, Continuous Scan Timing..................................................................... 27-67
Star-Ground at the Point of Power Supply Origin .................................................... 27-68
Input Signal Subjected to Negative Stress ................................................................ 27-69
Input Signal Subjected to Positive Stress ................................................................. 27-70
External Multiplexing of Analog Signal Sources ..................................................... 27-72

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27-53
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Electrical Model of an A/D Input Signal .................................................................. 27-73
Reset Controller Block Diagram................................................................................. 28-2
Reset Control Register (RCR) .................................................................................... 28-3
Reset Status Register (RSR) ....................................................................................... 28-4
Reset Control Flow ..................................................................................................... 28-9
Processor/Debug Module Interface ............................................................................ 29-1
CLKOUT Timing ....................................................................................................... 29-2
Example JMP Instruction Output on PST/DDATA ................................................... 29-5
Debug Programming Model ....................................................................................... 29-6
Address Attribute Trigger Register (AATR) .............................................................. 29-8
Address Breakpoint Registers (ABLR, ABHR) ......................................................... 29-9
Configuration/Status Register (CSR)........................................................................ 29-10
Data Breakpoint/Mask Registers (DBR/DBMR) ..................................................... 29-12
Program Counter Breakpoint Register (PBR) .......................................................... 29-14
Program Counter Breakpoint Mask Register (PBMR) ............................................. 29-14
Trigger Definition Register (TDR) ........................................................................... 29-15
BDM Serial Interface Timing ................................................................................... 29-18
Receive BDM Packet................................................................................................ 29-19
Transmit BDM Packet .............................................................................................. 29-19
BDM Command Format ........................................................................................... 29-21
Command Sequence Diagram .................................................................................. 29-22
RAREG/RDREG Command Format ............................................................................. 29-23
RAREG/RDREG Command Sequence.......................................................................... 29-23
WAREG/WDREG Command Format............................................................................ 29-24
WAREG/WDREG Command Sequence ........................................................................ 29-24
READ Command/Result Formats............................................................................... 29-25
READ Command Sequence........................................................................................ 29-25
WRITE Command Format .......................................................................................... 29-26
WRITE Command Sequence ...................................................................................... 29-27
DUMP Command/Result Formats ............................................................................. 29-28
DUMP Command Sequence ....................................................................................... 29-29
FILL Command Format ............................................................................................ 29-30
FILL Command Sequence.......................................................................................... 29-30
GO Command Format................................................................................................ 29-31
GO Command Sequence............................................................................................ 29-31
NOP Command Format.............................................................................................. 29-31
NOP Command Sequence .......................................................................................... 29-31
RCREG Command/Result Formats............................................................................. 29-32
RCREG Command Sequence...................................................................................... 29-33
WCREG Command/Result Formats............................................................................ 29-34
WCREG Command Sequence ..................................................................................... 29-35
RDMREG Command/Result Formats......................................................................... 29-35
RDMREG Command Sequence................................................................................... 29-36

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ILLUSTRATIONS
Figure
Number
29-39
29-40
29-41
30-1
30-2
30-3
30-4
31-1
31-2
31-3
32-1
32-2
33-1
33-2
33-3
33-4
33-5
33-6
33-7
33-8
33-9
33-10
33-11
33-12
33-13
33-14
33-15
33-16
33-17
33-18
33-19
33-20
33-21

xxxii

Title

Page
Number

BDM Command Format............................................................................ 29-36
Command Sequence .................................................................................. 29-36
Recommended BDM Connector............................................................................... 29-46
Chip Configuration Module Block Diagram .............................................................. 30-2
Chip Configuration Register (CCR) ........................................................................... 30-5
Reset Configuration Register (RCON) ....................................................................... 30-6
Chip Identification Register (CIR) ............................................................................. 30-8
JTAG Block Diagram ................................................................................................. 31-2
IDCODE Register ....................................................................................................... 31-5
TAP Controller State Machine Flow .......................................................................... 31-8
MCF5282 Pinout (256 MAPBGA)............................................................................. 32-2
256 MAPBGA Package Dimensions .......................................................................... 32-7
General Input Timing Requirements ........................................................................ 33-11
Read/Write (Internally Terminated) Timing............................................................. 33-13
Read Bus Cycle Terminated by TA .......................................................................... 33-14
Read Bus Cycle Terminated by TEA ....................................................................... 33-15
SDRAM Read Cycle................................................................................................. 33-16
SDRAM Write Cycle................................................................................................ 33-17
GPIO Timing ............................................................................................................ 33-18
RSTI and Configuration Override Timing................................................................ 33-19
I2C Input/Output Timings......................................................................................... 33-20
MII Receive Signal Timing Diagram ....................................................................... 33-21
MII Transmit Signal Timing Diagram...................................................................... 33-22
MII Async Inputs Timing Diagram .......................................................................... 33-22
MII Serial Management Channel Timing Diagram .................................................. 33-23
QSPI Timing ............................................................................................................. 33-24
Test Clock Input Timing........................................................................................... 33-25
Boundary Scan (JTAG) Timing................................................................................ 33-26
Test Access Port Timing........................................................................................... 33-26
TRST Timing ............................................................................................................ 33-26
BKPT Timing ........................................................................................................... 33-27
Real-Time Trace AC Timing .................................................................................... 33-28
BDM Serial Port AC Timing .................................................................................... 33-28

WDMREG
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MCF5282 User’s Manual

MOTOROLA

TABLES
Table
Number

1-1
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
2-16
2-17
2-18
3-1
3-2
3-3
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
5-1
5-2
6-1
6-2
6-3
6-4

Title

Page
Number

Cache Configuration ..................................................................................................... 1-8
CCR Field Descriptions ................................................................................................ 2-4
SR Field Descriptions ................................................................................................... 2-6
ColdFire CPU Registers................................................................................................ 2-8
ISA Revision A+ New Instructions ............................................................................ 2-10
Exception Vector Assignments................................................................................... 2-11
Format Field Encodings.............................................................................................. 2-12
Fault Status Encodings................................................................................................ 2-13
D0 Hardware Configuration Info Field Description................................................... 2-18
D1 Local Memory Hardware Configuration Information Field Description ............. 2-19
Misaligned Operand References ................................................................................. 2-22
Move Byte and Word Execution Times ..................................................................... 2-23
Move Long Execution Times .................................................................................... 2-23
One Operand Instruction Execution Times ................................................................ 2-24
Two Operand Instruction Execution Times................................................................ 2-24
Miscellaneous Instruction Execution Times............................................................... 2-26
EMAC Instruction Execution Times .......................................................................... 2-27
General Branch Instruction Execution Times............................................................. 2-28
BRA, Bcc Instruction Execution Times ..................................................................... 2-28
MACSR Field Descriptions .......................................................................................... 3-7
Summary of S/U, F/I, and R/T Control Bits ................................................................. 3-8
EMAC Instruction Summary ...................................................................................... 3-12
Initial Fetch Offset vs. CLNF Bits................................................................................ 4-5
Instruction Cache Operation as Defined by CACR[31, 10] ......................................... 4-6
Memory Map of Cache Registers ................................................................................. 4-7
CACR Field Descriptions ............................................................................................. 4-8
Cache Configuration as Defined by CACR[31, 23, 22] ............................................. 4-10
Cache Invalidate All as Defined by CACR[23, 22, 21, 20]........................................ 4-10
External Fetch Size Based on Miss Address and CLNF ............................................ 4-11
ACR Field Descriptions.............................................................................................. 4-11
SRAM Base Address Register ...................................................................................... 5-2
Typical RAMBAR Setting Examples........................................................................... 5-4
CFM Configuration Field ............................................................................................ 6-5
FLASHBAR Field Descriptions ................................................................................... 6-7
CFM Register Address Map ......................................................................................... 6-8
CFMCR Field Descriptions .......................................................................................... 6-9

MOTOROLA

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xxxiii

TABLES
Table
Page
Title
Number
Number
6-5
CFMCLKD Field Descriptions................................................................................... 6-10
6-6
CFMSEC Field Descriptions ...................................................................................... 6-11
6-7
CFMPROT Field Descriptions ................................................................................... 6-12
6-8
CFMSACC Field Descriptions ................................................................................... 6-14
6-9
CFMDACC Field Descriptions .................................................................................. 6-14
6-10
CFMUSTAT Field Descriptions................................................................................. 6-15
6-11
CFMCMD Field Descriptions .................................................................................... 6-16
6-12
CFMCMD User Mode Commands............................................................................. 6-16
6-13
Flash User Commands ................................................................................................ 6-20
6-14
CFM Interrupt Sources ............................................................................................... 6-25
7-1
Chip Configuration Module Memory Map................................................................... 7-2
7-2
LPICR Field Description .............................................................................................. 7-3
7-3
XLPM_IPL Settings ..................................................................................................... 7-4
7-4
LPCR Field Descriptions .............................................................................................. 7-4
7-5
Low-Power Modes........................................................................................................ 7-5
7-6
PLL/CLKOUT Stop Mode Operation .......................................................................... 7-5
7-7
CPU and Peripherals in Low-Power Modes ............................................................... 7-16
8-1
SCM Register Map ....................................................................................................... 8-2
8-2
IPSBAR Field Description............................................................................................ 8-4
8-3
RAMBAR Field Description ........................................................................................ 8-5
8-4
CRSR Field Descriptions.............................................................................................. 8-6
8-5
CWCR Field Description.............................................................................................. 8-8
8-6
Core Watchdog Timer Delay ........................................................................................ 8-8
8-7
MPARK Field Description ......................................................................................... 8-13
8-8
SACU Register Memory Map .................................................................................... 8-15
8-9
MPR[n] Field Descriptions ......................................................................................... 8-16
8-10
PACR Field Descriptions............................................................................................ 8-17
8-11
PACR ACCESSCTRL Bit Encodings ........................................................................ 8-17
8-12
Peripheral Access Control Registers (PACRs) ........................................................... 8-17
8-13
Grouped PeripheralAccess Control Register (GPACR) Field Descriptions............... 8-19
8-14
GPACR ACCESS_CTRL Bit Encodings ................................................................... 8-19
8-15
GPACR Address Space .............................................................................................. 8-20
9-1
Clock Module Operation in Low-power Modes........................................................... 9-2
9-2
Signal Properties .......................................................................................................... 9-4
9-3
Clock Module Memory Map ........................................................................................ 9-5
9-4
SYNCR Field Descriptions........................................................................................... 9-6
9-5
SYNSR Field Descriptions ........................................................................................... 9-9
9-6
System Clock Modes ................................................................................................. 9-10
9-7
Clock Out and Clock In Relationships ....................................................................... 9-11
9-8
Charge Pump Current and MFD in Normal Mode Operation .................................... 9-13
9-9
Loss of Clock Summary ............................................................................................. 9-16
9-10
Stop Mode Operation.................................................................................................. 9-17
10-1
Interrupt Priority Within a Level ................................................................................ 10-3
xxxiv

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Table
Page
Title
Number
Number
10-2
Interrupt Controller Base Addresses........................................................................... 10-5
10-3
Interrupt Controller Memory Map .............................................................................. 10-5
10-4
IPRHn Field Descriptions ........................................................................................... 10-7
10-5
IPRLn Field Descriptions ........................................................................................... 10-7
10-6
IMRHn Field Descriptions.......................................................................................... 10-8
10-8
INTFRCHn Field Descriptions ................................................................................... 10-9
10-7
IMRLn Field Descriptions .......................................................................................... 10-9
10-9
INTFRCLn Field Descriptions ................................................................................. 10-10
10-10 IRQn Field Descriptions ........................................................................................... 10-10
10-11 IACKLPRn Field Descriptions ................................................................................. 10-11
10-12 ICRnx Field Descriptions ......................................................................................... 10-12
10-13 Interrupt Source Assignment for INTC0 .................................................................. 10-12
10-14 Interrupt Source Assignment for INTC1 .................................................................. 10-15
10-15 SWIACK and L1IACK-L7IACK Field Descriptions............................................... 10-16
11-1
Edge Port Module Operation in Low-power Modes .................................................. 11-2
11-2
Edge Port Module Memory Map ................................................................................ 11-3
11-3
EPPAR Field Descriptions.......................................................................................... 11-4
11-4
EPDD Field Descriptions............................................................................................ 11-5
11-5
EPIER Field Descriptions ........................................................................................... 11-5
11-6
EPDR Field Descriptions............................................................................................ 11-6
11-7
EPPDR Field Descriptions.......................................................................................... 11-6
11-8
EPFR Field Descriptions ............................................................................................ 11-7
12-1
Chip Select Module Signals........................................................................................ 12-1
12-2
Byte Enables/Byte Write Enable Signal Settings ....................................................... 12-2
12-3
Accesses by Matches in CSARs and DACRs............................................................. 12-4
12-4
D[19:18] External Boot Chip Select Configuration ................................................... 12-5
12-5
Chip Select Registers .................................................................................................. 12-5
12-6
CSARn Field Description ........................................................................................... 12-7
12-7
CSMRn Field Descriptions ......................................................................................... 12-7
12-8
CSCRn Field Descriptions.......................................................................................... 12-9
13-1
ColdFire Bus Signal Summary .................................................................................. 13-1
13-2
Accesses by Matches in CSCRs and DACRs ............................................................. 13-4
13-3
Bus Cycle States ........................................................................................................ 13-5
13-4
Allowable Line Access Patterns ............................................................................... 13-11
14-1
MCF5282 Signal Description .................................................................................... 14-3
14-2
MCF5282 Alphabetical Signal Index ......................................................................... 14-8
14-3
MCF5282 Signals and Pin Numbers Sorted by Function......................................... 14-11
14-4
Pin Reset States at Reset (Single-Chip Mode).......................................................... 14-17
14-5
Default Signal Functions After System Reset (External Boot Mode) ...................... 14-17
14-6
Transfer Size Encoding............................................................................................. 14-20
14-7
Processor Status Encoding........................................................................................ 14-32
15-1
SDRAM Commands ................................................................................................... 15-3
15-2
Synchronous DRAM Signal Connections .................................................................. 15-4
MOTOROLA

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TABLES
Table
Page
Title
Number
Number
15-3
DRAM Controller Registers ....................................................................................... 15-4
15-4
DCR Field Descriptions.............................................................................................. 15-5
15-5
DACRn Field Descriptions ......................................................................................... 15-6
15-6
DMRn Field Descriptions ........................................................................................... 15-8
15-7
Generic Address Multiplexing Scheme ...................................................................... 15-9
15-8
MCF5282 to SDRAM Interface (8-Bit Port, 9-Column Address Lines).................. 15-10
15-9
MCF5282 to SDRAM Interface (8-Bit Port,10-Column Address Lines)................. 15-10
15-10
MCF5282 to SDRAM Interface (8-Bit Port,11-Column Address Lines)................ 15-10
15-11
MCF5282 to SDRAM Interface (8-Bit Port,12-Column Address Lines)................ 15-10
15-12 MCF5282 to SDRAM Interface (8-Bit Port,13-Column Address Lines)................. 15-10
15-13 MCF5282 to SDRAM Interface (16-Bit Port, 8-Column Address Lines)................ 15-11
15-14
MCF5282 to SDRAM Interface (16-Bit Port, 9-Column Address Lines)............... 15-11
15-15
MCF5282 to SDRAM Interface (16-Bit Port, 10-Column Address Lines)............. 15-11
15-16 MCF5282 to SDRAM Interface (16-Bit Port, 11-Column Address Lines).............. 15-11
15-17 MCF5282 to SDRAM Interface (16-Bit Port, 12-Column Address Lines).............. 15-11
15-18
MCF5282 to SDRAM Interface (16-Bit Port, 13-Column-Address Lines) ............ 15-12
15-19 MCF5282 to SDRAM Interface (32-Bit Port, 8-Column Address Lines)................ 15-12
15-20 MCF5282 to SDRAM Interface (32-Bit Port, 9-Column Address Lines)................ 15-12
15-21 MCF5282 to SDRAM Interface (32-Bit Port, 10-Column Address Lines).............. 15-12
15-22 MCF5282 to SDRAM Interface (32-Bit Port, 11-Column Address Lines).............. 15-12
15-23 MCF5282 to SDRAM Interface (32-Bit Port, 12-Column Address Lines).............. 15-13
15-24
SDRAM Hardware Connections ............................................................................. 15-13
15-25
SDRAM Example Specifications ............................................................................ 15-19
15-26
SDRAM Hardware Connections ............................................................................. 15-20
15-27 DCR Initialization Values......................................................................................... 15-20
15-28 DACR Initialization Values...................................................................................... 15-21
15-29 DMR0 Initialization Values...................................................................................... 15-22
15-30
Mode Register Initialization .................................................................................... 15-23
15-31 Mode Register Mapping to MCF5282 A[31:0] ........................................................ 15-24
16-1
DMAREQC Field Description.................................................................................... 16-3
16-2
Memory Map for DMA Controller Module Registers................................................ 16-5
16-3
DCRn Field Descriptions............................................................................................ 16-8
16-4
DSRn Field Descriptions ......................................................................................... 16-10
17-1
ECR[ETHER_EN] De-Assertion Effect on FEC ....................................................... 17-6
17-2
User Initialization (Before ECR[ETHER_EN]) ......................................................... 17-6
17-3
FEC User Initialization (Before ECR[ETHER_EN]) ................................................. 17-7
17-4
Microcontroller Initialization...................................................................................... 17-7
17-5
MII Mode .................................................................................................................... 17-8
17-6
7-Wire Mode Configuration ....................................................................................... 17-8
17-7
Destination Address to 6-Bit Hash ........................................................................... 17-14
17-8
PAUSE Frame Field Specification ........................................................................... 17-16
17-9
Module Memory Map ............................................................................................... 17-20
17-10 FEC Register Memory Map...................................................................................... 17-20
xxxvi

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TABLES
Table
Page
Title
Number
Number
17-11 MIB Counters Memory Map .................................................................................... 17-22
17-12 EIR Field Descriptions.............................................................................................. 17-24
17-13 EIMR Field Descriptions .......................................................................................... 17-26
17-14 RDAR Field Descriptions ......................................................................................... 17-27
17-15 TDAR Field Descriptions ......................................................................................... 17-28
17-16 ECR Field Descriptions ............................................................................................ 17-29
17-17 MMFR Field Descriptions ........................................................................................ 17-30
17-18 MSCR Field Descriptions ......................................................................................... 17-31
17-19 Programming Examples for MSCR .......................................................................... 17-32
17-20 MIBC Field Descriptions.......................................................................................... 17-32
17-21 RCR Field Descriptions ............................................................................................ 17-33
17-22 TCR Field Descriptions ............................................................................................ 17-35
17-23 PALR Field Descriptions.......................................................................................... 17-36
17-24 PAUR Field Descriptions ......................................................................................... 17-37
17-25 OPD Field Descriptions ............................................................................................ 17-37
17-26 IAUR Field Descriptions .......................................................................................... 17-38
17-27 IALR Field Descriptions........................................................................................... 17-39
17-28 GAUR Field Descriptions......................................................................................... 17-39
17-29 GALR Field Descriptions ......................................................................................... 17-40
17-30 TFWR Field Descriptions ......................................................................................... 17-41
17-31 FRBR Field Descriptions.......................................................................................... 17-41
17-32 FRSR Field Descriptions .......................................................................................... 17-42
17-33 ERDSR Field Descriptions ....................................................................................... 17-43
17-34 ETDSR Field Descriptions ....................................................................................... 17-44
17-35 EMRBR Field Descriptions ...................................................................................... 17-44
17-36 Receive Buffer Descriptor Field Definitions ............................................................ 17-48
17-37 Transmit Buffer Descriptor Field Definitions .......................................................... 17-50
18-1
Watchdog Module Operation in Low-power Modes .................................................. 18-1
18-2
Watchdog Timer Module Memory Map..................................................................... 18-3
18-3
WCR Field Descriptions ............................................................................................. 18-4
18-4
WMR Field Descriptions ............................................................................................ 18-5
18-5
WCNTR Field Descriptions........................................................................................ 18-5
19-1
PIT Module Operation in Low-power Modes ............................................................ 19-2
19-2
Programmable Interrupt Timer Modules Memory Map ............................................. 19-3
19-3
PCSR Field Descriptions ............................................................................................ 19-4
19-4
PIT Interrupt Requests ................................................................................................ 19-8
20-1
Watchdog Module Operation in Low-power Modes .................................................. 20-3
20-2
Signal Properties ......................................................................................................... 20-3
20-3
GPT Modules Memory Map....................................................................................... 20-4
20-4
GPTIOS Field Descriptions ........................................................................................ 20-6
20-5
GPTCFORC Field Descriptions ................................................................................. 20-6
20-6
GPTOC3M Field Descriptions ................................................................................... 20-7
20-7
GPTOC3D Field Descriptions .................................................................................... 20-7
MOTOROLA

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TABLES
Table
Page
Title
Number
Number
20-8
GPTCNT Field Descriptions ...................................................................................... 20-8
20-9
GPTSCR1 Field Descriptions ..................................................................................... 20-8
20-10 GPTTOV Field Description........................................................................................ 20-9
20-11 GPTCL1 Field Descriptions ..................................................................................... 20-10
20-12 GPTLCTL2 Field Descriptions ................................................................................ 20-10
20-13 GPTIE Field Descriptions......................................................................................... 20-11
20-14 GPTSCR2 Field Descriptions ................................................................................... 20-11
20-15 GPTFLG1 Field Descriptions ................................................................................... 20-12
20-16 GPTFLG2 Field Descriptions ................................................................................... 20-12
20-17 GPTCn Field Descriptions........................................................................................ 20-13
20-18 GPTPACTL Field Descriptions................................................................................ 20-13
20-19 GPTPAFLG Field Descriptions................................................................................ 20-15
20-20 GPTPACR Field Descriptions .................................................................................. 20-15
20-21 GPTPORT Field Descriptions .................................................................................. 20-16
20-22 GPTDDR Field Descriptions .................................................................................... 20-16
20-23 GPT Settings and Pin Functions ............................................................................... 20-20
20-24 GPT Interrupt Requests ............................................................................................ 20-21
21-1
DMA Timer Module Memory Map........................................................................... 21-3
21-2
DTMRn Field Descriptions ........................................................................................ 21-5
21-3
DTXMRn Field Descriptions...................................................................................... 21-6
21-4
DTERn Field Descriptions.......................................................................................... 21-7
22-1
QSPI Input and Output Signals and Functions ........................................................... 22-3
22-2
QSPI_CLK Frequency as Function of System Clock and Baud Rate ........................ 22-7
22-3
QSPI Registers ............................................................................................................ 22-9
22-4
QMR Field Descriptions ........................................................................................... 22-10
22-5
QDLYR Field Descriptions ...................................................................................... 22-12
22-6
QWR Field Descriptions........................................................................................... 22-12
22-7
QIR Field Descriptions ............................................................................................. 22-13
22-8
QCR0–QCR15 Field Descriptions............................................................................ 22-15
23-1
UART Module Memory Map ..................................................................................... 23-3
23-2
UMR1n Field Descriptions ......................................................................................... 23-5
23-3
UMR2n Field Descriptions ......................................................................................... 23-6
23-4
USRn Field Descriptions ............................................................................................ 23-7
23-5
UCSRn Field Descriptions.......................................................................................... 23-9
23-6
UCRn Field Descriptions.......................................................................................... 23-10
23-7
UIPCRn Field Descriptions ...................................................................................... 23-12
23-8
UACRn Field Descriptions ....................................................................................... 23-13
23-9
UISRn/UIMRn Field Descriptions ........................................................................... 23-14
23-10 UIPn Field Descriptions............................................................................................ 23-15
23-11 UOP1/UOP0 Field Descriptions ............................................................................... 23-16
23-12 UART Module Signals ............................................................................................. 23-18
23-13 UART Interrupts ....................................................................................................... 23-29
23-14 UART DMA Requests.............................................................................................. 23-30
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TABLES
Table
Page
Title
Number
Number
23-15 UART Module Initialization Sequence .................................................................... 23-30
24-1
I2C Interface Memory Map ....................................................................................... 24-6
24-2
I2ADR Field Descriptions .......................................................................................... 24-6
24-3
I2FDR Field Descriptions ........................................................................................... 24-7
24-4
I2CR Field Descriptions ............................................................................................. 24-8
24-5
I2SR Field Descriptions.............................................................................................. 24-9
25-1
FlexCAN Memory Map.............................................................................................. 25-3
25-2
Common Extended/Standard Format Frames............................................................. 25-6
25-3
Message Buffer Codes for Receive Buffers ............................................................... 25-6
25-4
Message Buffer Codes for Transmit Buffers .............................................................. 25-6
25-5
Extended Format Frames ............................................................................................ 25-7
25-6
Standard Format Frames ............................................................................................. 25-7
25-7
Examples of System Clock/CAN Bit-Rate/S-Clock................................................. 25-14
25-8
CANMCR Field Descriptions................................................................................... 25-21
25-9
CANCTRL0 Field Descriptions ............................................................................... 25-23
25-10 Transmit Pin Configuration ...................................................................................... 25-23
25-11 CANCTRL1 Field Descriptions ............................................................................... 25-24
25-12 PRESDIV Field Descriptions ................................................................................... 25-25
25-13 CANCTRL2 Field Descriptions ............................................................................... 25-25
25-14 TIMER Field Descriptions........................................................................................ 25-26
25-15 Mask examples for Normal/Extended Messages...................................................... 25-26
25-16 RXGMASK, RX14MASK, and RX15MASK Field Descriptions ........................... 25-28
25-17 ESTAT Field Descriptions........................................................................................ 25-29
25-18 IMASK Field Descriptions ....................................................................................... 25-31
25-19 IFLAG Field Descriptions ........................................................................................ 25-31
25-20 RXECTR Field Descriptions .................................................................................... 25-32
25-21 TXECTR Field Descriptions .................................................................................... 25-32
26-1
MCF5282 Ports External Signals ............................................................................... 26-4
26-2
MCF5282 Ports Module Memory Map ...................................................................... 26-6
26-3
PORTn (8-bit, 7-bit, 6-bit, and 4-bit) Field Descriptions ........................................... 26-9
26-4
DDRn (8-bit, 6-bit, and 4-bit) Field Descriptions .................................................... 26-10
26-5
PORTnP/SETn (8-bit, 6-bit, and 4-bit) Field Descriptions ...................................... 26-12
26-6
CLRn (8-bit,7-bit, 6-bit, and 4-bit) Field Descriptions............................................. 26-13
26-7
PBCDPAR Field Descriptions.................................................................................. 26-14
26-8
Reset Values for PBCDPAR Bits ............................................................................. 26-14
26-9
PEPAR Field Descriptions........................................................................................ 26-15
26-10 Reset Values for PEPAR Bits and Fields ................................................................. 26-16
26-11 PFPAR Field Descriptions........................................................................................ 26-17
26-12 PJPAR Field Descriptions ........................................................................................ 26-18
26-13 PSDPAR Field Descriptions ..................................................................................... 26-19
26-14 PASPAR Field Descriptions ..................................................................................... 26-20
26-15 PEHLPAR Field Descriptions .................................................................................. 26-21
26-16 PQSPAR Field Description ...................................................................................... 26-21
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TABLES
Table
Page
Title
Number
Number
26-17 PTCPAR Field Descriptions ..................................................................................... 26-22
26-18 PTDPAR Field Descriptions..................................................................................... 26-23
26-19 PUAPAR Field Descriptions .................................................................................... 26-24
27-1
Multiplexed Analog Input Channels........................................................................... 27-7
27-2
QADC Memory Map .................................................................................................. 27-8
27-3
QADCMCR Field Descriptions.................................................................................. 27-9
27-4
QACR0 Field Descriptions ....................................................................................... 27-12
27-5
Prescaler fSYS Divide-by Values............................................................................. 27-13
27-6
QACR1 Field Descriptions ....................................................................................... 27-14
27-7
Queue 1 Operating Modes ........................................................................................ 27-15
27-8
QACR2 Field Descriptions ....................................................................................... 27-18
27-9
Queue 2 Operating Modes ........................................................................................ 27-18
27-10 QASR0 Field Descriptions ....................................................................................... 27-23
27-11 CCW Pause Bit Response......................................................................................... 27-24
27-12 Queue Status ............................................................................................................. 27-24
27-13 QASR1 Field Descriptions ....................................................................................... 27-26
27-14 CCW Field Descriptions ........................................................................................... 27-27
27-15 Input Sample Times .................................................................................................. 27-28
27-16 Non-Multiplexed Channel Assignments and Signal Designations........................... 27-28
27-17 Multiplexed Channel Assignments and Signal Designations ................................... 27-29
27-18 RJURR Field Descriptions........................................................................................ 27-30
27-19 LJSRR Field Descriptions ........................................................................................ 27-30
27-20 LJURR Field Descriptions........................................................................................ 27-31
27-21 Analog Input Channels ............................................................................................. 27-34
27-22 Trigger Events........................................................................................................... 27-40
27-23 Status Bits ................................................................................................................. 27-40
27-24 External Circuit Settling Time to 1/2 LSB ............................................................... 27-74
27-25 Error Resulting from Input Leakage (IOff) .............................................................. 27-75
27-26 QADC Status Flags and Interrupt Sources ............................................................... 27-76
28-1
Reset Controller Signal Properties............................................................................. 28-2
28-2
Reset Controller Memory Map ................................................................................... 28-3
28-3
RCR Field Descriptions .............................................................................................. 28-3
28-4
RSR Field Descriptions .............................................................................................. 28-5
28-5
Reset Source Summary ............................................................................................... 28-6
29-1
Debug Module Signals................................................................................................ 29-2
29-2
Processor Status Encoding.......................................................................................... 29-3
29-3
BDM/Breakpoint Registers......................................................................................... 29-7
29-4
Rev. A Shared BDM/Breakpoint Hardware ............................................................... 29-7
29-5
AATR Field Descriptions ........................................................................................... 29-8
29-6
ABLR Field Description ........................................................................................... 29-10
29-7
ABHR Field Description .......................................................................................... 29-10
29-8
CSR Field Descriptions ............................................................................................ 29-11
29-9
DBR Field Descriptions............................................................................................ 29-13
xl

MCF5282 User’s Manual

MOTOROLA

TABLES
Table
Page
Title
Number
Number
29-10 DBMR Field Descriptions ........................................................................................ 29-13
29-11 Access Size and Operand Data Location .................................................................. 29-13
29-12 PBR Field Descriptions ............................................................................................ 29-14
29-13 PBMR Field Descriptions ......................................................................................... 29-14
29-14 TDR Field Descriptions ............................................................................................ 29-15
29-15 Receive BDM Packet Field Description ................................................................... 29-19
29-16 Transmit BDM Packet Field Description ................................................................. 29-19
29-17 BDM Command Summary ....................................................................................... 29-20
29-18 BDM Field Descriptions ........................................................................................... 29-21
29-19 Control Register Map................................................................................................ 29-32
29-20 Definition of DRc Encoding—Read......................................................................... 29-36
29-21 DDATA[3:0]/CSR[BSTAT] Breakpoint Response.................................................. 29-37
29-22 PST/DDATA Specification for User-Mode Instructions.......................................... 29-40
29-23 PST/DDATA Specification for MAC Instructions................................................... 29-43
29-24 PST/DDATA Specification for Supervisor-Mode Instructions................................ 29-44
30-1
Signal Properties ........................................................................................................ 30-3
30-2
Write-Once Bits Read/Write Accessibility................................................................. 30-4
30-3
Chip Configuration Module Memory Map................................................................. 30-4
30-4
CCR Field Descriptions .............................................................................................. 30-5
30-5
RCON Field Descriptions ........................................................................................... 30-6
30-6
RCSC Chip Select Configuration ............................................................................... 30-7
30-7
BOOTPS Port Size Configuration .............................................................................. 30-7
30-8
CIR Field Description ................................................................................................. 30-8
30-9
Reset Configuration Pin States During Reset ............................................................. 30-9
30-10
Configuration During Reset....................................................................................... 30-9
30-11 Chip Configuration Mode Selection ......................................................................... 30-11
30-12 Output Pad Driver Strength Selection ...................................................................... 30-11
30-13 Clock Mode Selection............................................................................................... 30-12
31-1
Signal Properties ......................................................................................................... 31-3
31-2
Pin Function Selected ................................................................................................. 31-3
31-3
Signal State to the Disable Module............................................................................. 31-4
31-4
IDCODE Register Field Descriptions......................................................................... 31-6
31-5
JTAG Instructions....................................................................................................... 31-8
32-1
MCF5282 Signal Description by Pin Number............................................................ 32-3
32-2
Orderable Part Numbers ............................................................................................. 32-7
33-1
Absolute Maximum Ratings, ..................................................................................... 33-1
33-2
Thermal Characteristics .............................................................................................. 33-3
33-3
DC Electrical Specifications ....................................................................................... 33-4
33-4
PLL Electrical Specifications ..................................................................................... 33-6
33-5
QADC Absolute Maximum Ratings........................................................................... 33-7
33-6
QADC Electrical Specifications (Operating) ............................................................ 33-7
33-7
QADC Conversion Specifications (Operating) .......................................................... 33-9
33-8
SGFM Flash Program and Erase Characteristics........................................................ 33-9
MOTOROLA

Tables

xli

TABLES
Table
Page
Title
Number
Number
33-9
SGFM Flash Module Life Characteristics ................................................................ 33-10
33-10 Processor Bus Input Timing Specifications.............................................................. 33-10
33-11 External Bus Output Timing Specifications ............................................................. 33-11
33-12 SDRAM Timing ....................................................................................................... 33-16
33-13 GPIO Timing, ........................................................................................................... 33-17
33-13 (VDD = 2.7 to 3.6 V, VSS = 0 V, VDDH = 5 V) ........................................................ 33-17
33-14 Reset and Configuration Override Timing ............................................................... 33-18
33-15 I2C Input Timing Specifications between SCL and SDA......................................... 33-19
33-16
I2C Output Timing Specifications between SCL and SDA..................................... 33-20
33-17 MII Receive Signal Timing ...................................................................................... 33-21
33-18 MII Transmit Signal Timing..................................................................................... 33-22
33-19 MII Async Inputs Signal Timing .............................................................................. 33-22
33-20 MII Serial Management Channel Timing ................................................................. 33-23
33-21 Timer Module AC Timing Specifications ................................................................ 33-24
33-22 QSPI Modules AC Timing Specifications................................................................ 33-24
33-23 JTAG and Boundary Scan Timing............................................................................ 33-25
33-24 Debug AC Timing Specification .............................................................................. 33-27
A-1
CPU Space Register Memory Map.............................................................................. A-1
A-2
Module Memory Map Overview ................................................................................. A-2
A-3
Register Memory Map ................................................................................................. A-3

xlii

MCF5282 User’s Manual

MOTOROLA

About This Book
The primary objective of this user’s manual is to define the functionality of the MCF5282
processors for use by software and hardware developers.
The information in this book, except for changes to the Flash functionality, also applies to
the MCF5281.
The information in this book is subject to change without notice, as described in the
disclaimers on the title page. As with any technical documentation, it is the reader’s
responsibility to be sure he is using the most recent version of the documentation.
To locate any published errata or updates for this document, refer to the world-wide web at
http://www.motorola.com/coldfire.

Audience
This manual is intended for system software and hardware developers and applications
programmers who want to develop products with the MCF5282. It is assumed that the
reader understands operating systems, microprocessor system design, basic principles of
software and hardware, and basic details of the ColdFire® architecture.

Organization
Following is a summary and brief description of the major sections of this manual:
•

Chapter 1, “Overview,” includes general descriptions of the modules and features
incorporated in the MCF5282, focussing in particular on new features.

•

Chapter 2, “ColdFire Core,” provides an overview of the microprocessor core of the
MCF5282. The chapter describes the organization of the Version 2 (V2) ColdFire
processor core and an overview of the program-visible registers (the programming
model) as they are implemented on the MCF5282.

•

Chapter 3, “Enhanced Multiply-Accumulate Unit (EMAC),” describes the
MCF5282 multiply/accumulate unit, which executes integer multiply,
multiply-accumulate, and miscellaneous register instructions. The EMAC is
integrated into the operand execution pipeline (OEP).

MOTOROLA

About This Book

xliii

Organization

xliv

•

Chapter 4, “Cache,” describes the MCF5282 cache implementation, including
organization, configuration, and coherency. It describes cache operations and how
the cache interacts with other memory structures.

•

Chapter 5, “Static RAM (SRAM),” describes the MCF5282 on-chip static RAM
(SRAM) implementation. It covers general operations, configuration, and
initialization. It also provides information and examples of how to minimize power
consumption when using the SRAM.

•

Chapter 6, “ColdFire Flash Module (CFM)” describe the functionality of the
MCF5282 Flash memory.

•

Chapter 7, “Power Management,” describes the low power operation of the
MCF5282 and peripheral behavior in low power modes.

•

Chapter 8, “System Control Module (SCM),” describes the functionality of the
SCM, which provides the programming model for the System Access Control Unit
(SACU), the system bus arbiter, a 32-bit Core Watchdog Timer (CWT), and the
system control registers and logic.

•

Chapter 9, “Clock Module,” describes the MCF5282’s different clocking methods.
It also describes clock module operation in low power modes.

•

Chapter 10, “Interrupt Controller Modules,” describes operation of the interrupt
controller portion of the SCM. Includes descriptions of the registers in the interrupt
controller memory map and the interrupt priority scheme.

•

Chapter 11, “Edge Port Module (EPORT),” describes EPORT module functionality,
including operation in low power mode.

•

Chapter 12, “Chip Select Module,” describes the MCF5282 chip-select
implementation, including the operation and programming model, which includes
the chip-select address, mask, and control registers.

•

Chapter 13, “External Interface Module (EIM),” describes data-transfer operations,
error conditions, bus arbitration, and reset operations.

•

Chapter 14, “Signal Descriptions,” describes MCF5282 signals. It includes an
alphabetical listing of signals that characterizes each signal as an input or output,
defines its state at reset, and identifies whether a pull-up resistor should be used.

•

Chapter 15, “Synchronous DRAM Controller Module,” describes the configuration
and operation of the SDRAM controller. It begins with a general description and
brief glossary, and includes a description of signals involved in DRAM operations.
The remainder of the chapter describes the programming model and signal timing,
as well as the command set required for synchronous operations.

•

Chapter 16, “DMA Controller Module,” describes the MCF5282 Direct Memory
Access (DMA) controller module. It provides an overview of the module and
describes in detail its signals and registers. The latter sections of this chapter
describe operations, features, and supported data transfer modes in detail.

MCF5282 User’s Manual

MOTOROLA

Organization

•

Chapter 17, “Fast Ethernet Controller (FEC),” provides a feature-set overview, a
functional block diagram, and transceiver connection information for both MII
(Media Independent Interface) and 7-wire serial interfaces. It also provides
describes operation and the programming model.

•

Chapter 18, “Watchdog Timer Module,” describes Watchdog timer functionality,
including operation in low power mode.

•

Chapter 19, “Programmable Interrupt Timer Modules (PIT0–PIT3),” describes the
functionality of the four PIT timers, including operation in low power mode.

•

Chapter 20, “General Purpose Timer Modules (GPTA and GPTB),” describes the
functionality of the two general purpose timers, including operation in low power
mode.

•

Chapter 21, “DMA Timers (DTIM0–DTIM3),” describes the configuration and
operation of the four DMA timer modules (DTIM0, DTIM1, DTIM2, and DTIM3).
These 32-bit timers provide input capture and reference compare capabilities with
optional signaling of events using interrupts or triggers. This chapter also provides
programming examples.

•

Chapter 22, “Queued Serial Peripheral Interface (QSPI) Module,” provides a
feature-set overview and a description of operation, including details of the QSPI’s
internal storage organization. The chapter concludes with the programming model
and a timing diagram.

•

Chapter 23, “UART Modules,” describes the use of the universal asynchronous
receiver/transmitters (UARTs) implemented on the MCF5282 and includes
programming examples.

•

Chapter 24, “I2C Interface,” describes the MCF5282 I2C module, including I2C
protocol, clock synchronization, and I2C programming model registers. It also
provides extensive programming examples.

•

Chapter 25, “FlexCAN,” describes the MCF5282 implementation of the controller
area network (CAN) protocol. This chapter describes FlexCAN module operation
and provides a programming model.

•

Chapter 26, “General Purpose I/O Module,” describes the operation and
programming model of the general purpose I/O (GPIO) ports on the MCF5282.

•

Chapter 30, “Chip Configuration Module (CCM),” describes CCM functionality,
detailing the two modes of chip operation: master mode and single-chip mode. This
chapter provides a description of signals used by the CCM and a programming
model.

•

Chapter 27, “Queued Analog-to-Digital Converter (QADC),” describes the use of
the QADC module implemented on the MCF5282.

•

Chapter 28, “Reset Controller Module,” describes the operation of the reset
controller module, detailing the different types of reset that can occur.

MOTOROLA

About This Book

xlv

Suggested Reading

•

Chapter 29, “Debug Support” describes the Revision A enhanced hardware debug
support in the MCF5282.

•

Chapter 31, “IEEE 1149.1 Test Access Port (JTAG),” describes configuration and
operation of the MCF5282 Joint Test Action Group (JTAG) implementation. It
describes those items required by the IEEE 1149.1 standard and provides additional
information specific to the MCF5282. For internal details and sample applications,
see the IEEE 1149.1 document.

•

Chapter 32, “Mechanical Data,” provides a functional pin listing and package
diagram for the MCF5282.

•

Chapter 33, “Electrical Characteristics,” describes AC and DC electrical
specifications and thermal characteristics for the MCF5282. Because additional
speeds may have become available since the publication of this book, consult
Motorola’s ColdFire web page, http://www.motorola.com/coldfire, to confirm that
this is the latest information.

This manual includes the following appendix:
•

Appendix A, “List of Memory Maps,” provides the entire address-map for
MCF5282 memory-mapped registers.

Suggested Reading
This section lists additional reading that provides background for the information in this
manual as well as general information about the ColdFire architecture.

General Information
The following documentation provides useful information about the ColdFire architecture
and computer architecture in general:
•

ColdFire Programmers Reference Manual, R1.0 (MCF5200PRM/AD)

•

Using Microprocessors and Microcomputers: The Motorola Family, William C.
Wray, Ross Bannatyne, Joseph D. Greenfield

•

Computer Architecture: A Quantitative Approach, Second Edition, by John L.
Hennessy and David A. Patterson.

•

Computer Organization and Design: The Hardware/Software Interface, Second
Edition, David A . Patterson and John L. Hennessy.

ColdFire Documentation
The ColdFire documentation is available from the sources listed on the back cover of this
manual. Document order numbers are included in parentheses for ease in ordering.
•

xlvi

User’s manuals—These books provide details about individual ColdFire
implementations and are intended to be used in conjunction with The ColdFire
Programmers Reference Manual. These include the following:
MCF5282 User’s Manual

MOTOROLA

Conventions

— ColdFire MCF5102 User’s Manual (MCF5102UM/AD)
— ColdFire MCF5202 User’s Manual (MCF5202UM/AD)
— ColdFire MCF5204 User’s Manual (MCF5204UM/AD)
— ColdFire MCF5206 User’s Manual (MCF5206EUM/AD)
— ColdFire MCF5206E User’s Manual (MCF5206EUM/AD)
— ColdFire MCF5307 User’s Manual (MCF5307UM/AD)
— ColdFire MCF5407 User’s Manual (MCF5407UM/AD)
Additional literature on ColdFire implementations is being released as new processors
become available. For a current list of ColdFire documentation, refer to the World Wide
Web at http://www.motorola.com/ColdFire/.

Conventions
This document uses the following notational conventions:
MNEMONICS

In text, instruction mnemonics are shown in uppercase.

mnemonics

In code and tables, instruction mnemonics are shown in lowercase.

italics
0x0

Italics indicate variable command parameters.
Book titles in text are set in italics.
Prefix to denote hexadecimal number

0b0

Prefix to denote binary number

REG[FIELD]

Abbreviations for registers are shown in uppercase. Specific bits,
fields, or ranges appear in brackets. For example, RAMBAR[BA]
identifies the base address field in the RAM base address register.

nibble

A 4-bit data unit

byte

An 8-bit data unit

word

A 16-bit data unit1

longword

A 32-bit data unit

x

In some contexts, such as signal encodings, x indicates a don’t care.

n

Used to express an undefined numerical value

~

NOT logical operator

&

AND logical operator

|

OR logical operator

1The

only exceptions to this appear in the discussion of serial communication modules that support variable-length data transmission units. To simplify the discussion these units are referred to as words regardless
of length.

MOTOROLA

About This Book

xlvii

Acronyms and Abbreviations

Acronyms and Abbreviations
Table i lists acronyms and abbreviations used in this document.
Table i. Acronyms and Abbreviated Terms
Term
ADC

Analog-to-digital conversion

ALU

Arithmetic logic unit

BDM

Background debug mode

BIST

Built-in self test

BSDL

Boundary-scan description language

CODEC

Code/decode

DAC

Digital-to-analog conversion

DMA

Direct memory access

DSP

Digital signal processing

EA

Effective address

FIFO

First-in, first-out

GPIO

General-purpose I/O

I

2C

IEEE

Inter-integrated circuit
Institute for Electrical and Electronics Engineers

IFP

Instruction fetch pipeline

IPL

Interrupt priority level

JEDEC

Joint Electron Device Engineering Council

JTAG

Joint Test Action Group

LIFO

Last-in, first-out

LRU

Least recently used

LSB

Least-significant byte

lsb
MAC
MBAR

xlviii

Meaning

Least-significant bit
Multiply accumulate unit, also Media access controller
Memory base address register

MSB

Most-significant byte

msb

Most-significant bit

Mux

Multiplex

NOP

No operation

OEP

Operand execution pipeline

PC

Program counter

PCLK

Processor clock

PLIC

Physical layer interface controller

PLL

Phase-locked loop

MCF5282 User’s Manual

MOTOROLA

Terminology Conventions

Table i. Acronyms and Abbreviated Terms (Continued)
Term

Meaning

POR

Power-on reset

PQFP

Plastic quad flat pack

PWM

Pulse width modulation

QSPI

Queued serial peripheral interface

RISC

Reduced instruction set computing

Rx

Receive

SIM

System integration module

SOF

Start of frame

TAP

Test access port

TTL

Transistor transistor logic

Tx
UART
USB

Transmit
Universal asynchronous/synchronous receiver transmitter
Universal serial bus

Terminology Conventions
Table ii shows terminology conventions used throughout this document.
Table ii. Notational Conventions
Instruction

Operand Syntax
Opcode Wildcard

cc

Logical condition (example: NE for not equal)
Register Specifications

An
Ay,Ax

Any address register n (example: A3 is address register 3)
Source and destination address registers, respectively

Dn

Any data register n (example: D5 is data register 5)

Dy,Dx

Source and destination data registers, respectively

Rc

Any control register (example VBR is the vector base register)

Rm

MAC registers (ACC, MAC, MASK)

Rn

Any address or data register

Rw

Destination register w (used for MAC instructions only)

Ry,Rx
Xi

MOTOROLA

Any source and destination registers, respectively
Index register i (can be an address or data register: Ai, Di)

About This Book

xlix

Terminology Conventions

Table ii. Notational Conventions (Continued)
Instruction

Operand Syntax
Register Names

ACC

MAC accumulator register

CCR

Condition code register (lower byte of SR)

MACSR

MAC status register

MASK

MAC mask register

PC

Program counter

SR

Status register
Port Name

DDATA
PST

Debug data port
Processor status port
Miscellaneous Operands

#

y,x

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