Intel(R) 64 And IA 32 Architectures Software Developer's Manual, Volume 2A 253666 Intel64 Archtectures Developers Manual Insruction Set Reference, A M

• Chapter 1 About This Manual
  • 1.1 IA-32 Processors Covered in this Manual
  • 1.2 Overview of Volume 2A and 2B: Instruction Set Reference
  • 1.3 Notational Conventions
    • 1.3.1 Bit and Byte Order
    • 1.3.2 Reserved Bits and Software Compatibility
    • 1.3.3 Instruction Operands
    • 1.3.4 Hexadecimal and Binary Numbers
    • 1.3.5 Segmented Addressing
    • 1.3.6 Exceptions
    • 1.3.7 A New Syntax for CPUID, CR, and MSR Values
  • 1.4 Related Literature
• Chapter 2 Instruction Format
  • 2.1 Instruction Format for Protected Mode, real-address Mode, and virtual-8086 mode
    • 2.1.1 Instruction Prefixes
    • 2.1.2 Opcodes
    • 2.1.3 ModR/M and SIB Bytes
    • 2.1.4 Displacement and Immediate Bytes
    • 2.1.5 Addressing-Mode Encoding of ModR/M and SIB Bytes
  • 2.2 IA-32e Mode
    • 2.2.1 REX Prefixes
      • 2.2.1.1 Encoding
      • 2.2.1.2 More on REX Prefix Fields
      • 2.2.1.3 Displacement
      • 2.2.1.4 Direct Memory-Offset MOVs
      • 2.2.1.5 Immediates
      • 2.2.1.6 RIP-Relative Addressing
      • 2.2.1.7 Default 64-Bit Operand Size
    • 2.2.2 Additional Encodings for Control and Debug Registers
  • 2.3 INTEL® ADVANCED VECTOR EXTENSIONS (INTEL® AVX)
    • 2.3.1 Instruction Format
    • 2.3.2 VEX and the LOCK prefix
    • 2.3.3 VEX and the 66H, F2H, and F3H prefixes
    • 2.3.4 VEX and the REX prefix
    • 2.3.5 The VEX Prefix
      • 2.3.5.1 VEX Byte 0, bits[7:0]
      • 2.3.5.2 VEX Byte 1, bit [7] - ‘R’
      • 2.3.5.3 3-byte VEX byte 1, bit[6] - ‘X’
      • 2.3.5.4 3-byte VEX byte 1, bit[5] - ‘B’
      • 2.3.5.5 3-byte VEX byte 2, bit[7] - ‘W’
      • 2.3.5.6 2-byte VEX Byte 1, bits[6:3] and 3-byte VEX Byte 2, bits [6:3]- ‘vvvv’ the Source or dest Register Specifier
    • 2.3.6 Instruction Operand Encoding and VEX.vvvv, ModR/M
      • 2.3.6.1 3-byte VEX byte 1, bits[4:0] - “m-mmmm”
      • 2.3.6.2 2-byte VEX byte 1, bit[2], and 3-byte VEX byte 2, bit [2]- “L”
      • 2.3.6.3 2-byte VEX byte 1, bits[1:0], and 3-byte VEX byte 2, bits [1:0]- “pp”
    • 2.3.7 The Opcode Byte
    • 2.3.8 The MODRM, SIB, and Displacement Bytes
    • 2.3.9 The Third Source Operand (Immediate Byte)
    • 2.3.10 AVX Instructions and the Upper 128-bits of YMM registers
    • 2.3.11 AVX Instruction Length
  • 2.4 Instruction Exception Specification
    • 2.4.1 Exceptions Type 1 (Aligned memory reference)
    • 2.4.2 Exceptions Type 2 (>=16 Byte Memory Reference, Unaligned)
    • 2.4.3 Exceptions Type 3 (<16 Byte memory argument)
    • 2.4.4 Exceptions Type 4 (>=16 Byte mem arg no alignment, no floating-point exceptions)
    • 2.4.5 Exceptions Type 5 (<16 Byte mem arg and no FP exceptions)
    • 2.4.6 Exceptions Type 6 (VEX-Encoded Instructions Without Legacy SSE Analogues)
    • 2.4.7 Exceptions Type 7 (No FP exceptions, no memory arg)
    • 2.4.8 Exceptions Type 8 (AVX and no memory argument)
    • 2.4.9 Exception Type 9 (Intel AVX)
• Chapter 3 Instruction Set Reference, A-M
  • 3.1 Interpreting the Instruction Reference Pages
    • 3.1.1 Instruction Format
      • 3.1.1.1 Opcode Column in the Instruction Summary Table (Instructions without VEX prefix)
      • 3.1.1.2 Opcode Column in the Instruction Summary Table (Instructions with VEX prefix)
      • 3.1.1.3 Instruction Column in the Opcode Summary Table
      • 3.1.1.4 Operand Encoding Column in the Instruction Summary Table
      • 3.1.1.5 64/32-bit Mode Column in the Instruction Summary Table
      • 3.1.1.6 CPUID Support Column in the Instruction Summary Table
      • 3.1.1.7 Description Column in the Instruction Summary Table
      • 3.1.1.8 Description Section
      • 3.1.1.9 Operation Section
      • 3.1.1.10 Intel® C/C++ Compiler Intrinsics Equivalents Section
      • 3.1.1.11 Flags Affected Section
      • 3.1.1.12 FPU Flags Affected Section
      • 3.1.1.13 Protected Mode Exceptions Section
      • 3.1.1.14 Real-Address Mode Exceptions Section
      • 3.1.1.15 Virtual-8086 Mode Exceptions Section
      • 3.1.1.16 Floating-Point Exceptions Section
      • 3.1.1.17 SIMD Floating-Point Exceptions Section
      • 3.1.1.18 Compatibility Mode Exceptions Section
      • 3.1.1.19 64-Bit Mode Exceptions Section
  • 3.2 Instructions (A-M)
    • AAA-ASCII Adjust After Addition
    • AAD-ASCII Adjust AX Before Division
    • AAM-ASCII Adjust AX After Multiply
    • AAS-ASCII Adjust AL After Subtraction
    • ADC-Add with Carry
    • ADD-Add
    • ADDPD-Add Packed Double-Precision Floating-Point Values
    • ADDPS-Add Packed Single-Precision Floating-Point Values
    • ADDSD-Add Scalar Double-Precision Floating-Point Values
    • ADDSS-Add Scalar Single-Precision Floating-Point Values
    • ADDSUBPD-Packed Double-FP Add/Subtract
    • ADDSUBPS-Packed Single-FP Add/Subtract
    • AESDEC-Perform One Round of an AES Decryption Flow
    • AESDECLAST-Perform Last Round of an AES Decryption Flow
    • AESENC-Perform One Round of an AES Encryption Flow
    • AESENCLAST-Perform Last Round of an AES Encryption Flow
    • AESIMC-Perform the AES InvMixColumn Transformation
    • AESKEYGENASSIST-AES Round Key Generation Assist
    • AND-Logical AND
    • ANDPD-Bitwise Logical AND of Packed Double-Precision Floating- Point Values
    • ANDPS-Bitwise Logical AND of Packed Single-Precision Floating-Point Values
    • ANDNPD-Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values
    • ANDNPS-Bitwise Logical AND NOT of Packed Single-Precision Floating-Point Values
    • ARPL-Adjust RPL Field of Segment Selector
    • BLENDPD - Blend Packed Double Precision Floating-Point Values
    • BLENDPS - Blend Packed Single Precision Floating-Point Values
    • BLENDVPD - Variable Blend Packed Double Precision Floating-Point Values
    • BLENDVPS - Variable Blend Packed Single Precision Floating-Point Values
    • BOUND-Check Array Index Against Bounds
    • VBROADCAST-Load with Broadcast
    • BSF-Bit Scan Forward
    • BSR-Bit Scan Reverse
    • BSWAP-Byte Swap
    • BT-Bit Test
    • BTC-Bit Test and Complement
    • BTR-Bit Test and Reset
    • BTS-Bit Test and Set
    • CALL-Call Procedure
    • CBW/CWDE/CDQE-Convert Byte to Word/Convert Word to Doubleword/Convert Doubleword to Quadword
    • CLC-Clear Carry Flag
    • CLD-Clear Direction Flag
    • CLFLUSH-Flush Cache Line
    • CLI - Clear Interrupt Flag
    • CLTS-Clear Task-Switched Flag in CR0
    • CMC-Complement Carry Flag
    • CMOVcc-Conditional Move
    • CMP-Compare Two Operands
    • CMPPD-Compare Packed Double-Precision Floating-Point Values
    • CMPPS-Compare Packed Single-Precision Floating-Point Values
    • CMPS/CMPSB/CMPSW/CMPSD/CMPSQ-Compare String Operands
    • CMPSD-Compare Scalar Double-Precision Floating-Point Values
    • CMPSS-Compare Scalar Single-Precision Floating-Point Values
    • CMPXCHG-Compare and Exchange
    • CMPXCHG8B/CMPXCHG16B-Compare and Exchange Bytes
    • COMISD-Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS
    • COMISS-Compare Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGS
    • CPUID-CPU Identification
    • CRC32 - Accumulate CRC32 Value
    • CVTDQ2PD-Convert Packed Dword Integers to Packed Double- Precision FP Values
    • CVTDQ2PS-Convert Packed Dword Integers to Packed Single- Precision FP Values
    • CVTPD2DQ-Convert Packed Double-Precision FP Values to Packed Dword Integers
    • CVTPD2PI-Convert Packed Double-Precision FP Values to Packed Dword Integers
    • CVTPD2PS-Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values
    • CVTPI2PD-Convert Packed Dword Integers to Packed Double- Precision FP Values
    • CVTPI2PS-Convert Packed Dword Integers to Packed Single-Precision FP Values
    • CVTPS2DQ-Convert Packed Single-Precision FP Values to Packed Dword Integers
    • CVTPS2PD-Convert Packed Single-Precision FP Values to Packed Double-Precision FP Values
    • CVTPS2PI-Convert Packed Single-Precision FP Values to Packed Dword Integers
    • CVTSD2SI-Convert Scalar Double-Precision FP Value to Integer
    • CVTSD2SS-Convert Scalar Double-Precision FP Value to Scalar Single- Precision FP Value
    • CVTSI2SD-Convert Dword Integer to Scalar Double-Precision FP Value
    • CVTSI2SS-Convert Dword Integer to Scalar Single-Precision FP Value
    • CVTSS2SD-Convert Scalar Single-Precision FP Value to Scalar Double- Precision FP Value
    • CVTSS2SI-Convert Scalar Single-Precision FP Value to Dword Integer
    • CVTTPD2DQ-Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers
    • CVTTPD2PI-Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers
    • CVTTPS2DQ-Convert with Truncation Packed Single-Precision FP Values to Packed Dword Integers
    • CVTTPS2PI-Convert with Truncation Packed Single-Precision FP Values to Packed Dword Integers
    • CVTTSD2SI-Convert with Truncation Scalar Double-Precision FP Value to Signed Integer
    • CVTTSS2SI-Convert with Truncation Scalar Single-Precision FP Value to Dword Integer
    • CWD/CDQ/CQO-Convert Word to Doubleword/Convert Doubleword to Quadword
    • DAA-Decimal Adjust AL after Addition
    • DAS-Decimal Adjust AL after Subtraction
    • DEC-Decrement by 1
    • DIV-Unsigned Divide
    • DIVPD-Divide Packed Double-Precision Floating-Point Values
    • DIVPS-Divide Packed Single-Precision Floating-Point Values
    • DIVSD-Divide Scalar Double-Precision Floating-Point Values
    • DIVSS-Divide Scalar Single-Precision Floating-Point Values
    • DPPD - Dot Product of Packed Double Precision Floating-Point Values
    • DPPS - Dot Product of Packed Single Precision Floating-Point Values
    • EMMS-Empty MMX Technology State
    • ENTER-Make Stack Frame for Procedure Parameters
    • VEXTRACTF128 - Extract Packed Floating-Point Values
    • EXTRACTPS - Extract Packed Single Precision Floating-Point Value
    • F2XM1-Compute 2x-1
    • FABS-Absolute Value
    • FADD/FADDP/FIADD-Add
    • FBLD-Load Binary Coded Decimal
    • FBSTP-Store BCD Integer and Pop
    • FCHS-Change Sign
    • FCLEX/FNCLEX-Clear Exceptions
    • FCMOVcc-Floating-Point Conditional Move
    • FCOMI/FCOMIP/ FUCOMI/FUCOMIP-Compare Floating Point Values and Set EFLAGS
    • FCOS-Cosine
    • FDECSTP-Decrement Stack-Top Pointer
    • FDIV/FDIVP/FIDIV-Divide
    • FDIVR/FDIVRP/FIDIVR-Reverse Divide
    • FFREE-Free Floating-Point Register
    • FICOM/FICOMP-Compare Integer
    • FILD-Load Integer
    • FINCSTP-Increment Stack-Top Pointer
    • FINIT/FNINIT-Initialize Floating-Point Unit
    • FIST/FISTP-Store Integer
    • FISTTP-Store Integer with Truncation
    • FLD-Load Floating Point Value
    • FLD1/FLDL2T/FLDL2E/FLDPI/FLDLG2/FLDLN2/FLDZ-Load Constant
    • FLDCW-Load x87 FPU Control Word
    • FLDENV-Load x87 FPU Environment
    • FMUL/FMULP/FIMUL-Multiply
    • FNOP-No Operation
    • FPATAN-Partial Arctangent
    • FPREM-Partial Remainder
    • FPREM1-Partial Remainder
    • FPTAN-Partial Tangent
    • FRNDINT-Round to Integer
    • FRSTOR-Restore x87 FPU State
    • FSAVE/FNSAVE-Store x87 FPU State
    • FSCALE-Scale
    • FSIN-Sine
    • FSINCOS-Sine and Cosine
    • FSQRT-Square Root
    • FST/FSTP-Store Floating Point Value
    • FSTCW/FNSTCW-Store x87 FPU Control Word
    • FSTENV/FNSTENV-Store x87 FPU Environment
    • FSTSW/FNSTSW-Store x87 FPU Status Word
    • FSUB/FSUBP/FISUB-Subtract
    • FSUBR/FSUBRP/FISUBR-Reverse Subtract
    • FTST-TEST
    • FUCOM/FUCOMP/FUCOMPP-Unordered Compare Floating Point Values
    • FXAM-Examine ModR/M
    • FXCH-Exchange Register Contents
    • FXRSTOR-Restore x87 FPU, MMX , XMM, and MXCSR State
    • FXSAVE-Save x87 FPU, MMX Technology, and SSE State
    • FXTRACT-Extract Exponent and Significand
    • FYL2X-Compute y * log2x
    • FYL2XP1-Compute y * log2(x +1)
    • HADDPD-Packed Double-FP Horizontal Add
    • HADDPS-Packed Single-FP Horizontal Add
    • HLT-Halt
    • HSUBPD-Packed Double-FP Horizontal Subtract
    • HSUBPS-Packed Single-FP Horizontal Subtract
    • IDIV-Signed Divide
    • IMUL-Signed Multiply
    • IN-Input from Port
    • INC-Increment by 1
    • INS/INSB/INSW/INSD-Input from Port to String
    • VINSERTF128 - Insert Packed Floating-Point Values
    • INSERTPS - Insert Packed Single Precision Floating-Point Value
    • INT n/INTO/INT 3-Call to Interrupt Procedure
    • INVD-Invalidate Internal Caches
    • INVLPG-Invalidate TLB Entry
    • IRET/IRETD-Interrupt Return
    • Jcc-Jump if Condition Is Met
    • JMP-Jump
    • LAHF-Load Status Flags into AH Register
    • LAR-Load Access Rights Byte
    • LDDQU-Load Unaligned Integer 128 Bits
    • LDMXCSR-Load MXCSR Register
    • LDS/LES/LFS/LGS/LSS-Load Far Pointer
    • LEA-Load Effective Address
    • LEAVE-High Level Procedure Exit
    • LFENCE-Load Fence
    • LGDT/LIDT-Load Global/Interrupt Descriptor Table Register
    • LLDT-Load Local Descriptor Table Register
    • LMSW-Load Machine Status Word
    • LOCK-Assert LOCK# Signal Prefix
    • LODS/LODSB/LODSW/LODSD/LODSQ-Load String
    • LOOP/LOOPcc-Loop According to ECX Counter
    • LSL-Load Segment Limit
    • LTR-Load Task Register
    • MASKMOVDQU-Store Selected Bytes of Double Quadword
    • VMASKMOV-Conditional SIMD Packed Loads and Stores
    • MASKMOVQ-Store Selected Bytes of Quadword
    • MAXPD-Return Maximum Packed Double-Precision Floating-Point Values
    • MAXPS-Return Maximum Packed Single-Precision Floating-Point Values
    • MAXSD-Return Maximum Scalar Double-Precision Floating-Point Value
    • MAXSS-Return Maximum Scalar Single-Precision Floating-Point Value
    • MFENCE-Memory Fence
    • MINPD-Return Minimum Packed Double-Precision Floating-Point Values
    • MINPS-Return Minimum Packed Single-Precision Floating-Point Values
    • MINSD-Return Minimum Scalar Double-Precision Floating-Point Value
    • MINSS-Return Minimum Scalar Single-Precision Floating-Point Value
    • MONITOR-Set Up Monitor Address
    • MOV-Move
    • MOV-Move to/from Control Registers
    • MOV-Move to/from Debug Registers
    • MOVAPD-Move Aligned Packed Double-Precision Floating-Point Values
    • MOVAPS-Move Aligned Packed Single-Precision Floating-Point Values
    • MOVBE-Move Data After Swapping Bytes
    • MOVD/MOVQ-Move Doubleword/Move Quadword
    • MOVDDUP-Move One Double-FP and Duplicate
    • MOVDQA-Move Aligned Double Quadword
    • MOVDQU-Move Unaligned Double Quadword
    • MOVDQ2Q-Move Quadword from XMM to MMX Technology Register
    • MOVHLPS- Move Packed Single-Precision Floating-Point Values High to Low
    • MOVHPD-Move High Packed Double-Precision Floating-Point Value
    • MOVHPS-Move High Packed Single-Precision Floating-Point Values
    • MOVLHPS-Move Packed Single-Precision Floating-Point Values Low to High
    • MOVLPD-Move Low Packed Double-Precision Floating-Point Value
    • MOVLPS-Move Low Packed Single-Precision Floating-Point Values
    • MOVMSKPD-Extract Packed Double-Precision Floating-Point Sign Mask
    • MOVMSKPS-Extract Packed Single-Precision Floating-Point Sign Mask
    • MOVNTDQA - Load Double Quadword Non-Temporal Aligned Hint
    • MOVNTDQ-Store Double Quadword Using Non-Temporal Hint
    • MOVNTI-Store Doubleword Using Non-Temporal Hint
    • MOVNTPD-Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint
    • MOVNTPS-Store Packed Single-Precision Floating-Point Values Using Non-Temporal Hint
    • MOVNTQ-Store of Quadword Using Non-Temporal Hint
    • MOVQ-Move Quadword
    • MOVQ2DQ-Move Quadword from MMX Technology to XMM Register
    • MOVS/MOVSB/MOVSW/MOVSD/MOVSQ-Move Data from String to String
    • MOVSD-Move Scalar Double-Precision Floating-Point Value
    • MOVSHDUP-Move Packed Single-FP High and Duplicate
    • MOVSLDUP-Move Packed Single-FP Low and Duplicate
    • MOVSS-Move Scalar Single-Precision Floating-Point Values
    • MOVSX/MOVSXD-Move with Sign-Extension
    • MOVUPD-Move Unaligned Packed Double-Precision Floating-Point Values
    • MOVUPS-Move Unaligned Packed Single-Precision Floating-Point Values
    • MOVZX-Move with Zero-Extend
    • MPSADBW - Compute Multiple Packed Sums of Absolute Difference
    • MUL-Unsigned Multiply
    • MULPD-Multiply Packed Double-Precision Floating-Point Values
    • MULPS-Multiply Packed Single-Precision Floating-Point Values
    • MULSD-Multiply Scalar Double-Precision Floating-Point Values
    • MULSS-Multiply Scalar Single-Precision Floating-Point Values
    • MWAIT-Monitor Wait