ATmega8A Datasheet Atmel 8159 8 Bit Avr Microcontroller

2017-12-16

• Introduction
• Features
• Table of Contents
• 1. Description
• 2. Configuration Summary
• 3. Ordering Information
• 4. Block Diagram
• 5. Pin Configurations
  • 5.1. Pin Descriptions
    • 5.1.1. VCC
    • 5.1.2. GND
    • 5.1.3. Port B (PB7:PB0) – XTAL1/XTAL2/TOSC1/TOSC2
    • 5.1.4. Port C (PC5:PC0)
    • 5.1.5. PC6/RESET
    • 5.1.6. Port D (PD7:PD0)
    • 5.1.7. RESET
    • 5.1.8. AVCC
    • 5.1.9. AREF
    • 5.1.10. ADC7:6 (TQFP and QFN/MLF Package Only)
  • 5.2. Accessing 16-bit Registers
• 6. I/O Multiplexing
• 7. Resources
• 8. Data Retention
• 9. About Code Examples
• 10. Capacitive Touch Sensing
• 11. AVR CPU Core
  • 11.1. Overview
  • 11.2. ALU – Arithmetic Logic Unit
  • 11.3. Status Register
    • 11.3.1. SREG – The AVR Status Register
  • 11.4. General Purpose Register File
    • 11.4.1. The X-register, Y-register and Z-register
  • 11.5. Stack Pointer
    • 11.5.1. SPH and SPL - Stack Pointer High and Stack Pointer Low Register
  • 11.6. Instruction Execution Timing
  • 11.7. Reset and Interrupt Handling
    • 11.7.1. Interrupt Response Time
• 12. AVR Memories
  • 12.1. Overview
  • 12.2. In-System Reprogrammable Flash Program Memory
  • 12.3. SRAM Data Memory
    • 12.3.1. Data Memory Access Times
  • 12.4. EEPROM Data Memory
    • 12.4.1. EEPROM Read/Write Access
    • 12.4.2. EEPROM Write during Power-down Sleep Mode
    • 12.4.3. Preventing EEPROM Corruption
  • 12.5. I/O Memory
  • 12.6. Register Description
    • 12.6.1. EEARL – The EEPROM Address Register Low
    • 12.6.2. EEARH – The EEPROM Address Register High
    • 12.6.3. EEDR – The EEPROM Data Register
    • 12.6.4. EECR – The EEPROM Control Register
• 13. System Clock and Clock Options
  • 13.1. Clock Systems and their Distribution
    • 13.1.1. CPU Clock – clkCPU
    • 13.1.2. I/O Clock – clkI/O
    • 13.1.3. Flash Clock – clkFLASH
    • 13.1.4. Asynchronous Timer Clock – clkASY
    • 13.1.5. ADC Clock – clkADC
  • 13.2. Clock Sources
  • 13.3. Crystal Oscillator
  • 13.4. Low-frequency Crystal Oscillator
  • 13.5. External RC Oscillator
  • 13.6. Calibrated Internal RC Oscillator
  • 13.7. External Clock
  • 13.8. Timer/Counter Oscillator
  • 13.9. Register Description
    • 13.9.1. OSCCAL – The Oscillator Calibration Register
• 14. Power Management and Sleep Modes
  • 14.1. Sleep Modes
  • 14.2. Idle Mode
  • 14.3. ADC Noise Reduction Mode
  • 14.4. Power-down Mode
  • 14.5. Power-save Mode
  • 14.6. Standby Mode
  • 14.7. Minimizing Power Consumption
    • 14.7.1. Analog-to-Digital Converter (ADC)
    • 14.7.2. Analog Comparator
    • 14.7.3. Brown-out Detector
    • 14.7.4. Internal Voltage Reference
    • 14.7.5. Watchdog Timer
    • 14.7.6. Port Pins
  • 14.8. Register Description
    • 14.8.1. MCUCR – MCU Control Register
• 15. System Control and Reset
  • 15.1. Resetting the AVR
  • 15.2. Reset Sources
    • 15.2.1. Power-on Reset
    • 15.2.2. External Reset
    • 15.2.3. Brown-out Detection
    • 15.2.4. Watchdog Reset
  • 15.3. Internal Voltage Reference
    • 15.3.1. Voltage Reference Enable Signals and Start-up Time
  • 15.4. Watchdog Timer
  • 15.5. Timed Sequences for Changing the Configuration of the Watchdog Timer
    • 15.5.1. Safety Level 1 (WDTON Fuse Unprogrammed)
    • 15.5.2. Safety Level 2 (WDTON Fuse Programmed)
  • 15.6. Register Description
    • 15.6.1. MCUCSR – MCU Control and Status Register
    • 15.6.2. WDTCR – Watchdog Timer Control Register
• 16. Interrupts
  • 16.1. Interrupt Vectors in ATmega8A
    • 16.1.1. Moving Interrupts Between Application and Boot Space
  • 16.2. Register Description
    • 16.2.1. GICR – General Interrupt Control Register
• 17. External Interrupts
  • 17.1. Register Description
    • 17.1.1. MCUCR – MCU Control Register
    • 17.1.2. GICR – General Interrupt Control Register
    • 17.1.3. GIFR – General Interrupt Flag Register
• 18. I/O Ports
  • 18.1. Overview
  • 18.2. Ports as General Digital I/O
    • 18.2.1. Configuring the Pin
    • 18.2.2. Reading the Pin Value
    • 18.2.3. Digital Input Enable and Sleep Modes
    • 18.2.4. Unconnected Pins
  • 18.3. Alternate Port Functions
    • 18.3.1. Alternate Functions of Port B
    • 18.3.2. Alternate Functions of Port C
    • 18.3.3. Alternate Functions of Port D
  • 18.4. Register Description
    • 18.4.1. SFIOR – Special Function IO Register
    • 18.4.2. PORTB – The Port B Data Register
    • 18.4.3. DDRB – The Port B Data Direction Register
    • 18.4.4. PINB – The Port B Input Pins Address
    • 18.4.5. PORTC – The Port C Data Register
    • 18.4.6. DDRC – The Port C Data Direction Register
    • 18.4.7. PINC – The Port C Input Pins Address
    • 18.4.8. PORTD – The Port D Data Register
    • 18.4.9. DDRD – The Port D Data Direction Register
    • 18.4.10. PIND – The Port D Input Pins Address
• 19. 8-bit Timer/Counter0
  • 19.1. Features
  • 19.2. Overview
    • 19.2.1. Registers
    • 19.2.2. Definitions
  • 19.3. Timer/Counter Clock Sources
  • 19.4. Counter Unit
  • 19.5. Operation
  • 19.6. Timer/Counter Timing Diagrams
  • 19.7. Register Description
    • 19.7.1. TCCR0 – Timer/Counter Control Register
    • 19.7.2. TCNT0 – Timer/Counter Register
    • 19.7.3. TIMSK – Timer/Counter Interrupt Mask Register
    • 19.7.4. TIFR – Timer/Counter Interrupt Flag Register
• 20. Timer/Counter0 and Timer/Counter1 Prescalers
  • 20.1. Overview
  • 20.2. Internal Clock Source
  • 20.3. Prescaler Reset
  • 20.4. External Clock Source
  • 20.5. Register Description
    • 20.5.1. SFIOR – Special Function IO Register
• 21. 16-bit Timer/Counter1
  • 21.1. Features
  • 21.2. Overview
    • 21.2.1. Registers
    • 21.2.2. Definitions
    • 21.2.3. Compatibility
  • 21.3. Accessing 16-bit Registers
    • 21.3.1. Reusing the Temporary High Byte Register
  • 21.4. Timer/Counter Clock Sources
  • 21.5. Counter Unit
  • 21.6. Input Capture Unit
    • 21.6.1. Input Capture Pin Source
    • 21.6.2. Noise Canceler
    • 21.6.3. Using the Input Capture Unit
  • 21.7. Output Compare Units
    • 21.7.1. Force Output Compare
    • 21.7.2. Compare Match Blocking by TCNT1 Write
    • 21.7.3. Using the Output Compare Unit
  • 21.8. Compare Match Output Unit
    • 21.8.1. Compare Output Mode and Waveform Generation
  • 21.9. Modes of Operation
    • 21.9.1. Normal Mode
    • 21.9.2. Clear Timer on Compare Match (CTC) Mode
    • 21.9.3. Fast PWM Mode
    • 21.9.4. Phase Correct PWM Mode
    • 21.9.5. Phase and Frequency Correct PWM Mode
  • 21.10. Timer/Counter Timing Diagrams
  • 21.11. Register Description
    • 21.11.1. TCCR1A – Timer/Counter1 Control Register A
    • 21.11.2. TCCR1B – Timer/Counter1 Control Register B
    • 21.11.3. TCNT1L – Timer/Counter1 Low byte
    • 21.11.4. TCNT1H – Timer/Counter1 High byte
    • 21.11.5. OCR1AL – Output Compare Register 1 A Low byte
    • 21.11.6. OCR1AH – Output Compare Register 1 A High byte
    • 21.11.7. OCR1BL – Output Compare Register 1 B Low byte
    • 21.11.8. OCR1BH – Output Compare Register 1 B High byte
    • 21.11.9. ICR1L – Input Capture Register 1 Low byte
    • 21.11.10. ICR1H – Input Capture Register 1 High byte
    • 21.11.11. TIMSK – Timer/Counter Interrupt Mask Register
    • 21.11.12. TIFR – Timer/Counter Interrupt Flag Register
• 22. 8-bit Timer/Counter2 with PWM and Asynchronous Operation
  • 22.1. Features
  • 22.2. Overview
    • 22.2.1. Registers
    • 22.2.2. Definitions
  • 22.3. Timer/Counter Clock Sources
  • 22.4. Counter Unit
  • 22.5. Output Compare Unit
    • 22.5.1. Force Output Compare
    • 22.5.2. Compare Match Blocking by TCNT2 Write
    • 22.5.3. Using the Output Compare Unit
  • 22.6. Compare Match Output Unit
    • 22.6.1. Compare Output Mode and Waveform Generation
  • 22.7. Modes of Operation
    • 22.7.1. Normal Mode
    • 22.7.2. Clear Timer on Compare Match (CTC) Mode
    • 22.7.3. Fast PWM Mode
    • 22.7.4. Phase Correct PWM Mode
  • 22.8. Timer/Counter Timing Diagrams
  • 22.9. Asynchronous Operation of the Timer/Counter
    • 22.9.1. Asynchronous Operation of Timer/Counter2
  • 22.10. Timer/Counter Prescaler
  • 22.11. Register Description
    • 22.11.1. TCCR2 – Timer/Counter Control Register
    • 22.11.2. TCNT2 – Timer/Counter Register
    • 22.11.3. OCR2 – Output Compare Register
    • 22.11.4. ASSR – Asynchronous Status Register
    • 22.11.5. TIMSK – Timer/Counter Interrupt Mask Register
    • 22.11.6. TIFR – Timer/Counter Interrupt Flag Register
    • 22.11.7. SFIOR – Special Function IO Register
• 23. SPI – Serial Peripheral Interface
  • 23.1. Features
  • 23.2. Overview
  • 23.3. SS Pin Functionality
    • 23.3.1. Slave Mode
    • 23.3.2. Master Mode
  • 23.4. Data Modes
  • 23.5. Register Description
    • 23.5.1. SPCR – SPI Control Register
    • 23.5.2. SPSR – SPI Status Register
    • 23.5.3. SPDR – SPI Data Register is a read/write register
• 24. USART - Universal Synchronous and Asynchronous serial Receiver and Transmitter
  • 24.1. Features
  • 24.2. Overview
    • 24.2.1. AVR USART vs. AVR UART – Compatibility
  • 24.3. Clock Generation
    • 24.3.1. Internal Clock Generation – The Baud Rate Generator
    • 24.3.2. Double Speed Operation (U2X)
    • 24.3.3. External Clock
    • 24.3.4. Synchronous Clock Operation
  • 24.4. Frame Formats
    • 24.4.1. Parity Bit Calculation
  • 24.5. USART Initialization
  • 24.6. Data Transmission – The USART Transmitter
    • 24.6.1. Sending Frames with 5 to 8 Data Bits
    • 24.6.2. Sending Frames with 9 Data Bits
    • 24.6.3. Transmitter Flags and Interrupts
    • 24.6.4. Parity Generator
    • 24.6.5. Disabling the Transmitter
  • 24.7. Data Reception – The USART Receiver
    • 24.7.1. Receiving Frames with 5 to 8 Data Bits
    • 24.7.2. Receiving Frames with 9 Data Bits
    • 24.7.3. Receive Compete Flag and Interrupt
    • 24.7.4. Receiver Error Flags
    • 24.7.5. Parity Checker
    • 24.7.6. Disabling the Receiver
    • 24.7.7. Flushing the Receive Buffer
  • 24.8. Asynchronous Data Reception
    • 24.8.1. Asynchronous Clock Recovery
    • 24.8.2. Asynchronous Data Recovery
    • 24.8.3. Asynchronous Operational Range
  • 24.9. Multi-Processor Communication Mode
    • 24.9.1. Using MPCM
  • 24.10. Accessing UBRRH/UCSRC Registers
    • 24.10.1. Write Access
    • 24.10.2. Read Access
  • 24.11. Register Description
    • 24.11.1. UDR – USART I/O Data Register
    • 24.11.2. UCSRA – USART Control and Status Register A
    • 24.11.3. UCSRB – USART Control and Status Register B
    • 24.11.4. UCSRC – USART Control and Status Register C
    • 24.11.5. UBRRL – USART Baud Rate Register Low
    • 24.11.6. UBBRH – USART Baud Rate Register High
  • 24.12. Examples of Baud Rate Setting
• 25. TWI - Two-wire Serial Interface
  • 25.1. Features
  • 25.2. Overview
    • 25.2.1. SCL and SDA Pins
    • 25.2.2. Bit Rate Generator Unit
    • 25.2.3. Bus Interface Unit
    • 25.2.4. Address Match Unit
    • 25.2.5. Control Unit
  • 25.3. Two-Wire Serial Interface Bus Definition
    • 25.3.1. TWI Terminology
    • 25.3.2. Electrical Interconnection
  • 25.4. Data Transfer and Frame Format
    • 25.4.1. Transferring Bits
    • 25.4.2. START and STOP Conditions
    • 25.4.3. Address Packet Format
    • 25.4.4. Data Packet Format
    • 25.4.5. Combining Address and Data Packets Into a Transmission
  • 25.5. Multi-master Bus Systems, Arbitration and Synchronization
  • 25.6. Using the TWI
    • 25.6.1. Transmission Modes
    • 25.6.2. Master Transmitter Mode
    • 25.6.3. Master Receiver Mode
    • 25.6.4. Slave Receiver Mode
    • 25.6.5. Slave Transmitter Mode
    • 25.6.6. Miscellaneous States
    • 25.6.7. Combining Several TWI Modes
  • 25.7. Multi-master Systems and Arbitration
  • 25.8. Register Description
    • 25.8.1. TWBR – TWI Bit Rate Register
    • 25.8.2. TWCR – TWI Control Register
    • 25.8.3. TWSR – TWI Status Register
    • 25.8.4. TWDR – TWI Data Register
    • 25.8.5. TWAR – TWI (Slave) Address Register
• 26. Analog Comparator
  • 26.1. Overview
  • 26.2. Analog Comparator Multiplexed Input
  • 26.3. Register Description
    • 26.3.1. SFIOR – Analog Comparator Control and Status Register
    • 26.3.2. ACSR – Analog Comparator Control and Status Register
• 27. ADC - Analog to Digital Converter
  • 27.1. Features
  • 27.2. Overview
  • 27.3. Starting a Conversion
  • 27.4. Prescaling and Conversion Timing
  • 27.5. Changing Channel or Reference Selection
    • 27.5.1. ADC Input Channels
    • 27.5.2. ADC Voltage Reference
  • 27.6. ADC Noise Canceler
    • 27.6.1. Analog Input Circuitry
    • 27.6.2. Analog Noise Canceling Techniques
    • 27.6.3. ADC Accuracy Definitions
  • 27.7. ADC Conversion Result
  • 27.8. Register Description
    • 27.8.1. ADMUX – ADC Multiplexer Selection Register
    • 27.8.2. ADCSRA – ADC Control and Status Register A
    • 27.8.3. ADCL – ADC Data Register Low (ADLAR=0)
    • 27.8.4. ADCH – ADC Data Register High (ADLAR=0)
    • 27.8.5. ADCL – ADC Data Register Low (ADLAR=1)
    • 27.8.6. ADCH – ADC Data Register High (ADLAR=1)
• 28. Boot Loader Support – Read-While-Write Self-Programming
  • 28.1. Features
  • 28.2. Overview
  • 28.3. Application and Boot Loader Flash Sections
    • 28.3.1. Application Section
    • 28.3.2. BLS – Boot Loader Section
  • 28.4. Read-While-Write and No Read-While-Write Flash Sections
    • 28.4.1. RWW – Read-While-Write Section
    • 28.4.2. NRWW – No Read-While-Write Section
  • 28.5. Boot Loader Lock Bits
  • 28.6. Entering the Boot Loader Program
  • 28.7. Addressing the Flash During Self-Programming
  • 28.8. Self-Programming the Flash
    • 28.8.1. Performing Page Erase by SPM
    • 28.8.2. Filling the Temporary Buffer (Page Loading)
    • 28.8.3. Performing a Page Write
    • 28.8.4. Using the SPM Interrupt
    • 28.8.5. Consideration While Updating Boot Loader Section (BLS)
    • 28.8.6. Prevent Reading the RWW Section During Self-Programming
    • 28.8.7. Setting the Boot Loader Lock Bits by SPM
    • 28.8.8. EEPROM Write Prevents Writing to SPMCR
    • 28.8.9. Reading the Fuse and Lock Bits from Software
    • 28.8.10. Preventing Flash Corruption
    • 28.8.11. Programming Time for Flash when Using SPM
    • 28.8.12. Simple Assembly Code Example for a Boot Loader
    • 28.8.13. ATmega8A Boot Loader Parameters
  • 28.9. Register Description
    • 28.9.1. SPMCR – Store Program Memory Control Register
• 29. Memory Programming
  • 29.1. Program and Data Memory Lock Bits
  • 29.2. Fuse Bits
    • 29.2.1. Latching of Fuses
  • 29.3. Signature Bytes
  • 29.4. Calibration Byte
  • 29.5. Page Size
  • 29.6. Parallel Programming Parameters, Pin Mapping, and Commands
    • 29.6.1. Signal Names
  • 29.7. Parallel Programming
    • 29.7.1. Enter Programming Mode
    • 29.7.2. Considerations for Efficient Programming
    • 29.7.3. Chip Erase
    • 29.7.4. Programming the Flash
    • 29.7.5. Programming the EEPROM
    • 29.7.6. Reading the Flash
    • 29.7.7. Reading the EEPROM
    • 29.7.8. Programming the Fuse Low Bits
    • 29.7.9. Programming the Fuse High Bits
    • 29.7.10. Programming the Lock Bits
    • 29.7.11. Reading the Fuse and Lock Bits
    • 29.7.12. Reading the Signature Bytes
    • 29.7.13. Reading the Calibration Byte
    • 29.7.14. Parallel Programming Characteristics
  • 29.8. Serial Downloading
  • 29.9. Serial Programming Pin Mapping
    • 29.9.1. Serial Programming Algorithm
    • 29.9.2. Data Polling Flash
    • 29.9.3. Data Polling EEPROM
    • 29.9.4. SPI Serial Programming Characteristics
• 30. Electrical Characteristics – TA = -40°C to 85°C
  • 30.1. DC Characteristics
  • 30.2. Speed Grades
  • 30.3. Clock Characteristics
    • 30.3.1. External Clock Drive Waveforms
    • 30.3.2. External Clock Drive
  • 30.4. System and Reset Characteristics
  • 30.5. Two-wire Serial Interface Characteristics
  • 30.6. SPI Timing Characteristics
  • 30.7. ADC Characteristics
• 31. Electrical Characteristics – TA = -40°C to 105°C
  • 31.1. DC Characteristics
• 32. Typical Characteristics – TA = -40°C to 85°C
  • 32.1. Active Supply Current
  • 32.2. Idle Supply Current
  • 32.3. Power-down Supply Current
  • 32.4. Power-save Supply Current
  • 32.5. Standby Supply Current
  • 32.6. Pin Pull-up
  • 32.7. Pin Driver Strength
  • 32.8. Pin Thresholds and Hysteresis
  • 32.9. Bod Thresholds and Analog Comparator Offset
  • 32.10. Internal Oscillator Speed
  • 32.11. Current Consumption of Peripheral Units
  • 32.12. Current Consumption in Reset and Reset Pulsewidth
• 33. Typical Characteristics – TA = -40°C to 105°C
  • 33.1. ATmega8A Typical Characteristics
    • 33.1.1. Active Supply Current
    • 33.1.2. Idle Supply Current
    • 33.1.3. Power-down Supply Current
    • 33.1.4. Power-save Supply Current
    • 33.1.5. Standby Supply Current
    • 33.1.6. Pin Pull-up
    • 33.1.7. Pin Driver Strength
    • 33.1.8. Pin Threshold and Hysteresis
    • 33.1.9. BOD Threshold
    • 33.1.10. Internal Oscillator Speed
    • 33.1.11. Current Consumption of Peripheral Units
    • 33.1.12. Current Consumption in Reset and Reset Pulsewidth
• 34. Register Summary
• 35. Instruction Set Summary
• 36. Packaging Information
  • 36.1. 32A
  • 36.2. 28P3
  • 36.3. 32M1-A
• 37. Errata
  • 37.1. ATmega8A, rev. L
• 38. Datasheet Revision History
  • 38.1. Rev.8159F – 07/2015
  • 38.2. Rev.8159E – 02/2013
  • 38.3. Rev.8159D – 02/11
  • 38.4. DRH_Rev.8159C – 07/09
  • 38.5. Rev.8159B – 05/09
  • 38.6. Rev.8159A – 08/08