ATmega8A Datasheet Atmel 8159 8 Bit Avr Microcontroller

2017-12-16

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8-bit AVR Microcontroller

ATmega8A
DATASHEET COMPLETE

Introduction
®

The Atmel ATmega8A is a low-power CMOS 8-bit microcontroller based on
®
the AVR enhanced RISC architecture. By executing powerful instructions in
a single clock cycle, the ATmega8A achieves throughputs close to 1MIPS
per MHz. This empowers system designer to optimize the device for power
consumption versus processing speed.

Features
•
•

•

High-performance, Low-power Atmel AVR 8-bit Microcontroller
Advanced RISC Architecture
– 130 Powerful Instructions - Most Single-clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16MIPS Throughput at 16MHz
– On-chip 2-cycle Multiplier
High Endurance Non-volatile Memory segments
– 8KBytes of In-System Self-programmable Flash program
memory
– 512Bytes EEPROM
– 1KByte Internal SRAM
– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C(1)
– Optional Boot Code Section with Independent Lock Bits
• In-System Programming by On-chip Boot Program
• True Read-While-Write Operation
– Programming Lock for Software Security
Atmel QTouch® library support
– Capacitive touch buttons, sliders and wheels
– Atmel QTouch and QMatrix acquisition
– Up to 64 sense channels
Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescaler, one Compare
Mode

Atmel-8159F-8-bit AVR Microcontroller_Datasheet_Complete-09/2015

–
–
–
–
–
–

•

•
•
•

One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode
Real Time Counter with Separate Oscillator
Three PWM Channels
8-channel ADC in TQFP and QFN/MLF package
• Eight Channels 10-bit Accuracy
6-channel ADC in PDIP package
• Six Channels 10-bit Accuracy
Byte-oriented Two-wire Serial Interface

– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and Standby
I/O and Packages
– 23 Programmable I/O Lines
– 28-lead PDIP, 32-lead TQFP, and 32-pad QFN/MLF
Operating Voltages
– 2.7 - 5.5V
Speed Grades
– 0 - 16MHz
Power Consumption at 4MHz, 3V, 25°C
– Active: 3.6mA
– Idle Mode: 1.0mA
– Power-down Mode: 0.5μA

Atmel ATmega8A [DATASHEET]
Atmel-8159F-8-bit AVR Microcontroller_Datasheet_Complete-09/2015

Table of Contents
Introduction......................................................................................................................1
Features.......................................................................................................................... 1
1. Description.................................................................................................................9
2. Configuration Summary........................................................................................... 10
3. Ordering Information................................................................................................ 11
4. Block Diagram......................................................................................................... 12
5. Pin Configurations................................................................................................... 13
5.1.
5.2.

Pin Descriptions..........................................................................................................................15
Accessing 16-bit Registers.........................................................................................................17

6. I/O Multiplexing........................................................................................................ 20
7. Resources................................................................................................................21
8. Data Retention.........................................................................................................22
9. About Code Examples............................................................................................. 23
10. Capacitive Touch Sensing....................................................................................... 24
11. AVR CPU Core........................................................................................................ 25
11.1.
11.2.
11.3.
11.4.
11.5.

Overview.....................................................................................................................................25
ALU – Arithmetic Logic Unit........................................................................................................26
Status Register...........................................................................................................................26
General Purpose Register File................................................................................................... 28
Stack Pointer.............................................................................................................................. 29

11.6. Instruction Execution Timing...................................................................................................... 30
11.7. Reset and Interrupt Handling..................................................................................................... 31

12. AVR Memories.........................................................................................................33
12.1. Overview.....................................................................................................................................33
12.2.
12.3.
12.4.
12.5.
12.6.

In-System Reprogrammable Flash Program Memory................................................................ 33
SRAM Data Memory...................................................................................................................34
EEPROM Data Memory............................................................................................................. 35
I/O Memory.................................................................................................................................36
Register Description................................................................................................................... 37

13. System Clock and Clock Options............................................................................ 44
13.1. Clock Systems and their Distribution..........................................................................................44
13.2. Clock Sources............................................................................................................................ 45
13.3. Crystal Oscillator........................................................................................................................ 46

13.4. Low-frequency Crystal Oscillator................................................................................................47
13.5.
13.6.
13.7.
13.8.
13.9.

External RC Oscillator................................................................................................................ 48
Calibrated Internal RC Oscillator................................................................................................48
External Clock............................................................................................................................ 49
Timer/Counter Oscillator.............................................................................................................50
Register Description................................................................................................................... 50

14. Power Management and Sleep Modes................................................................... 52
14.1.
14.2.
14.3.
14.4.
14.5.
14.6.
14.7.
14.8.

Sleep Modes...............................................................................................................................52
Idle Mode....................................................................................................................................53
ADC Noise Reduction Mode.......................................................................................................53
Power-down Mode......................................................................................................................53
Power-save Mode.......................................................................................................................53
Standby Mode............................................................................................................................ 54
Minimizing Power Consumption................................................................................................. 54
Register Description................................................................................................................... 55

15. System Control and Reset.......................................................................................57
15.1.
15.2.
15.3.
15.4.
15.5.
15.6.

Resetting the AVR...................................................................................................................... 57
Reset Sources............................................................................................................................57
Internal Voltage Reference.........................................................................................................60
Watchdog Timer......................................................................................................................... 61
Timed Sequences for Changing the Configuration of the Watchdog Timer............................... 61
Register Description................................................................................................................... 62

16. Interrupts................................................................................................................. 66
16.1. Interrupt Vectors in ATmega8A...................................................................................................66
16.2. Register Description................................................................................................................... 70

17. External Interrupts................................................................................................... 73
17.1. Register Description................................................................................................................... 73

18. I/O Ports.................................................................................................................. 77
18.1.
18.2.
18.3.
18.4.

Overview.....................................................................................................................................77
Ports as General Digital I/O........................................................................................................78
Alternate Port Functions.............................................................................................................81
Register Description................................................................................................................... 90

19. 8-bit Timer/Counter0..............................................................................................101
19.1.
19.2.
19.3.
19.4.
19.5.
19.6.
19.7.

Features................................................................................................................................... 101
Overview...................................................................................................................................101
Timer/Counter Clock Sources.................................................................................................. 102
Counter Unit............................................................................................................................. 102
Operation..................................................................................................................................103
Timer/Counter Timing Diagrams...............................................................................................103
Register Description................................................................................................................. 103

20. Timer/Counter0 and Timer/Counter1 Prescalers................................................... 108
20.1. Overview...................................................................................................................................108

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20.2. Internal Clock Source............................................................................................................... 108
20.3. Prescaler Reset........................................................................................................................108
20.4. External Clock Source..............................................................................................................108
20.5. Register Description................................................................................................................. 109

21. 16-bit Timer/Counter1............................................................................................ 111
21.1. Features....................................................................................................................................111
21.2. Overview................................................................................................................................... 111
21.3. Accessing 16-bit Registers....................................................................................................... 113
21.4. Timer/Counter Clock Sources...................................................................................................116
21.5. Counter Unit..............................................................................................................................116
21.6. Input Capture Unit.....................................................................................................................117
21.7. Output Compare Units.............................................................................................................. 119
21.8. Compare Match Output Unit.....................................................................................................121
21.9. Modes of Operation..................................................................................................................122
21.10. Timer/Counter Timing Diagrams.............................................................................................. 130
21.11. Register Description................................................................................................................. 131

22. 8-bit Timer/Counter2 with PWM and Asynchronous Operation............................. 147
22.1. Features................................................................................................................................... 147
22.2. Overview...................................................................................................................................147
22.3. Timer/Counter Clock Sources.................................................................................................. 148
22.4. Counter Unit............................................................................................................................. 148
22.5. Output Compare Unit................................................................................................................149
22.6. Compare Match Output Unit.....................................................................................................151
22.7. Modes of Operation..................................................................................................................152
22.8. Timer/Counter Timing Diagrams...............................................................................................156
22.9. Asynchronous Operation of the Timer/Counter........................................................................ 158
22.10. Timer/Counter Prescaler.......................................................................................................... 159
22.11. Register Description................................................................................................................. 160

23. SPI – Serial Peripheral Interface........................................................................... 170
23.1.
23.2.
23.3.
23.4.
23.5.

Features................................................................................................................................... 170
Overview...................................................................................................................................170
SS Pin Functionality................................................................................................................. 173
Data Modes.............................................................................................................................. 174
Register Description................................................................................................................. 175

24. USART - Universal Synchronous and Asynchronous serial Receiver and
Transmitter.............................................................................................................180
24.1.
24.2.
24.3.
24.4.
24.5.
24.6.
24.7.
24.8.
24.9.

Features................................................................................................................................... 180
Overview...................................................................................................................................180
Clock Generation......................................................................................................................182
Frame Formats.........................................................................................................................185
USART Initialization..................................................................................................................186
Data Transmission – The USART Transmitter......................................................................... 187
Data Reception – The USART Receiver.................................................................................. 190
Asynchronous Data Reception.................................................................................................193
Multi-Processor Communication Mode.....................................................................................196

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24.10. Accessing UBRRH/UCSRC Registers..................................................................................... 197
24.11. Register Description................................................................................................................. 198
24.12. Examples of Baud Rate Setting............................................................................................... 207

25. TWI - Two-wire Serial Interface..............................................................................211
25.1.
25.2.
25.3.
25.4.
25.5.
25.6.
25.7.
25.8.

Features....................................................................................................................................211
Overview...................................................................................................................................211
Two-Wire Serial Interface Bus Definition..................................................................................213
Data Transfer and Frame Format.............................................................................................214
Multi-master Bus Systems, Arbitration and Synchronization....................................................217
Using the TWI...........................................................................................................................218
Multi-master Systems and Arbitration.......................................................................................235
Register Description................................................................................................................. 236

26. Analog Comparator............................................................................................... 243
26.1. Overview...................................................................................................................................243
26.2. Analog Comparator Multiplexed Input...................................................................................... 243
26.3. Register Description................................................................................................................. 244

27. ADC - Analog to Digital Converter.........................................................................248
27.1.
27.2.
27.3.
27.4.
27.5.
27.6.
27.7.
27.8.

Features................................................................................................................................... 248
Overview...................................................................................................................................248
Starting a Conversion...............................................................................................................250
Prescaling and Conversion Timing...........................................................................................250
Changing Channel or Reference Selection.............................................................................. 252
ADC Noise Canceler................................................................................................................ 253
ADC Conversion Result............................................................................................................257
Register Description................................................................................................................. 257

28. Boot Loader Support – Read-While-Write Self-Programming............................... 266
28.1.
28.2.
28.3.
28.4.
28.5.
28.6.
28.7.
28.8.
28.9.

Features................................................................................................................................... 266
Overview...................................................................................................................................266
Application and Boot Loader Flash Sections............................................................................266
Read-While-Write and No Read-While-Write Flash Sections...................................................267
Boot Loader Lock Bits.............................................................................................................. 269
Entering the Boot Loader Program...........................................................................................270
Addressing the Flash During Self-Programming...................................................................... 271
Self-Programming the Flash.....................................................................................................272
Register Description................................................................................................................. 280

29. Memory Programming........................................................................................... 283
29.1.
29.2.
29.3.
29.4.
29.5.
29.6.
29.7.
29.8.

Program and Data Memory Lock Bits.......................................................................................283
Fuse Bits...................................................................................................................................284
Signature Bytes........................................................................................................................ 286
Calibration Byte........................................................................................................................ 286
Page Size................................................................................................................................. 286
Parallel Programming Parameters, Pin Mapping, and Commands.......................................... 286
Parallel Programming...............................................................................................................288
Serial Downloading...................................................................................................................297

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29.9. Serial Programming Pin Mapping.............................................................................................297

30. Electrical Characteristics – TA = -40°C to 85°C.....................................................302
30.1.
30.2.
30.3.
30.4.
30.5.
30.6.
30.7.

DC Characteristics....................................................................................................................302
Speed Grades.......................................................................................................................... 304
Clock Characteristics................................................................................................................304
System and Reset Characteristics........................................................................................... 305
Two-wire Serial Interface Characteristics................................................................................. 306
SPI Timing Characteristics....................................................................................................... 308
ADC Characteristics................................................................................................................. 309

31. Electrical Characteristics – TA = -40°C to 105°C...................................................312
31.1. DC Characteristics....................................................................................................................312

32. Typical Characteristics – TA = -40°C to 85°C........................................................ 314
32.1. Active Supply Current...............................................................................................................314
32.2. Idle Supply Current...................................................................................................................318
32.3. Power-down Supply Current.....................................................................................................321
32.4. Power-save Supply Current......................................................................................................322
32.5. Standby Supply Current........................................................................................................... 323
32.6. Pin Pull-up................................................................................................................................ 326
32.7. Pin Driver Strength................................................................................................................... 328
32.8. Pin Thresholds and Hysteresis.................................................................................................332
32.9. Bod Thresholds and Analog Comparator Offset.......................................................................337
32.10. Internal Oscillator Speed..........................................................................................................339
32.11. Current Consumption of Peripheral Units.................................................................................346
32.12. Current Consumption in Reset and Reset Pulsewidth............................................................. 349

33. Typical Characteristics – TA = -40°C to 105°C...................................................... 351
33.1. ATmega8A Typical Characteristics...........................................................................................351

34. Register Summary.................................................................................................380
35. Instruction Set Summary....................................................................................... 382
36. Packaging Information...........................................................................................387
36.1. 32A........................................................................................................................................... 387
36.2. 28P3......................................................................................................................................... 388
36.3. 32M1-A.....................................................................................................................................389

37. Errata.....................................................................................................................390
37.1. ATmega8A, rev. L..................................................................................................................... 390

38. Datasheet Revision History................................................................................... 392
38.1.
38.2.
38.3.
38.4.
38.5.

Rev.8159F – 07/2015............................................................................................................... 392
Rev.8159E – 02/2013............................................................................................................... 392
Rev.8159D – 02/11................................................................................................................... 392
DRH_Rev.8159C – 07/09......................................................................................................... 392
Rev.8159B – 05/09................................................................................................................... 392

Atmel ATmega8A [DATASHEET]
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38.6. Rev.8159A – 08/08................................................................................................................... 392

Atmel ATmega8A [DATASHEET]
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Description
The Atmel AVR core combines a rich instruction set with 32 general purpose working registers. All the 32
registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to
be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code
efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The ATmega8A provides the following features: 8K bytes of In-System Programmable Flash with ReadWhile- Write capabilities, 512 bytes of EEPROM, 1K byte of SRAM, 23 general purpose I/O lines, 32
general purpose working registers, three flexible Timer/Counters with compare modes, internal and
external interrupts, a serial programmable USART, one byte oriented Two-wire Serial Interface, a 6channel ADC (eight channels in TQFP and QFN/MLF packages) with 10-bit accuracy, a programmable
Watchdog Timer with Internal Oscillator, an SPI serial port, and five software selectable power saving
modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, one SPI port, and
interrupt system to continue functioning. The Power-down mode saves the register contents but freezes
the Oscillator, disabling all other chip functions until the next Interrupt or Hardware Reset. In Power-save
mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest
of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except
asynchronous timer and ADC, to minimize switching noise during ADC conversions. In Standby mode,
the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast
start-up combined with low-power consumption.
Atmel offers the QTouch library for embedding capacitive touch buttons, sliders and wheels functionality
into AVR microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and
includes fully debounced reporting of touch keys and includes Adjacent Key Suppression® (AKS®)
technology for unambiguous detection of key events. The easy-to-use QTouch Composer allows you to
explore, develop and debug your own touch applications.
The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP
Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by a
conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core.
The Boot program can use any interface to download the application program in the Application Flash
memory. Software in the Boot Flash section will continue to run while the Application Flash section is
updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System
Self-Programmable Flash on a monolithic chip, the Atmel ATmega8A is a powerful microcontroller that
provides a highly flexible and cost effective solution to many embedded control applications.
The device is supported with a full suite of program and system development tools including: C
Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kit.

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Configuration Summary
Features

ATmega8A

Pin count

Flash (KB)

SRAM (KB)

EEPROM (Bytes)

512

General Purpose I/O pins

SPI

TWI (I2C)

USART

ADC

10-bit 15ksps

ADC channels

6 (8 in TQFP and QFN/MLF packages)

AC propagation delay

Typ 400ns

8-bit Timer/Counters

16-bit Timer/Counters

PWM channels

RC Oscillator

+/-3%

Operating voltage

2.7 - 5.5V

Max operating frequency

16MHz

Temperature range

-40°C to +105°C

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Atmel-8159F-8-bit AVR Microcontroller_Datasheet_Complete-09/2015

Ordering Information
Speed (MHz)

Power Supply

2.7 - 5.5V

Ordering Code(2)

Package(1)

ATmega8A-AU
ATmega8A-AUR(3)

32A
32A

ATmega8A-PU

28P3

ATmega8A-MU

32M1-A

ATmega8A-MUR(3)

32M1-A

ATmega8A-AN
ATmega8A-ANR(3)

32A
32A

ATmega8A-MN

32M1-A

ATmega8A-MNR(3)

32M1-A

ATmega8A-PN

28P3

Operational Range

Industrial (-40oC to 85oC)

Extended (-40oC to 105oC)

Note:
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for
detailed ordering information and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances
(RoHS directive). Also Halide free and fully Green.
3. Tape and Reel
Package Type
32A

32-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP)

28P3

28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)

32M1-A 32-pad, 5 x 5 x 1.0mm body, lead pitch 0.50mm, Quad Flat No-Lead/Micro Lead Frame
Package (QFN/MLF)

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Block Diagram
Figure 4-1 Block Diagram

SRAM
CPU
FLASH
XTAL1/
TOSC1

XTAL2/
TOSC2

VCC
RESET
GND

Clock generation
8 MHz
Crystal Osc

1/2/4/8MHz
Calib RC

12MHz
External
RC Osc

32.768kHz
XOSC

External
clock

1MHz int
osc

Power
Supervision
POR/BOD &
RESET

ADC[7:0]
AREF

AIN0
AIN1
ADCMUX

Power
management
and clock
control

EEPROMIF

NVM
programming

Watchdog
Timer
Internal
Reference
ADC

D
A
T
A
B
U
S

SPI

MISO
MOSI
SCK
SS

I/O
PORTS

PB[7:0]
PC[6:0]
PD[7:0]

EXTINT

INT[1:0]

AC
(8-bit)

USART

TC 1

(16-bit)
SDA
SCL

PARPROG

Serial
Programming

TC 0
RxD
TxD
XCK

EEPROM

TWI

TC 2

(8-bit async)

T0
OC1A/B
T1
ICP1
OC2

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Pin Configurations
Figure 5-1 PDIP

(RESET) PC6

PC5 (ADC5/SCL)

(RXD) PD0

PC4 (ADC4/SDA)

(TXD) PD1

PC3 (ADC3)

(INT0) PD2

PC2 (ADC2)

(INT1) PD3

PC1 (ADC1)

(XCK/T0) PD4

PC0 (ADC0)

VCC

GND

AREF

(XTAL1/TOSC1) PB6

AVCC

(XTAL2/TOSC2) PB7

PB5 (SCK)

(T1) PD5

PB4 (MISO)

(AIN0) PD6

PB3 (MOSI/OC2)

(AIN1) PD7

PB2 (SS/OC1B)

(ICP1) PB0

PB1 (OC1A)

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PD2 (INT0)

PD1 (TXD)

PD0 (RXD)

PC6 (RESET)

PC5 (ADC5/SCL)

PC4 (ADC4/SDA)

PC3 (ADC3)

PC2 (ADC2)

Figure 5-2 TQFP Top View

GND

AREF

VCC

ADC6

(XTAL1/TOSC1) PB6

AVCC

(XTAL2/TOSC2) PB7

PB5 (SCK)

GND

(MISO) PB4

(MOSI/OC2) PB3

VCC

ADC7

(SS/OC1B) PB2

(OC1A) PB1

GND

PC0 (ADC0)

(ICP1) PB0

(AIN1) PD7

(XCK/T0) PD4

PC1 (ADC1)

(AIN0) PD6

(T1) PD5

(INT1) PD3

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PD2 (INT0)

PD1 (TXD)

PD0 (RXD)

PC6 (RESET)

PC5 (ADC5/SCL)

PC4 (ADC4/SDA)

PC3 (ADC3)

PC2 (ADC2)

Figure 5-3 MLF Top View

GND

ADC7

VCC

GND

AREF

VCC

ADC6

(XTAL1/TOSC1) PB6

AVCC

(XTAL2/TOSC2) PB7

PB5 (SCK)

Pin Descriptions

5.1.1.

VCC

(MISO) PB4

(MOSI/OC2) PB3

(SS/OC1B) PB2

(OC1A) PB1

(ICP1) PB0

(AIN1) PD7

(AIN0) PD6

(T1) PD5

5.1.

PC0 (ADC0)

(XCK/T0) PD4

PC1 (ADC1)

(INT1) PD3

NOTE:
The large center pad underneath
the MLF packages is made of
metal and internally connected to
GND. It should be soldered or
glued to the PCB to ensure good
mechanical stability. If the center
pad is left unconneted, the
package might loosen from the
PCB.

Digital supply voltage.
5.1.2.

GND
Ground.

5.1.3.

Port B (PB7:PB0) – XTAL1/XTAL2/TOSC1/TOSC2
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B
output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,
Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port
B pins are tri-stated when a reset condition becomes active, even if the clock is not running.
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Depending on the clock selection fuse settings, PB6 can be used as input to the inverting Oscillator
amplifier and input to the internal clock operating circuit.
Depending on the clock selection fuse settings, PB7 can be used as output from the inverting Oscillator
amplifier.
If the Internal Calibrated RC Oscillator is used as chip clock source, PB7:6 is used as TOSC2:1 input for
the Asynchronous Timer/Counter2 if the AS2 bit in ASSR is set.
The various special features of Port B are elaborated in Alternate Functions of Port B and System Clock
and Clock Options.
5.1.4.

Port C (PC5:PC0)
Port C is an 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C
output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,
Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port
C pins are tri-stated when a reset condition becomes active, even if the clock is not running.

5.1.5.

PC6/RESET
If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical characteristics
of PC6 differ from those of the other pins of Port C.
If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on this pin for longer
than the minimum pulse length will generate a Reset, even if the clock is not running. The minimum pulse
length is given in Table 30-5. Shorter pulses are not guaranteed to generate a Reset.
The various special features of Port C are elaborated in Alternate Functions of Port C.

5.1.6.

Port D (PD7:PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D
output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,
Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port
D pins are tri-stated when a reset condition becomes active, even if the clock is not running.
Port D also serves the functions of various special features of the ATmega8A as listed in Alternate
Functions of Port D.

5.1.7.

RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if
the clock is not running. The minimum pulse length is given in Table 30-5. Shorter pulses are not
guaranteed to generate a reset.

5.1.8.

AVCC
AVCC is the supply voltage pin for the A/D Converter, Port C (3:0), and ADC (7:6). It should be externally
connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through
a low-pass filter. Note that Port C (5:4) use digital supply voltage, VCC.

5.1.9.

AREF
AREF is the analog reference pin for the A/D Converter.

5.1.10.

ADC7:6 (TQFP and QFN/MLF Package Only)
In the TQFP and QFN/MLF package, ADC7:6 serve as analog inputs to the A/D converter. These pins are
powered from the analog supply and serve as 10-bit ADC channels.
Atmel ATmega8A [DATASHEET]
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5.2.

Accessing 16-bit Registers
The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit
data bus. A 16-bit register must be byte accessed using two read or write operations. The 16-bit timer has
a single 8-bit register for temporary storing of the High byte of the 16-bit access. The same temporary
register is shared between all 16-bit registers within the 16-bit timer. Accessing the Low byte triggers the
16-bit read or write operation. When the Low byte of a 16-bit register is written by the CPU, the High byte
stored in the temporary register, and the Low byte written are both copied into the 16-bit register in the
same clock cycle. When the Low byte of a 16-bit register is read by the CPU, the High byte of the 16-bit
register is copied into the temporary register in the same clock cycle as the Low byte is read.
Not all 16-bit accesses uses the temporary register for the High byte. Reading the OCR1A/B 16-bit
registers does not involve using the temporary register.
To do a 16-bit write, the High byte must be written before the Low byte. For a 16-bit read, the Low byte
must be read before the High byte.
The following code examples show how to access the 16-bit Timer Registers assuming that no interrupts
updates the temporary register. The same principle can be used directly for accessing the OCR1A/B and
ICR1 Registers. Note that when using “C”, the compiler handles the 16-bit access.
Assembly Code Example(1)
:.
; Set TCNT1 to 0x01FF
ldi
r17,0x01
ldi
r16,0xFF
out
TCNT1H,r17
out
TCNT1L,r16
; Read TCNT1 into r17:r16
in
r16,TCNT1L
in
r17,TCNT1H
:.
C Code Example(1)
unsigned int i;
:.
/* Set TCNT1 to 0x01FF */
TCNT1 = 0x1FF;
/* Read TCNT1 into i */
i = TCNT1;
:.
Note: 1. See About Code Examples.
The assembly code example returns the TCNT1 value in the r17:r16 Register pair.
It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt occurs
between the two instructions accessing the 16-bit register, and the interrupt code updates the temporary
register by accessing the same or any other of the 16-bit Timer Registers, then the result of the access
outside the interrupt will be corrupted. Therefore, when both the main code and the interrupt code update
the temporary register, the main code must disable the interrupts during the 16-bit access.
The following code examples show how to do an atomic read of the TCNT1 Register contents. Reading
any of the OCR1A/B or ICR1 Registers can be done by using the same principle.

Atmel ATmega8A [DATASHEET]
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Asesmbly Code Example(1)
TIM16_ReadTCNT1:
; Save global interrupt flag
in
r18,SREG
; Disable interrupts
cli
; Read TCNT1 into r17:r16
in
r16,TCNT1L
in
r17,TCNT1H
; Restore global interrupt flag
out
SREG,r18
ret
C Code Example(1)
unsigned int TIM16_ReadTCNT1( void )
{
unsigned char sreg;
unsigned int i;
/* Save global interrupt flag */
sreg = SREG;
/* Disable interrupts */
_CLI();
/* Read TCNT1 into i */
i = TCNT1;
/* Restore global interrupt flag */
SREG = sreg;
return i;
}
Note: 1. See About Code Examples.
The assembly code example returns the TCNT1 value in the r17:r16 Register pair.
The following code examples show how to do an atomic write of the TCNT1 Register contents. Writing
any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
Assembly Code Example(1)
TIM16_WriteTCNT1:
; Save global interrupt flag
in
r18,SREG
; Disable interrupts
cli
; Set TCNT1 to r17:r16
out
TCNT1H,r17
out
TCNT1L,r16
; Restore global interrupt flag
out
SREG,r18
ret
C Code Example(1)
void TIM16_WriteTCNT1( unsigned int i )
{
unsigned char sreg;
unsigned int i;
/* Save global interrupt flag */

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}

sreg = SREG;
/* Disable interrupts */
_CLI();
/* Set TCNT1 to i */
TCNT1 = i;
/* Restore global interrupt flag */
SREG = sreg;

Note: 1. See About Code Examples.
The assembly code example requires that the r17:r16 Register pair contains the value to be written to
TCNT1.
Related Links
About Code Examples on page 23

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I/O Multiplexing
Each pin is by default controlled by the PORT as a general purpose I/O and alternatively it can be
assigned to one of the peripheral functions. This table describes the peripheral signals multiplexed to the
PORT I/O pins.

Table 6-1 PORT Function Multiplexing
PAD

Pin #

PD[4]

EXTINT

PCINT

Custom

OSC

TC1(16bit)

TC2(8-bit)

PCINT20

ACO

O1CA

PB[6]

PCINT06

EXTCLK

PD[5]

PCINT21

AINP1

CLK1

PD[6]

PCINT22

AINP0

ICP1

PD[7]

PCINT23

AINN0

PB[2]

PCINT02

CLO0

CLKOUT

PB[3]

PCINT03

PB[4]

PCINT04

PB[5]

PCINT05

CLO1

PC[4]

PCINT12

AINN1

PC[5]

PCINT13

AINN2

PC[6]/
RESET

PCINT14

VCC

GND

INT0

USART

SPI

Misc

SII

SDO

TC2-OCB

SDI

TC1-OCB

TC2-OCA

TXD

MOSI

RXD

MISO

XCK

SCK

HVRST/d
W

Atmel ATmega8A [DATASHEET]
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Resources
A comprehensive set of development tools, application notes and datasheets are available for download
on http://www.atmel.com/avr.

Atmel ATmega8A [DATASHEET]
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Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM
over 20 years at 85°C or 100 years at 25°C.

Atmel ATmega8A [DATASHEET]
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About Code Examples
This datasheet contains simple code examples that briefly show how to use various parts of the device.
These code examples assume that the part specific header file is included before compilation. Be aware
that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is
compiler dependent. Please confirm with the C compiler documentation for more details.
For I/O registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions
must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS”
combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.

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10.

Capacitive Touch Sensing
The Atmel QTouch Library provides a simple to use solution to realize touch sensitive interfaces on most
®
Atmel AVR microcontrollers. The QTouch Library includes support for the QTouch and QMatrix
acquisition methods.
Touch sensing can be added to any application by linking the appropriate Atmel QTouch Library for the
AVR Microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors,
and then calling the touch sensing API’s to retrieve the channel information and determine the touch
sensor states.
The QTouch Library is FREE and downloadable from the Atmel website at the following location:
www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the Atmel
QTouch Library User Guide - also available for download from the Atmel website.

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11.

AVR CPU Core

11.1.

Overview
This section discusses the Atmel AVR core architecture in general. The main function of the CPU core is
to ensure correct program execution. The CPU must therefore be able to access memories, perform
calculations, control peripherals, and handle interrupts.
Figure 11-1 Block Diagram of the AVR MCU Architecture
Da ta Bus 8-bit

Fla s h
P rogra m
Me mory

P rogra m
Counte r

S ta tus
a nd Control

32 x 8
Ge ne ra l
P urpos e
Re gis tre rs

Control Line s

Dire ct Addre s s ing

Ins truction
De code r

Indire ct Addre s s ing

Ins truction
Re gis te r

Inte rrupt
Unit
SPI
Unit
Wa tchdog
Time r

ALU

Ana log
Compa ra tor

i/O Module 1

Da ta
S RAM

i/O Module 2

i/O Module n
EEP ROM

I/O Line s

In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate
memories and buses for program and data. Instructions in the Program memory are executed with a
single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the
Program memory. This concept enables instructions to be executed in every clock cycle. The Program
memory is In-System Reprogrammable Flash memory.
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock
cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU
operation, two operands are output from the Register File, the operation is executed, and the result is
stored back in the Register File – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space
addressing – enabling efficient address calculations. One of the these address pointers can also be used
as an address pointer for look up tables in Flash Program memory. These added function registers are
the 16-bit X-, Y-, and Z-register, described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and a
register. Single register operations can also be executed in the ALU. After an arithmetic operation, the
Status Register is updated to reflect information about the result of the operation.
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The Program flow is provided by conditional and unconditional jump and call instructions, able to directly
address the whole address space. Most AVR instructions have a single 16-bit word format. Every
Program memory address contains a 16- or 32-bit instruction.
Program Flash memory space is divided in two sections, the Boot program section and the Application
program section. Both sections have dedicated Lock Bits for write and read/write protection. The SPM
instruction that writes into the Application Flash memory section must reside in the Boot program section.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack.
The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only
limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the
reset routine (before subroutines or interrupts are executed). The Stack Pointer SP is read/write
accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing
modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional global interrupt
enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector
table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the
Interrupt Vector address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI,
and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations
following those of the Register File, 0x20 - 0x5F. In addition, the ATmega8A has Extended I/O space from
$60 in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used.

11.2.

ALU – Arithmetic Logic Unit
The high-performance Atmel AVR ALU operates in direct connection with all the 32 general purpose
working registers. Within a single clock cycle, arithmetic operations between general purpose registers or
between a register and an immediate are executed. The ALU operations are divided into three main
categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide
a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the
“Instruction Set” section for a detailed description.

11.3.

Status Register
The Status Register contains information about the result of the most recently executed arithmetic
instruction. This information can be used for altering program flow in order to perform conditional
operations. Note that the Status Register is updated after all ALU operations, as specified in the
Instruction Set Reference. This will in many cases remove the need for using the dedicated compare
instructions, resulting in faster and more compact code.
The Status Register is not automatically stored when entering an interrupt routine and restored when
returning from an interrupt. This must be handled by software.

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11.3.1.

SREG – The AVR Status Register
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset
addresses. The device is a complex microcontroller with more peripheral units than can be supported
within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space
from 0x60 in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Name: SREG
Offset: 0x3F
Reset: 0x00
Property: When addressing I/O Registers as data space the offset address is 0x5F
Bit

Access
Reset

R/W

Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt
enable control is then performed in separate control registers. If the Global Interrupt Enable Register is
cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The Ibit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable
subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI
instructions, as described in the Instruction Set Reference.
Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for
the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and
a bit in T can be copied into a bit in a register in the Register File by the BLD instruction.
Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful in BCD
arithmetic. See the “Instruction Set Description” for detailed information.
Bit 4 – S: Sign Bit, S = N ⊕ V
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow
Flag V. See the “Instruction Set Description” for detailed information.
Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set
Description” for detailed information.
Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction
Set Description” for detailed information.
Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set
Description” for detailed information.

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Bit 0 – C: Carry Flag
The Carry Flag C indicates a Carry in an arithmetic or logic operation. See the “Instruction Set
Description” for detailed information.

11.4.

General Purpose Register File
The Register File is optimized for the Atmel AVR Enhanced RISC instruction set. In order to achieve the
required performance and flexibility, the following input/output schemes are supported by the Register
File:
•
•
•
•

One 8-bit output operand and one 8-bit result input.
Two 8-bit output operands and one 8-bit result input.
Two 8-bit output operands and one 16-bit result input.
One 16-bit output operand and one 16-bit result input.

The following figure shows the structure of the 32 general purpose working registers in the CPU.
Figure 11-2 AVR CPU General Purpose Working Registers
7

Addr.

0x00

0x01

0x02

…
R13

0x0D

Ge ne ra l

R14

0x0E

P urpos e

R15

0x0F

Working

R16

0x10

Re gis te rs

R17

0x11

…
R26

0x1A

X-re gis te r Low Byte

R27

0x1B

X-re gis te r High Byte

R28

0x1C

Y-re gis te r Low Byte

R29

0x1D

Y-re gis te r High Byte

R30

0x1E

Z-re gis te r Low Byte

R31

0x1F

Z-re gis te r High Byte

Most of the instructions operating on the Register File have direct access to all registers, and most of
them are single cycle instructions.
As shown in the figure above, each register is also assigned a Data memory address, mapping them
directly into the first 32 locations of the user Data Space. Although not being physically implemented as
SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-,
Y-, and Z-pointer Registers can be set to index any register in the file.
11.4.1.

The X-register, Y-register and Z-register
The registers R26:R31 have some added functions to their general purpose usage. These registers are
16-bit address pointers for indirect addressing of the Data Space. The three indirect address registers X,
Y and Z are defined as described in the following figure.

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Figure 11-3 The X-, Y- and Z-Registers
15
X-re gis te r

R27 (0x1B)
15
Y-re gis te r

Z-re gis te r

R29 (0x1D)
ZH

0
R26 (0x1A)

0
R28 (0x1C)
ZL

R31 (0x1F)

0
0

R30 (0x1E)

In the different addressing modes these address registers have functions as fixed displacement,
automatic increment, and automatic decrement (see the Instruction Set Reference for details).

11.5.

Stack Pointer
The Stack is mainly used for storing temporary data, for storing local variables and for storing return
addresses after interrupts and subroutine calls. Note that the Stack is implemented as growing from
higher to lower memory locations. The Stack Pointer Register always points to the top of the Stack. The
Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located.
A Stack PUSH command will decrease the Stack Pointer.
The Stack in the data SRAM must be defined by the program before any subroutine calls are executed or
interrupts are enabled. Initial Stack Pointer value equals the last address of the internal SRAM and the
Stack Pointer must be set to point above start of the SRAM, see Figure Data Memory Map in SRAM Data
Memory.
See table below for Stack Pointer details.
Table 11-1 Stack Pointer instructions

Instruction Stack pointer

Description

PUSH

Decremented by 1 Data is pushed onto the stack

CALL
ICALL
RCALL

Decremented by 2 Return address is pushed onto the stack with a subroutine call or
interrupt

POP

Incremented by 1

Data is popped from the stack

RET
RETI

Incremented by 2

Return address is popped from the stack with return from subroutine or
return from interrupt

The Atmel AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits
actually used is implementation dependent. Note that the data space in some implementations of the AVR
architecture is so small that only SPL is needed. In this case, the SPH Register will not be present.
Related Links
SRAM Data Memory on page 34

Atmel ATmega8A [DATASHEET]
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11.5.1.

SPH and SPL - Stack Pointer High and Stack Pointer Low Register
Bit

0x3E

S P15

S P14

S P13

S P12

S P11

S P10

S P9

S P8

S PH

0x3D

S P7

S P6

S P5

S P4

S P3

S P2

S P1

S P0

S PL

R/W

Re a d/Write

Initia l Va lue

0
0

11.6.

Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The Atmel AVR CPU
is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No
internal clock division is used.
The following figure shows the parallel instruction fetches and instruction executions enabled by the
Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to
obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per
clocks, and functions per power-unit.
Figure 11-4 The Parallel Instruction Fetches and Instruction Executions
T1

clkCP U
1s t Ins truction Fe tch
1s t Ins truction Exe cute
2nd Ins truction Fe tch
2nd Ins truction Exe cute
3rd Ins truction Fe tch
3rd Ins truction Exe cute
4th Ins truction Fe tch

The next figure shows the internal timing concept for the Register File. In a single clock cycle an ALU
operation using two register operands is executed, and the result is stored back to the destination
register.
Figure 11-5 Single Cycle ALU Operation
T1

clkCP U
Tota l Exe cution Time
Re gis te r Ope ra nds Fe tch
ALU Ope ra tion Exe cute
Re s ult Write Ba ck

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11.7.

Reset and Interrupt Handling
The Atmel AVR provides several different interrupt sources. These interrupts and the separate Reset
Vector each have a separate Program Vector in the Program memory space. All interrupts are assigned
individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the
Status Register in order to enable the interrupt. Depending on the Program Counter value, interrupts may
be automatically disabled when Boot Lock Bits BLB02 or BLB12 are programmed. This feature improves
software security. See the section Memory Programming for details.
The lowest addresses in the Program memory space are by default defined as the Reset and Interrupt
Vectors. The complete list of Vectors is shown in Interrupts . The list also determines the priority levels of
the different interrupts. The lower the address the higher is the priority level. RESET has the highest
priority, and next is INT0 – the External Interrupt Request 0. The Interrupt Vectors can be moved to the
start of the boot Flash section by setting the Interrupt Vector Select (IVSEL) bit in the General Interrupt
Control Register (GICR). Refer to Interrupts for more information. The Reset Vector can also be moved to
the start of the boot Flash section by programming the BOOTRST Fuse, see Boot Loader Support –
Read-While-Write Self-Programming.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The
user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then
interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt
instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt
Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to
execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt
Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt
condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and
remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more
interrupt conditions occur while the global interrupt enable bit is cleared, the corresponding Interrupt
Flag(s) will be set and remembered until the global interrupt enable bit is set, and will then be executed by
order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do
not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled,
the interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one more
instruction before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored
when returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No
interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction.
The following example shows how this can be used to avoid interrupts during the timed EEPROM write
sequence.

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Assembly Code Example
in r16, SREG ; store SREG value
cli ; disable interrupts during timed sequence
sbi EECR, EEMWE ; start EEPROM write
sbi EECR, EEWE
out SREG, r16 ; restore SREG value (I-bit)
C Code Example
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
_CLI();
EECR |= (1<

XXX

;
$013

RESET:

; Enable
interrupts

When the BOOTRST Fuse is unprogrammed, the boot section size set to 2K bytes and the IVSEL bit in
the GICR Register is set before any interrupts are enabled, the most typical and general program setup
for the Reset and Interrupt Vector Addresses is:
Adddress

Labels

$000

Code

Comments

rjmp

RESET

; Reset handler

ldi

r16,high(RAMEND)

; Main program
start

$002

out

SPH,r16

; Set Stack
Pointer to top of
RAM

$003

ldi

r16,low(RAMEND)

;
$001

RESET:

Atmel ATmega8A [DATASHEET]
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Adddress

Labels

Code

Comments

$004

out

SPL,r16

$005

sei

$006

XXX

$c01

rjmp

EXT_INT0

; IRQ Handler

$c02

rjmp

EXT_INT1

; IRQ| Handler

$c12

rjmp

SPM_RDY

; Enable
interrupts

;
.org $c01

; Store Program
Memory Ready
Handler

When the BOOTRST Fuse is programmed and the boot section size set to 2K bytes, the most typical and
general program setup for the Reset and Interrupt Vector Addresses is:
Address

Labels

Code

Comments

.org $001
$001

rjmp

$002

EXT_INT0

; IRQ0 Handler

EXT_INT1

; IRQ1 Handler

;

$012

rjmp

SPM_RDY

; Store Program
Memory Handler

rjmp

RESET

; Reset handler

ldi

r16,high(RAMEND)

; Main program
start

$c02

out

SPH,r16

; Set Stack
Pointer to top of
RAM

$c03

ldi

r16,low(RAMENSPL,r
16D)

$c04

out

SPL,r16

$c05

sei

$c06

;
.org $c00
$c00
;
$c01

RESET:

; Enable
interrupts
XXX

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When the BOOTRST Fuse is programmed, the boot section size set to 2K bytes, and the IVSEL bit in the
GICR Register is set before any interrupts are enabled, the most typical and general program setup for
the Reset and Interrupt Vector Addresses is:
Address

Labels

Code

Comments

;
.org $c00
$c00

rjmp

RESET

; Reset handler

$c01

rjmp

EXT_INT0

; IRQ0 Handler

$c02

rjmp

EXT_INT1

; IRQ1 Handler

$c12

rjmp

SPM_RDY

; Store Program
Memory Ready
Handler

ldi

r16,high(RAMEND)

; Main program
start

$c14

out

SPH,r16

; Set Stack
Pointer to top of
RAM

$c15

ldi

r16,low(RAMEND)

$c16

out

SPL,r16

$c17

sei

$c18

$c13

RESET:

; Enable
interrupts
XXX

Related Links
Boot Loader Support – Read-While-Write Self-Programming on page 266
ATmega8A Boot Loader Parameters on page 278
16.1.1.

Moving Interrupts Between Application and Boot Space
The General Interrupt Control Register controls the placement of the Interrupt Vector table.

16.2.

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16.2.1.

GICR – General Interrupt Control Register
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset
addresses. The device is a complex microcontroller with more peripheral units than can be supported
within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space
from 0x60 in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Name: GICR
Offset: 0x3B
Reset: 0
Property: When addressing I/O Registers as data space the offset address is 0x5B
Bit

Access
Reset

IVSEL

IVCE

R/W

Bit 1 – IVSEL: Interrupt Vector Select
When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory.
When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot Loader section of
the Flash. The actual address of the start of the boot Flash section is determined by the BOOTSZ Fuses.
Refer to the section Boot Loader Support – Read-While-Write Self-Programming for details. To avoid
unintentional changes of Interrupt Vector tables, a special write procedure must be followed to change the
IVSEL bit:
1.
2.

Write the Interrupt Vector Change Enable (IVCE) bit to one.
Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.

Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the
cycle IVCE is set, and they remain disabled until after the instruction following the write to IVSEL. If
IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status Register is
unaffected by the automatic disabling.
Note: 1. If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is
programmed, interrupts are disabled while executing from the Application section. If Interrupt Vectors are
placed in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while
executing from the Boot Loader section. Refer to the section Boot Loader Support – Read-While-Write
Self-Programming for details on Boot Lock Bits.
Bit 0 – IVCE: Interrupt Vector Change Enable
The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware
four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as
explained in the IVSEL description above. See Code Example below.

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Assembly Code Example
Move_interrupts:
; Enable change of Interrupt Vectors
ldi r16, (1< CSn2:0 > 1). The number of system clock cycles from when the timer is enabled to the first
count occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256,
or 1024).
It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execution.
However, care must be taken if the other Timer/Counter that shares the same prescaler also uses
prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it is connected to.

20.4.

External Clock Source
An external clock source applied to the T1/T0 pin can be used as Timer/Counter clock (clkT1/clkT0). The
T1/T0 pin is sampled once every system clock cycle by the pin synchronization logic. The synchronized
(sampled) signal is then passed through the edge detector. The figure below shows a functional
equivalent block diagram of the T1/T0 synchronization and edge detector logic. The registers are clocked
at the positive edge of the internal system clock (clkI/O). The latch is transparent in the high period of the
internal system clock.
The edge detector generates one clkT1/clkT0 pulse for each positive (CSn2:0 = 7) or negative (CSn2:0 =
6) edge it detects.
Figure 20-1 T1/T0 Pin Sampling

D Q

Tn_s ync
(To Clock
S e le ct Logic)

D Q

LE
clk I/O
S ynchroniza tion

Edge De te ctor

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The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an
edge has been applied to the T1/T0 pin to the counter is updated.
Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least one
system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.
Each half period of the external clock applied must be longer than one system clock cycle to ensure
correct sampling. The external clock must be guaranteed to have less than half the system clock
frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses sampling, the
maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling
theorem). However, due to variation of the system clock frequency and duty cycle caused by Oscillator
source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an
external clock source is less than fclk_I/O/2.5.
An external clock source can not be prescaled.
Figure 20-2 Prescaler for Timer/Counter1 and Timer/Counter0(1)

clk I/O

10-BIT T/C PRESCALER
CK/1024

CK/256

PSR10

CK/64

CK/8

Clear

OFF
Tn

Synchronization

CSn0
CSn1
CSn2

TIMER /COUNTERn CLOCK
SOURCE clk Tn
Note: 1. The synchronization logic on the input pins (T1/T0) is shown in figure T1/T0 Pin Sampling in
this section.

20.5.

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20.5.1.

SFIOR – Special Function IO Register
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset
addresses. The device is a complex microcontroller with more peripheral units than can be supported
within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space
from 0x60 in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Name: SFIOR
Offset: 0x30
Reset: 0
Property: When addressing I/O Registers as data space the offset address is 0x50
Bit

0
PSR10

Access
Reset

R/W
0

Bit 0 – PSR10: Prescaler Reset Timer/Counter1 and Timer/Counter0
When this bit is written to one, the Timer/Counter1 and Timer/Counter0 prescaler will be reset. The bit will
be cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect. Note
that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect
both timers. This bit will always be read as zero.

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21.

16-bit Timer/Counter1

21.1.

Features
•
•
•
•
•
•
•
•
•
•
•

21.2.

True 16-bit Design (i.e., allows 16-bit PWM)
Two independent Output Compare Units
Double Buffered Output Compare Registers
One Input Capture Unit
Input Capture Noise Canceler
Clear Timer on Compare Match (Auto Reload)
Glitch-free, Phase Correct Pulse Width Modulator (PWM)
Variable PWM Period
Frequency Generator
External Event Counter
Four independent interrupt Sources (TOV1, OCF1A, OCF1B, and ICF1)

Overview
The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave
generation, and signal timing measurement. Most register and bit references in this section are written in
general form. A lower case “n” replaces the Timer/Counter number, and a lower case “x” replaces the
Output Compare unit channel. However, when using the register or bit defines in a program, the precise
form must be used i.e., TCNT1 for accessing Timer/Counter1 counter value and so on.
A simplified block diagram of the 16-bit Timer/Counter is shown in the following figure. For the actual
placement of I/O pins, refer to Pin Configurations. CPU accessible I/O Registers, including I/O bits and
I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the Register
Description.

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Figure 21-1 16-bit Timer/Counter Block Diagram(1)

Note: 1. Refer to Pin Configurations, table Port B Pins Alternate Functions in Alternate Functions of Port
B, and table Port D Pins Alternate Functions in Alternate Functions of Port D for Timer/Counter1 pin
placement and description.
Related Links
Pin Configurations on page 13
Alternate Functions of Port B on page 83
Alternate Functions of Port D on page 88
21.2.1.

Registers
The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Register (ICR1)
are all 16-bit registers. Special procedures must be followed when accessing the 16-bit registers. These
procedures are described in the section Accessing 16-bit Registers on page 17. The Timer/Counter
Control Registers (TCCR1A/B) are 8-bit registers and have no CPU access restrictions. Interrupt requests
(abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR). All
interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK). TIFR and TIMSK are
not shown in the figure since these registers are shared by other timer units.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the T1
pin. The Clock Select logic block controls which clock source and edge the Timer/Counter uses to
increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The
output from the clock select logic is referred to as the timer clock (clkT1).
The double buffered Output Compare Registers (OCR1A/B) are compared with the Timer/Counter value
at all time. The result of the compare can be used by the waveform generator to generate a PWM or
variable frequency output on the Output Compare Pin (OC1A/B). See Output Compare Units on page
119. The Compare Match event will also set the Compare Match Flag (OCF1A/B) which can be used to
generate an Output Compare interrupt request.

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The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered)
event on either the Input Capture Pin (ICP1) or on the Analog Comparator pins (see Analog Comparator).
The Input Capture unit includes a digital filtering unit (Noise Canceler) for reducing the chance of
capturing noise spikes.
The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined by either
the OCR1A Register, the ICR1 Register, or by a set of fixed values. When using OCR1A as TOP value in
a PWM mode, the OCR1A Register can not be used for generating a PWM output. However, the TOP
value will in this case be double buffered allowing the TOP value to be changed in run time. If a fixed TOP
value is required, the ICR1 Register can be used as an alternative, freeing the OCR1A to be used as
PWM output.
Related Links
Analog Comparator on page 243
21.2.2.

Definitions
The following definitions are used extensively throughout the document:
Table 21-1 Definitions

BOTTOM The counter reaches the BOTTOM when it becomes 0x0000.

21.2.3.

MAX

The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65535).

TOP

The counter reaches the TOP when it becomes equal to the highest value in the count
sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF, or
0x03FF, or to the value stored in the OCR1A or ICR1 Register. The assignment is dependent
of the mode of operation.

Compatibility
The 16-bit Timer/Counter has been updated and improved from previous versions of the 16-bit AVR
Timer/Counter. This 16-bit Timer/Counter is fully compatible with the earlier version regarding:
•
•
•

All 16-bit Timer/Counter related I/O Register address locations, including Timer Interrupt Registers.
Bit locations inside all 16-bit Timer/Counter Registers, including Timer Interrupt Registers.
Interrupt Vectors.

The following control bits have changed name, but have same functionality and register location:
•
•
•

PWM10 is changed to WGM10.
PWM11 is changed to WGM11.
CTC1 is changed to WGM12.

The following bits are added to the 16-bit Timer/Counter Control Registers:
•
•

FOC1A and FOC1B are added to TCCR1A.
WGM13 is added to TCCR1B.

The 16-bit Timer/Counter has improvements that will affect the compatibility in some special cases.

21.3.

113

16-bit read or write operation. When the Low byte of a 16-bit register is written by the CPU, the High byte
stored in the temporary register, and the Low byte written are both copied into the 16-bit register in the
same clock cycle. When the Low byte of a 16-bit register is read by the CPU, the High byte of the 16-bit
register is copied into the temporary register in the same clock cycle as the Low byte is read.
Not all 16-bit accesses uses the temporary register for the High byte. Reading the OCR1A/B 16-bit
registers does not involve using the temporary register.
To do a 16-bit write, the High byte must be written before the Low byte. For a 16-bit read, the Low byte
must be read before the High byte.
The following code examples show how to access the 16-bit Timer Registers assuming that no interrupts
updates the temporary register. The same principle can be used directly for accessing the OCR1A/B and
ICR1 Registers. Note that when using “C”, the compiler handles the 16-bit access.
Assembly Code Example(1)
:.
; Set TCNT1 to 0x01FF
ldi
r17,0x01
ldi
r16,0xFF
out
TCNT1H,r17
out
TCNT1L,r16
; Read TCNT1 into r17:r16
in
r16,TCNT1L
in
r17,TCNT1H
:.
C Code Example(1)
unsigned int i;
:.
/* Set TCNT1 to 0x01FF */
TCNT1 = 0x1FF;
/* Read TCNT1 into i */
i = TCNT1;
:.
Note: 1. See About Code Examples.
The assembly code example returns the TCNT1 value in the r17:r16 Register pair.
It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt occurs
between the two instructions accessing the 16-bit register, and the interrupt code updates the temporary
register by accessing the same or any other of the 16-bit Timer Registers, then the result of the access
outside the interrupt will be corrupted. Therefore, when both the main code and the interrupt code update
the temporary register, the main code must disable the interrupts during the 16-bit access.
The following code examples show how to do an atomic read of the TCNT1 Register contents. Reading
any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
Asesmbly Code Example(1)
TIM16_ReadTCNT1:
; Save global interrupt flag
in
r18,SREG
; Disable interrupts
cli

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; Read TCNT1 into r17:r16
in
r16,TCNT1L
in
r17,TCNT1H
; Restore global interrupt flag
out
SREG,r18
ret
C Code Example(1)
unsigned int TIM16_ReadTCNT1( void )
{
unsigned char sreg;
unsigned int i;
/* Save global interrupt flag */
sreg = SREG;
/* Disable interrupts */
_CLI();
/* Read TCNT1 into i */
i = TCNT1;
/* Restore global interrupt flag */
SREG = sreg;
return i;
}
Note: 1. See About Code Examples.
The assembly code example returns the TCNT1 value in the r17:r16 Register pair.
The following code examples show how to do an atomic write of the TCNT1 Register contents. Writing
any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
Assembly Code Example(1)
TIM16_WriteTCNT1:
; Save global interrupt flag
in
r18,SREG
; Disable interrupts
cli
; Set TCNT1 to r17:r16
out
TCNT1H,r17
out
TCNT1L,r16
; Restore global interrupt flag
out
SREG,r18
ret
C Code Example(1)
void TIM16_WriteTCNT1( unsigned int i )
{
unsigned char sreg;
unsigned int i;
/* Save global interrupt flag */
sreg = SREG;
/* Disable interrupts */
_CLI();
/* Set TCNT1 to i */
TCNT1 = i;
/* Restore global interrupt flag */

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}

SREG = sreg;

Note: 1. See About Code Examples.
The assembly code example requires that the r17:r16 Register pair contains the value to be written to
TCNT1.
Related Links
About Code Examples on page 23
21.3.1.

Reusing the Temporary High Byte Register
If writing to more than one 16-bit register where the High byte is the same for all registers written, then the
High byte only needs to be written once. However, note that the same rule of atomic operation described
previously also applies in this case.

21.4.

Timer/Counter Clock Sources
The Timer/Counter can be clocked by an internal or an external clock source. The clock source is
selected by the clock select logic which is controlled by the clock select (CS12:0) bits located in the
Timer/Counter Control Register B (TCCR1B). For details on clock sources and prescaler, see Timer/
Counter1 and Timer/Counter0 Prescalers.
Related Links
Timer/Counter0 and Timer/Counter1 Prescalers on page 108

21.5.

Counter Unit
The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. The
figure below shows a block diagram of the counter and its surroundings.
Figure 21-2 Counter Unit Block Diagram

DATA BUS (8-bit)
TOVn
(Int.Req.)
TEMP (8-bit)
Clock Select
Count
TCNTnH (8-bit)

TCNTnL (8-bit)

TCNTn (16-bit Counter)

Clear
Direction

Control Logic

clkTn

Edge
Detector

( From Prescaler )
TOP

BOTTOM

Signal description (internal signals):
count

Increment or decrement TCNT1 by 1.

direction

Select between increment and decrement.

clear

Clear TCNT1 (set all bits to zero).

clkT1

Timer/Counter clock.

TOP

Signalize that TCNT1 has reached maximum value.
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BOTTOM

Signalize that TCNT1 has reached minimum value (zero).

The 16-bit counter is mapped into two 8-bit I/O memory locations: counter high (TCNT1H) containing the
upper eight bits of the counter, and Counter Low (TCNT1L) containing the lower eight bits. The TCNT1H
Register can only be indirectly accessed by the CPU. When the CPU does an access to the TCNT1H I/O
location, the CPU accesses the High byte temporary register (TEMP). The temporary register is updated
with the TCNT1H value when the TCNT1L is read, and TCNT1H is updated with the temporary register
value when TCNT1L is written. This allows the CPU to read or write the entire 16-bit counter value within
one clock cycle via the 8-bit data bus. It is important to notice that there are special cases of writing to the
TCNT1 Register when the counter is counting that will give unpredictable results. The special cases are
described in the sections where they are of importance.
Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each
timer clock (clkT1). The clkT1 can be generated from an external or internal clock source, selected by the
clock select bits (CS12:0). When no clock source is selected (CS12:0 = 0) the timer is stopped. However,
the TCNT1 value can be accessed by the CPU, independent of whether clkT1 is present or not. A CPU
write overrides (has priority over) all counter clear or count operations.
The counting sequence is determined by the setting of the Waveform Generation mode bits (WGM13:0)
located in the Timer/Counter Control Registers A and B (TCCR1A and TCCR1B). There are close
connections between how the counter behaves (counts) and how waveforms are generated on the Output
Compare Outputs OC1x. For more details about advanced counting sequences and waveform
generation, see Modes of Operation on page 122.
The Timer/Counter Overflow (TOV1) flag is set according to the mode of operation selected by the
WGM13:0 bits. TOV1 can be used for generating a CPU interrupt.

21.6.

Input Capture Unit
The Timer/Counter incorporates an Input Capture unit that can capture external events and give them a
timestamp indicating time of occurrence. The external signal indicating an event, or multiple events, can
be applied via the ICP1 pin or alternatively, via the Analog Comparator unit. The time-stamps can then be
used to calculate frequency, duty-cycle, and other features of the signal applied. Alternatively the timestamps can be used for creating a log of the events.
The Input Capture unit is illustrated by the block diagram below. The elements of the block diagram that
are not directly a part of the Input Capture unit are gray shaded. The small “n” in register and bit names
indicates the Timer/Counter number.

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Figure 21-3 Input Capture Unit Block Diagram

DATA BUS

(8-bit)

TEMP (8-bit)

ICRnH (8-bit)
WRITE

ICRnL (8-bit)

TCNTnH (8-bit)

ICRn (16-bit Register)

ACO*
Analog
Comparator

TCNTnL (8-bit)

TCNTn (16-bit Counter)

ACIC*

ICNC

ICES

Noise
Canceler

Edge
Detector

ICFn (Int.Req.)

ICPn

When a change of the logic level (an event) occurs on the Input Capture Pin (ICP1), alternatively on the
Analog Comparator Output (ACO), and this change confirms to the setting of the edge detector, a capture
will be triggered. When a capture is triggered, the 16-bit value of the counter (TCNT1) is written to the
Input Capture Register (ICR1). The Input Capture Flag (ICF1) is set at the same system clock as the
TCNT1 value is copied into ICR1 Register. If enabled (TICIE1 = 1), the Input Capture Flag generates an
Input Capture interrupt. The ICF1 Flag is automatically cleared when the interrupt is executed.
Alternatively the ICF1 Flag can be cleared by software by writing a logical one to its I/O bit location.
Reading the 16-bit value in the Input Capture Register (ICR1) is done by first reading the Low byte
(ICR1L) and then the High byte (ICR1H). When the Low byte is read the High byte is copied into the High
byte temporary register (TEMP). When the CPU reads the ICR1H I/O location it will access the TEMP
Register.
The ICR1 Register can only be written when using a Waveform Generation mode that utilizes the ICR1
Register for defining the counter’s TOP value. In these cases the Waveform Generation mode
(WGM13:0) bits must be set before the TOP value can be written to the ICR1 Register. When writing the
ICR1 Register the High byte must be written to the ICR1H I/O location before the Low byte is written to
ICR1L.
For more information on how to access the 16-bit registers refer to Accessing 16-bit Registers on page
17.
21.6.1.

Input Capture Pin Source
The main trigger source for the Input Capture unit is the Input Capture Pin (ICP1). Timer/Counter 1 can
alternatively use the Analog Comparator Output as trigger source for the Input Capture unit. The Analog
Comparator is selected as trigger source by setting the Analog Comparator Input Capture (ACIC) bit in
the Analog Comparator Control and Status Register (ACSR). Be aware that changing trigger source can
trigger a capture. The Input Capture Flag must therefore be cleared after the change.

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Both the Input Capture Pin (ICP1) and the Analog Comparator Output (ACO) inputs are sampled using
the same technique as for the T1 pin (see figure T1 Pin Sampling in section External Clock Source). The
edge detector is also identical. However, when the noise canceler is enabled, additional logic is inserted
before the edge detector, which increases the delay by four system clock cycles. Note that the input of the
noise canceler and edge detector is always enabled unless the Timer/Counter is set in a Waveform
Generation mode that uses ICR1 to define TOP.
An Input Capture can be triggered by software by controlling the port of the ICP1 pin.
Related Links
External Clock Source on page 108
21.6.2.

Noise Canceler
The noise canceler improves noise immunity by using a simple digital filtering scheme. The noise
canceler input is monitored over four samples, and all four must be equal for changing the output that in
turn is used by the edge detector.
The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNC1) bit in Timer/Counter
Control Register B (TCCR1B). When enabled the noise canceler introduces additional four system clock
cycles of delay from a change applied to the input, to the update of the ICR1 Register. The noise canceler
uses the system clock and is therefore not affected by the prescaler.

21.6.3.

Using the Input Capture Unit
The main challenge when using the Input Capture unit is to assign enough processor capacity for
handling the incoming events. The time between two events is critical. If the processor has not read the
captured value in the ICR1 Register before the next event occurs, the ICR1 will be overwritten with a new
value. In this case the result of the capture will be incorrect.
When using the Input Capture interrupt, the ICR1 Register should be read as early in the interrupt handler
routine as possible. Even though the Input Capture interrupt has relatively high priority, the maximum
interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of
the other interrupt requests.
Using the Input Capture unit in any mode of operation when the TOP value (resolution) is actively
changed during operation, is not recommended.
Measurement of an external signal’s duty cycle requires that the trigger edge is changed after each
capture. Changing the edge sensing must be done as early as possible after the ICR1 Register has been
read. After a change of the edge, the Input Capture Flag (ICF1) must be cleared by software (writing a
logical one to the I/O bit location). For measuring frequency only, the clearing of the ICF1 Flag is not
required (if an interrupt handler is used).

21.7.

Output Compare Units
The 16-bit comparator continuously compares TCNT1 with the Output Compare Register (OCR1x). If
TCNT equals OCR1x the comparator signals a match. A match will set the Output Compare Flag
(OCF1x) at the next timer clock cycle. If enabled (OCIE1x = 1), the Output Compare Flag generates an
Output Compare interrupt. The OCF1x Flag is automatically cleared when the interrupt is executed.
Alternatively the OCF1x Flag can be cleared by software by writing a logical one to its I/O bit location. The
waveform generator uses the match signal to generate an output according to operating mode set by the
Waveform Generation mode (WGM13:0) bits and Compare Output mode (COM1x1:0) bits. The TOP and
BOTTOM signals are used by the waveform generator for handling the special cases of the extreme
values in some modes of operation (See Modes of Operation on page 122.)
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A special feature of Output Compare unit A allows it to define the Timer/Counter TOP value (i.e. counter
resolution). In addition to the counter resolution, the TOP value defines the period time for waveforms
generated by the waveform generator.
The figure below shows a block diagram of the Output Compare unit. The small “n” in the register and bit
names indicates the device number (n = 1 for Timer/Counter 1), and the “x” indicates Output Compare
unit (A/B). The elements of the block diagram that are not directly a part of the Output Compare unit are
gray shaded.
Figure 21-4 Output Compare Unit, Block Diagram

DATA BUS (8-bit)

TEMP (8-bit)

OCRnxH Buf. (8-bit)

OCRnxL Buf. (8-bit)

TCNTnH (8-bit)

OCRnx Buffer (16-bit Register)

OCRnxH (8-bit)

TCNTnL (8-bit)

TCNTn (16-bit Counter)

OCRnxL (8-bit)

OCRnx (16-bit Register)

= (16-bit Comparator )
OCFnx (Int.Req.)
TOP
BOTTOM

Waveform Generator

WGMn3:0

OCnx

COMnx1:0

The OCR1x Register is double buffered when using any of the twelve Pulse Width Modulation (PWM)
modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is
disabled. The double buffering synchronizes the update of the OCR1x Compare Register to either TOP or
BOTTOM of the counting sequence. The synchronization prevents the occurrence of odd-length, nonsymmetrical PWM pulses, thereby making the output glitch-free.
The OCR1x Register access may seem complex, but this is not case. When the double buffering is
enabled, the CPU has access to the OCR1x Buffer Register, and if double buffering is disabled the CPU
will access the OCR1x directly. The content of the OCR1x (Buffer or Compare) Register is only changed
by a write operation (the Timer/Counter does not update this register automatically as the TCNT1 and
ICR1 Register). Therefore OCR1x is not read via the High byte temporary register (TEMP). However, it is
a good practice to read the Low byte first as when accessing other 16-bit registers. Writing the OCR1x
Registers must be done via the TEMP Register since the compare of all 16-bit is done continuously. The
High byte (OCR1xH) has to be written first. When the High byte I/O location is written by the CPU, the
TEMP Register will be updated by the value written. Then when the Low byte (OCR1xL) is written to the
lower eight bits, the High byte will be copied into the upper 8-bits of either the OCR1x buffer or OCR1x
Compare Register in the same system clock cycle.
For more information of how to access the 16-bit registers refer to Accessing 16-bit Registers on page 17.

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21.7.1.

Force Output Compare
In non-PWM Waveform Generation modes, the match output of the comparator can be forced by writing a
one to the Force Output Compare (FOC1x) bit. Forcing Compare Match will not set the OCF1x Flag or
reload/clear the timer, but the OC1x pin will be updated as if a real Compare Match had occurred (the
COM1x1:0 bits settings define whether the OC1x pin is set, cleared or toggled).

21.7.2.

Compare Match Blocking by TCNT1 Write
All CPU writes to the TCNT1 Register will block any Compare Match that occurs in the next timer clock
cycle, even when the timer is stopped. This feature allows OCR1x to be initialized to the same value as
TCNT1 without triggering an interrupt when the Timer/Counter clock is enabled.

21.7.3.

Using the Output Compare Unit
Since writing TCNT1 in any mode of operation will block all compare matches for one timer clock cycle,
there are risks involved when changing TCNT1 when using any of the Output Compare channels,
independent of whether the Timer/Counter is running or not. If the value written to TCNT1 equals the
OCR1x value, the Compare Match will be missed, resulting in incorrect waveform generation. Do not
write the TCNT1 equal to TOP in PWM modes with variable TOP values. The Compare Match for the
TOP will be ignored and the counter will continue to 0xFFFF. Similarly, do not write the TCNT1 value
equal to BOTTOM when the counter is downcounting.
The setup of the OC1x should be performed before setting the Data Direction Register for the port pin to
output. The easiest way of setting the OC1x value is to use the Force Output Compare (FOC1x) strobe
bits in Normal mode. The OC1x Register keeps its value even when changing between Waveform
Generation modes.
Be aware that the COM1x1:0 bits are not double buffered together with the compare value. Changing the
COM1x1:0 bits will take effect immediately.

21.8.

Compare Match Output Unit
The Compare Output mode (COM1x1:0) bits have two functions. The waveform generator uses the
COM1x1:0 bits for defining the Output Compare (OC1x) state at the next Compare Match. Secondly the
COM1x1:0 bits control the OC1x pin output source. The figure below shows a simplified schematic of the
logic affected by the COM1x1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are
shown in bold. Only the parts of the general I/O Port Control Registers (DDR and PORT) that are affected
by the COM1x1:0 bits are shown. When referring to the OC1x state, the reference is for the internal OC1x
Register, not the OC1x pin. If a System Reset occur, the OC1x Register is reset to “0”.

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Figure 21-5 Compare Match Output Unit, Schematic

COMnx1
COMnx0
FOCnx

Waveform
Generator

Q
1

OCnx

DATA BUS

OCnx
Pin

PORT
D

DDR
clk I/O

The general I/O port function is overridden by the Output Compare (OC1x) from the waveform generator
if either of the COM1x1:0 bits are set. However, the OC1x pin direction (input or output) is still controlled
by the Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC1x pin
(DDR_OC1x) must be set as output before the OC1x value is visible on the pin. The port override function
is generally independent of the Waveform Generation mode, but there are some exceptions. Refer to
Table 21-2 Compare Output Mode, non-PWM on page 132, Table 21-3 Compare Output Mode, Fast
PWM(1) on page 133 and Table 21-4 Compare Output Mode, Phase Correct and Phase and Frequency
Correct PWM(1) on page 133 for details.
The design of the Output Compare Pin logic allows initialization of the OC1x state before the output is
enabled. Note that some COM1x1:0 bit settings are reserved for certain modes of operation. See
Register Description.
The COM1x1:0 bits have no effect on the Input Capture unit.
21.8.1.

Compare Output Mode and Waveform Generation
The waveform generator uses the COM1x1:0 bits differently in normal, CTC, and PWM modes. For all
modes, setting the COM1x1:0 = 0 tells the waveform generator that no action on the OC1x Register is to
be performed on the next Compare Match. For compare output actions in the non-PWM modes refer to
Table 21-2 Compare Output Mode, non-PWM on page 132. For fast PWM mode refer to Table 21-3
Compare Output Mode, Fast PWM(1) on page 133, and for phase correct and phase and frequency
correct PWM refer to Table 21-4 Compare Output Mode, Phase Correct and Phase and Frequency
Correct PWM(1) on page 133.
A change of the COM1x1:0 bits state will have effect at the first Compare Match after the bits are written.
For nonPWM modes, the action can be forced to have immediate effect by using the FOC1x strobe bits.

21.9.

Modes of Operation
The mode of operation (i.e., the behavior of the Timer/Counter and the Output Compare pins) is defined
by the combination of the Waveform Generation mode (WGM13:0) and Compare Output mode
(COM1x1:0) bits. The Compare Output mode bits do not affect the counting sequence, while the
Waveform Generation mode bits do. The COM1x1:0 bits control whether the PWM output generated
should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COM1x1:0 bits
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control whether the output should be set, cleared or toggle at a Compare Match. See Compare Match
Output Unit on page 121.
For detailed timing information refer to Timer/Counter Timing Diagrams on page 130.
21.9.1.

Normal Mode
The simplest mode of operation is the Normal mode (WGM13:0 = 0). In this mode the counting direction
is always up (incrementing), and no counter clear is performed. The counter simply overruns when it
passes its maximum 16-bit value (MAX = 0xFFFF) and then restarts from the BOTTOM (0x0000). In
normal operation the Timer/Counter Overflow Flag (TOV1) will be set in the same timer clock cycle as the
TCNT1 becomes zero. The TOV1 Flag in this case behaves like a 17th bit, except that it is only set, not
cleared. However, combined with the timer overflow interrupt that automatically clears the TOV1 Flag, the
timer resolution can be increased by software. There are no special cases to consider in the Normal
mode, a new counter value can be written anytime.
The Input Capture unit is easy to use in Normal mode. However, observe that the maximum interval
between the external events must not exceed the resolution of the counter. If the interval between events
are too long, the timer overflow interrupt or the prescaler must be used to extend the resolution for the
capture unit.
The Output Compare units can be used to generate interrupts at some given time. Using the Output
Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of
the CPU time.

21.9.2.

Clear Timer on Compare Match (CTC) Mode
In Clear Timer on Compare or CTC mode (WGM13:0 = 4 or 12), the OCR1A or ICR1 Register are used to
manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value
(TCNT1) matches either the OCR1A (WGM13:0 = 4) or the ICR1 (WGM13:0 = 12). The OCR1A or ICR1
define the top value for the counter, hence also its resolution. This mode allows greater control of the
Compare Match output frequency. It also simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown below. The counter value (TCNT1) increases until a
Compare Match occurs with either OCR1A or ICR1, and then counter (TCNT1) is cleared.
Figure 21-6 CTC Mode, Timing Diagram
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)

TCNTn

OCnA
(Toggle)
Period

(COMnA1:0 = 1)
1

An interrupt can be generated at each time the counter value reaches the TOP value by either using the
OCF1A or ICF1 Flag according to the register used to define the TOP value. If the interrupt is enabled,
the interrupt handler routine can be used for updating the TOP value. However, changing the TOP to a
value close to BOTTOM when the counter is running with none or a low prescaler value must be done
with care since the CTC mode does not have the double buffering feature. If the new value written to
OCR1A or ICR1 is lower than the current value of TCNT1, the counter will miss the Compare Match. The
counter will then have to count to its maximum value (0xFFFF) and wrap around starting at 0x0000 before
the Compare Match can occur. In many cases this feature is not desirable. An alternative will then be to
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use the fast PWM mode using OCR1A for defining TOP (WGM13:0 = 15) since the OCR1A then will be
double buffered.
For generating a waveform output in CTC mode, the OC1A output can be set to toggle its logical level on
each Compare Match by setting the Compare Output mode bits to toggle mode (COM1A1:0 = 1). The
OC1A value will not be visible on the port pin unless the data direction for the pin is set to output
(DDR_OC1A = 1). The waveform generated will have a maximum frequency of fOC1A = fclk_I/O/2 when
OCR1A is set to zero (0x0000). The waveform frequency is defined by the following equation:
�OCnA =

�clk_I/O
2 ⋅ � ⋅ 1 + OCRnA

N represents the prescaler factor (1, 8, 64, 256, or 1024).
As for the Normal mode of operation, the Timer Counter TOV1 Flag is set in the same timer clock cycle
that the counter counts from MAX to 0x0000.
21.9.3.

Fast PWM Mode
The fast Pulse Width Modulation or fast PWM mode (WGM13:0 = 5, 6, 7, 14, or 15) provides a high
frequency PWM waveform generation option. The fast PWM differs from the other PWM options by its
single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOTTOM. In noninverting Compare Output mode, the Output Compare (OC1x) is cleared on the Compare Match between
TCNT1 and OCR1x, and set at BOTTOM. In inverting Compare Output mode output is set on Compare
Match and cleared at BOTTOM. Due to the singleslope operation, the operating frequency of the fast
PWM mode can be twice as high as the phase correct and phase and frequency correct PWM modes that
use dual-slope operation. This high frequency makes the fast PWM mode well suited for power
regulation, rectification, and DAC applications. High frequency allows physically small sized external
components (coils, capacitors), hence reduces total system cost.
The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A.
The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is
16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated by using the following
equation:
�FPWM =

log TOP+1
log 2

In fast PWM mode the counter is incremented until the counter value matches either one of the fixed
values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 5, 6, or 7), the value in ICR1 (WGM13:0 = 14), or the
value in OCR1A (WGM13:0 = 15). The counter is then cleared at the following timer clock cycle. The
timing diagram for the fast PWM mode is shown in the figure below. The figure shows fast PWM mode
when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in the timing diagram shown as a
histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted
PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare matches
between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a Compare Match occurs.

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Figure 21-7 Fast PWM Mode, Timing Diagram
OCRnx/TOP Update and
TOVn Interrupt Flag Set and
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)

TCNTn

OCnx

(COMnx1:0 = 2)

OCnx

(COMnx1:0 = 3)

Period

The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches TOP. In addition the
OCF1A or ICF1 Flag is set at the same timer clock cycle as TOV1 is set when either OCR1A or ICR1 is
used for defining the TOP value. If one of the interrupts are enabled, the interrupt handler routine can be
used for updating the TOP and compare values.
When changing the TOP value the program must ensure that the new TOP value is higher or equal to the
value of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a
Compare Match will never occur between the TCNT1 and the OCR1x. Note that when using fixed TOP
values the unused bits are masked to zero when any of the OCR1x Registers are written.
The procedure for updating ICR1 differs from updating OCR1A when used for defining the TOP value.
The ICR1 Register is not double buffered. This means that if ICR1 is changed to a low value when the
counter is running with none or a low prescaler value, there is a risk that the new ICR1 value written is
lower than the current value of TCNT1. The result will then be that the counter will miss the Compare
Match at the TOP value. The counter will then have to count to the MAX value (0xFFFF) and wrap around
starting at 0x0000 before the Compare Match can occur. The OCR1A Register, however, is double
buffered. This feature allows the OCR1A I/O location to be written anytime. When the OCR1A I/O location
is written the value written will be put into the OCR1A Buffer Register. The OCR1A Compare Register will
then be updated with the value in the Buffer Register at the next timer clock cycle the TCNT1 matches
TOP. The update is done at the same timer clock cycle as the TCNT1 is cleared and the TOV1 Flag is
set.
Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using ICR1, the
OCR1A Register is free to be used for generating a PWM output on OC1A. However, if the base PWM
frequency is actively changed (by changing the TOP value), using the OCR1A as TOP is clearly a better
choice due to its double buffer feature.
In fast PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins. Setting the
COM1x1:0 bits to 2 will produce a non-inverted PWM and an inverted PWM output can be generated by
setting the COM1x1:0 to 3. Refer to table Table 21-3 Compare Output Mode, Fast PWM(1) on page 133.
The actual OC1x value will only be visible on the port pin if the data direction for the port pin is set as
output (DDR_OC1x). The PWM waveform is generated by setting (or clearing) the OC1x Register at the
Compare Match between OCR1x and TCNT1, and clearing (or setting) the OC1x Register at the timer
clock cycle the counter is cleared (changes from TOP to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
�OCnxPWM =

�clk_I/O
� ⋅ 1 + TOP
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N represents the prescale divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR1x Register represents special cases when generating a PWM waveform
output in the fast PWM mode. If the OCR1x is set equal to BOTTOM (0x0000) the output will be a narrow
spike for each TOP+1 timer clock cycle. Setting the OCR1x equal to TOP will result in a constant high or
low output (depending on the polarity of the output set by the COM1x1:0 bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC1A
to toggle its logical level on each Compare Match (COM1A1:0 = 1). This applies only if OCR1A is used to
define the TOP value (WGM13:0 = 15). The waveform generated will have a maximum frequency of fOC1A
= fclk_I/O/2 when OCR1A is set to zero (0x0000). This feature is similar to the OC1A toggle in CTC mode,
except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode.
21.9.4.

Phase Correct PWM Mode
The phase correct Pulse Width Modulation or phase correct PWM mode (WGM13:0 = 1, 2, 3, 10, or 11)
provides a high resolution phase correct PWM waveform generation option. The phase correct PWM
mode is, like the phase and frequency correct PWM mode, based on a dual-slope operation. The counter
counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting
Compare Output mode, the Output Compare (OC1x) is cleared on the Compare Match between TCNT1
and OCR1x while upcounting, and set on the Compare Match while downcounting. In inverting Output
Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation
frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM
modes, these modes are preferred for motor control applications.
The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined by either
ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the
maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated
by using the following equation:
�PCPWM =

log TOP+1
log 2

In phase correct PWM mode the counter is incremented until the counter value matches either one of the
fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 1, 2, or 3), the value in ICR1 (WGM13:0 = 10), or
the value in OCR1A (WGM13:0 = 11). The counter has then reached the TOP and changes the count
direction. The TCNT1 value will be equal to TOP for one timer clock cycle. The timing diagram for the
phase correct PWM mode is shown in the figure below. The figure shows phase correct PWM mode when
OCR1A or ICR1 is used to define TOP. The TCNT1 value is in the timing diagram shown as a histogram
for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs.
The small horizontal line marks on the TCNT1 slopes represent compare matches between OCR1x and
TCNT1. The OC1x Interrupt Flag will be set when a Compare Match occurs.

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Figure 21-8 Phase Correct PWM Mode, Timing Diagram
OCRnx/TOP Update and
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)

TOVn Interrupt Flag Set
(Interrupt on Bottom)

TCNTn

OCnx

(COMnx1:0 = 2)

OCnx

(COMnx1:0 = 3)

Period

The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOTTOM. When either
OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 Flag is set accordingly at the same
timer clock cycle as the OCR1x Registers are updated with the double buffer value (at TOP). The
Interrupt Flags can be used to generate an interrupt each time the counter reaches the TOP or BOTTOM
value.
When changing the TOP value the program must ensure that the new TOP value is higher or equal to the
value of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a
Compare Match will never occur between the TCNT1 and the OCR1x. Note that when using fixed TOP
values, the unused bits are masked to zero when any of the OCR1x Registers are written. As the third
period shown in the timing diagram above illustrates, changing the TOP actively while the Timer/Counter
is running in the Phase Correct mode can result in an unsymmetrical output. The reason for this can be
found in the time of update of the OCR1x Register. Since the OCR1x update occurs at TOP, the PWM
period starts and ends at TOP. This implies that the length of the falling slope is determined by the
previous TOP value, while the length of the rising slope is determined by the new TOP value. When these
two values differ the two slopes of the period will differ in length. The difference in length gives the
unsymmetrical result on the output.
It is recommended to use the Phase and Frequency Correct mode instead of the Phase Correct mode
when changing the TOP value while the Timer/Counter is running. When using a static TOP value there
are practically no differences between the two modes of operation.
In phase correct PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins.
Setting the COM1x1:0 bits to 2 will produce a non-inverted PWM and an inverted PWM output can be
generated by setting the COM1x1:0 to 3. Refer to Table 21-4 Compare Output Mode, Phase Correct and
Phase and Frequency Correct PWM(1) on page 133. The actual OC1x value will only be visible on the
port pin if the data direction for the port pin is set as output (DDR_OC1x). The PWM waveform is
generated by setting (or clearing) the OC1x Register at the Compare Match between OCR1x and TCNT1
when the counter increments, and clearing (or setting) the OC1x Register at Compare Match between
OCR1x and TCNT1 when the counter decrements. The PWM frequency for the output when using phase
correct PWM can be calculated by the following equation:
�OCnxPCPWM =

�clk_I/O
2 ⋅ � ⋅ TOP

N variable represents the prescale divider (1, 8, 64, 256, or 1024).
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The extreme values for the OCR1x Register represent special cases when generating a PWM waveform
output in the phase correct PWM mode. If the OCR1x is set equal to BOTTOM the output will be
continuously low and if set equal to TOP the output will be continuously high for non-inverted PWM mode.
For inverted PWM the output will have the opposite logic values.
If OCR1A is used to define the TOP value (WGM13:0 = 11) and COM1A1:0 = 1, the OC1A output will
toggle with a 50% duty cycle.
21.9.5.

Phase and Frequency Correct PWM Mode
The phase and frequency correct Pulse Width Modulation, or phase and frequency correct PWM mode
(WGM13:0 = 8 or 9) provides a high resolution phase and frequency correct PWM waveform generation
option. The phase and frequency correct PWM mode is, like the phase correct PWM mode, based on a
dual-slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP
to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1x) is cleared on the
Compare Match between TCNT1 and OCR1x while upcounting, and set on the Compare Match while
downcounting. In inverting Compare Output mode, the operation is inverted. The dual-slope operation
gives a lower maximum operation frequency compared to the single-slope operation. However, due to the
symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control
applications.
The main difference between the phase correct, and the phase and frequency correct PWM mode is the
time the OCR1x Register is updated by the OCR1x Buffer Register, (see Figure 21-8 Phase Correct
PWM Mode, Timing Diagram on page 127 and Figure 21-9 Phase and Frequency Correct PWM Mode,
Timing Diagram on page 129).
The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICR1 or
OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum
resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated using the
following equation:
�PFCPWM =

log TOP+1
log 2

In phase and frequency correct PWM mode the counter is incremented until the counter value matches
either the value in ICR1 (WGM13:0 = 8), or the value in OCR1A (WGM13:0 = 9). The counter has then
reached the TOP and changes the count direction. The TCNT1 value will be equal to TOP for one timer
clock cycle. The timing diagram for the phase correct and frequency correct PWM mode is shown on
timing diagram below. The figure shows phase and frequency correct PWM mode when OCR1A or ICR1
is used to define TOP. The TCNT1 value is in the timing diagram shown as a histogram for illustrating the
dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal
line marks on the TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x
Interrupt Flag will be set when a Compare Match occurs.

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Figure 21-9 Phase and Frequency Correct PWM Mode, Timing Diagram
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)

OCRnx/TOP Updateand
TOVn Interrupt Flag Set
(Interrupt on Bottom)

TCNTn

OCnx

(COMnx1:0 = 2)

OCnx

(COMnx1:0 = 3)

Period

The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the OCR1x Registers
are updated with the double buffer value (at BOTTOM). When either OCR1A or ICR1 is used for defining
the TOP value, the OC1A or ICF1 Flag set when TCNT1 has reached TOP. The Interrupt Flags can then
be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value.
When changing the TOP value the program must ensure that the new TOP value is higher or equal to the
value of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a
Compare Match will never occur between the TCNT1 and the OCR1x.
As the timing diagram above shows the output generated is, in contrast to the Phase Correct mode,
symmetrical in all periods. Since the OCR1x Registers are updated at BOTTOM, the length of the rising
and the falling slopes will always be equal. This gives symmetrical output pulses and is therefore
frequency correct.
Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using ICR1, the
OCR1A Register is free to be used for generating a PWM output on OC1A. However, if the base PWM
frequency is actively changed by changing the TOP value, using the OCR1A as TOP is clearly a better
choice due to its double buffer feature.
In phase and frequency correct PWM mode, the compare units allow generation of PWM waveforms on
the OC1x pins. Setting the COM1x1:0 bits to 2 will produce a non-inverted PWM and an inverted PWM
output can be generated by setting the COM1x1:0 to 3. Refer to Table 21-4 Compare Output Mode,
Phase Correct and Phase and Frequency Correct PWM(1) on page 133. The actual OC1x value will only
be visible on the port pin if the data direction for the port pin is set as output (DDR_OC1x). The PWM
waveform is generated by setting (or clearing) the OC1x Register at the Compare Match between OCR1x
and TCNT1 when the counter increments, and clearing (or setting) the OC1x Register at Compare Match
between OCR1x and TCNT1 when the counter decrements. The PWM frequency for the output when
using phase and frequency correct PWM can be calculated by the following equation:
�OCnxPFCPWM =

�clk_I/O
2 ⋅ � ⋅ TOP

The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR1x Register represents special cases when generating a PWM waveform
output in the phase correct PWM mode. If the OCR1x is set equal to BOTTOM the output will be

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continuously low and if set equal to TOP the output will be set to high for non-inverted PWM mode. For
inverted PWM the output will have the opposite logic values.
If OCR1A is used to define the TOP value (WGM13:0 = 9) and COM1A1:0 = 1, the OC1A output will
toggle with a 50% duty cycle.

21.10. Timer/Counter Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clkT1) is therefore shown as a clock
enable signal in the following figures. The figures include information on when Interrupt Flags are set, and
when the OCR1x Register is updated with the OCR1x buffer value (only for modes utilizing double
buffering). The next figure shows a timing diagram for the setting of OCF1x.
Figure 21-10 Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling

clkI/O
clkTn

(clkI/O /1)

TCNTn

OCRnx - 1

OCRnx

OCRnx + 1

OCRnx + 2

OCRnx Value

OCFnx
The next figure shows the same timing data, but with the prescaler enabled.
Figure 21-11 Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (fclk_I/O/8)

clkI/O
clkTn

(clkI/O /8)

TCNTn
OCRnx

OCRnx - 1

OCRnx

OCRnx + 1

OCRnx + 2

OCRnx Value

OCFnx
The next figure shows the count sequence close to TOP in various modes. When using phase and
frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams will be
the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same
renaming applies for modes that set the TOV1 Flag at BOTTOM.
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Figure 21-12 Timer/Counter Timing Diagram, no Prescaling.
clkI/O
clkTn

(clkI/O /1)

TCNTn
(CTC and FPWM)

TCNTn
(PC and PFC PWM)

TOP - 1

TOP

BOTTOM

TOP - 1

TOP

TOP - 1

BOTTOM + 1
TOP - 2

TOVn (FPWM)
and ICF n (if used
as TOP)

OCRnx
(Update at TOP)

New OCRnx Value

Old OCRnx Value

The next figure shows the same timing data, but with the prescaler enabled.
Figure 21-13 Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)
clkI/O
clkTn

(clkI/O/8)

TCNTn
(CTC and FPWM)

TCNTn
(PC and PFC PWM)

TOP - 1

TOP

BOTTOM

TOP - 1

TOP

TOP - 1

BOTTOM + 1
TOP - 2

TOVn(FPWM)
and ICF n (if used
as TOP)

OCRnx
(Update at TOP)

Old OCRnx Value

New OCRnx Value

21.11. Register Description

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21.11.1. TCCR1A – Timer/Counter1 Control Register A
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset
addresses. The device is a complex microcontroller with more peripheral units than can be supported
within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space
from 0x60 in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Name: TCCR1A
Offset: 0x2F
Reset: 0x00
Property: When addressing I/O Registers as data space the offset address is 0x4F
Bit
Access
Reset

COM1A1

COM1A0

COM1B1

COM1B0

FOC1A

FOC1B

WGM11

WGM10

R/W

Bits 7:6 – COM1An: Compare Output Mode for Channel A [n = 1:0]
Bits 5:4 – COM1Bn: Compare Output Mode for Channel B [n = 1:0]
The COM1A1:0 and COM1B1:0 control the Output Compare pins (OC1A and OC1B respectively)
behavior. If one or both of the COM1A1:0 bits are written to one, the OC1A output overrides the normal
port functionality of the I/O pin it is connected to. If one or both of the COM1B1:0 bit are written to one,
the OC1B output overrides the normal port functionality of the I/O pin it is connected to. However, note
that the Data Direction Register (DDR) bit corresponding to the OC1A or OC1B pin must be set in order
to enable the output driver.
When the OC1A or OC1B is connected to the pin, the function of the COM1n1:0 bits is dependent of the
WGM13:0 bits setting. The table below shows the COM1n1:0 bit functionality when the WGM13:0 bits are
set to a Normal or a CTC mode (non-PWM).
Table 21-2 Compare Output Mode, non-PWM

COM1A1/COM1B1 COM1A0/COM1B0 Description
0

Normal port operation, OC1A/OC1B disconnected.

Toggle OC1A/OC1B on Compare Match.

Clear OC1A/OC1B on Compare Match (Set output to low
level).

Set OC1A/OC1B on Compare Match (Set output to high
level).

The next table shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the fast PWM
mode.

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Table 21-3 Compare Output Mode, Fast PWM(1)

COM1A1/
COM1B1

COM1A0/
COM1B0

Description

Normal port operation, OC1A/OC1B disconnected.

WGM13:0 = 15: Toggle OC1A on Compare Match, OC1B
disconnected (normal port operation). For all other WGM1
settings, normal port operation, OC1A/OC1B disconnected.

Clear OC1A/OC1B on Compare Match, set OC1A/OC1B at
BOTTOM (non-inverting mode)

Set OC1A/OC1B on Compare Match, clear OC1A/OC1B at
BOTTOM (inverting mode)

Note: 1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In this
case the compare match is ignored, but the set or clear is done at BOTTOM. Refer to Fast PWM Mode
on page 124 for details.
The table below shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the phase
correct or the phase and frequency correct, PWM mode.
Table 21-4 Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM(1)

COM1A1/
COM1B1

COM1A0/
COM1B0

Description

Normal port operation, OC1A/OC1B disconnected.

WGM13:0 = 9 or 14: Toggle OC1A on Compare Match, OC1B
disconnected (normal port operation). For all other WGM1 settings,
normal port operation, OC1A/OC1B disconnected.

Clear OC1A/OC1B on Compare Match when up-counting. Set
OC1A/OC1B on Compare Match when down-counting.

Set OC1A/OC1B on Compare Match when up-counting. Clear
OC1A/OC1B on Compare Match when down-counting.

Note: 1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. Refer
to Phase Correct PWM Mode on page 126 for details.
Bit 3 – FOC1A: Force Output Compare for channel A
Bit 2 – FOC1B: Force Output Compare for channel B
The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM mode. However,
for ensuring compatibility with future devices, these bits must be set to zero when TCCR1A is written
when operating in a PWM mode. When writing a logical one to the FOC1A/FOC1B bit, an immediate
Compare Match is forced on the waveform generation unit. The OC1A/OC1B output is changed
according to its COM1x1:0 bits setting. Note that the FOC1A/FOC1B bits are implemented as strobes.
Therefore it is the value present in the COM1x1:0 bits that determine the effect of the forced compare.
A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on
Compare Match (CTC) mode using OCR1A as TOP.
The FOC1A/FOC1B bits are always read as zero.
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Bits 1:0 – WGM1n: Waveform Generation Mode [n = 1:0]
Combined with the WGM13:2 bits found in the TCCR1B Register, these bits control the counting
sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform
generation to be used, refer to the table below. Modes of operation supported by the Timer/Counter unit
are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width
Modulation (PWM) modes. (See Modes of Operation on page 122).
Table 21-5 Waveform Generation Mode Bit Description
Mode

WGM13

WGM12

WGM11

WGM10

Timer/Counter
Mode of Operation(1)

(CTC1)

(PWM11)

(PWM10)

TOP

Update of

TOV1 Flag

OCR1x at

Set on

Normal

0xFFFF

Immediate

MAX

PWM, Phase Correct, 8-bit

0x00FF

TOP

BOTTOM

PWM, Phase Correct, 9-bit

0x01FF

TOP

BOTTOM

PWM, Phase Correct, 10-bit

0x03FF

TOP

BOTTOM

CTC

OCR1A

Immediate

MAX

Fast PWM, 8-bit

0x00FF

BOTTOM

TOP

Fast PWM, 9-bit

0x01FF

BOTTOM

TOP

Fast PWM, 10-bit

0x03FF

BOTTOM

TOP

PWM, Phase and Frequency
Correct

ICR1

BOTTOM

PWM, Phase and Frequency
Correct

OCR1A

BOTTOM

PWM, Phase Correct

ICR1

TOP

BOTTOM

PWM, Phase Correct

OCR1A

TOP

BOTTOM

CTC

ICR1

Immediate

MAX

Reserved

Fast PWM

ICR1

BOTTOM

TOP

Fast PWM

OCR1A

BOTTOM

TOP

Note:
1. The CTC1 and PWM11:0 bit definition names are obsolete. Use the WGM12:0 definitions.
However, the functionality and location of these bits are compatible with previous versions of the
timer.

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21.11.2. TCCR1B – Timer/Counter1 Control Register B
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset
addresses. The device is a complex microcontroller with more peripheral units than can be supported
within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space
from 0x60 in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Name: TCCR1B
Offset: 0x2E
Reset: 0x00
Property: When addressing I/O Registers as data space the offset address is 0x4E
Bit
Access
Reset

ICNC1

ICES1

WGM13

WGM12

CS12

CS11

CS10

R/W

Bit 7 – ICNC1: Input Capture Noise Canceler
Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is activated,
the input from the Input Capture pin (ICP1) is filtered. The filter function requires four successive equal
valued samples of the ICP1 pin for changing its output. The Input Capture is therefore delayed by four
Oscillator cycles when the noise canceler is enabled.
Bit 6 – ICES1: Input Capture Edge Select
This bit selects which edge on the Input Capture pin (ICP1) that is used to trigger a capture event. When
the ICES1 bit is written to zero, a falling (negative) edge is used as trigger, and when the ICES1 bit is
written to one, a rising (positive) edge will trigger the capture.
When a capture is triggered according to the ICES1 setting, the counter value is copied into the Input
Capture Register (ICR1). The event will also set the Input Capture Flag (ICF1), and this can be used to
cause an Input Capture Interrupt, if this interrupt is enabled.
When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the TCCR1A and
the TCCR1B Register), the ICP1 is disconnected and consequently the Input Capture function is
disabled.
Bit 4 – WGM13: Waveform Generation Mode
Refer to TCCR1A.
Bit 3 – WGM12: Waveform Generation Mode
Refer to TCCR1A.
Bits 2:0 – CS1n: Clock Select [n = 0:2]
The three Clock Select bits select the clock source to be used by the Timer/Counter. Refer to figures
Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling and Timer/Counter Timing Diagram,
Setting of OCF1x, with Prescaler (fclk_I/O/8).

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Table 21-6 Clock Select Bit Description

CA12

CA11

CS10

Description

No clock source (Timer/Counter stopped).

clkI/O/1 (No prescaling)

clkI/O/8 (From prescaler)

clkI/O/64 (From prescaler)

clkI/O/256 (From prescaler)

clkI/O/1024 (From prescaler)

External clock source on T1 pin. Clock on falling edge.

External clock source on T1 pin. Clock on rising edge.

If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the counter
even if the pin is configured as an output. This feature allows software control of the counting.

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21.11.3. TCNT1L – Timer/Counter1 Low byte
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset
addresses. The device is a complex microcontroller with more peripheral units than can be supported
within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space
from 0x60 in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Name: TCNT1L
Offset: 0x2C
Reset: 0x00
Property: When addressing I/O Registers as data space the offset address is 0x4C
Bit

TCNT1L[7:0]
Access
Reset

R/W

Bits 7:0 – TCNT1L[7:0]: Timer/Counter 1 Low byte
The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct access, both
for read and for write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high
and low bytes are read and written simultaneously when the CPU accesses these registers, the access is
performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all
the other 16-bit registers. Refer to Accessing 16-bit Registers for details.
Modifying the counter (TCNT1) while the counter is running introduces a risk of missing a compare match
between TCNT1 and one of the OCR1x Registers.
Writing to the TCNT1 Register blocks (removes) the compare match on the following timer clock for all
compare units.

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21.11.4. TCNT1H – Timer/Counter1 High byte
Name: TCNT1H
Offset: 0x2D
Reset: 0x00
Property: When addressing I/O Registers as data space the offset address is 0x4D
Bit

TCNT1H[7:0]
Access
Reset

R/W

Bits 7:0 – TCNT1H[7:0]: Timer/Counter 1 High byte
Refer to TCNT1L.

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21.11.5. OCR1AL – Output Compare Register 1 A Low byte
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset
addresses. The device is a complex microcontroller with more peripheral units than can be supported
within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space
from 0x60 in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Name: OCR1AL
Offset: 0x2A
Reset: 0x00
Property: When addressing I/O Registers as data space the offset address is 0x4A
Bit

OCR1AL[7:0]
Access
Reset

R/W

Bits 7:0 – OCR1AL[7:0]: Output Compare 1 A Low byte
The Output Compare Registers contain a 16-bit value that is continuously compared with the counter
value (TCNT1). A match can be used to generate an Output Compare interrupt, or to generate a
waveform output on the OC1x pin.
The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written
simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary
High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. Refer to
Accessing 16-bit Registers for details.

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21.11.6. OCR1AH – Output Compare Register 1 A High byte
Name: OCR1AH
Offset: 0x2B
Reset: 0x00
Property: When addressing I/O Registers as data space the offset address is 0x4B
Bit

OCR1AH[7:0]
Access
Reset

R/W

Bits 7:0 – OCR1AH[7:0]: Output Compare 1 A High byte
Refer to OCR1AL.

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21.11.7. OCR1BL – Output Compare Register 1 B Low byte
Name: OCR1BL
Offset: 0x28
Reset: 0x00
Property: When addressing I/O Registers as data space the offset address is 0x48
Bit

OCR1BL[7:0]
Access
Reset

R/W

Bits 7:0 – OCR1BL[7:0]: Output Compare 1 B Low byte
Refer to OCR1AL.

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21.11.8. OCR1BH – Output Compare Register 1 B High byte
Name: OCR1BH
Offset: 0x29
Reset: 0x00
Property: When addressing I/O Registers as data space the offset address is 0x49
Bit

OCR1BH[7:0]
Access
Reset

R/W

Bits 7:0 – OCR1BH[7:0]: Output Compare 1 B High byte
Refer to OCR1AL.

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21.11.9. ICR1L – Input Capture Register 1 Low byte
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset
addresses. The device is a complex microcontroller with more peripheral units than can be supported
within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space
from 0x60 in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Name: ICR1L
Offset: 0x26
Reset: 0x00
Property: When addressing I/O Registers as data space the offset address is 0x46
Bit

ICR1L[7:0]
Access
Reset

R/W

Bits 7:0 – ICR1L[7:0]: Input Capture 1 Low byte
The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin
(or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture can be used for
defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers.
Refer to Accessing 16.bit Registers for details.

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21.11.10. ICR1H – Input Capture Register 1 High byte
Name: ICR1H
Offset: 0x27
Reset: 0x00
Property: When addressing I/O Registers as data space the offset address is 0x47
Bit

ICR1H[7:0]
Access
Reset

R/W

Bits 7:0 – ICR1H[7:0]: Input Capture 1 High byte
Refer to ICR1L.

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21.11.11. TIMSK – Timer/Counter Interrupt Mask Register
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset
addresses. The device is a complex microcontroller with more peripheral units than can be supported
within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space
from 0x60 in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Note: 1. This register contains interrupt control bits for several Timer/Counters, but only Timer1 bits are
described in this section. The remaining bits are described in their respective timer sections.
Name: TIMSK
Offset: 0x39
Reset: 0x00
Property: When addressing I/O Registers as data space the offset address is 0x59
Bit
Access
Reset

TICIE1

OCIE1A

OCIE1B

TOIE1

R/W

Bit 5 – TICIE1: Timer/Counter1, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the
Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt Vector (see Interrupts on
page 66) is executed when the ICF1 Flag, located in TIFR, is set.
Bit 4 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the
Timer/Counter1 Output Compare A match interrupt is enabled. The corresponding Interrupt Vector (see
Interrupts on page 66) is executed when the OCF1A Flag, located in TIFR, is set.
Bit 3 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the
Timer/Counter1 Output Compare B match interrupt is enabled. The corresponding Interrupt Vector (see
Interrupts on page 66) is executed when the OCF1B Flag, located in TIFR, is set.
Bit 2 – TOIE1: Timer/Counter1, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the
Timer/Counter1 Overflow Interrupt is enabled. The corresponding Interrupt Vector (see Interrupts on page
66) is executed when the TOV1 Flag, located in TIFR, is set.

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21.11.12. TIFR – Timer/Counter Interrupt Flag Register
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset
addresses. The device is a complex microcontroller with more peripheral units than can be supported
within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space
from 0x60 in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Note: 1. This register contains flag bits for several Timer/Counters, but only Timer1 bits are described in
this section. The remaining bits are described in their respective timer sections.
Name: TIFR
Offset: 0x38
Reset: 0x00
Property: When addressing I/O Registers as data space the offset address is 0x58
Bit
Access
Reset

ICF1

OCF1A

OCF1B

TOV1

R/W

Bit 5 – ICF1: Timer/Counter1, Input Capture Flag
This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) is
set by the WGM13:0 to be used as the TOP value, the ICF1 Flag is set when the counter reaches the
TOP value.
ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICF1 can
be cleared by writing a logic one to its bit location.
Bit 4 – OCF1A: Timer/Counter1, Output Compare A Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare
Register A (OCR1A).
Note that a Forced Output Compare (FOC1A) strobe will not set the OCF1A Flag.
OCF1A is automatically cleared when the Output Compare Match A Interrupt Vector is executed.
Alternatively, OCF1A can be cleared by writing a logic one to its bit location.
Bit 3 – OCF1B: Timer/Counter1, Output Compare B Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare
Register B (OCR1B).
Note that a Forced Output Compare (FOC1B) strobe will not set the OCF1B Flag.
OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is executed.
Alternatively, OCF1B can be cleared by writing a logic one to its bit location.
Bit 2 – TOV1: Timer/Counter1, Overflow Flag
The setting of this flag is dependent of the WGM13:0 bits setting. In Normal and CTC modes, the TOV1
Flag is set when the timer overflows. Refer to table Waveform Generation Mode Bit Description for the
TOV1 Flag behavior when using another WGM13:0 bit setting.
TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed.
Alternatively, TOV1 can be cleared by writing a logic one to its bit location.

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22.

8-bit Timer/Counter2 with PWM and Asynchronous Operation

22.1.

Features
• Single Channel Counter
• Clear Timer on Compare Match (Auto Reload)
• Glitch-free, phase Correct Pulse Width Modulator (PWM)
• Frequency Generator
• 10-bit Clock Prescaler
• Overflow and Compare Match Interrupt Sources (TOV2 and OCF2)
• Allows Clocking from External 32kHz Watch Crystal Independent of the I/O Clock

Overview
Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. A simplified block
diagram of the 8-bit Timer/Counter is shown in the figure below. For the actual placement of I/O pins, refer
to Pin Configurations. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold.
The device-specific I/O Register and bit locations are listed in the Register Description on page 160.
Figure 22-1 8-bit Timer/Counter Block Diagram
TCCRn

count

TOVn
(Int. Re q.)

cle a r

Control Logic

dire ction

clkTn
TOS C1

BOTTOM

TOP

T/C
Os cilla tor

P re s ca le r

TOS C2

Time r/Counte r
TCNTn

= 0xFF
clkI/O

OCn
(Int. Re q.)
Wave form
Ge ne ra tion

OCn

OCRn

DATA BUS

22.2.

S ynchronize d S ta tus Fla gs

clkI/O
S ync hro nizatio n Unit
clkAS Y

S ta tus Fla gs
AS S Rn
a s ynchronous Mode
S e le ct (AS n)

Related Links
Pin Configurations on page 13
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22.2.1.

Registers
The Timer/Counter (TCNT2) and Output Compare Register (OCR2) are 8-bit registers. Interrupt request
(shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR). All interrupts are
individually masked with the Timer Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown in
the figure since these registers are shared by other timer units.
The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from the
TOSC1/2 pins, as detailed later in this section. The asynchronous operation is controlled by the
Asynchronous Status Register (ASSR). The Clock Select logic block controls which clock source the
Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock
source is selected. The output from the clock select logic is referred to as the timer clock (clkT2).
The double buffered Output Compare Register (OCR2) is compared with the Timer/Counter value at all
times. The result of the compare can be used by the waveform generator to generate a PWM or variable
frequency output on the Output Compare Pin (OC2). For details, see Output Compare Unit. The Compare
Match event will also set the Compare Flag (OCF2) which can be used to generate an Output Compare
interrupt request.

22.2.2.

Definitions
Many register and bit references in this document are written in general form. A lower case “n” replaces
the Timer/Counter number, in this case 2. However, when using the register or bit defines in a program,
the precise form must be used (i.e., TCNT2 for accessing Timer/Counter2 counter value and so on).
The definitions in the following table are also used extensively throughout the document.
Table 22-1 Definitions

22.3.

BOTTOM

The counter reaches the BOTTOM when it becomes zero (0x00).

MAX

The counter reaches its MAXimum when it becomes 0xFF (decimal 255).

TOP

The counter reaches the TOP when it becomes equal to the highest value in the
count sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX)
or the value stored in the OCR2 Register. The assignment is dependent on the
mode of operation.

Timer/Counter Clock Sources
The Timer/Counter can be clocked by an internal synchronous or an external asynchronous clock source.
The clock source clkT2 is by default equal to the MCU clock, clkI/O. When the AS2 bit in the ASSR
Register is written to logic one, the clock source is taken from the Timer/Counter Oscillator connected to
TOSC1 and TOSC2. For details on asynchronous operation, refer to Asynchronous Operation of the
Timer/Counter on page 158. For details on clock sources and prescaler, refer to Timer/Counter Prescaler
on page 159.
Related Links
Timer/Counter0 and Timer/Counter1 Prescalers on page 108

22.4.

Counter Unit
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. The following
figure shows a block diagram of the counter and its surrounding environment.

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Figure 22-2 Counter Unit Block Diagram
TOVn
(Int. Re q.)

DATA BUS

TOS C1
count
TCNTn

cle a r

Control Logic

clk Tn

T/C
Os cilla tor

P re s ca le r

dire ction

BOTTOM

TOS C2

TOP

clkI/O

Signal description (internal signals):
count

Increment or decrement TCNT2 by 1.

direction

Selects between increment and decrement.

clear

Clear TCNT2 (set all bits to zero).

clkT2

Timer/Counter clock.

TOP

Signalizes that TCNT2 has reached maximum value.

BOTTOM

Signalizes that TCNT2 has reached minimum value (zero).

Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each
timer clock (clkT2). clkT2 can be generated from an external or internal clock source, selected by the clock
select bits (CS22:0). When no clock source is selected (CS22:0 = 0) the timer is stopped. However, the
TCNT2 value can be accessed by the CPU, regardless of whether clkT2 is present or not. A CPU write
overrides (has priority over) all counter clear or count operations.
The counting sequence is determined by the setting of the WGM21 and WGM20 bits located in the Timer/
Counter Control Register (TCCR2). There are close connections between how the counter behaves
(counts) and how waveforms are generated on the Output Compare Output OC2. For more details about
advanced counting sequences and waveform generation, refer to Modes of Operation on page 152 .
The Timer/Counter Overflow (TOV2) Flag is set according to the mode of operation selected by the
WGM21:0 bits. TOV2 can be used for generating a CPU interrupt.

22.5.

Output Compare Unit
The 8-bit comparator continuously compares TCNT2 with the Output Compare Register (OCR2).
Whenever TCNT2 equals OCR2, the comparator signals a match. A match will set the Output Compare
Flag (OCF2) at the next timer clock cycle. If enabled (OCIE2 = 1), the Output Compare Flag generates an
Output Compare interrupt. The OCF2 Flag is automatically cleared when the interrupt is executed.
Alternatively, the OCF2 Flag can be cleared by software by writing a logical one to its I/O bit location. The
waveform generator uses the match signal to generate an output according to operating mode set by the
WGM21:0 bits and Compare Output mode (COM21:0) bits. The max and bottom signals are used by the
waveform generator for handling the special cases of the extreme values in some modes of operation
(refer to Modes of Operation on page 152).
The following figure shows a block diagram of the Output Compare unit.

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Figure 22-3 Output Compare Unit, Block Diagram

DATA BUS

OCRn

TCNTn

= (8-bit Compa ra tor )

OCFn (Int. Re q.)

TOP
BOTTOM

Wave form Ge ne ra tor

OCxy

FOCn

WGMn1:0

COMn1:0

The OCR2 Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For
the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The
double buffering synchronizes the update of the OCR2 Compare Register to either top or bottom of the
counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM
pulses, thereby making the output glitch-free.
The OCR2 Register access may seem complex, but this is not case. When the double buffering is
enabled, the CPU has access to the OCR2 Buffer Register, and if double buffering is disabled the CPU
will access the OCR2 directly.
22.5.1.

Force Output Compare
In non-PWM Waveform Generation modes, the match output of the comparator can be forced by writing a
one to the Force Output Compare (FOC2) bit. Forcing Compare Match will not set the OCF2 Flag or
reload/clear the timer, but the OC2 pin will be updated as if a real Compare Match had occurred (the
COM21:0 bits settings define whether the OC2 pin is set, cleared or toggled).

22.5.2.

Compare Match Blocking by TCNT2 Write
All CPU write operations to the TCNT2 Register will block any Compare Match that occurs in the next
timer clock cycle, even when the timer is stopped. This feature allows OCR2 to be initialized to the same
value as TCNT2 without triggering an interrupt when the Timer/Counter clock is enabled.

22.5.3.

Using the Output Compare Unit
Since writing TCNT2 in any mode of operation will block all compare matches for one timer clock cycle,
there are risks involved when changing TCNT2 when using the Output Compare channel, independently
of whether the Timer/Counter is running or not. If the value written to TCNT2 equals the OCR2 value, the

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Compare Match will be missed, resulting in incorrect waveform generation. Similarly, do not write the
TCNT2 value equal to BOTTOM when the counter is downcounting.
The setup of the OC2 should be performed before setting the Data Direction Register for the port pin to
output. The easiest way of setting the OC2 value is to use the Force Output Compare (FOC2) strobe bit
in Normal mode. The OC2 Register keeps its value even when changing between waveform generation
modes.
Be aware that the COM21:0 bits are not double buffered together with the compare value. Changing the
COM21:0 bits will take effect immediately.

Compare Match Output Unit
The Compare Output mode (COM21:0) bits have two functions. The waveform generator uses the
COM21:0 bits for defining the Output Compare (OC2) state at the next Compare Match. Also, the
COM21:0 bits control the OC2 pin output source. The figure below shows a simplified schematic of the
logic affected by the COM21:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown
in bold. Only the parts of the general I/O Port Control Registers (DDR and PORT) that are affected by the
COM21:0 bits are shown. When referring to the OC2 state, the reference is for the internal OC2 Register,
not the OC2 pin.
Figure 22-4 Compare Match Output Unit, Schematic

COMn1
COMn0
FOCn

Wave form
Ge ne ra tor

Q
1

OCn
D

DATABUS

22.6.

OCn
Pin

PORT
D

DDR
clk I/O

The general I/O port function is overridden by the Output Compare (OC2) from the waveform generator if
either of the COM21:0 bits are set. However, the OC2 pin direction (input or output) is still controlled by
the Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC2 pin
(DDR_OC2) must be set as output before the OC2 value is visible on the pin. The port override function is
independent of the Waveform Generation mode.

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The design of the Output Compare Pin logic allows initialization of the OC2 state before the output is
enabled. Note that some COM21:0 bit settings are reserved for certain modes of operation. See Register
Description.
22.6.1.

Compare Output Mode and Waveform Generation
The Waveform Generator uses the COM21:0 bits differently in normal, CTC, and PWM modes. For all
modes, setting the COM21:0 = 0 tells the waveform generator that no action on the OC2 Register is to be
performed on the next Compare Match. For compare output actions in the non-PWM modes refer to table
Compare Output Mode, Non-PWM Mode. For fast PWM mode, refer to table Compare Output Mode, Fast
PWM Mode, and for phase correct PWM refer to table Compare Output Mode, Phase Correct PWM
Mode.
A change of the COM21:0 bits state will have effect at the first Compare Match after the bits are written.
For non-PWM modes, the action can be forced to have immediate effect by using the FOC2 strobe bits.

22.7.

Modes of Operation
The mode of operation (i.e., the behavior of the Timer/Counter and the Output Compare pins) is defined
by the combination of the Waveform Generation mode (WGM21:0) and Compare Output mode
(COM21:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform
Generation mode bits do. The COM21:0 bits control whether the PWM output generated should be
inverted or not (inverted or non-inverted PWM). For non-PWM modes the COM21:0 bits control whether
the output should be set, cleared, or toggled at a Compare Match (refer to Compare Match Output Unit on
page 151).
For detailed timing information refer to Timer/Counter Timing Diagrams on page 156.

22.7.1.

Normal Mode
The simplest mode of operation is the Normal mode (WGM21:0 = 0). In this mode the counting direction
is always up (incrementing), and no counter clear is performed. The counter simply overruns when it
passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal
operation the Timer/Counter Overflow Flag (TOV2) will be set in the same timer clock cycle as the TCNT2
becomes zero. The TOV2 Flag in this case behaves like a ninth bit, except that it is only set, not cleared.
However, combined with the timer overflow interrupt that automatically clears the TOV2 Flag, the timer
resolution can be increased by software. There are no special cases to consider in the Normal mode, a
new counter value can be written anytime.
The Output Compare unit can be used to generate interrupts at some given time. Using the Output
Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of
the CPU time.

22.7.2.

Clear Timer on Compare Match (CTC) Mode
In Clear Timer on Compare or CTC mode (WGM21:0 = 2), the OCR2 Register is used to manipulate the
counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT2) matches
the OCR2. The OCR2 defines the top value for the counter, hence also its resolution. This mode allows
greater control of the Compare Match output frequency. It also simplifies the operation of counting
external events.
The timing diagram for the CTC mode is shown in the figure below. The counter value (TCNT2) increases
until a Compare Match occurs between TCNT2 and OCR2, and then counter (TCNT2) is cleared.

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Figure 22-5 CTC Mode, Timing Diagram
OCn Inte rrupt Fla g S e t

TCNTn

OCn
(Toggle )
Pe riod

(COMn1:0 = 1)
1

An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2
Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
However, changing the TOP to a value close to BOTTOM when the counter is running with none or a low
prescaler value must be done with care since the CTC mode does not have the double buffering feature.
If the new value written to OCR2 is lower than the current value of TCNT2, the counter will miss the
Compare Match. The counter will then have to count to its maximum value (0xFF) and wrap around
starting at 0x00 before the Compare Match can occur.
For generating a waveform output in CTC mode, the OC2 output can be set to toggle its logical level on
each Compare Match by setting the Compare Output mode bits to toggle mode (COM21:0 = 1). The OC2
value will not be visible on the port pin unless the data direction for the pin is set to output. The waveform
generated will have a maximum frequency of fOC2 = fclk_I/O/2 when OCR2 is set to zero (0x00). The
waveform frequency is defined by the following equation:
�OCn =

�clk_I/O
2 ⋅ � ⋅ 1 + OCRn

The N variable represents the prescaler factor (1, 8, 32, 64, 128, 256, or 1024).
As for the Normal mode of operation, the TOV2 Flag is set in the same timer clock cycle that the counter
counts from MAX to 0x00.
22.7.3.

Fast PWM Mode
The fast Pulse Width Modulation or fast PWM mode (WGM21:0 = 3) provides a high frequency PWM
waveform generation option. The fast PWM differs from the other PWM option by its single-slope
operation. The counter counts from BOTTOM to MAX then restarts from BOTTOM. In non-inverting
Compare Output mode, the Output Compare (OC2) is cleared on the Compare Match between TCNT2
and OCR2, and set at BOTTOM. In inverting Compare Output mode, the output is set on Compare Match
and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM
mode can be twice as high as the phase correct PWM mode that uses dual-slope operation. This high
frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC
applications. High frequency allows physically small sized external components (coils, capacitors), and
therefore reduces total system cost.
In fast PWM mode, the counter is incremented until the counter value matches the MAX value. The
counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is
shown in the following figure. The TCNT2 value is in the timing diagram shown as a histogram for
illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The

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small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2 and
TCNT2.
Figure 22-6 Fast PWM Mode, Timing Diagram
OCRn Inte rrupt Fla g S e t

OCRn Upda te
a nd
TOVn Inte rrupt Fla g S e t

TCNTn

OCn

(COMn1:0 = 2)

OCn

(COMn1:0 = 3)

Pe riod

The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches MAX. If the interrupt is
enabled, the interrupt handler routine can be used for updating the compare value.
In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2 pin. Setting the
COM21:0 bits to 2 will produce a non-inverted PWM and an inverted PWM output can be generated by
setting the COM21:0 to 3 (refer to Table 22-4 Compare Output Mode, Fast PWM Mode(1) on page 162).
The actual OC2 value will only be visible on the port pin if the data direction for the port pin is set as
output. The PWM waveform is generated by setting (or clearing) the OC2 Register at the Compare Match
between OCR2 and TCNT2, and clearing (or setting) the OC2 Register at the timer clock cycle the
counter is cleared (changes from MAX to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
�OCnPWM =

�clk_I/O
� ⋅ 256

The N variable represents the prescaler factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR2 Register represent special cases when generating a PWM waveform
output in the fast PWM mode. If the OCR2 is set equal to BOTTOM, the output will be a narrow spike for
each MAX+1 timer clock cycle. Setting the OCR2 equal to MAX will result in a constantly high or low
output (depending on the polarity of the output set by the COM21:0 bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC2 to
toggle its logical level on each Compare Match (COM21:0 = 1). The waveform generated will have a
maximum frequency of foc2 = fclk_I/O/2 when OCR2 is set to zero. This feature is similar to the OC2 toggle
in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM
mode.
22.7.4.

Phase Correct PWM Mode
The phase correct PWM mode (WGM21:0 = 1) provides a high resolution phase correct PWM waveform
generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts
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repeatedly from BOTTOM to MAX and then from MAX to BOTTOM. In non-inverting Compare Output
mode, the Output Compare (OC2) is cleared on the Compare Match between TCNT2 and OCR2 while
upcounting, and set on the Compare Match while downcounting. In inverting Output Compare mode, the
operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope
operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are
preferred for motor control applications.
The PWM resolution for the phase correct PWM mode is fixed to eight bits. In phase correct PWM mode
the counter is incremented until the counter value matches MAX. When the counter reaches MAX, it
changes the count direction. The TCNT2 value will be equal to MAX for one timer clock cycle. The timing
diagram for the phase correct PWM mode is shown on the following figure. The TCNT2 value is in the
timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes noninverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent
compare matches between OCR2 and TCNT2.
Figure 22-7 Phase Correct PWM Mode, Timing Diagram
OCn Inte rrupt Fla g S e t

OCRn Upda te

TOVn Inte rrupt Fla g S e t

TCNTn

OCn

(COMn1:0 = 2)

OCn

(COMn1:0 = 3)

Pe riod

The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The Interrupt
Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2 pin.
Setting the COM21:0 bits to 2 will produce a non-inverted PWM. An inverted PWM output can be
generated by setting the COM21:0 to 3 (refer to table Compare Output Mode, Phase Correct PWM
Mode). The actual OC2 value will only be visible on the port pin if the data direction for the port pin is set
as output. The PWM waveform is generated by clearing (or setting) the OC2 Register at the Compare
Match between OCR2 and TCNT2 when the counter increments, and setting (or clearing) the OC2
Register at Compare Match between OCR2 and TCNT2 when the counter decrements. The PWM
frequency for the output when using phase correct PWM can be calculated by the following equation:
�OCnPCPWM =

�clk_I/O
� ⋅ 510

The N variable represents the prescaler factor (1, 8, 32, 64, 128, 256, or 1024).

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The extreme values for the OCR2 Register represent special cases when generating a PWM waveform
output in the phase correct PWM mode. If the OCR2 is set equal to BOTTOM, the output will be
continuously low and if set equal to MAX the output will be continuously high for non-inverted PWM
mode. For inverted PWM the output will have the opposite logic values.
At the very start of period 2 in the timing diagram above OCn has a transition from high to low even
though there is no Compare Match. The point of this transition is to guarantee symmetry around
BOTTOM. There are two cases that give a transition without Compare Match:
• OCR2A changes its value from MAX, like in the timing diagram above. When the OCR2A value is MAX
the OCn pin value is the same as the result of a down-counting Compare Match. To ensure symmetry
around BOTTOM the OCn value at MAX must correspond to the result of an up-counting Compare
Match.
• The timer starts counting from a value higher than the one in OCR2A, and for that reason misses the
Compare Match and hence the OCn change that would have happened on the way up.

22.8.

Timer/Counter Timing Diagrams
The following figures show the Timer/Counter in Synchronous mode, and the timer clock (clkT2) is
therefore shown as a clock enable signal. In Asynchronous mode, clkI/O should be replaced by the Timer/
Counter Oscillator clock. The figures include information on when Interrupt Flags are set. The following
figure contains timing data for basic Timer/Counter operation. The figure shows the count sequence close
to the MAX value in all modes other than phase correct PWM mode.
Figure 22-8 Timer/Counter Timing Diagram, no Prescaling

clkI/O
clkTn

(clkI/O /1)

TCNTn

MAX - 1

MAX

BOTTOM

BOTTOM + 1

TOVn
The next figure shows the same timing data, but with the prescaler enabled.

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Figure 22-9 Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)

clkI/O
clkTn

(clkI/O /8)

TCNTn

MAX - 1

MAX

BOTTOM

BOTTOM + 1

TOVn
The next figure shows the setting of OCF2 in all modes except CTC mode.
Figure 22-10 Timer/Counter Timing Diagram, Setting of OCF2, with Prescaler (fclk_I/O/8)

clkI/O
clkTn

(clkI/O /8)

TCNTn

OCRn - 1

OCRn

OCRn + 1

OCRn + 2

OCRn Va lue

OCFn
The figure below shows the setting of OCF2 and the clearing of TCNT2 in CTC mode.
Figure 22-11 Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Prescaler (fclk_I/O/8)

clkI/O
clkTn

(clkI/O /8)

TCNTn
(CTC)
OCRn

TOP - 1

TOP

BOTTOM

BOTTOM + 1

TOP

OCFn

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22.9.

Asynchronous Operation of the Timer/Counter

22.9.1.

Asynchronous Operation of Timer/Counter2
When Timer/Counter2 operates asynchronously, some considerations must be taken.
•

Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the
Timer Registers TCNT2, OCR2, and TCCR2 might be corrupted. A safe procedure for switching
clock source is:

1.
2.
3.
4.
5.
6.

Disable the Timer/Counter2 interrupts by clearing OCIE2 and TOIE2.
Select clock source by setting AS2 as appropriate.
Write new values to TCNT2, OCR2, and TCCR2.
To switch to asynchronous operation: Wait for TCN2UB, OCR2UB, and TCR2UB.
Clear the Timer/Counter2 Interrupt Flags.
Enable interrupts, if needed.

•

The Oscillator is optimized for use with a 32.768kHz watch crystal. Applying an external clock to the
TOSC1 pin may result in incorrect Timer/Counter2 operation. The CPU main clock frequency must
be more than four times the Oscillator frequency.
When writing to one of the registers TCNT2, OCR2, or TCCR2, the value is transferred to a
temporary register, and latched after two positive edges on TOSC1. The user should not write a
new value before the contents of the temporary register have been transferred to its destination.
Each of the three mentioned registers have their individual temporary register, which means that
e.g. writing to TCNT2 does not disturb an OCR2 write in progress. To detect that a transfer to the
destination register has taken place, the Asynchronous Status Register – ASSR has been
implemented.
When entering Power-save mode after having written to TCNT2, OCR2, or TCCR2, the user must
wait until the written register has been updated if Timer/Counter2 is used to wake up the device.
Otherwise, the MCU will enter sleep mode before the changes are effective. This is particularly
important if the Output Compare2 interrupt is used to wake up the device, since the Output
Compare function is disabled during writing to OCR2 or TCNT2. If the write cycle is not finished,
and the MCU enters sleep mode before the OCR2UB bit returns to zero, the device will never
receive a Compare Match interrupt, and the MCU will not wake up.
If Timer/Counter2 is used to wake the device up from Power-save or Extended Standby mode,
precautions must be taken if the user wants to re-enter one of these modes: The interrupt logic
needs one TOSC1 cycle to be reset. If the time between wake-up and re-entering sleep mode is
less than one TOSC1 cycle, the interrupt will not occur, and the device will fail to wake up. If the
user is in doubt whether the time before re-entering Power-save or Extended Standby mode is
sufficient, the following algorithm can be used to ensure that one TOSC1 cycle has elapsed:

•

1.
2.
3.

Write a value to TCCR2, TCNT2, or OCR2.
Wait until the corresponding Update Busy Flag in ASSR returns to zero.
Enter Power-save or Extended Standby mode.

•

When the asynchronous operation is selected, the 32.768kHz Oscillator for Timer/Counter2 is
always running, except in Power-down and Standby modes. After a Power-up Reset or Wake-up
from Power-down or Standby mode, the user should be aware of the fact that this Oscillator might
take as long as one second to stabilize. The user is advised to wait for at least one second before
using Timer/Counter2 after Power-up or Wake-up from Power-down or Standby mode. The
contents of all Timer/Counter2 Registers must be considered lost after a wake-up from Power-down

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•

or Standby mode due to unstable clock signal upon start-up, no matter whether the Oscillator is in
use or a clock signal is applied to the TOSC1 pin.
Description of wake up from Power-save or Extended Standby mode when the timer is clocked
asynchronously: When the interrupt condition is met, the wake up process is started on the
following cycle of the timer clock, that is, the timer is always advanced by at least one before the
processor can read the counter value. After wake-up, the MCU is halted for four cycles, it executes
the interrupt routine, and resumes execution from the instruction following SLEEP.
Reading of the TCNT2 Register shortly after wake-up from Power-save may give an incorrect
result. Since TCNT2 is clocked on the asynchronous TOSC clock, reading TCNT2 must be done
through a register synchronized to the internal I/O clock domain. Synchronization takes place for
every rising TOSC1 edge. When waking up from Power-save mode, and the I/O clock (clkI/O) again
becomes active, TCNT2 will read as the previous value (before entering sleep) until the next rising
TOSC1 edge. The phase of the TOSC clock after waking up from Power-save mode is essentially
unpredictable, as it depends on the wake-up time. The recommended procedure for reading
TCNT2 is thus as follows:

1.
2.
3.

Write any value to either of the registers OCR2 or TCCR2.
Wait for the corresponding Update Busy Flag to be cleared.
Read TCNT2.

•

During asynchronous operation, the synchronization of the Interrupt Flags for the asynchronous
timer takes three processor cycles plus one timer cycle. The timer is therefore advanced by at least
one before the processor can read the timer value causing the setting of the Interrupt Flag. The
Output Compare Pin is changed on the timer clock and is not synchronized to the processor clock.

•

22.10. Timer/Counter Prescaler
Figure 22-12 Prescaler for Timer/Counter2

P S R2

clkT2S /1024

clkT2S /256

clkT2S /128

clkT2S /64

AS 2

10-BIT T/C P RES CALER

Cle a r

clkT2S /32

TOS C1

clkT2S

clkT2S /8

clkI/O

CS 20
CS 21
CS 22

TIMER/COUNTER2 CLOCK S OURCE
clkT2

The clock source for Timer/Counter2 is named clkT2S. clkT2S is by default connected to the main system
clock clkI/O. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously clocked from the TOSC1
pin. This enables use of Timer/Counter2 as a Real Time Counter (RTC). When AS2 is set, pins TOSC1
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and TOSC2 are disconnected from Port B. A crystal can then be connected between the TOSC1 and
TOSC2 pins to serve as an independent clock source for Timer/Counter2. The Oscillator is optimized for
use with a 32.768kHz crystal. Applying an external clock source to TOSC1 is not recommended.
For Timer/Counter2, the possible prescaled selections are: clkT2S/8, clkT2S/32, clkT2S/64, clkT2S/128,
clkT2S/256, and clkT2S/1024. Additionally, clkT2S as well as 0 (stop) may be selected. Setting the PSR2 bit
in SFIOR resets the prescaler. This allows the user to operate with a predictable prescaler.

22.11. Register Description

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22.11.1. TCCR2 – Timer/Counter Control Register
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset
addresses. The device is a complex microcontroller with more peripheral units than can be supported
within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space
from 0x60 in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Name: TCCR2
Offset: 0x25
Reset: 0x00
Property: When addressing I/O Registers as data space the offset address is 0x45
Bit

FOC2

WGM20

COM21

COM20

WGM21

CS22

CS21

CS20

Access

R/W

Reset

Bit 7 – FOC2: Force Output Compare
The FOC2 bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring
compatibility with future devices, this bit must be set to zero when TCCR2 is written when operating in
PWM mode. When writing a logical one to the FOC2 bit, an immediate Compare Match is forced on the
waveform generation unit. The OC2 output is changed according to its COM21:0 bits setting. Note that
the FOC2 bit is implemented as a strobe. Therefore it is the value present in the COM21:0 bits that
determines the effect of the forced compare.
A FOC2 strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR2 as
TOP.
The FOC2 bit is always read as zero.
Bit 6 – WGM20: Waveform Generation Mode [n=0:1]
These bits control the counting sequence of the counter, the source for the maximum (TOP) counter
value, and what type of waveform generation to be used. Modes of operation supported by the Timer/
Counter unit are: Normal mode, Clear Timer on Compare Match (CTC) mode, and two types of Pulse
Width Modulation (PWM) modes. See table below and Modes of Operation.
Table 22-2 Waveform Generation Mode Bit Description

Mode WGM21 WGM20 Timer/Counter Mode of Operation(1)
(CTC2) (PWM2)

TOP

Update of
OCR2

TOV2 Flag
Set

Normal

0xFF

Immediate

MAX

PWM, Phase Correct

0xFF

TOP

BOTTOM

CTC

OCR2 Immediate

MAX

Fast PWM

0xFF

MAX

BOTTOM

Note: 1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 definitions.
However, the functionality and location of these bits are compatible with previous versions of the timer.

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Bits 5:4 – COM2n: Compare Match Output Mode [n = 1:0]
These bits control the Output Compare Pin (OC2) behavior. If one or both of the COM21:0 bits are set,
the OC2 output overrides the normal port functionality of the I/O pin it is connected to. However, note that
the Data Direction Register (DDR) bit corresponding to OC2 pin must be set in order to enable the output
driver.
When OC2 is connected to the pin, the function of the COM21:0 bits depends on the WGM21:0 bit
setting. The following table shows the COM21:0 bit functionality when the WGM21:0 bits are set to a
normal or CTC mode (non-PWM).
Table 22-3 Compare Output Mode, Non-PWM Mode

COM21

COM20

Description

Normal port operation, OC2 disconnected.

Toggle OC2 on Compare Match

Clear OC2 on Compare Match

Set OC2 on Compare Match

The next table shows the COM21:0 bit functionality when the WGM21:0 bits are set to fast PWM mode.
Table 22-4 Compare Output Mode, Fast PWM Mode(1)

COM21

COM20

Description

Normal port operation, OC2 disconnected.

Reserved

Clear OC2 on Compare Match, set OC2 at BOTTOM,
(non-inverting mode)

Set OC2 on Compare Match, clear OC2 at BOTTOM,
(inverting mode)

Note: 1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the Compare
Match is ignored, but the set or clear is done at BOTTOM. See Fast PWM Mode for more details.
The table below shows the COM21:0 bit functionality when the WGM21:0 bits are set to phase correct
PWM mode.
Table 22-5 Compare Output Mode, Phase Correct PWM Mode(1)

COM21 COM20 Description
0

Normal port operation, OC2 disconnected.

Reserved

Clear OC2 on Compare Match when up-counting. Set OC2 on Compare Match when
downcounting.

Set OC2 on Compare Match when up-counting. Clear OC2 on Compare Match when
downcounting.

Note: 1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the Compare
Match is ignored, but the set or clear is done at TOP. See Phase Correct PWM Mode for more details.

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Bit 3 – WGM21: Waveform Generation Mode [n=0:1]
Refer to WGM20.
Bits 2:0 – CS2n: Clock Select [n = 2:0]
The three Clock Select bits select the clock source to be used by the Timer/Counter.
Table 22-6 Clock Select Bit Description

CS22

CS21

CS20

Description

No clock source (Timer/Counter stopped).

clkI/O/1 (No prescaling)

clkI/O/8 (From prescaler)

clkI/O/32 (From prescaler)

clkI/O/64 (From prescaler)

clkI/O/128 (From prescaler)

clkI/O/256 (From prescaler)

clkI/O/1024 (From prescaler)

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22.11.2. TCNT2 – Timer/Counter Register
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset
addresses. The device is a complex microcontroller with more peripheral units than can be supported
within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space
from 0x60 in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter
unit 8-bit counter. Writing to the TCNT2 Register blocks (removes) the Compare Match on the following
timer clock. Modifying the counter (TCNT2) while the counter is running, introduces a risk of missing a
Compare Match between TCNT2 and the OCR2 Register.
Name: TCNT2
Offset: 0x24
Reset: 0x00
Property: When addressing I/O Registers as data space the offset address is 0x44
Bit

TCNT2[7:0]
Access
Reset

R/W

Bits 7:0 – TCNT2[7:0]

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22.11.3. OCR2 – Output Compare Register
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset
addresses. The device is a complex microcontroller with more peripheral units than can be supported
within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space
from 0x60 in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
The Output Compare Register contains an 8-bit value that is continuously compared with the counter
value (TCNT2). A match can be used to generate an Output Compare interrupt, or to generate a
waveform output on the OC2 pin.
Name: OCR2
Offset: 0x23
Reset: 0x00
Property: When addressing I/O Registers as data space the offset address is 0x43
Bit

R/W

OCR2[7:0]
Access
Reset

Bits 7:0 – OCR2[7:0]

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22.11.4. ASSR – Asynchronous Status Register
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset
addresses. The device is a complex microcontroller with more peripheral units than can be supported
within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space
from 0x60 in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Name: ASSR
Offset: 0x22
Reset: 0x00
Property: When addressing I/O Registers as data space the offset address is 0x42
Bit
Access
Reset

AS2

TCN2UB

OCR2UB

TCR2UB

R/W

Bit 3 – AS2: Asynchronous Timer/Counter2
When AS2 is written to zero, Timer/Counter 2 is clocked from the I/O clock, clkI/O. When AS2 is written to
one, Timer/Counter 2 is clocked from a crystal Oscillator connected to the Timer Oscillator 1 (TOSC1) pin.
When the value of AS2 is changed, the contents of TCNT2, OCR2, and TCCR2 might be corrupted.
Bit 2 – TCN2UB: Timer/Counter2 Update Busy
When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set. When
TCNT2 has been updated from the temporary storage register, this bit is cleared by hardware. A logical
zero in this bit indicates that TCNT2 is ready to be updated with a new value.
Bit 1 – OCR2UB: Output Compare Register2 Update Busy
When Timer/Counter2 operates asynchronously and OCR2 is written, this bit becomes set. When OCR2
has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in
this bit indicates that OCR2 is ready to be updated with a new value.
Bit 0 – TCR2UB: Timer/Counter Control Register2 Update Busy
When Timer/Counter2 operates asynchronously and TCCR2 is written, this bit becomes set. When
TCCR2 has been updated from the temporary storage register, this bit is cleared by hardware. A logical
zero in this bit indicates that TCCR2 is ready to be updated with a new value.
If a write is performed to any of the three Timer/Counter2 Registers while its update busy flag is set, the
updated value might get corrupted and cause an unintentional interrupt to occur.
The mechanisms for reading TCNT2, OCR2, and TCCR2 are different. When reading TCNT2, the actual
timer value is read. When reading OCR2 or TCCR2, the value in the temporary storage register is read.

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22.11.5. TIMSK – Timer/Counter Interrupt Mask Register
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset
addresses. The device is a complex microcontroller with more peripheral units than can be supported
within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space
from 0x60 in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Name: TIMSK
Offset: 0x39
Reset: 0x00
Property: When addressing I/O Registers as data space the offset address is 0x59
Bit
Access
Reset

OCIE2

TOIE2

R/W

Bit 7 – OCIE2: Timer/Counter2 Output Compare Match Interrupt Enable
When the OCIE2 bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2
Compare Match interrupt is enabled. The corresponding interrupt is executed if a Compare Match in
Timer/Counter2 occurs (i.e., when the OCF2 bit is set in the Timer/Counter Interrupt Flag Register –
TIFR).
Bit 6 – TOIE2: Timer/Counter2 Overflow Interrupt Enable
When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2
Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter2
occurs (i.e., when the TOV2 bit is set in the Timer/Counter Interrupt Flag Register – TIFR).

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22.11.6. TIFR – Timer/Counter Interrupt Flag Register
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset
addresses. The device is a complex microcontroller with more peripheral units than can be supported
within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space
from 0x60 in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Name: TIFR
Offset: 0x38
Reset: 0x00
Property: When addressing I/O Registers as data space the offset address is 0x58
Bit
Access
Reset

OCF2

TOV2

R/W

Bit 7 – OCF2: Output Compare Flag 2
The OCF2 bit is set (one) when a Compare Match occurs between the Timer/Counter2 and the data in
OCR2 – Output Compare Register2. OCF2 is cleared by hardware when executing the corresponding
interrupt Handling Vector. Alternatively, OCF2 is cleared by writing a logic one to the flag. When the I-bit
in SREG, OCIE2 (Timer/Counter2 Compare Match Interrupt Enable), and OCF2 are set (one), the Timer/
Counter2 Compare Match Interrupt is executed.
Bit 6 – TOV2: Timer/Counter2 Overflow Flag
The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hardware
when executing the corresponding interrupt Handling Vector. Alternatively, TOV2 is cleared by writing a
logic one to the flag. When the SREG I-bit, TOIE2 (Timer/Counter2 Overflow Interrupt Enable), and TOV2
are set (one), the Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when
Timer/Counter2 changes counting direction at 0x00.

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22.11.7. SFIOR – Special Function IO Register
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset
addresses. The device is a complex microcontroller with more peripheral units than can be supported
within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space
from 0x60 in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Name: SFIOR
Offset: 0x30
Reset: 0
Property: When addressing I/O Registers as data space the offset address is 0x50
Bit

PSR2
Access
Reset

R/W
0

Bit 1 – PSR2: Prescaler Reset Timer/Counter2
When this bit is written to one, the Timer/Counter2 prescaler will be reset. The bit will be cleared by
hardware after the operation is performed. Writing a zero to this bit will have no effect. This bit will always
be read as zero if Timer/Counter2 is clocked by the internal CPU clock. If this bit is written when Timer/
Counter2 is operating in Asynchronous mode, the bit will remain one until the prescaler has been reset.

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23.

SPI – Serial Peripheral Interface

23.1.

Features
Full-duplex, Three-wire Synchronous Data Transfer
Master or Slave Operation
LSB First or MSB First Data Transfer

•

Seven Programmable Bit Rates

•
•
•
•

End of Transmission Interrupt Flag
Write Collision Flag Protection
Wake-up from Idle Mode
Double Speed (CK/2) Master SPI Mode

Overview
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the
ATmega8A and peripheral devices or between several AVR devices.
Figure 23-1 SPI Block Diagram(1)

DIVIDER
/2/4/8/16/32/64/128

SPI2X

23.2.

•
•
•

Note: 1. Refer to Pin Configurations, table Port B Pins Alternate Functions in Alternate Functions of Port
B for SPI pin placement.
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The interconnection between Master and Slave CPUs with SPI is shown in the figure below. The system
consists of two shift registers, and a Master Clock generator. The SPI Master initiates the communication
cycle when pulling low the Slave Select SS pin of the desired Slave. Master and Slave prepare the data
to be sent in their respective Shift Registers, and the Master generates the required clock pulses on the
SCK line to interchange data. Data is always shifted from Master to Slave on the Master Out – Slave In,
MOSI, line, and from Slave to Master on the Master In – Slave Out, MISO, line. After each data packet,
the Master will synchronize the Slave by pulling high the Slave Select, SS, line.
When configured as a Master, the SPI interface has no automatic control of the SS line. This must be
handled by user software before communication can start. When this is done, writing a byte to the SPI
Data Register starts the SPI clock generator, and the hardware shifts the eight bits into the Slave. After
shifting one byte, the SPI clock generator stops, setting the end of Transmission Flag (SPIF). If the SPI
interrupt enable bit (SPIE) in the SPCR Register is set, an interrupt is requested. The Master may
continue to shift the next byte by writing it into SPDR, or signal the end of packet by pulling high the Slave
Select, SS line. The last incoming byte will be kept in the Buffer Register for later use.
When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated as long as the SS
pin is driven high. In this state, software may update the contents of the SPI Data Register, SPDR, but the
data will not be shifted out by incoming clock pulses on the SCK pin until the SS pin is driven low. As one
byte has been completely shifted, the end of Transmission Flag, SPIF is set. If the SPI Interrupt Enable
bit, SPIE, in the SPCR Register is set, an interrupt is requested. The Slave may continue to place new
data to be sent into SPDR before reading the incoming data. The last incoming byte will be kept in the
Buffer Register for later use.
Figure 23-2 SPI Master-slave Interconnection

SHIFT
ENABLE

Vcc

The system is single buffered in the transmit direction and double buffered in the receive direction. This
means that bytes to be transmitted cannot be written to the SPI Data Register before the entire shift cycle
is completed. When receiving data, however, a received character must be read from the SPI Data
Register before the next character has been completely shifted in. Otherwise, the first byte is lost.
In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct
sampling of the clock signal, the minimum low and high periods should be:
Low period: longer than 2 CPU clock cycles.
High period: longer than 2 CPU clock cycles.
When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden
according to the table below. For more details on automatic port overrides, refer to Alternate Port
Functions.

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Table 23-1 SPI Pin Overrides(1)

Direction, Master SPI

Direction, Slave SPI

MOSI

User Defined

Input

MISO

Input

User Defined

SCK

User Defined

Input

User Defined

Input

Note: 1. Refer to table Port B Pins Alternate Functions in Alternate Functions of Port B for a detailed
description of how to define the direction of the user defined SPI pins.
The following code examples show how to initialize the SPI as a Master and how to perform a simple
transmission. DDR_SPI in the examples must be replaced by the actual Data Direction Register
controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction
bits for these pins. E.g. if MOSI is placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with
DDRB.
Assembly Code Example(1)
SPI_MasterInit:
; Set MOSI and SCK output, all others input
ldi
r17,(1<>8);
UBRR0L = (unsigned char)ubrr;
Enable receiver and transmitter */
UCSRB = (1<> 1) & 0x01;
return ((resh << 8) | resl);
}
Note: 1. See About Code Examples.
The receive function example reads all the I/O Registers into the Register File before any
computation is done. This gives an optimal receive buffer utilization since the buffer
location read will be free to accept new data as early as possible.
Related Links
About Code Examples on page 23
24.7.3.

Receive Compete Flag and Interrupt
The USART Receiver has one flag that indicates the Receiver state.
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The Receive Complete (RXC) Flag indicates if there are unread data present in the receive buffer. This
flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (i.e.,
does not contain any unread data). If the Receiver is disabled (RXEN = 0), the receive buffer will be
flushed and consequently the RXC bit will become zero.
When the Receive Complete Interrupt Enable (RXCIE) in UCSRB is set, the USART Receive Complete
Interrupt will be executed as long as the RXC Flag is set (provided that global interrupts are enabled).
When interrupt-driven data reception is used, the receive complete routine must read the received data
from UDR in order to clear the RXC Flag, otherwise a new interrupt will occur once the interrupt routine
terminates.
24.7.4.

Receiver Error Flags
The USART Receiver has three error flags: Frame Error (FE), Data OverRun (DOR) and Parity Error
(PE). All can be accessed by reading UCSRA. Common for the error flags is that they are located in the
receive buffer together with the frame for which they indicate the error status. Due to the buffering of the
error flags, the UCSRA must be read before the receive buffer (UDR), since reading the UDR I/O location
changes the buffer read location. Another equality for the error flags is that they can not be altered by
software doing a write to the flag location. However, all flags must be set to zero when the UCSRA is
written for upward compatibility of future USART implementations. None of the error flags can generate
interrupts.
The Frame Error (FE) Flag indicates the state of the first stop bit of the next readable frame stored in the
receive buffer. The FE Flag is zero when the stop bit was correctly read (as one), and the FE Flag will be
one when the stop bit was incorrect (zero). This flag can be used for detecting out-of-sync conditions,
detecting break conditions and protocol handling. The FE Flag is not affected by the setting of the USBS
bit in UCSRC since the Receiver ignores all, except for the first, stop bits. For compatibility with future
devices, always set this bit to zero when writing to UCSRA.
The Data OverRun (DOR) Flag indicates data loss due to a Receiver buffer full condition. A Data
OverRun occurs when the receive buffer is full (two characters), it is a new character waiting in the
Receive Shift Register, and a new start bit is detected. If the DOR Flag is set there was one or more serial
frame lost between the frame last read from UDR, and the next frame read from UDR. For compatibility
with future devices, always write this bit to zero when writing to UCSRA. The DOR Flag is cleared when
the frame received was successfully moved from the Shift Register to the receive buffer.
The Parity Error (PE) Flag indicates that the next frame in the receive buffer had a parity error when
received. If parity check is not enabled the PE bit will always be read zero. For compatibility with future
devices, always set this bit to zero when writing to UCSRA. For more details see Parity Bit Calculation
and Parity Checker.

24.7.5.

Parity Checker
The Parity Checker is active when the high USART Parity mode (UPM1) bit is set. Type of parity check to
be performed (odd or even) is selected by the UPM0 bit. When enabled, the Parity Checker calculates the
parity of the data bits in incoming frames and compares the result with the parity bit from the serial frame.
The result of the check is stored in the receive buffer together with the received data and stop bits. The
Parity Error (PE) Flag can then be read by software to check if the frame had a parity error.
The PE bit is set if the next character that can be read from the receive buffer had a parity error when
received and the parity checking was enabled at that point (UPM1 = 1). This bit is valid until the receive
buffer (UDR) is read.

24.7.6.

Disabling the Receiver
In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing receptions
will therefore be lost. When disabled (i.e., the RXEN is set to zero) the Receiver will no longer override
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the normal function of the RxD port pin. The Receiver buffer FIFO will be flushed when the Receiver is
disabled. Remaining data in the buffer will be lost.
24.7.7.

Flushing the Receive Buffer
The Receiver buffer FIFO will be flushed when the Receiver is disabled (i.e., the buffer will be emptied of
its contents). Unread data will be lost. If the buffer has to be flushed during normal operation, due to for
instance an error condition, read the UDR I/O location until the RXC Flag is cleared. The following code
example shows how to flush the receive buffer.
Assembly Code Example(1)
USART_Flush:
sbis
r16, RXC
ret
in
r16, UDR
rjmp
USART_Flush
C Code Example(1)
void USART_Flush( void )
{
unsigned char dummy;
while ( UCSRA & (1< 2 CPU clock cycles for fck < 12MHz, 3 CPU clock cycles for fck ≥ 12MHz
High: > 2 CPU clock cycles for fck < 12MHz, 3 CPU clock cycles for fck ≥ 12MHz
29.9.1.

Serial Programming Algorithm
When writing serial data to the ATmega8A, data is clocked on the rising edge of SCK.
When reading data from the ATmega8A, data is clocked on the falling edge of SCK. Please refer to the
figure, Serial Programming Waveforms in SPI Serial Programming Characteristics section for timing
details.
To program and verify the ATmega8A in the serial programming mode, the following sequence is
recommended (See Serial Programming Instruction set in Serial Programming Instruction Set Serial
Programming Waveforms:
1.

Power-up sequence:

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2.
3.

5.
6.

7.
8.
9.

Apply power between VCC and GND while RESET and SCK are set to “0”. In some systems, the
programmer can not guarantee that SCK is held low during power-up. In this case, RESET must be
given a positive pulse of at least two CPU clock cycles duration after SCK has been set to “0”.
Wait for at least 20ms and enable serial programming by sending the Programming Enable serial
instruction to pin MOSI.
The serial programming instructions will not work if the communication is out of synchronization.
When in sync. the second byte (0x53), will echo back when issuing the third byte of the
Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction
must be transmitted. If the 0x53 did not echo back, give RESET a positive pulse and issue a new
Programming Enable command.
The Flash is programmed one page at a time. The memory page is loaded one byte at a time by
supplying the 5 LSB of the address and data together with the Load Program Memory Page
instruction. To ensure correct loading of the page, the data low byte must be loaded before data
high byte is applied for a given address. The Program Memory Page is stored by loading the Write
Program Memory Page instruction with the 7 MSB of the address. If polling is not used, the user
must wait at least tWD_FLASH before issuing the next page.
Note: If other commands than polling (read) are applied before any write operation (FLASH,
EEPROM, Lock Bits, Fuses) is completed, it may result in incorrect programming.
The EEPROM array is programmed one byte at a time by supplying the address and data together
with the appropriate Write instruction. An EEPROM memory location is first automatically erased
before new data is written. If polling is not used, the user must wait at least tWD_EEPROM before
issuing the next byte. In a chip erased device, no 0xFFs in the data file(s) need to be programmed.
Any memory location can be verified by using the Read instruction which returns the content at the
selected address at serial output MISO.
At the end of the programming session, RESET can be set high to commence normal operation.
Power-off sequence (if needed):
Set RESET to “1”.
Turn VCC power off.

29.9.2.

Data Polling Flash
When a page is being programmed into the Flash, reading an address location within the page being
programmed will give the value 0xFF. At the time the device is ready for a new page, the programmed
value will read correctly. This is used to determine when the next page can be written. Note that the entire
page is written simultaneously and any address within the page can be used for polling. Data polling of
the Flash will not work for the value 0xFF, so when programming this value, the user will have to wait for
at least tWD_FLASH before programming the next page. As a chip-erased device contains 0xFF in all
locations, programming of addresses that are meant to contain 0xFF, can be skipped. See table in next
section for tWD_FLASH value.

29.9.3.

Data Polling EEPROM
When a new byte has been written and is being programmed into EEPROM, reading the address location
being programmed will give the value 0xFF. At the time the device is ready for a new byte, the
programmed value will read correctly. This is used to determine when the next byte can be written. This
will not work for the value 0xFF, but the user should have the following in mind: As a chip-erased device
contains 0xFF in all locations, programming of addresses that are meant to contain 0xFF, can be skipped.
This does not apply if the EEPROM is Reprogrammed without chip-erasing the device. In this case, data
polling cannot be used for the value 0xFF, and the user will have to wait at least tWD_EEPROM before
programming the next byte. See table below for tWD_EEPROM value.

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Table 29-14 Minimum Wait Delay Before Writing the Next Flash or EEPROM Location

Symbol

Minimum Wait Delay

tWD_FUSE

4.5ms

tWD_FLASH

4.5ms

tWD_EEPROM

9.0ms

tWD_ERASE

9.0ms

Figure 29-10 Serial Programming Waveforms
SERIAL DATA INPUT
(MOSI)

MSB

LSB

SERIAL DATA OUTPUT
(MISO)

MSB

LSB

SERIAL CLOCK INPUT
(SCK)
SAMPLE

Table 29-15 Serial Programming Instruction Set
Instruction Format
Instruction

Byte 1

Byte 2

Byte 3

Byte 4

Operation

Programming
Enable

1010 1100

0101 0011

xxxx xxxx

Enable Serial Programming after
RESET goes low.

Chip Erase

1010 1100

100x xxxx

xxxx xxxx

Chip Erase EEPROM and Flash.

Read Program
Memory

0010 H000

0000 aaaa

bbbb bbbb

oooo oooo

Read H (high or low) data o from
Program memory at word address
a:b.

Load Program
Memory Page

0100 H000

0000 xxxx

xxxb bbbb

iiii iiii

Write H (high or low) data i to
Program memory page at word
address b. Data Low byte must be
loaded before Data High byte is
applied within the same address.

Write Program
Memory Page

0100 1100

0000 aaaa

bbbx xxxx

xxxx xxxx

Write Program memory Page at
address a:b.

Read EEPROM
Memory

1010 0000

00xx xxxa

bbbb bbbb

oooo oooo

Read data o from EEPROM
memory at address a:b.

Write EEPROM
Memory

1100 0000

00xx xxxa

bbbb bbbb

iiii iiii

Write data i to EEPROM memory at
address a:b.

Read Lock Bits

0101 1000

0000 0000

xxxx xxxx

xxoo oooo

Read Lock Bits. “0” = programmed,
“1” = unprogrammed. See Table
Lock Bit Byte for details.

Write Lock Bits

1010 1100

111x xxxx

xxxx xxxx

11ii iiii

Write Lock Bits. Set bits = “0” to
program Lock Bits. See Table Lock
Bit Byte for details.

Read Signature
Byte

0011 0000

00xx xxxx

xxxx xxbb

oooo oooo

Read Signature Byte o at address
b.

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Instruction Format
Instruction

Byte 1

Byte 2

Byte 3

Byte 4

Operation

Write Fuse Bits

1010 1100

1010 0000

xxxx xxxx

iiii iiii

Set bits = “0” to program, “1” to
unprogram. See Table Fuse Low
Byte for details.

Write Fuse High
Bits

1010 1100

1010 1000

xxxx xxxx

iiii iiii

Set bits = “0” to program, “1” to
unprogram. See Table Fuse High
Byte for details.

Read Fuse Bits

0101 0000

0000 0000

xxxx xxxx

oooo oooo

Read Fuse Bits. “0” = programmed,
“1” = unprogrammed. See Table
Fuse Low Byte for details.

Read Fuse High
Bits

0101 1000

0000 1000

xxxx xxxx

oooo oooo

Read Fuse high bits. “0” =
programmed, “1” = unprogrammed.
See Table Fuse High Byte for
details.

Read Calibration
Byte

0011 1000

00xx xxxx

0000 00bb

oooo oooo

Read Calibration Byte

Note:
a = address high bits
b = address low bits
H = 0 – Low byte, 1 – High byte
o = data out
i = data in
x = don’t care
29.9.4.

SPI Serial Programming Characteristics
For characteristics of the SPI module, see SPI Timing Characteristics.
Related Links
SPI Timing Characteristics on page 308

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30.

Electrical Characteristics – TA = -40°C to 85°C
Note: Typical values contained in this datasheet are based on simulations and characterization of other
AVR microcontrollers manufactured on the same process technology. Min and Max values will be
available after the device is characterized.
Table 30-1 Absolute Maximum Ratings*

30.1.

Operating
Temperature

-55°C to
+125°C

Storage Temperature

-65°C to
+150°C

Voltage on any Pin
except RESET
with respect to
Ground

-0.5V to VCC
+0.5V

Voltage on RESET
with respect to
Ground

-0.5V to +13.0V

Maximum Operating
Voltage

6.0V

DC Current per I/O
Pin

40.0mA

DC Current VCC and
GND Pins

300.0mA

*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at these or other conditions beyond those indicated
in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

DC Characteristics
Table 30-2 TA = -40°C to 85°C, VCC = 2.7V to 5.5V (unless otherwise noted)

Symbol Parameter

Condition

Min

Typ Max

VIL

Input Low Voltage except XTAL1
and RESET pins

VCC = 2.7V - 5.5V

-0.5

0.2 VCC(1) V

VIH

Input High Voltage except XTAL1 VCC = 2.7V - 5.5V
and RESET pins

0.6
VCC(2)

VCC + 0.5 V

VIL1

Input Low Voltage
XTAL1 pin

VCC = 2.7V - 5.5V

-0.5

0.1 VCC(1) V

VIH1

Input High Voltage
XTAL 1 pin

VCC = 2.7V - 5.5V

0.8
VCC(2)

VCC + 0.5 V

VIL2

Input Low Voltage
RESET pin

VCC = 2.7V - 5.5V

-0.5

0.2 VCC

VIH2

Input High Voltage
RESET pin

VCC = 2.7V - 5.5V

0.9
VCC(2)

VCC + 0.5 V

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Symbol Parameter

Condition

Min

VIL3

Input Low Voltage
RESET pin as I/O

VCC = 2.7V - 5.5V

-0.5

0.2 VCC

VIH3

Input High Voltage
RESET pin as I/O

VCC = 2.7V - 5.5V

0.6
VCC(2)
0.7
VCC(2)

VCC + 0.5 V

VOL

Output Low Voltage(3)
(Ports B,C,D)

IOL = 20mA, VCC = 5V
IOL = 10mA, VCC = 3V

VOH

Output High Voltage(4)
(Ports B,C,D)

IOH = -20mA, VCC = 5V
IOH = -10mA, VCC = 3V

IIL

Input Leakage
Current I/O Pin

VCC = 5.5V, pin low
(absolute value)

μA

IIH

Input Leakage
Current I/O Pin

VCC = 5.5V, pin high
(absolute value)

μA

RRST

Reset Pull-up Resistor

kΩ

Rpu

I/O Pin Pull-up Resistor

kΩ

ICC

Power Supply Current

Power-down mode(5)

Typ Max

0.9
0.6
4.2
2.2

Units
V

V
V
V
V

Active 4MHz, VCC = 3V

Active 8MHz, VCC = 5V

Idle 4MHz, VCC = 3V

0.5 2

Idle 8MHz, VCC = 5V

2.2 7

WDT enabled, VCC = 3V

<10 28

μA

WDT disabled, VCC = 3V

μA

VACIO

Analog Comparator
Input Offset Voltage

VCC = 5V
Vin = VCC/2

IACLK

Analog Comparator
Input Leakage Current

VCC = 5V
Vin = VCC/2

tACPD

Analog Comparator
Propagation Delay

VCC = 2.7V
VCC = 5.0V

-50
750
500

Note:
1. “Max” means the highest value where the pin is guaranteed to be read as low
2. “Min” means the lowest value where the pin is guaranteed to be read as high
3. Although each I/O port can sink more than the test conditions (20mA at VCC = 5V, 10mA at VCC = 3V)
under steady state conditions (non-transient), the following must be observed:
PDIP, TQFP, and QFN/MLF Package:
1] The sum of all IOL, for all ports, should not exceed 300mA.
2] The sum of all IOL, for ports C0 - C5 should not exceed 100mA.
3] The sum of all IOL, for ports B0 - B7, C6, D0 - D7 and XTAL2, should not exceed 200mA.

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If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to
sink current greater than the listed test condition.
4. Although each I/O port can source more than the test conditions (20mA at VCC = 5V, 10mA at VCC =
3V) under steady state conditions (non-transient), the following must be observed:
PDIP, TQFP, and QFN/MLF Package:
1] The sum of all IOH, for all ports, should not exceed 300mA.
2] The sum of all IOH, for port C0 - C5, should not exceed 100mA.
3] The sum of all IOH, for ports B0 - B7, C6, D0 - D7 and XTAL2, should not exceed 200mA.
If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to
source current greater than the listed test condition.
5. Minimum VCC for Power-down is 2.5V.

30.2.

Speed Grades
Figure 30-1 Maximum Frequency vs. Vcc

16 MHz

8 MHz

S a fe Ope ra ting Are a

2.7V

30.3.
30.3.1.

4.5V

5.5V

Clock Characteristics
External Clock Drive Waveforms
Figure 30-2 External Clock Drive Waveforms

VIH1
VIL1

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30.3.2.

External Clock Drive
Table 30-3 External Clock Drive

Symbol Parameter

VCC = 2.7V to 5.5V VCC = 4.5V to 5.5V Units
Min

Max

Min

Max

1/tCLCL

Oscillator Frequency

MHz

tCLCL

Clock Period

125

62.5

tCHCX

High Time

tCLCX

Low Time

tCLCH

Rise Time

1.6

0.5

μs

tCHCL

Fall Time

1.6

0.5

μs

ΔtCLCL

Change in period from one clock cycle to the
next

Table 30-4 External RC Oscillator, Typical Frequencies

R [kΩ](1)

C [pF]

f(2)

650kHz

2.0MHz

Note:
1. R should be in the range 3kΩ - 100kΩ, and C should be at least 20pF. The C values given in the
table includes pin capacitance. This will vary with package type.
2. The frequency will vary with package type and board layout.

30.4.

System and Reset Characteristics
Table 30-5 Reset, Brown-out and Internal Voltage Reference Characteristics

Symbol Parameter
VPOT

Condition

Min Typ Max Units

Power-on Reset Threshold Voltage (rising)(1)

1.4

2.3

Power-on Reset Threshold Voltage (falling)

1.3

2.3

0.9

VCC

1.5

μs

VRST

RESET Pin Threshold Voltage

tRST

Minimum pulse width on RESET Pin

VBOT

Brown-out Reset Threshold Voltage(2)

0.2

BODLEVEL = 1 2.40 2.60 2.90 V
BODLEVEL = 0 3.70 4.00 4.50

tBOD

Minimum low voltage period for Brown-out Detection BODLEVEL = 1

μs

BODLEVEL = 0

μs

130

VHYST

Brown-out Detector hysteresis

VBG

Bandgap reference voltage

1.15 1.23 1.35 V

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Symbol Parameter

Condition

Min Typ Max Units

tBG

Bandgap reference start-up time

IBG

Bandgap reference current consumption

μs
μs

Note:
1. The Power-on Reset will not work unless the supply voltage has been below VPOT (falling).
2. VBOT may be below nominal minimum operating voltage for some devices. For devices where this
is the case, the device is tested down to VCC = VBOT during the production test. This guarantees
that a Brown-out Reset will occur before VCC drops to a voltage where correct operation of the
microcontroller is no longer guaranteed. The test is performed using BODLEVEL = 1 and
BODLEVEL = 0 for ATmega8A.

30.5.

Two-wire Serial Interface Characteristics
The table below describes the requirements for devices connected to the Two-wire Serial Bus. The
ATmega8A Two-wire Serial Interface meets or exceeds these requirements under the noted conditions.
Timing symbols refer to Figure 30-3.
Table 30-6 Two-wire Serial Bus Requirements

Symbol Parameter

Condition

Min

Max

Units
V

VIL

Input Low-voltage

-0.5

0.3VCC

VIH

Input High-voltage

0.7VCC

VCC + 0.5 V

Vhys(1)

Hysteresis of Schmitt Trigger
Inputs

0.05VCC(2)

–

VOL(1)

Output Low-voltage

0.4

tr(1)

Rise Time for both SDA and
SCL

tof(1)

Output Fall Time from VIHmin to
VILmax

tSP(1)

Spikes Suppressed by Input
Filter

Input Current each I/O Pin

Ci(1)

Capacitance for each I/O Pin

fSCL

SCL Clock Frequency

Value of Pull-up resistor

3mA sink current

10pF < Cb < 400pF(3)

20 + 0.1Cb(3)(2) 300

20 + 0.1Cb(3)(2) 250

50(2)

-10

μA

–

fCK(4) > max(16fSCL,
250kHz)(5)

400

kHz

fSCL ≤ 100kHz

�CC − 0.4V
3mA

1000ns
��

�

0.1VCC < Vi < 0.9VCC

fSCL > 100kHz

�CC − 0.4V
3mA

300ns
��

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Symbol Parameter

Condition

Min

Max

Units

tHD;STA

fSCL ≤ 100kHz

4.0

–

μs

fSCL > 100kHz

0.6

–

μs

fSCL ≤ 100kHz(6)

4.7

–

μs

fSCL > 100kHz(7)

1.3

–

μs

fSCL ≤ 100kHz

4.0

–

μs

fSCL > 100kHz

0.6

–

μs

fSCL ≤ 100kHz

4.7

–

μs

fSCL > 100kHz

0.6

–

μs

fSCL ≤ 100kHz

3.45

μs

fSCL > 100kHz

0.9

μs

fSCL ≤ 100kHz

250

–

fSCL > 100kHz

100

–

fSCL ≤ 100kHz

4.0

–

μs

fSCL > 100kHz

0.6

–

μs

fSCL ≤ 100kHz

4.7

–

μs

fSCL > 100kHz

1.3

–

μs

tLOW

tHIGH

tSU;STA

tHD;DAT

tSU;DAT

tSU;STO

tBUF

Hold Time (repeated) START
Condition
Low Period of the SCL Clock

High period of the SCL clock

Set-up time for a repeated
START condition
Data hold time

Data setup time

Setup time for STOP condition

Bus free time between a STOP
and START condition

Note:
1. In ATmega8A, this parameter is characterized and not 100% tested.
2. Required only for fSCL > 100kHz.
3. Cb = capacitance of one bus line in pF.
4. fCK = CPU clock frequency
5. This requirement applies to all ATmega8A Two-wire Serial Interface operation. Other devices
connected to the Two-wire Serial Bus need only obey the general fSCL requirement.
6. The actual low period generated by the ATmega8A Two-wire Serial Interface is (1/fSCL - 2/fCK), thus
fCK must be greater than 6MHz for the low time requirement to be strictly met at fSCL = 100kHz.
7. The actual low period generated by the ATmega8A Two-wire Serial Interface is (1/fSCL - 2/fCK), thus
the low time requirement will not be strictly met for fSCL > 308kHz when fCK = 8MHz. Still,
ATmega8A devices connected to the bus may communicate at full speed (400kHz) with other
ATmega8A devices, as well as any other device with a proper tLOW acceptance margin.
Figure 30-3 Two-wire Serial Bus Timing
tof

tHIGH

tLOW

tr
tLOW

S CL
tS U;S TA
S DA

tHD;S TA

tHD;DAT

tS U;DAT

tS U;S TO

tBUF

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30.6.

SPI Timing Characteristics
See figures below for details.
Table 30-7 SPI Timing Parameters

Description

Mode

Min

SCK period

Master

See Table 23-5 Relationship between SCK and
Oscillator Frequency on page 177

SCK high/low

Master

50% duty cycle

Rise/Fall time

Master

3.6

Setup

Master

Hold

Master

Out to SCK

Master

0.5 • tSCK

SCK to out

Master

SCK to out high

Master

SS low to out

Slave

10 SCK period

Slave

4 • tck

11 SCK high/low(1)

Slave

2 • tck

12 Rise/Fall time

Slave

13 Setup

Slave

14 Hold

Slave

15 SCK to out

Slave

16 SCK to SS high

Slave

Salve

Max

1.6

15
20

17 SS high to tri-state Slave
18 SS low to SCK

Typ

10
2 • tck

Note:
1. In SPI Programming mode the minimum SCK high/low period is:
- 2tCLCL for fCK < 12MHz
- 3tCLCL for fCK > 12MHz

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Figure 30-4 SPI interface timing requirements (Master Mode)
SS
6

S CK
(CP OL = 0)
2

S CK
(CP OL = 1)
4

MIS O
(Da ta Input)

MS B

...

LS B
8

MOS I
(Da ta Output)

MS B

...

LS B

SPI interface timing requirements (Slave Mode)
18

SS
10

S CK
(CP OL = 0)
11

S CK
(CP OL = 1)
13

MOS I
(Da ta Input)

MS B

...

LS B
17

MIS O
(Da ta Output)

MS B

...

LS B

Min(1)

Typ(1) Max(1)

Units

Single Ended Conversion

Bits

Differential Conversion
Gain = 1x or 20x

Bits

Differential Conversion
Gain = 200x

Bits

Related Links
SPCR on page 176

30.7.

ADC Characteristics

Table 30-8 ADC Characteristics

Symbol Parameter
Resolution

Condition

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Symbol Parameter

Min(1)

Condition
Single Ended Conversion
VREF = 4V, VCC = 4V

Absolute accuracy (Including INL,
DNL, Quantization Error, Gain, and
Offset Error)

Typ(1) Max(1)

Units

1.75

LSB

0.75

LSB

0.5

LSB

ADC clock = 200kHz
Single Ended Conversion
VREF = 4V, VCC = 4V
ADC clock = 1MHz

Integral Non-linearity (INL)

Single Ended Conversion
VREF = 4V, VCC = 4V
ADC clock = 200kHz

Differential Non-linearity (DNL)

Single Ended Conversion
VREF = 4V, VCC = 4V
ADC clock = 200kHz

Gain Error

Single Ended Conversion
VREF = 4V, VCC = 4V
ADC clock = 200kHz

Offset Error

Single Ended Conversion
VREF = 4V, VCC = 4V
ADC clock = 200kHz

Conversion Time(4)

Free Running Conversion 13

260

μs
kHz

Clock Frequency

1000

AVCC

Analog Supply Voltage

VCC - 0.3(2)

VCC + 0.3(3) V

VREF

Reference Voltage

2.0

AVCC

2.0

AVCC - 0.2

GND

VREF

TBD

VIN

Input voltage

Input bandwidth
Differential channels
VINT

Internal Voltage Reference

RREF

Reference Input Resistance

RAIN

Analog Input Resistance

2.3

38.5

kHz

2.56

2.8

kΩ

100

MΩ

Note:
1. Values are guidelines only.
2. Minimum for AVCC is 2.7V.
3. Maximum for AVCC is 5.5V.

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Maximum conversion time is 1/50kHz*25 = 0.5ms.

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31.

Electrical Characteristics – TA = -40°C to 105°C
Absolute Maximum Ratings*

31.1.

Operating
Temperature

-55°C to
+125°C

Storage Temperature

-65°C to
+150°C

Voltage on any Pin
except RESET
with respect to
Ground

-0.5V to VCC
+0.5V

Voltage on RESET
with respect to
Ground

-0.5V to +13.0V

Maximum Operating
Voltage

6.0V

DC Current per I/O
Pin

40.0mA

DC Current VCC and
GND Pins

200.0mA

DC Characteristics
Table 31-1 TA = -40°C to 105°C, VCC = 2.7V to 5.5V (unless otherwise noted)

Symbol Parameter

Condition

Min.

Typ. Max.

VIL

Input Low Voltage, Except XTAL1
and RESET pin

VCC = 2.7V - 5.5V

-0.5

0.2VCC(1) V

VIL1

Input Low Voltage,
XTAL1 pin

VCC = 2.7V - 5.5V

-0.5

0.1VCC(1) V

VIL2

Input Low Voltage, RESET pin

VCC = 2.7V - 5.5V

-0.5

0.1VCC(1) V

VIH

Input High Voltage, Except XTAL1
and RESET pins

VCC = 2.7V - 5.5V

0.6VCC(2)

VCC + 0.5 V

VIH1

Input High Voltage, XTAL1 pin

VCC = 2.7V - 5.5V

0.8VCC(2)

VCC + 0.5 V

VIH2

Input High Voltage, RESET pin

VCC = 2.7V - 5.5V

0.9VCC(2)

VCC + 0.5 V

VOL

Output Low Voltage(3),
Port B (except RESET)

IOL =20mA, VCC = 5V
IOL =10mA, VCC = 3V

VOH

Output High Voltage(4),
Port B (except RESET)

IOH = -20mA, VCC = 5V 4.0
IOH = -10mA, VCC = 3V 2.2

IIL

Input Leakage
Current I/O Pin

0.8
0.6

Units

V
V

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312

Symbol Parameter

Condition

IIH

Input Leakage
Current I/O Pin

RRST

Reset Pull-up Resistor

RPU

I/O Pin Pull-up Resistor

VACIO

Analog Comparator
Input Offset Voltage

VCC = 5V
Vin = VCC/2

IACLK

Analog Comparator
Input Leakage Current

VCC = 5V
Vin = VCC/2

Min.

Typ. Max.

Units

μA

kΩ

-50

Note:
1. “Max” means the highest value where the pin is guaranteed to be read as low
2. “Min” means the lowest value where the pin is guaranteed to be read as high
3. Although each I/O port can sink more than the test conditions (20mA at Vcc = 5V, 10mA at Vcc =
3V) under steady state conditions (non-transient), the following must be observed:
PDIP, TQFP, and QFN/MLF Package:
3.1.
The sum of all IOL, for all ports, should not exceed 300mA.
3.2.
The sum of all IOL, for ports C0 - C5 should not exceed 100mA.
3.3.
The sum of all IOL, for ports B0 - B7, C6, D0 - D7 and XTAL2, should not exceed 200mA.

If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not
guaranteed to sink current greater than the listed test condition.
Although each I/O port can source more than the test conditions (20mA at Vcc = 5V, 10mA at Vcc =
3V) under steady state conditions (non-transient), the following must be observed:
PDIP, TQFP, and QFN/MLF Package:
4.1.
The sum of all IOH, for all ports, should not exceed 300mA.
4.2.
The sum of all IOH, for port C0 - C5, should not exceed 100mA
4.3.
The sum of all IOH, for ports B0 - B7, C6, D0 - D7 and XTAL2, should not exceed 200mA.
If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not
guaranteed to source current greater than the listed test condition.

Table 31-2 ATmega8A DC Characteristics

TA = -40°C to 105°C, VCC = 1.8V to 5.5V (unless otherwise noted)
Symbol

Parameter

Condition

Power Supply Current

ICC
Power-down mode(1)

Min.

Typ.

Max.

Units

Active 4MHz, VCC = 3V

Active 8MHz, VCC = 5V

Idle 4MHz, VCC = 3V

Idle 8MHz, VCC = 5V

WDT enabled, VCC = 3V

μA

WDT disabled, VCC = 3V

μA

Note: 1. The current consumption values include input leakage current.

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32.

Typical Characteristics – TA = -40°C to 85°C
The following charts show typical behavior. These figures are not tested during manufacturing. All current
consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups
enabled. A sine wave generator with Rail-to-Rail output is used as clock source.
The power consumption in Power-down mode is independent of clock selection.
The current consumption is a function of several factors such as: operating voltage, operating frequency,
loading of I/O pins, switching rate of I/O pins, code executed and ambient temperature. The dominating
factors are operating voltage and frequency.
The current drawn from capacitive loaded pins may be estimated (for one pin) as CL*VCC*f where CL =
load capacitance, VCC = operating voltage and f = average switching frequency of I/O pin.
The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function
properly at frequencies higher than the ordering code indicates.
The difference between current consumption in Power-down mode with Watchdog Timer enabled and
Power-down mode with Watchdog Timer disabled represents the differential current drawn by the
Watchdog Timer.

Active Supply Current
Figure 32-1 Active Supply Current vs. Frequency (0.1 - 1.0MHz)

ACTIVE S UP P LY CURRENT vs . LOW FREQUENCY
0.1 - 1.0 MHz

1.8
5.5
5.0
4.5
4.0
3.6
3.3

1.6
1.4
1.2
ICC (mA)

32.1.

V
V
V
V
V
V

2.7 V

1
0.8
0.6
0.4
0.2
0
0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

Fre que ncy (MHz)

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Figure 32-2 Active Supply Current vs. Frequency (1 - 16MHz)

ACTIVE S UP P LY CURRENT vs . FREQUENCY
1 - 16 MHZ
14
5.5 V

5.0 V

ICC (mA)

4.5 V

8
4.0 V

3.6 V
3.3 V

4
2.7 V

2
0
0

Fre que ncy (MHz)

Figure 32-3 Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz)

ACTIVE S UP P LY CURRENT vs . VCC
INTERNAL RC OS CILLATOR, 8 MHz

10
-40 °C
25 °C
85 °C

ICC (mA)

8
7
6
5
4
3
2.5

3.5

4.5

5.5

VCC (V)

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Figure 32-4 Active Supply Current vs. VCC (Internal RC Oscillator, 4MHz)

ACTIVE S UP P LY CURRENT vs . VCC
INTERNAL RC OS CILLATOR, 4 MHz

6
-40 °C

5.5

25 °C

85 °C

ICC (mA)

4.5
4
3.5
3
2.5
2
1.5
2.5

3.5

4.5

5.5

VCC (V)

Figure 32-5 Active Supply Current vs. VCC (Internal RC Oscillator, 2MHz)

ACTIVE S UP P LY CURRENT vs . VCC
INTERNAL RC OS CILLATOR, 2 MHz

3.6

-40 °C
25 °C

3.2

85 °C

ICC (mA)

2.8

2.4

1.6

1.2
2.5

3.5

4.5

5.5

VCC (V)

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Figure 32-6 Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz)

ACTIVE S UP P LY CURRENT vs . VCC
INTERNAL RC OS CILLATOR, 1 MHz

1.9

25 °C
85 °C
-40 °C

1.8
1.7

ICC (mA)

1.6
1.5
1.4
1.3
1.2
1.1
1
2.5

3.5

4.5

5.5

VCC (V)

Figure 32-7 Active Supply Current vs. VCC (32kHz External Oscillator)

ACTIVE S UP P LY CURRENT vs . VCC
EXTERNAL OS CILLATOR, 32 kHz

25 °C

ICC (µA)

40
2.5

3.5

4.5

5.5

VCC (V)

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Idle Supply Current
Figure 32-8 Idle Supply Current vs. Frequency (0.1 - 1.0MHz)

IDLE S UP P LY CURRENT vs . LOW FREQUENCY
0.1 - 1.0 MHz
0.35
5.5 V

0.3
5.0 V

ICC (mA)

0.25

4.5 V

0.2

4.0 V

0.15

3.6 V
3.3 V
2.7 V

0.1
0.05
0
0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

Fre que ncy (MHz)

Figure 32-9 Idle Supply Current vs. Frequency (1 - 16MHz)

IDLE S UP P LY CURRENT vs . FREQUENCY
1 - 16 MHz

6
5.5 V

5.0 V

4
ICC (mA)

32.2.

4.5 V

4.0 V
3.6 V

2
3.3 V

2.7 V

0
0

Fre que ncy (MHz)

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Figure 32-10 Idle Supply Current vs. VCC (Internal RC Oscillator, 8MHz)

IDLE S UP P LY CURRENT vs . VCC
INTERNAL RC OS CILLATOR, 8 MHz

-40 °C
25 °C
85 °C

3.5

ICC (mA)

2.5

1.5

1
2.5

3.5

4.5

5.5

VCC (V)

Figure 32-11 Idle Supply Current vs. VCC (Internal RC Oscillator, 4MHz)

IDLE S UP P LY CURRENT vs . VCC
INTERNAL RC OS CILLATOR, 4 MHz

-40 °C
25 °C
85 °C

2
1.8

ICC (mA)

1.6
1.4
1.2
1
0.8
0.6
2.5

3.5

4.5

5.5

VCC (V)

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Figure 32-12 Idle Supply Current vs. VCC (Internal RC Oscillator, 2MHz)

IDLE S UP P LY CURRENT vs . VCC
INTERNAL RC OS CILLATOR, 2 MHz

1
85 °C
25 °C
-40 °C

ICC (mA)

0.8

0.6

0.4

0.2

0
2.5

3.5

4.5

5.5

VCC (V)

Figure 32-13 Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz)

IDLE S UP P LY CURRENT vs . VCC
INTERNAL RC OS CILLATOR, 1 MHz

0.5

85 °C
25 °C
-40 °C

ICC (mA)

0.4

0.3

0.2

0.1

0
2.5

3.5

4.5

5.5

VCC (V)

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Figure 32-14 Idle Supply Current vs. VCC (32kHz External Oscillator)

IDLE S UP P LY CURRENT vs . VCC
32kHz EXTERNAL OS CILLATOR

ICC (uA)

25 °C

0
2.5

3.5

4.5

5.5

VCC (V)

Power-down Supply Current
Figure 32-15 Power-down Supply Current vs. VCC (Watchdog Timer Disabled)

P OWER-DOWN S UP P LY CURRENT vs . VCC
WATCHDOG TIMER DIS ABLED

2.5

85 °C

ICC (uA)

32.3.

-40 °C
25 °C

1.5

0.5

0
2.5

3.5

4.5

5.5

VCC (V)

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Power-down Supply Current vs. VCC (Watchdog Timer Enabled)
P OWER-DOWN S UP P LY CURRENT vs . VCC
WATCHDOG TIMER ENABLED

85 °C
25 °C
-40 °C

ICC (uA)

0
2.5

3.5

4.5

5.5

VCC (V)

Power-save Supply Current
Figure 32-16 Power-save Supply Current vs. VCC (Watchdog Timer Disabled)

P OWER-S AVE S UP P LY CURRENT vs . VCC
WATCHDOG TIMER DIS ABLED

25 °C

ICC (uA)

32.4.

2
2.5

3.5

4.5

5.5

VCC (V)

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Standby Supply Current
Figure 32-17 Standby Supply Current vs. VCC (455kHz Resonator, Watchdog Timer Disabled)

S TANDBY S UP P LY CURRENT vs . VCC

450 kHZ RES ONATOR, WATCHDOG TIMER DIS ABLED

60
25 °C

ICC (uA)

0
2.5

3.5

4.5

5.5

VCC (V)

Figure 32-18 Standby Supply Current vs. VCC (1MHz Resonator, Watchdog Timer Disabled)

S TANDBY S UP P LY CURRENT vs . VCC
1 MHz RES ONATOR, WATCHDOG TIMER DIS ABLED

25 °C

40
ICC (uA)

32.5.

0
2.5

3.5

4.5

5.5

VCC (V)

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Figure 32-19 Standby Supply Current vs. VCC (1MHz Xtal, Watchdog Timer Disabled)

S TANDBY S UP P LY CURRENT vs . VCC

1 MHz XTAL, WATCHDOG TIMER DIS ABLED
60
25 °C

ICC (uA)

0
2.5

3.5

4.5

5.5

VCC (V)

Figure 32-20 Standby Supply Current vs. VCC (4MHz Resonator, Watchdog Timer Disabled)

S TANDBY S UP P LY CURRENT vs . VCC
4 MHz RES ONATOR, WATCHDOG TIMER DIS ABLED

25 °C

ICC (uA)

0
2.5

3.5

4.5

5.5

VCC (V)

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Figure 32-21 Standby Supply Current vs. VCC (4MHz Xtal, Watchdog Timer Disabled)

S TANDBY S UP P LY CURRENT vs . VCC

4 MHz XTAL, WATCHDOG TIMER DIS ABLED

80
25 °C

70
60

ICC (uA)

50
40
30
20
10
0
2.5

3.5

4.5

5.5

VCC (V)

Figure 32-22 Standby Supply Current vs. VCC (6MHz Resonator, Watchdog Timer Disabled)

S TANDBY S UP P LY CURRENT vs . VCC

6 MHz RES ONATOR, WATCHDOG TIMER DIS ABLED

100
25 °C

ICC (uA)

0
2.5

3.5

4.5

5.5

VCC (V)

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Figure 32-23 Standby Supply Current vs. VCC (6MHz Xtal, Watchdog Timer Disabled)

S TANDBY S UP P LY CURRENT vs . VCC

6 MHz XTAL, WATCHDOG TIMER DIS ABLED

120
25 °C

100

ICC (uA)

0
2.5

3.5

4.5

5.5

VCC (V)

Pin Pull-up
Figure 32-24 I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V)

I/O P IN P ULL-UP RES IS TOR CURRENT vs . INP UT VOLTAGE
Vcc = 5V

140
120
100
IOP (uA)

32.6.

80
60
40
20

-40 °C
85 °C
25 °C

0
0

VOP (V)

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Figure 32-25 I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V)

I/O P IN P ULL-UP RES IS TOR CURRENT vs . INP UT VOLTAGE
Vcc = 2.7V

80
70
60

IOP (uA)

50
40
30
20
10

-40 °C
85 °C
25 °C

0
0

0.5

1.5

2.5

VOP (V)

Figure 32-26 Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V)

RES ET P ULL-UP RES IS TOR CURRENT vs . RES ET P IN VOLTAGE
Vcc = 5V

120

100

IRES ET (uA)

85 °C
-40 °C
25 °C

0
0

VRES ET (V)

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Figure 32-27 Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V)
RES ET P ULL-UP RES IS TOR CURRENT vs . RES ET P IN VOLTAGE
Vcc = 2.7V

IRES ET (uA)

85 °C
-40 °C
25 °C

0
0

0.5

1.5

2.5

VRES ET (V)

Pin Driver Strength
Figure 32-28 I/O Pin Output Voltage vs. Source Current (VCC = 5.0V)

I/O P IN OUTP UT VOLTAGE vs . S OURCE CURRENT
VCC = 5V

5
4.9
4.8
VOH (V)

32.7.

4.7
4.6
-40 °C

4.5

25 °C
85 °C

4.4
4.3
0

IOH (mA)

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Figure 32-29 I/O Pin Output Voltage vs. Source Current (VCC = 3.0V)

I/O P IN OUTP UT VOLTAGE vs . S OURCE CURRENT
VCC = 3V

3.5

VOH (V)

2.5
-40 °C
25 °C
85 °C

1.5

1
0

IOH (mA)

Figure 32-30 I/O Pin Output Voltage vs. Sink Current (VCC = 5.0V)

I/O P IN OUTP UT VOLTAGE vs . S INK CURRENT
VCC = 5V

0.6
85 °C

0.5

25 °C

VOL (V)

0.4

-40 °C

0.3

0.2

0.1

0
0

IOL (mA)

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Figure 32-31 I/O Pin Output Voltage vs. Sink Current (VCC = 3.0V)

I/O P IN OUTP UT VOLTAGE vs . S INK CURRENT
VCC = 3V

1
85 °C

0.8
25 °C
VOL (V)

0.6
-40 °C

0.4

0.2

0
0

IOL (mA)

Figure 32-32 Reset Pin as I/O - Pin Source Current vs. Output Voltage (VCC = 5.0V)

RES ET P IN AS I/O - S OURCE CURRENT vs . OUTP UT VOLTAGE
VCC = 5V

5
85 °C

Curre nt (mA)

25 °C

3
-40 °C

0
2

2.5

3.5

4.5

VOH (V)

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Figure 32-33 Reset Pin as I/O - Pin Source Current vs. Output Voltage (VCC = 2.7V)

RES ET P IN AS I/O - S OURCE CURRENT vs . OUTP UT VOLTAGE
VCC = 2.7V

-40 °C

3.5

Curre nt (mA)

25 °C

2.5
2

85 °C

1.5
1
0.5
0
0

0.5

1.5

2.5

VOH (V)

Figure 32-34 Reset Pin as I/O - Pin Sink Current vs. Output Voltage (VCC = 5.0V)

RES ET P IN AS I/O - S INK CURRENT vs . OUTP UT VOLTAGE
VCC = 5V

-40 °C
12

25 °C

Curre nt (mA)

85 °C

8
6
4
2
0
0

0.5

1.5

VOL (V)

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Figure 32-35 Reset Pin as I/O - Pin Sink Current vs. Output Voltage (VCC = 2.7V)

RES ET P IN AS I/O - S INK CURRENT vs . OUTP UT VOLTAGE
VCC = 2.7V
4.5
-40 °C

4
3.5

25 °C

Curre nt (mA)

85 °C

2.5
2
1.5
1
0.5
0
0

0.5

1.5

VOL (V)

Pin Thresholds and Hysteresis
Figure 32-36 I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as “1”)

I/O P IN INP UT THRES HOLD VOLTAGE vs . VCC
VIH, IO P IN READ AS '1'

85 °C
25 °C
-40 °C

2.5
Thre s hold (V)

32.8.

1.5

1
2.5

3.5

4.5

5.5

VCC (V)

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Figure 32-37 I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as “0”)

I/O P IN INP UT THRES HOLD VOLTAGE vs . VCC
VIL, IO P IN READ AS '0'
85 °C
25 °C
-40 °C

2.5

Thre s hold (V)

1.5

0.5

0
2.5

3.5

4.5

5.5

VCC (V)

Figure 32-38 I/O Pin Input Hysteresis vs. VCC

I/O P IN INP UT HYS TERES IS vs . VCC
0.5

-40 °C
25 °C
85 °C

Input Hys te re s is (mV)

0.45

0.4

0.35

0.3

0.25

0.2
2.5

3.5

4.5

5.5

VCC (V)

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333

Figure 32-39 Reset Pin as I/O - Input Threshold Voltage vs. VCC (VIH, Reset Pin Read as “1”)

RES ET P IN AS I/O - INP UT THRES HOLD VOLTAGE vs . VCC
VIH, RES ET P IN READ AS '1'

85 °C
-40 °C
25 °C

2.5

Thre s hold (V)

1.5

0.5

0
2.5

3.5

4.5

5.5

VCC (V)

Figure 32-40 Reset Pin as I/O - Input Threshold Voltage vs. VCC (VIL, Reset Pin Read as “0”)

RES ET P IN AS I/O - INP UT THRES HOLD VOLTAGE vs . VCC
VIL, RES ET P IN READ AS '0'

2.5

25 °C
85 °C
-40 °C

Thre s hold (V)

1.5

0.5

0
2.5

3.5

4.5

5.5

VCC (V)

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Figure 32-41 Reset Pin as I/O - Pin Hysteresis vs. VCC

RES ET P IN AS IO, P IN HYS TERES IS vs . VCC
0.5

85 °C
-40 °C
25 °C

Input Hys te re s is (mV)

0.4

0.3

0.2

0.1

0
2.5

3.5

4.5

5.5

VCC (V)

Figure 32-42 Reset Input Threshold Voltage vs. VCC (VIH, Reset Pin Read as “1”)

RES ET INP UT THRES HOLD VOLTAGE vs . VCC
VIH, RES ET P IN READ AS '1'

2.5

85 °C
-40 °C
25 °C

Thre s hold (V)

1.5

0.5

0
2.5

3.5

4.5

5.5

VCC (V)

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Figure 32-43 Reset Input Threshold Voltage vs. VCC (VIL, Reset Pin Read as “0”)

RES ET INP UT THRES HOLD VOLTAGE vs . VCC
VIL, RES ET P IN READ AS '0'

2.5

85 °C
25 °C
-40 °C

Thre s hold (V)

1.5

0.5

0
2.5

3.5

4.5

5.5

VCC (V)

Figure 32-44 Reset Input Pin Hysteresis vs. VCC

RES ET INP UT P IN HYS TERES IS vs . VCC
0.5

Input Hys te re s is (mV)

0.4

0.3

0.2

0.1

85 °C
25 °C
-40 °C

0
2.5

3.5

4.5

5.5

VCC (V)

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Bod Thresholds and Analog Comparator Offset
Figure 32-45 BOD Thresholds vs. Temperature (BOD Level is 4.0V)

BOD THRES HOLDS vs . TEMP ERATURE
BOD LEVEL IS 4.0V

3.95
Ris ing Vcc

Thre s hold (V)

3.9

3.85

3.8

Fa lling Vcc

3.75

3.7
-40

-30

-20

-10

Te mpe ra ture (°C )

Figure 32-46 BOD Thresholds vs. Temperature (BOD Level is 2.7v)

BOD THRES HOLDS vs . TEMP ERATURE
BOD LEVEL IS 2.7V

2.8

2.75

Ris ing Vcc

2.7
Thre s hold (V)

32.9.

2.65
Fa lling Vcc

2.6

2.55

2.5
-40

-30

-20

-10

Te mpe ra ture (°C )

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Figure 32-47 Bandgap Voltage vs. VCC

BANDGAP VOLTAGE vs . VCC
1.215
85 °C
25 °C

Ba ndga p Volta ge (V)

1.21
1.205

-40 °C

1.2
1.195
1.19
1.185
1.18
2.5

3.5

4.5

5.5

Vcc (V)

Figure 32-48 Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC = 5V)

ANALOG COMP ARATOR OFFS ET VOLTAGE vs . COMMON MODE VOLTAGE
VCC = 5V

0.003

0.002

Compa ra tor Offs e t Volta ge (V)

0.001

85 °C
0

25 °C

-0.001

-0.002

-0.003

-40 °C
-0.004

0.5

1.5

2.5

3.5

4.5

Common Mode Volta ge (V)

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Figure 32-49 Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC = 2.8V)

ANALOG COMP ARATOR OFFS ET VOLTAGE vs . COMMON MODE VOLTAGE
VCC = 2.8V
0.003

Compa ra tor Offs e t Volta ge (V)

0.002

25 °C
85 °C

0.001

-0.001

-40 °C

-0.002

-0.003

-0.004

0.25

0.50

0.75

1.00

1.25

1.5

1.75

2.00

2.25

2.50

2.75

Common Mode Volta ge (V)

32.10. Internal Oscillator Speed
Figure 32-50 Watchdog Oscillator Frequency vs. VCC

WATCHDOG OS CILLATOR FREQUENCY vs . VCC
1050

25 °C
85 °C
-40 °C

F RC (kHz)

1025

1000

975

950

925
2.5

3.5

4.5

5.5

VCC (V)

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Figure 32-51 Calibrated 8MHz RC Oscillator Frequency vs. Temperature

CALIBRATED 8 MHz RC OS CILLATOR FREQUENCY vs . TEMP ERATURE
8,5

F RC (MHz)

5.5 V

7,5

4.0 V

7
2.7 V

6,5

6
-40

-20

100

Te mpe ra ture (°C)

Figure 32-52 Calibrated 8MHz RC Oscillator Frequency vs. VCC

CALIBRATED 8 MHz RC OS CILLATOR FREQUENCY vs . VCC
8.5
-40 °C
25 °C

F RC (MHz)

85 °C

7.5

6.5

6
2.5

3.5

4.5

5.5

VCC (V)

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Figure 32-53 Calibrated 8MHz RC Oscillator Frequency vs. Osccal Value

CALIBRATED 8 MHz RC OS CILLATOR FREQUENCY vs . OS CCAL VALUE
14
25 °C

F RC (MHz)

2
0

112 128 144 160 176 192 208 224 240 256
OS CCAL VALUE

Figure 32-54 Calibrated 4MHz RC Oscillator Frequency vs. Temperature

CALIBRATED 4 MHz RC OS CILLATOR FREQUENCY vs . TEMP ERATURE
4.1

4
5.5 V

F RC (MHz)

3.9

4.0 V

3.8

3.7
2.7 V

3.6

3.5
-40

-20

100

Te mpe ra ture (°C)

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Figure 32-55 Calibrated 4MHz RC Oscillator Frequency vs. VCC

CALIBRATED 4 MHz RC OS CILLATOR FREQUENCY vs . VCC
4.1
-40 °C
25 °C

85 °C

F RC (MHz)

3.9

3.8

3.7

3.6

3.5
2.5

3.5

4.5

5.5

VCC (V)

Figure 32-56 Calibrated 4MHz RC Oscillator Frequency vs. Osccal Value

CALIBRATED 4 MHz RC OS CILLATOR FREQUENCY vs . OS CCAL VALUE
7
25 °C

F RC (MHz)

1
0

112 128 144 160 176 192 208 224 240 256
OS CCAL VALUE

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Figure 32-57 Calibrated 2MHz RC Oscillator Frequency vs. Temperature

CALIBRATED 2 MHz RC OS CILLATOR FREQUENCY vs . TEMP ERATURE
2.1
2.05
5.5 V

F RC (MHz)

2
1.95

4.0 V

1.9
2.7 V

1.85
1.8
1.75
-40

-20

100

Te mpe ra ture (°C)

Figure 32-58 Calibrated 2MHz RC Oscillator Frequency vs. VCC

CALIBRATED 2 MHz RC OS CILLATOR FREQUENCY vs . VCC
2.1
-40 °C
25 °C

2.05

85 °C

F RC (MHz)

1.95

1.9

1.85

1.8
2.5

3.5

4.5

5.5

VCC (V)

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Figure 32-59 Calibrated 2MHz RC Oscillator Frequency vs. Osccal Value

CALIBRATED 2 MHz RC OS CILLATOR FREQUENCY vs . OS CCAL VALUE
3

25 °C

F RC (MHz)

2.5

1.5

0.5
0

112 128 144 160 176 192 208 224 240 256
OS CCAL VALUE

Figure 32-60 Calibrated 1MHz RC Oscillator Frequency vs. Temperature

CALIBRATED 1 MHz RC OS CILLATOR FREQUENCY vs . TEMP ERATURE
1.04
1.02
5.5 V

F RC (MHz)

1
0.98

4.0 V

0.96
0.94

2.7 V

0.92
0.9
-40

-20

100

Te mpe ra ture (°C)

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Figure 32-61 Calibrated 1MHz RC Oscillator Frequency vs. VCC

CALIBRATED 1 MHz RC OS CILLATOR FREQUENCY vs . VCC
1.04

-40 °C
25 °C

1.02

85 °C

F RC (MHz)

1
0.98
0.96
0.94
0.92
0,9
2.5

3.5

4.5

5.5

VCC (V)

Figure 32-62 Calibrated 1MHz RC Oscillator Frequency vs. Osccal Value

CALIBRATED 1 MHz RC OS CILLATOR FREQUENCY vs . OS CCAL VALUE
1.6

25 °C
1.4

F RC (MHz)

1.2
1
0.8
0.6
0.4
0.2
0

112 128 144 160 176 192 208 224 240 256
OS CCAL VALUE

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32.11. Current Consumption of Peripheral Units
Figure 32-63 Brown-out Detector Current vs. VCC

BROWN-OUT DETECTOR CURRENT vs . VCC
20
-40 °C
25 °C

ICC (uA)

85 °C

0
2.5

3.5

4.5

5.5

VCC (V)

Figure 32-64 ADC Current vs. VCC (AREF = AVCC)

ADC CURRENT vs . VCC
AREF = AVCC

300
275

-40 °C
25 °C
85 °C

250

ICC (uA)

225
200
175
150
125
100
2.5

3.5

4.5

5.5

VCC (V)

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Figure 32-65 AREF External Reference Current vs. VCC

AREF EXTERNAL REFERENCE CURRENT vs . VCC
85 °C
25 °C
-40 °C

160

140

ICC (uA)

120

100

40
2.5

3.5

4.5

5.5

VCC (V)

Figure 32-66 32kHz TOSC Current vs. VCC (Watchdog Timer Disabled)

32 kHz TOS C CURRENT vs . VCC
WATCHDOG TIMER DIS ABLED

85 °C
25 °C

ICC (uA)

-40 °C

0
2.5

3.5

4.5

5.5

VCC (V)

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Figure 32-67 Watchdog Timer Current vs. VCC

WATCHDOG TIMER CURRENT vs . VCC
20

85 °C
25 °C
-40 °C

ICC (uA)

0
2.5

3.5

4.5

5.5

VCC (V)

Figure 32-68 Analog Comparator Current vs. VCC

ANALOG COMP ARATOR CURRENT vs . VCC
70

85 °C

25 °C

ICC (uA)

-40 °C

40
30
20
10
0
2.5

3.5

4.5

5.5

VCC (V)

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Figure 32-69 Programming Current vs. VCC

P ROGRAMMING CURRENT vs . VCC
6
-40 °C

5
25 °C

ICC (mA)

85 °C

0
2.5

3.5

4.5

5.5

VCC (V)

32.12. Current Consumption in Reset and Reset Pulsewidth
Figure 32-70 Reset Supply Current vs. VCC (0.1 - 1.0MHz, Excluding Current Through The Reset Pull-up)

RES ET S UP P LY CURRENT vs . VCC

0.1 - 1.0 MHz EXCLUDING CURRENT THROUGH THE RES ET P ULLUP

5.5 V
5.0 V

2.5

ICC (mA)

4.5 V

4.0 V
3.6 V
3.3 V

1.5

2.7 V

0.5

0
0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

Fre que ncy (MHz)

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Figure 32-71 Reset Supply Current vs. VCC (1 - 16MHz, Excluding Current Through The Reset Pull-up)

RES ET S UP P LY CURRENT vs . VCC

1 - 16 MHz EXCLUDING CURRENT THROUGH THE RES ET P ULLUP

12
5.5 V

5.0 V
4.5 V

ICC (mA)

4.0 V
3.6 V

3.3 V
2.7 V

0
0

Fre que ncy (MHz)

Figure 32-72 Reset Pulse Width vs. VCC

MINIMUM RESET PULSE WIDTH vs. VCC
750

Pulsewidth (ns)

600

450

85 °C

300

25 °C
-40 °C

150

0
2,5

3,5

4,5

5,5

VCC (V)

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33.

Typical Characteristics – TA = -40°C to 105°C
The following charts show typical behavior. These figures are not tested during manufacturing. All current
consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups
enabled. A sine wave generator with rail-to-rail output is used as clock source.
All Active- and Idle current consumption measurements are done with all bits in the PRR registers set and
thus, the corresponding I/O modules are turned off. Also the Analog Comparator is disabled during these
measurements. The power consumption in Power-down mode is independent of clock selection.
The current consumption is a function of several factors such as: operating voltage, operating frequency,
loading of I/O pins, switching rate of I/O pins, code executed and ambient temperature. The dominating
factors are operating voltage and frequency.
The current drawn from capacitive loaded pins may be estimated (for one pin) as CL*VCC*f where CL =
load capacitance, VCC = operating voltage and f = average switching frequency of I/O pin.
The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function
properly at frequencies higher than the ordering code indicates.
The difference between current consumption in Power-down mode with Watchdog Timer enabled and
Power-down mode with Watchdog Timer disabled represents the differential current drawn by the
Watchdog Timer.

33.1.

ATmega8A Typical Characteristics

33.1.1.

Active Supply Current
Figure 33-1 Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz)

ACTIVE S UP P LY CURRENT vs . VCC
INTERNAL RC OS CILLATOR, 8 MHz
9.5

-40
25
85
105

8.5

ICC (mA)

7.5

°C
°C
°C
°C

6.5
5.5
4.5
3.5
2.5
2.5

2.8

3.1

3.4

3.7

4.3

4.6

4.9

5.2

5.5

VCC (V)

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Figure 33-2 Active Supply Current vs. VCC (Internal RC Oscillator, 4 MHz)

ACTIVE S UP P LY CURRENT vs . VCC
INTERNAL RC OS CILLATOR, 4 MHz
5.5

-40 °C
25 °C
85 °C
105 °C

5
4.5

ICC (mA)

4
3.5
3
2.5
2
1.5
2.5

2.8

3.1

3.4

3.7

4.3

4.6

4.9

5.2

5.5

VCC (V)

Figure 33-3 Active Supply Current vs. VCC (Internal RC Oscillator, 2 MHz)

ACTIVE S UP P LY CURRENT vs . VCC
INTERNAL RC OS CILLATOR, 2 MHz
3.5

-40 °C

3.25

25 °C

85 °C
105 °C

ICC (mA)

2.75
2.5
2.25
2
1.75
1.5
1.25
1
2.5

2.8

3.1

3.4

3.7

4.3

4.6

4.9

5.2

5.5

VCC (V)

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Figure 33-4 Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz)

ACTIVE S UP P LY CURRENT vs . VCC
INTERNAL RC OS CILLATOR, 1 MHz

25
-40
85
105

1.8
1.7
1.6

°C
°C
°C
°C

ICC (mA)

1.5
1.4
1.3
1.2
1.1
1
0.9
0.8
2.5

2.8

3.1

3.4

3.7

4.3

4.6

4.9

5.2

5.5

VCC (V)

Figure 33-5 Active Supply Current vs. VCC (32 kHz External Oscillator)
ICC ACTIVE S UP P LY CURRENT vs . VCC
32 kHz Crys ta l Os cilla tor WDT DIS ABLED

105
85
25
-40

65
62
59

°C
°C
°C
°C

ICC (uA)

56
53
50
47
44
41
38
35
2.5

2.8

3.1

3.4

3.7

4.3

4.6

4.9

5.2

5.5

VCC (V)

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Idle Supply Current
Figure 33-6 Idle Supply Current vs. VCC (Internal RC Oscillator, 8MHz)

IDLE S UP P LY CURRENT vs . VCC
INTERNAL RC OS CILLATOR, 8 MHz
4.2

-40
25
85
105

3.9
3.6

°C
°C
°C
°C

ICC (mA)

3.3
3
2.7
2.4
2.1
1.8
1.5
1.2
2.5

2.8

3.1

3.4

3.7

4.3

4.6

4.9

5.2

5.5

VCC (V)

Figure 33-7 Idle Supply Current vs. VCC (Internal RC Oscillator, 4MHz)

IDLE S UP P LY CURRENT vs . VCC
INTERNAL RC OS CILLATOR, 4 MHz
2.1

-40
25
85
105

1.9

°C
°C
°C
°C

1.7
ICC (mA)

33.1.2.

1.5
1.3
1.1
0.9
0.7
2.5

2.8

3.1

3.4

3.7

4.3

4.6

4.9

5.2

5.5

VCC (V)

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Figure 33-8 Idle Supply Current vs. VCC (Internal RC Oscillator, 2MHz)

IDLE S UP P LY CURRENT vs . VCC
INTERNAL RC OS CILLATOR, 2 MHz

105
85
25
-40

0.9
0.8

°C
°C
°C
°C

ICC (mA)

0.7
0.6
0.5
0.4
0.3
0.2
2.5

2.8

3.1

3.4

3.7

4.3

4.6

4.9

5.2

5.5

VCC (V)

Figure 33-9 Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz)

IDLE S UP P LY CURRENT vs . VCC
INTERNAL RC OS CILLATOR, 1 MHz
0.5

105
85
25
-40

0.45

°C
°C
°C
°C

0.4

ICC (mA)

0.35
0.3
0.25
0.2
0.15
0.1
2.5

2.8

3.1

3.4

3.7

4.3

4.6

4.9

5.2

5.5

VCC (V)

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Figure 33-10 Idle Supply Current vs. VCC (32kHz External RC Oscillator)

P OWER-S AVE S UP P LY CURRENT vs . VCC
WATCHDOG TIMER DIS ABLED
24.5

105 °C

22.5

85 °C

20.5

25 °C
-40 °C

ICC (uA)

18.5
16.5
14.5
12.5
10.5
8.5
6.5
2.5

2.8

3.1

3.4

3.7

4.3

4.6

4.9

5.2

5.5

VCC (V)

Power-down Supply Current
Figure 33-11 Power-down Supply Current vs. VCC (Watchdog Timer Disabled)

P OWER-DOWN S UP P LY CURRENT vs . VCC
WATCHDOG TIMER DIS ABLED
4.5

105 °C

4
3.5
3
ICC (uA)

33.1.3.

2.5

85 °C

2
1.5

-40 °C
25 °C

1
0.5
0
2.5

2.8

3.1

3.4

3.7

4.3

4.6

4.9

5.2

5.5

VCC (V)

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Power-down Supply Current vs. VCC (Watchdog Timer Enabled)
P OWER-DOWN S UP P LY CURRENT vs . VCC
WATCHDOG TIMER ENABLED
24

105 °C
85 °C
25 °C
-40 °C

ICC (uA)

18
15
12
9
6
3
2.5

2.8

3.1

3.4

3.7

4.3

4.6

4.9

5.2

5.5

VCC (V)

Power-save Supply Current
Figure 33-12 Power-save Supply Current vs. VCC (Watchdog Timer Disabled)

P OWER-S AVE S UP P LY CURRENT vs . VCC
WATCHDOG TIMER DIS ABLED

105 °C

15
14
13

85 °C

12
11
ICC (uA)

33.1.4.

25 °C
-40 °C

10
9
8
7
6
5
4
2.5

2.8

3.1

3.4

3.7

4.3

4.6

4.9

5.2

5.5

VCC (V)

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33.1.5.

Standby Supply Current
Figure 33-13 Standby Supply Current vs. VCC (32kHz External RC Oscillator)

S TANDBY CURRENT vs . VCC
32 kHz Crys ta l Os cilla tor WDT DIS ABLED
25

105 °C

85 °C

25 °C
-40 °C

ICC (uA)

19
17
15
13
11
9
7
2.5

2.8

3.1

3.4

3.7

4.3

4.6

4.9

5.2

5.5

VCC (V)

Pin Pull-up
Figure 33-14 I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V)

I/O P IN P ULL-UP RES IS TOR CURRENT vs . INP UT VOLTAGE

140
120
100
IOP (uA)

33.1.6.

80
60
40

85
25
-40
105

20
0
0

0.5

1.5

2.5

3.5

4.5

°C
°C
°C
°C

VOP (V)

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Figure 33-15 I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V)

I/O P IN P ULL-UP RES IS TOR CURRENT vs . INP UT VOLTAGE

80
70
60

IOP (uA)

50
40
30
20

85
25
-40
105

10
0
0

0.3

0.6

0.9

1.2

1.5

1.8

2.1

2.4

°C
°C
°C
°C

2.7

VOP (V)

Figure 33-16 Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V)

RES ET P ULL-UP RES IS TOR CURRENT vs . RES ET P IN VOLTAGE

110
100
90
80
IRES ET (uA)

70
60
50
40
30

25
-40
85
105

20
10
0
0

0.5

1.5

2.5

3.5

4.5

°C
°C
°C
°C

VRES ET (V)

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Figure 33-17 Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V)

RES ET P ULL-UP RES IS TOR CURRENT vs . RES ET P IN VOLTAGE

60
50

IRES ET (uA)

40
30
20

25
-40
85
105

10
0
0

0.3

0.6

0.9

1.2

1.5

1.8

2.1

2.4

°C
°C
°C
°C

2.7

VRES ET (V)

Pin Driver Strength
Figure 33-18 I/O Pin Output Voltage vs. Source Current (VCC = 5V)

I/O P IN OUTP UT VOLTAGE vs . S OURCE CURRENT
NORMAL P OWER P INS
5.1
5
4.9
4.8
VOH (V)

33.1.7.

4.7
4.6

-40 °C

4.5

25 °C

4.4

85 °C
105 °C

4.3
0

IOH (mA)

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Figure 33-19 I/O Pin Output Voltage vs. Source Current (VCC = 3V)

I/O P IN OUTP UT VOLTAGE vs . S OURCE CURRENT
NORMAL P OWER P INS
3.1
2.9

VOH (V)

2.7
2.5

-40 °C

2.3

25 °C

2.1

85 °C
105 °C

1.9
1.7
0

IOH (mA)

Figure 33-20 I/O Pin Output Voltage vs. Sink Current (VCC = 5V)

I/O P IN OUTP UT VOLTAGE vs . S INK CURRENT
NORMAL P OWER P INS

105 °C
85 °C

0.6
0.5

25 °C

VOL (V)

0.4

-40 °C

0.3
0.2
0.1
0
0

IOL (mA)

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Figure 33-21 I/O Pin Output Voltage vs. Sink Current (VCC = 3V)

I/O P IN OUTP UT VOLTAGE vs . S INK CURRENT
NORMAL P OWER P INS
1

105 °C
85 °C

0.9
0.8

VOL (V)

0.7

25 °C

0.6

-40 °C

0.5
0.4
0.3
0.2
0.1
0
0

IOL(mA)

Pin Threshold and Hysteresis
Figure 33-22 I/O Pin Input Threshold vs. VCC (VIH , I/O Pin Read as ‘1’)

I/O P IN INP UT THRES HOLD VOLTAGE vs . VCC
VIH, IO P IN READ AS '1'
3

105
85
25
-40

2.8
2.6
Thre s hold (V)

33.1.8.

°C
°C
°C
°C

2.4
2.2
2
1.8
1.6
1.4
1.2
2.5

2.8

3.1

3.4

3.7

4.3

4.6

4.9

5.2

5.5

VCC (V)

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Figure 33-23 I/O Pin Input Threshold vs. VCC (VIL, I/O Pin Read as ‘0’)

I/O P IN INP UT THRES HOLD VOLTAGE vs . VCC
VIL, IO P IN READ AS '0'
2.5

105
85
25
-40

Thre s hold (V)

2.2

°C
°C
°C
°C

1.9

1.6

1.3

1
2.5

2.8

3.1

3.4

3.7

4.3

4.6

4.9

5.2

5.5

VCC (V)

Figure 33-24 I/O Pin Input Hysteresis vs. VCC

I/O P IN INP UT HYS TERES IS vs . VCC

0.5

85 °C
105 °C

Input Hys te re s is (mV)

0.45

0.4

0.35

-40 °C
25 °C

0.3

0.25
2.5

2.8

3.1

3.4

3.7

4.3

4.6

4.9

5.2

5.5

VCC (V)

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Figure 33-25 Reset Pin as I/O - Input Threshold vs. VCC (VIH , I/O Pin Read as ‘1’)

I/O P IN INP UT THRES HOLD VOLTAGE vs . VCC
VIH, IO P IN READ AS '1'
3.1

-40
25
85
105

Thre s hold (V)

2.8

°C
°C
°C
°C

2.5
2.2
1.9
1.6
1.3
2.5

2.8

3.1

3.4

3.7

4.3

4.6

4.9

5.2

5.5

VCC (V)

Figure 33-26 Reset Pin as I/O - Input Threshold vs. VCC (VIL, I/O Pin Read as ‘0’)

I/O P IN INP UT THRES HOLD VOLTAGE vs . VCC
VIL, IO P IN READ AS '0'

105
85
25
-40

2.3
2.1

°C
°C
°C
°C

Thre s hold (V)

1.9
1.7
1.5
1.3
1.1
0.9
2.5

2.8

3.1

3.4

3.7

4.3

4.6

4.9

5.2

5.5

VCC (V)

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Figure 33-27 Reset Pin as I/O - Pin Hysteresis vs. VCC

RES ET P IN AS IO, INP UT HYS TERES IS vs . VCC
VIL, IO P IN READ AS "0"

-40
25
85
105

0.7

Input Hys te re s is (mV)

0.65

°C
°C
°C
°C

0.6
0.55
0.5
0.45
0.4
2.5

2.8

3.1

3.4

3.7

4.3

4.6

4.9

5.2

5.5

VCC (V)

Figure 33-28 Reset Input Threshold vs. VCC (VIH , Reset Pin Read as ‘1’)

RES ET INP UT THRES HOLD VOLTAGE vs . VCC
VIH, IO P IN READ AS '1'

-40
25
85
105

2.5
2.3

°C
°C
°C
°C

Thre s hold (V)

2.1
1.9
1.7
1.5
1.3
1.1
0.9
2.5

2.8

3.1

3.4

3.7

4.3

4.6

4.9

5.2

5.5

VCC (V)

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Figure 33-29 Reset Input Threshold vs. VCC (VIL, Reset Pin Read as ‘0’)

RES ET INP UT THRES HOLD VOLTAGE vs . VCC
VIL, IO P IN READ AS '0'
2.4

105
85
25
-40

2.2

°C
°C
°C
°C

Thre s hold (V)

2
1.8
1.6
1.4
1.2
1
2.5

2.8

3.1

3.4

3.7

4.3

4.6

4.9

5.2

5.5

VCC (V)

Figure 33-30 Reset Pin Input Hysteresis vs. VCC

RES ET P IN INP UT HYS TERES IS vs . VCC

0.5
0.45

Input Hys te re s is (mV)

0.4
0.35
0.3

-40 °C

0.25

25 °C

0.2
0.15

105 °C
85 °C

0.1
0.05
0
2.5

2.8

3.1

3.4

3.7

4.3

4.6

4.9

5.2

5.5

VCC (V)

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BOD Threshold
Figure 33-31 BOD Threshold vs. Temperature (VCC = 4.3V)

BOD THRES HOLDS vs . TEMP ERATURE

Ris ing Vcc

3.98
3.96

Thre s hold (V)

3.94
3.92
3.9
3.88

Fa lling Vcc

3.86
3.84
3.82
3.8
-40

-30

-20

-10

100 110

Te mpe ra ture (°C)

Figure 33-32 BOD Threshold vs. Temperature (VCC = 2.7V)

BOD THRES HOLDS vs . TEMP ERATURE

2.63

Ris ing Vcc

2.61
2.59
Thre s hold (V)

33.1.9.

2.57
2.55
2.53

Fa lling Vcc

2.51
2.49
2.47
-40

-30

-20

-10

100 110

Te mpe ra ture (°C)

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Figure 33-33 Bandgap Voltage vs. Temperature

BANDGAP VOLTAGE vs . TEMP ERATURE

1.215
1.21

5.5V

Ba ndga p Volta ge (V)

1.205

5.0V

1.2

4.0V
3.3V
2.7V

1.195
1.19
1.185

1.8V

1.18
1.175
-40

-30

-20

-10

100 110

Te mpe ra ture (°C)

Figure 33-34 Bandgap Voltage vs. VCC

CALIB BANDGAP VOLTAGE vs . VCC

1.215

25
85
105
-40

1.21

Ba ndga p Volta ge (V)

1.205

°C
°C
°C
°C

1.2
1.195
1.19
1.185
1.18
1.175
1.5

2.5

3.5

4.5

5.5

VCC (V)

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33.1.10. Internal Oscillator Speed
Figure 33-35 Watchdog Oscillator Frequency vs. VCC

WATCHDOG OS CILLATOR FREQUENCY vs . OP ERATING VOLTAGE

25
-40
85
105

1120
1100

°C
°C
°C
°C

F RC (kHz)

1080
1060
1040
1020
1000
980
2.5

2.8

3.1

3.4

3.7

4.3

4.6

4.9

5.2

5.5

VCC (V)

Figure 33-36 Watchdog Oscillator Frequency vs. Temperature

WATCHDOG OS CILLATOR FREQUENCY vs . TEMP ERATURE

1130
1110

5.5 V

F RC (kHz)

1090
1070

5.0 V

1050

4.5 V
4.0 V
3.6 V

1030
1010

2.7 V

990
970
-40

-30

-20

-10

100 110

Te mpe ra ture (°C)

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Figure 33-37 Calibrated 8MHz RC Oscillator vs. Temperature

CALIBRATED 8MHz RC OS CILLATOR FREQUENCY vs . TEMP ERATURE

8.4
8.2
8

F RC (MHz)

7.8

5.5
5.0
4.5
4.0
3.6

7.6
7.4
7.2

V
V
V
V
V

3.0 V

6.8

2.7 V

6.6
-40

-30

-20

-10

100 110

Te mpe ra ture (°C)

Figure 33-38 Calibrated 8MHz RC Oscillator vs. VCC

CALIBRATED 8MHz RC OS CILLATOR FREQUENCY vs . OP ERATING
VOLTAGE
8.4

-40 °C

8.2

25 °C

85 °C
105 °C

F RC (MHz)

7.8
7.6
7.4
7.2
7
6.8
6.6
2.5

2.8

3.1

3.4

3.7

4.3

4.6

4.9

5.2

5.5

VCC (V)

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Figure 33-39 Calibrated 8MHz RC Oscillator vs. OSCCAL Value

CALIBRATED 8MHz RC OS CILLATOR FREQUENCY vs . OS CCAL VALUE

-40
25
85
105

°C
°C
°C
°C

F RC (MHz)

10
8
6
4
2
0

112 128 144 160 176 192 208 224 240 256
OS CCAL (X1)

Figure 33-40 Calibrated 4MHz RC Oscillator vs. Temperature

CALIBRATED 4MHz RC OS CILLATOR FREQUENCY vs . TEMP ERATURE

4.15
4.05

F RC (MHz)

3.95

5.5
5.0
4.5
4.0
3.6

3.85
3.75

V
V
V
V
V

3.0 V

3.65

2.7 V
3.55
-40

-30

-20

-10

100 110

Te mpe ra ture (°C)

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Figure 33-41 Calibrated 4MHz RC Oscillator vs. VCC

CALIBRATED 4MHz RC OS CILLATOR FREQUENCY vs . OP ERATING
VOLTAGE
4.1

-40 °C

4.05

25 °C

85 °C
105 °C

F RC (MHz)

3.95
3.9
3.85
3.8
3.75
3.7
3.65
3.6
2.5

2.8

3.1

3.4

3.7

4.3

4.6

4.9

5.2

5.5

VCC (V)

Figure 33-42 Calibrated 4MHz RC Oscillator vs. OSCCAL Value

CALIBRATED 4MHz RC OS CILLATOR FREQUENCY vs . OS CCAL VALUE

-40
25
85
105

F RC (MHz)

°C
°C
°C
°C

5
4
3
2
1
0

112 128 144 160 176 192 208 224 240 256
OS CCAL (X1)

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Figure 33-43 Calibrated 2MHz RC Oscillator vs. Temperature

CALIBRATED 2MHz RC OS CILLATOR FREQUENCY vs . TEMP ERATURE

2.05
2.02
1.99

5.5 V

F RC (MHz)

1.96

5.0
4.5
4.0
3.6

1.93
1.9
1.87
1.84

V
V
V
V

3.0 V
2.7 V

1.81
1.78
-40

-30

-20

-10

100 110

Te mpe ra ture (°C)

Figure 33-44 Calibrated 2MHz RC Oscillator vs. VCC

CALIBRATED 2MHz RC OS CILLATOR FREQUENCY vs . OP ERATING
VOLTAGE
2.07

-40 °C
25 °C

2.04
2.01

85 °C
105 °C

F RC (MHz)

1.98
1.95
1.92
1.89
1.86
1.83
1.8
2.5

2.8

3.1

3.4

3.7

4.3

4.6

4.9

5.2

5.5

VCC (V)

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Figure 33-45 Calibrated 2MHz RC Oscillator vs. OSCCAL Value

CALIBRATED 2MHz RC OS CILLATOR FREQUENCY vs . OS CCAL
VALUE
3.5

-40
25
85
105

3.2
2.9

°C
°C
°C
°C

F RC (MHz)

2.6
2.3
2
1.7
1.4
1.1
0.8
0

112 128 144 160 176 192 208 224 240 256
OS CCAL (X1)

Figure 33-46 Calibrated 1MHz RC Oscillator vs. Temperature

CALIBRATED 1MHz RC OS CILLATOR FREQUENCY vs . TEMP ERATURE

1.03
1.01

5.5 V

F RC (MHz)

0.99

5.0
4.5
4.0
3.6

0.97
0.95

V
V
V
V

3.0 V
2.7 V

0.93
0.91
-40

-30

-20

-10

100 110

Te mpe ra ture (°C)

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Figure 33-47 Calibrated 1MHz RC Oscillator vs. VCC

CALIBRATED 1 MHz RC OS CILLATOR FREQUENCY vs . OP ERATING
VOLTAGE

F RC (MHz)

1.04
1.02

-40 °C
25 °C

85 °C
105 °C

0.98
0.96
0.94
0.92
0.9
2.5

2.8

3.1

3.4

3.7

4.3

4.6

4.9

5.2

5.5

VCC (V)

Figure 33-48 Calibrated 1MHz RC Oscillator vs. OSCCAL Value

CALIBRATED 1MHz RC OS CILLATOR FREQUENCY vs . OS CCAL VALUE

1.8

-40
25
85
105

1.6

F RC (MHz)

1.4

°C
°C
°C
°C

1.2
1
0.8
0.6
0.4
0.2
0

112 128 144 160 176 192 208 224 240 256
OS CCAL (X1)

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33.1.11. Current Consumption of Peripheral Units
Figure 33-49 Brown-out Detector Current vs. VCC

BROWNOUT DETECTOR CURRENT vs . VCC

-40 °C

25 °C

ICC (uA)

85 °C
105 °C

14
13
12
11
10
9
8
2.5

2.8

3.1

3.4

3.7

4.3

4.6

4.9

5.2

5.5

VCC (V)

Figure 33-50 ADC Current vs. VCC (AREF = AVCC)

ACTIVE S UP P LY CURRENT WITH ADC AT 50KHz vs . VCC

300

-40
25
85
105

280
260

°C
°C
°C
°C

ICC (uA)

240
220
200
180
160
140
2.5

2.8

3.1

3.4

3.7

4.3

4.6

4.9

5.2

5.5

VCC (V)

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Figure 33-51 Watchdog Timer Current vs. VCC

WATCHDOG TIMER CURRENT vs . VCC

85
105
25
-40

18
16

°C
°C
°C
°C

ICC (uA)

14
12
10
8
6
4
2.5

2.8

3.1

3.4

3.7

4.3

4.6

4.9

5.2

5.5

VCC (V)

Figure 33-52 Analog Comparator Current vs. VCC

ANALOG COMP ARATOR CURRENT vs . VCC

105 °C

85 °C

ICC (mA)

25 °C

56
52
48

-40 °C

44
40
36
32
2.5

2.8

3.1

3.4

3.7

4.3

4.6

4.9

5.2

5.5

VCC (V)

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Figure 33-53 Programming Current vs. VCC

EEP ROM WRITE CURRENT vs . Vcc
Ext Clk
6

-40 °C

25 °C

ICC (mA)

85 °C
105 °C

3
2
1
0
2.5

2.8

3.1

3.4

3.7

4.3

4.6

4.9

5.2

5.5

VCC (V)

33.1.12. Current Consumption in Reset and Reset Pulsewidth
Figure 33-54 Reset Supply Current vs. VCC (0.1 - 1.0MHz, Excluding Current Through the Reset Pull-up)

RES ET S UP P LY CURRENT vs . VCC
EXCLUDING CURRENT THROUGH THE RES ET P ULLUP
3

ICC (mA)

5.5 V
2.5

5.0 V

4.5 V
4.0 V
3.6 V

1.5

2.7 V
1
0.5
0
0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

Fre que ncy (MHz)

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Figure 33-55 Reset Supply Current vs. VCC (1 - 16MHz, Excluding Current Through the Reset Pull-up)

RES ET S UP P LY CURRENT vs . VCC
EXCLUDING CURRENT THROUGH THE RES ET P ULLUP
12

5.5 V

5.0 V
4.5 V

ICC (mA)

4.0 V

3.6 V
4

2.7 V
2
0
0

Fre que ncy (MHz)

Figure 33-56 Minimum Reset Pulsewidth vs. VCC

MINIMUM RES ET P ULS E WIDTH vs . VCC

800
700

P uls e width (ns )

600
500
400

105
85
25
-40

300
200

°C
°C
°C
°C

100
2.5

2.8

3.1

3.4

3.7

4.3

4.6

4.9

5.2

5.5

VCC (V)

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34.

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x3F (0x5F)

SREG

0x3E (0x5E)

SPH

–

SP10

SP9

SP8

0x3D (0x5D)

SPL

SP7

SP6

SP5

SP4

SP3

SP2

SP1

SP0

0x3C (0x5C)

Reserved

–

0x3B (0x5B)

GICR

INT1

INT0

–

IVSEL

IVCE

0x3A (0x5A)

GIFR

INTF1

INTF0

–

0x39 (0x59)

TIMSK

OCIE2

TOIE2

TICIE1

OCIE1A

OCIE1B

TOIE1

–

TOIE0

0x38 (0x58)

TIFR

OCF2

TOV2

ICF1

OCF1A

OCF1B

TOV1

–

TOV0

0x37 (0x57)

SPMCR

SPMIE

RWWSB

–

RWWSRE

BLBSET

PGWRT

PGERS

SPMEN

0x36 (0x56)

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

0x35 (0x55)

MCUCR

SM2

SM1

SM0

ISC11

ISC10

ISC01

ISC00

0x34 (0x54)

MCUCSR

–

WDRF

BORF

EXTRF

PORF

0x33 (0x53)

TCCR0

–

CS02

CS01

CS00

0x32 (0x52)

TCNT0

0x31 (0x51)

OSCCAL

0x30 (0x50)

SFIOR

–

ACME

PUD

PSR2

PSR10

0x2F (0x4F)

TCCR1A

COM1A1

COM1A0

COM1B1

COM1B0

FOC1A

FOC1B

WGM11

WGM10

0x2E (0x4E)

TCCR1B

ICNC1

ICES1

–

WGM13

WGM12

CS12

CS11

CS10

0x2D (0x4D)

TCNT1H

CS21

CS20

Timer/Counter0 (8 Bits)
Oscillator Calibration Register

Timer/Counter1 – Counter Register High byte

0x2C (0x4C)

TCNT1L

Timer/Counter1 – Counter Register Low byte

0x2B (0x4B)

OCR1AH

Timer/Counter1 – Output Compare Register A High byte

0x2A (0x4A)

OCR1AL

Timer/Counter1 – Output Compare Register A Low byte

0x29 (0x49)

OCR1BH

Timer/Counter1 – Output Compare Register B High byte

0x28 (0x48)

OCR1BL

Timer/Counter1 – Output Compare Register B Low byte

0x27 (0x47)

ICR1H

Timer/Counter1 – Input Capture Register High byte

0x26 (0x46)

ICR1L

0x25 (0x45)

TCCR2

Timer/Counter1 – Input Capture Register Low byte
FOC2

WGM20

COM21

COM20

WGM21

CS22

0x24 (0x44)

TCNT2

Timer/Counter2 (8 Bits)

0x23 (0x43)

OCR2

Timer/Counter2 Output Compare Register

0x22 (0x42)

ASSR

0x21 (0x41)
0x20(1)

–

AS2

TCN2UB

OCR2UB

TCR2UB

WDTCR

–

WDCE

WDE

WDP2

WDP1

WDP0

UBRRH

URSEL

–

(0x40)(1)

UCSRC

URSEL

UMSEL

UPM1

UPM0

UBRR[11:8]
USBS

UCSZ1

UCSZ0

UCPOL

0x1F (0x3F)

EEARH

–

EEAR8

0x1E (0x3E)

EEARL

EEAR7

EEAR6

EEAR5

EEAR4

EEAR3

EEAR2

EEAR1

EEAR0

0x1D (0x3D)

EEDR

0x1C (0x3C)

EECR

–

EERIE

EEMWE

EEWE

EERE

0x1B (0x3B)

Reserved

0x1A (0x3A)

Reserved

0x19 (0x39)

Reserved

0x18 (0x38)

PORTB

PORTB7

PORTB6

PORTB5

PORTB4

PORTB3

PORTB2

PORTB1

PORTB0

0x17 (0x37)

DDRB

DDB7

DDB6

DDB5

DDB4

DDB3

DDB2

DDB1

DDB0

0x16 (0x36)

PINB

PINB7

PINB6

PINB5

PINB4

PINB3

PINB2

PINB1

PINB0

0x15 (0x35)

PORTC

–

PORTC6

PORTC5

PORTC4

PORTC3

PORTC2

PORTC1

PORTC0

EEPROM Data Register

Atmel ATmega8A [DATASHEET]
Atmel-8159F-8-bit AVR Microcontroller_Datasheet_Complete-09/2015

380

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x14 (0x34)

DDRC

–

DDC6

DDC5

DDC4

DDC3

DDC2

DDC1

DDC0

0x13 (0x33)

PINC

–

PINC6

PINC5

PINC4

PINC3

PINC2

PINC1

PINC0

0x12 (0x32)

PORTD

PORTD7

PORTD6

PORTD5

PORTD4

PORTD3

PORTD2

PORTD1

PORTD0

0x11 (0x31)

DDRD

DDD7

DDD6

DDD5

DDD4

DDD3

DDD2

DDD1

DDD0

0x10 (0x30)

PIND

PIND7

PIND6

PIND5

PIND4

PIND3

PIND2

PIND1

PIND0

0x0F (0x2F)

SPDR

0x0E (0x2E)

SPSR

SPIF

WCOL

–

SPI Data Register
–

–

SPI2X

0x0D (0x2D)

SPCR

SPIE

SPE

DORD

MSTR

CPOL

CPHA

SPR1

SPR0

0x0C (0x2C)

UDR

0x0B (0x2B)

UCSRA

RXC

TXC

UDRE

USART I/O Data Register
FE

DOR

U2X

MPCM

0x0A (0x2A)

UCSRB

RXCIE

TXCIE

UDRIE

RXEN

TXEN

UCSZ2

RXB8

TXB8

0x09 (0x29)

UBRRL

0x08 (0x28)

ACSR

ACD

ACBG

ACO

ACIC

ACIS1

ACIS0

USART Baud Rate Register Low byte
ACI

ACIE

0x07 (0x27)

ADMUX

REFS1

REFS0

ADLAR

–

MUX3

MUX2

MUX1

MUX0

0x06 (0x26)

ADCSRA

ADEN

ADSC

ADFR

ADIF

ADIE

ADPS2

ADPS1

ADPS0

0x05 (0x25)

ADCH

ADC Data Register High byte

0x04 (0x24)

ADCL

ADC Data Register Low byte

0x03 (0x23)

TWDR

Two-wire Serial Interface Data Register

0x02 (0x22)

TWAR

TWA6

TWA5

TWA4

0x01 (0x21)

TWSR

TWS7

TWS6

TWS5

0x00 (0x20)

TWBR

TWA3

TWA2

TWA1

TWA0

TWGCE

TWS4

TWS3

–

TWPS1

TWPS0

Two-wire Serial Interface Bit Rate Register

Note:
1. Refer to the USART description for details on how to access UBRRH and UCSRC.
2. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved
I/O memory addresses should never be written.
3. Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI
instructions will operate on all bits in the I/O Register, writing a one back into any flag read as set,
thus clearing the flag. The CBI and SBI instructions work with registers 0x00 to 0x1F only.

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381

35.

Instruction Set Summary

ARITHMETIC AND LOGIC INSTRUCTIONS
Mnemonics

Operands

Description

Operation

Flags

#Clocks

ADD

Rd, Rr

Add two Registers

Rd ← Rd + Rr

Z,C,N,V,H

ADC

Rd, Rr

Add with Carry two Registers

Rd ← Rd + Rr + C

Z,C,N,V,H

ADIW

Rdl,K

Add Immediate to Word

Rdh:Rdl ← Rdh:Rdl + K

Z,C,N,V,S

SUB

Rd, Rr

Subtract two Registers

Rd ← Rd - Rr

Z,C,N,V,H

SUBI

Rd, K

Subtract Constant from Register

Rd ← Rd - K

Z,C,N,V,H

SBC

Rd, Rr

Subtract with Carry two Registers

Rd ← Rd - Rr - C

Z,C,N,V,H

SBCI

Rd, K

Subtract with Carry Constant from Reg.

Rd ← Rd - K - C

Z,C,N,V,H

SBIW

Rdl,K

Subtract Immediate from Word

Rdh:Rdl ← Rdh:Rdl - K

Z,C,N,V,S

AND

Rd, Rr

Logical AND Registers

Rd ← Rd · Rr

Z,N,V

ANDI

Rd, K

Logical AND Register and Constant

Rd ← Rd · K

Z,N,V

Rd, Rr

Logical OR Registers

Rd ← Rd v Rr

Z,N,V

ORI

Rd, K

Logical OR Register and Constant

Rd ← Rd v K

Z,N,V

EOR

Rd, Rr

Exclusive OR Registers

Rd ← Rd ⊕ Rr

Z,N,V

COM

One’s Complement

Rd ← 0xFF - Rd

Z,C,N,V

NEG

Two’s Complement

Rd ← 0x00 - Rd

Z,C,N,V,H

SBR

Rd,K

Set Bit(s) in Register

Rd ← Rd v K

Z,N,V

CBR

Rd,K

Clear Bit(s) in Register

Rd ← Rd · (0xFF - K)

Z,N,V

INC

Increment

Rd ← Rd + 1

Z,N,V

DEC

Decrement

Rd ← Rd - 1

Z,N,V

TST

Test for Zero or Minus

Rd ← Rd · Rd

Z,N,V

CLR

Clear Register

Rd ← Rd ⊕ Rd

Z,N,V

SER

Set Register

Rd ← 0xFF

None

MUL

Rd, Rr

Multiply Unsigned

R1:R0 ← Rd x Rr

Z,C

MULS

Rd, Rr

Multiply Signed

R1:R0 ← Rd x Rr

Z,C

MULSU

Rd, Rr

Multiply Signed with Unsigned

R1:R0 ← Rd x Rr

Z,C

FMUL

Rd, Rr

Fractional Multiply Unsigned

R1:R0 ← (Rd x Rr) << 1

Z,C

FMULS

Rd, Rr

Fractional Multiply Signed

R1:R0 ← (Rd x Rr) << 1

Z,C

FMULSU

Rd, Rr

Fractional Multiply Signed with Unsigned

R1:R0 ← (Rd x Rr) << 1

Z,C

BRANCH INSTRUCTIONS
Mnemonics

Operands

Description

Operation

Flags

#Clocks

RJMP

Relative Jump

PC ← PC + k + 1

None

Indirect Jump to (Z)

PC ← Z

None

IJMP
JMP(1)

Direct Jump

PC ← k

None

RCALL

Relative Subroutine Call

PC ← PC + k + 1

None

Atmel ATmega8A [DATASHEET]
Atmel-8159F-8-bit AVR Microcontroller_Datasheet_Complete-09/2015

382

BRANCH INSTRUCTIONS
Mnemonics

Operands

Description

Operation

Flags

#Clocks

Indirect Call to (Z)

PC ← Z

None

Direct Subroutine Call

PC ← k

None

RET

Subroutine Return

PC ← STACK

None

RETI

Interrupt Return

PC ← STACK

ICALL
CALL(1)

CPSE

Rd,Rr

Compare, Skip if Equal

if (Rd = Rr) PC ← PC + 2 or 3

None

1/2/3

Rd,Rr

Compare

Rd - Rr

Z, N,V,C,H

CPC

Rd,Rr

Compare with Carry

Rd - Rr - C

Z, N,V,C,H

CPI

Rd,K

Compare Register with Immediate

Rd - K

Z, N,V,C,H

SBRC

Rr, b

Skip if Bit in Register Cleared

if (Rr(b)=0) PC ← PC + 2 or 3

None

1/2/3

SBRS

Rr, b

Skip if Bit in Register is Set

if (Rr(b)=1) PC ← PC + 2 or 3

None

1/2/3

SBIC

P, b

Skip if Bit in I/O Register Cleared

if (P(b)=0) PC ← PC + 2 or 3

None

1/2/3

SBIS

P, b

Skip if Bit in I/O Register is Set

if (P(b)=1) PC ← PC + 2 or 3

None

1/2/3

BRBS

s, k

Branch if Status Flag Set

if (SREG(s) = 1) then PC←PC+k + 1

None

1/2

BRBC

s, k

Branch if Status Flag Cleared

if (SREG(s) = 0) then PC←PC+k + 1

None

1/2

BREQ

Branch if Equal

if (Z = 1) then PC ← PC + k + 1

None

1/2

BRNE

Branch if Not Equal

if (Z = 0) then PC ← PC + k + 1

None

1/2

BRCS

Branch if Carry Set

if (C = 1) then PC ← PC + k + 1

None

1/2

BRCC

Branch if Carry Cleared

if (C = 0) then PC ← PC + k + 1

None

1/2

BRSH

Branch if Same or Higher

if (C = 0) then PC ← PC + k + 1

None

1/2

BRLO

Branch if Lower

if (C = 1) then PC ← PC + k + 1

None

1/2

BRMI

Branch if Minus

if (N = 1) then PC ← PC + k + 1

None

1/2

BRPL

Branch if Plus

if (N = 0) then PC ← PC + k + 1

None

1/2

BRGE

Branch if Greater or Equal, Signed

if (N Å V= 0) then PC ← PC + k + 1

None

1/2

BRLT

Branch if Less Than Zero, Signed

if (N Å V= 1) then PC ← PC + k + 1

None

1/2

BRHS

Branch if Half Carry Flag Set

if (H = 1) then PC ← PC + k + 1

None

1/2

BRHC

Branch if Half Carry Flag Cleared

if (H = 0) then PC ← PC + k + 1

None

1/2

BRTS

Branch if T Flag Set

if (T = 1) then PC ← PC + k + 1

None

1/2

BRTC

Branch if T Flag Cleared

if (T = 0) then PC ← PC + k + 1

None

1/2

BRVS

Branch if Overflow Flag is Set

if (V = 1) then PC ← PC + k + 1

None

1/2

BRVC

Branch if Overflow Flag is Cleared

if (V = 0) then PC ← PC + k + 1

None

1/2

BRIE

Branch if Interrupt Enabled

if ( I = 1) then PC ← PC + k + 1

None

1/2

BRID

Branch if Interrupt Disabled

if ( I = 0) then PC ← PC + k + 1

None

1/2

BIT AND BIT-TEST INSTRUCTIONS
Mnemonics

Operands

Description

Operation

Flags

#Clocks

SBI

P,b

Set Bit in I/O Register

I/O(P,b) ← 1

None

CBI

P,b

Clear Bit in I/O Register

I/O(P,b) ← 0

None

Atmel ATmega8A [DATASHEET]
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383

BIT AND BIT-TEST INSTRUCTIONS
Mnemonics

Operands

Description

Operation

Flags

#Clocks

LSL

Logical Shift Left

Rd(n+1) ← Rd(n), Rd(0) ← 0

Z,C,N,V

LSR

Logical Shift Right

Rd(n) ← Rd(n+1), Rd(7) ← 0

Z,C,N,V

ROL

Rotate Left Through Carry

Rd(0)←C,Rd(n+1)← Rd(n),C¬Rd(7)

Z,C,N,V

ROR

Rotate Right Through Carry

Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)

Z,C,N,V

ASR

Arithmetic Shift Right

Rd(n) ← Rd(n+1), n=0:6

Z,C,N,V

SWAP

Swap Nibbles

Rd(3:0)←Rd(7:4),Rd(7:4)¬Rd(3:0)

None

BSET

Flag Set

SREG(s) ← 1

SREG(s)

BCLR

Flag Clear

SREG(s) ← 0

SREG(s)

BST

Rr, b

Bit Store from Register to T

T ← Rr(b)

BLD

Rd, b

Bit load from T to Register

Rd(b) ← T

None

SEC

Set Carry

C←1

CLC

Clear Carry

C←0

SEN

Set Negative Flag

N←1

CLN

Clear Negative Flag

N←0

SEZ

Set Zero Flag

Z←1

CLZ

Clear Zero Flag

Z←0

SEI

Global Interrupt Enable

I←1

CLI

Global Interrupt Disable

I←0

SES

Set Signed Test Flag

S←1

CLS

Clear Signed Test Flag

S←0

SEV

Set Twos Complement Overflow.

V←1

CLV

Clear Twos Complement Overflow

V←0

SET

Set T in SREG

T←1

CLT

Clear T in SREG

T←0

SEH

Set Half Carry Flag in SREG

H←1

CLH

Clear Half Carry Flag in SREG

H←0

DATA TRANSFER INSTRUCTIONS
Mnemonics

Operands

Description

Operation

Flags

#Clocks

MOV

Rd, Rr

Move Between Registers

Rd ← Rr

None

MOVW

Rd, Rr

Copy Register Word

Rd+1:Rd ← Rr+1:Rr

None

LDI

Rd, K

Load Immediate

Rd ← K

None

Rd, X

Load Indirect

Rd ← (X)

None

Rd, X+

Load Indirect and Post-Inc.

Rd ← (X), X ← X + 1

None

Rd, - X

Load Indirect and Pre-Dec.

X ← X - 1, Rd ← (X)

None

Rd, Y

Load Indirect

Rd ← (Y)

None

Atmel ATmega8A [DATASHEET]
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384

DATA TRANSFER INSTRUCTIONS
Mnemonics

Operands

Description

Operation

Flags

#Clocks

Rd, Y+

Load Indirect and Post-Inc.

Rd ← (Y), Y ← Y + 1

None

Rd, - Y

Load Indirect and Pre-Dec.

Y ← Y - 1, Rd ← (Y)

None

LDD

Rd,Y+q

Load Indirect with Displacement

Rd ← (Y + q)

None

Rd, Z

Load Indirect

Rd ← (Z)

None

Rd, Z+

Load Indirect and Post-Inc.

Rd ← (Z), Z ← Z+1

None

Rd, -Z

Load Indirect and Pre-Dec.

Z ← Z - 1, Rd ← (Z)

None

LDD

Rd, Z+q

Load Indirect with Displacement

Rd ← (Z + q)

None

LDS

Rd, k

Load Direct from SRAM

Rd ← (k)

None

X, Rr

Store Indirect

(X) ← Rr

None

X+, Rr

Store Indirect and Post-Inc.

(X) ← Rr, X ← X + 1

None

#NAME?

Store Indirect and Pre-Dec.

X ← X - 1, (X) ← Rr

None

Y, Rr

Store Indirect

(Y) ¬ Rr

None

Y+, Rr

Store Indirect and Post-Inc.

(Y) ← Rr, Y ← Y + 1

None

#NAME?

Store Indirect and Pre-Dec.

Y ← Y - 1, (Y) ← Rr

None

STD

Y+q,Rr

Store Indirect with Displacement

(Y + q) ← Rr

None

Z, Rr

Store Indirect

(Z) ← Rr

None

Z+, Rr

Store Indirect and Post-Inc.

(Z) ← Rr, Z ← Z + 1

None

#NAME?

Store Indirect and Pre-Dec.

Z ← Z - 1, (Z) ← Rr

None

STD

Z+q,Rr

Store Indirect with Displacement

(Z + q) ← Rr

None

STS

k, Rr

Store Direct to SRAM

(k) ← Rr

None

Load Program Memory

R0 ← (Z)

None

LPM
LPM

Rd, Z

Load Program Memory

Rd ← (Z)

None

LPM

Rd, Z+

Load Program Memory and Post-Inc

Rd ← (Z), Z ← Z+1

None

Store Program Memory

(Z) ← R1:R0

None

SPM
IN

Rd, P

In Port

Rd ← P

None

OUT

P, Rr

Out Port

P ← Rr

None

PUSH

Push Register on Stack

STACK ← Rr

None

POP

Pop Register from Stack

Rd ← STACK

None

Atmel ATmega8A [DATASHEET]
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385

MCU CONTROL INSTRUCTIONS
Mnemonics

Operands

Description

Operation

Flags

#Clocks

NOP

No Operation

None

SLEEP

Sleep

(see specific descr. for Sleep function)

None

WDR

Watchdog Reset

(see specific descr. for WDR/timer)

None

BREAK

Break

For On-chip Debug Only

None

N/A

Note: 1. Instruction not available in all devices.

Atmel ATmega8A [DATASHEET]
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386

36.

Packaging Information

36.1.

32A

PIN 1 IDENTIFIER

PIN 1
e

B
E1

D1
D

0°~7°

A
COMMON DIMENSIONS
(Unit of measure = mm)

Notes:
1. This package conforms to JEDEC reference MS-026, Variation ABA.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable
protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.10mm maximum.

SYMBOL

MIN

NOM

MAX

–

1.20

0.05

–

0.15

0.95

1.00

1.05

8.75

9.00

9.25

6.90

7.00

7.10

8.75

9.00

9.25

6.90

7.00

7.10

–

0.45

–

0.20

–

0.75

0.30

0.09

0.45

NOTE

Note 2
Note 2

0.80 TYP

2010-10-20
TITLE
32A, 32-lead, 7 x 7mm body size, 1.0mm body thickness,
0.8mm lead pitch, thin profile plastic quad flat package (TQFP)

DRAWING NO.

REV.

32A

Atmel ATmega8A [DATASHEET]
Atmel-8159F-8-bit AVR Microcontroller_Datasheet_Complete-09/2015

387

36.2.

28P3

PIN
1

SEATING PLANE

B2
B1

(4 PLACES)

0º ~ 15º

REF

e
E

COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL

Note:

1. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25mm (0.010").

MIN

NOM

MAX

–

4.5724

0.508

–

34.544

–

34.798

7.620

–

8.255

7.112

–

7.493

0.381

–

0.533

1.143

–

1.397

0.762

–

1.143

3.175

–

3.429

0.203

–

0.356

–

10.160

NOTE

Note 1
Note 1

2.540 TYP

09/28/01
2325 Orchard Parkway
San Jose, CA 95131

TITLE
28P3, 28-lead (0.300"/7.62mm Wide) Plastic Dual
Inline Package (PDIP)

DRAWING NO.

REV.

28P3

Atmel ATmega8A [DATASHEET]
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388

36.3.

32M1-A
D
D1

1
2
3

Pin 1 ID
E1

SIDE VIEW

TOP VIEW
A2

A3
A1

0.08 C

P
D2

1
2
3

Pin #1 Notch
(0.20 R)

NOM

MAX

0.80

0.90

1.00

–

0.02

0.05

–

0.65

1.00

A3
E2

MIN

SYMBOL

COMMON DIMENSIONS
(Unit of Measure = mm)

BOTTOM VIEW

0.20 REF

0.18

0.23

0.30

4.90

5.00

5.10

4.70

4.75

4.80

2.95

3.10

3.25

4.90

5.00

5.10

4.70

4.75

4.80

2.95

3.10

3.25

Note : JEDEC Standard MO-220, Fig

. 2 (Anvil Singulation), VHHD-2 .

NOTE

0.50 BSC

0.30

0.40

0.50

–

0.60
o
12

0.20

–

03/14/2014

32M1-A , 32-pad, 5 x 5 x 1.0mm Bod y, Lead Pitch 0.50mm ,
3.10mm Exposed P ad, Micro Lead Frame P a ckage (MLF)

32M1-A

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37.

Errata
The revision letter in this section refers to the revision of the ATmega8A device.

37.1.

ATmega8A, rev. L
•
•
•
•
•
1.

First Analog Comparator conversion may be delayed
Interrupts may be lost when writing the timer registers in the asynchronous timer
Signature may be Erased in Serial Programming Mode
CKOPT Does not Enable Internal Capacitors on XTALn/TOSCn Pins when 32kHz Oscillator is
Used to Clock the Asynchronous Timer/Counter2
Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request
First Analog Comparator conversion may be delayed
If the device is powered by a slow rising VCC, the first Analog Comparator conversion will take
longer than expected on some devices.
Problem Fix / Workaround:

When the device has been powered or reset, disable then enable theAnalog Comparator before the
first conversion.
Interrupts may be lost when writing the timer registers in the asynchronous timer
The interrupt will be lost if a timer register that is synchronous timer clock is written when the
asynchronous Timer/Counter register (TCNTx) is 0x00.
Problem Fix / Workaround:

Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor 0x00
before writing to the asynchronous Timer Control Register (TCCRx), asynchronous Timer Counter
Register (TCNTx), or asynchronous Output Compare Register (OCRx).
Signature may be Erased in Serial Programming Mode
If the signature bytes are read before a chiperase command is completed, the signature may be
erased causing the device ID and calibration bytes to disappear. This is critical, especially, if the
part is running on internal RC oscillator.
Problem Fix / Workaround:

Ensure that the chiperase command has exceeded before applying the next command.
CKOPT Does not Enable Internal Capacitors on XTALn/TOSCn Pins when 32kHz Oscillator is
Used to Clock the Asynchronous Timer/Counter2
When the internal RC Oscillator is used as the main clock source, it is possible to run the Timer/
Counter2 asynchronously by connecting a 32kHz Oscillator between XTAL1/TOSC1 and XTAL2/
TOSC2. But when the internal RC Oscillator is selected as the main clock source, the CKOPT Fuse
does not control the internal capacitors on XTAL1/TOSC1 and XTAL2/TOSC2. As long as there are
no capacitors connected to XTAL1/TOSC1 and XTAL2/TOSC2, safe operation of the Oscillator is
not guaranteed.
Problem Fix / Workaround:
Use external capacitors in the range of 20 - 36 pF on XTAL1/TOSC1 and XTAL2/TOSC2. This will
be fixed in ATmega8A Rev. G where the CKOPT Fuse will control internal capacitors also when
internal RC Oscillator is selected as main clock source. For ATmega8A Rev. G, CKOPT = 0
(programmed) will enable the internal capacitors on XTAL1 and XTAL2. Customers who want

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compatibility between Rev. G and older revisions, must ensure that CKOPT is unprogrammed
(CKOPT = 1).
Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request.
Reading EEPROM by using the ST or STS command to set the EERE bit in the EECR register
triggers an unexpected EEPROM interrupt request.
Problem Fix / Workaround:
Always use OUT or SBI to set EERE in EECR.

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38.

Datasheet Revision History
Please note that the referring page numbers in this section are referred to this document. The referring
revision in this section refers to the document revision.

38.1.

Rev.8159F – 07/2015
1.

38.2.

Rev.8159E – 02/2013
1.
2.
3.
4.
5.

38.3.

Updated Errata.

Rev.8159B – 05/09
1.
2.
3.
4.
5.

38.6.

Updated the datasheet according to the Atmel new Brand Style Guide.
Updated Performing Page Erase by SPM by adding an extra note.
Updated Ordering Information to include Tape & Reel.

DRH_Rev.8159C – 07/09
1.

38.5.

Applied the Atmel new page layout for datasheets including new logo and last page.
Removed the reference to the debuggers and In-Circuit Emulators.
Added Capacitive touch sensing.
Added Electrical Characteristics – TA = -40°C to 105°C.
Added Typical Characteristics – TA = -40°C to 105°C.

Rev.8159D – 02/11
1.
2.
3.

38.4.

New workflow used for the publication.

Updated System and Reset Characteristics with new BODLEVEL values
Updated ADC Characteristics with new VINT values.
Updated Typical Characteristics – TA = -40°C to 85°C view.
Updated Errata. ATmega8A, rev L.
Created a new Table Of Contents.

Rev.8159A – 08/08
1.
2.

Initial revision (Based on the ATmega8/L datasheet 2486T-AVR-05/08)
Changes done compared to ATmega8/L datasheet 2486T-AVR-05/08:
– All Electrical Characteristics are moved to Electrical Characteristics – TA = -40°C to 85°C.
– Updated DC Characteristics with new VOL Max (0.9V and 0.6V) and typical value for ICC.
– Added Speed Grades.
– Added a new sub section System and Reset Characteristics.
– Updated System and Reset Characteristics with new VBOT BODLEVEL = 0 (3.6V, 4.0V and
4.2V).
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–
–
–

Register descriptions are moved to sub section at the end of each chapter.
New graphics in Typical Characteristics – TA = -40°C to 85°C.
New Ordering Information.

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Atmel Corporation

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®

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Keywords                        : Atmel 8-bit AVR MCU FLASH Microcontroller, ATmega8A, high performance, low power, up to 16MIPS at 16MHz, in-system,  self programmable, flash program memory, EEPROM, Internal SRAM, On-chip boot program, QTouch library, Timer/Counters, RTC, Oscillator, PWM, ADC, USART, SPI, AC, POR, BOD
Format                          : application/pdf
Title                           : ATmega8A Datasheet Complete
Description                     : Atmel 8-bit AVR MCU FLASH Microcontroller, ATmega8A
Creator                         : Atmel Corporation
Subject                         : Atmel 8-bit AVR MCU FLASH Microcontroller, ATmega8A, high performance, low power, up to 16MIPS at 16MHz, in-system, self programmable, flash program memory, EEPROM, Internal SRAM, On-chip boot program, QTouch library, Timer/Counters, RTC, Oscillator, PWM, ADC, USART, SPI, AC, POR, BOD
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Author                          : Atmel Corporation

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ATmega8A Datasheet Atmel 8159 8 Bit Avr Microcontroller

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