ZedBoard_HW_Users_Guide Zed Board User's Guide

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ZedBoard
(Zynq™ Evaluation and Development)
Hardware User’s Guide

Version 2.2
27 January 2014

Table of Contents
1

INTRODUCTION .................................................................................................................................. 2
1.1

ZYNQ BANK PIN ASSIGNMENTS ...................................................................................................... 4

FUNCTIONAL DESCRIPTION ............................................................................................................ 5
2.1
ALL PROGRAMMABLE SOC ............................................................................................................. 5
2.2
MEMORY ......................................................................................................................................... 5
2.2.1
DDR3 ...................................................................................................................................... 5
2.2.2
SPI Flash ................................................................................................................................ 7
2.2.3
SD Card Interface ..................................................................................................................10
2.3
USB ...............................................................................................................................................11
2.3.1
USB OTG ...............................................................................................................................11
2.3.2
USB-to-UART Bridge ............................................................................................................11
2.3.3
USB-JTAG .............................................................................................................................12
2.3.4
USB circuit protection ...........................................................................................................13
2.4
DISPLAY AND AUDIO ......................................................................................................................13
2.4.1
HDMI Output.........................................................................................................................13
2.4.2
VGA Connector......................................................................................................................16
2.4.3
I2S Audio Codec ....................................................................................................................17
2.4.4
OLED .....................................................................................................................................18
2.5
CLOCK SOURCES.............................................................................................................................18
2.6
RESET SOURCES .............................................................................................................................18
2.6.1
Power‐on Reset (PS_POR_B)................................................................................................18
2.6.2
Program Push Button Switch.................................................................................................19
2.6.3
Processor Subsystem Reset ....................................................................................................19
2.7
USER I/O ........................................................................................................................................19
2.7.1
User Push Buttons .................................................................................................................19
2.7.2
User DIP Switches .................................................................................................................19
2.7.3
User LEDs .............................................................................................................................20
2.8
10/100/1000 ETHERNET PHY ........................................................................................................20
2.9
EXPANSION HEADERS ....................................................................................................................21
2.9.1
LPC FMC Connector.............................................................................................................21
2.9.2
Digilent Pmod™ Compatible Headers (2x6).........................................................................22
2.9.3
Agile Mixed Signaling (AMS) Connector, J2 .........................................................................23
2.10 CONFIGURATION MODES ................................................................................................................26
2.10.1 JTAG ......................................................................................................................................27
2.11 POWER ...........................................................................................................................................28
2.11.1 Primary Power Input .............................................................................................................28
2.11.2 On/Off Switch ........................................................................................................................28
2.11.3 Regulators..............................................................................................................................28
2.11.4 Sequencing .............................................................................................................................29
2.11.5 Power Good LED ..................................................................................................................30
2.11.6 Power Estimation ..................................................................................................................30
2.11.7 Testing ...................................................................................................................................31
2.11.8 Probes ....................................................................................................................................31

ZYNQ-7000 AP SOC BANKS .............................................................................................................32
3.1

ZYNQ-7000 AP SOC BANK VOLTAGES ..........................................................................................33

JUMPER SETTINGS ............................................................................................................................34

MECHANICAL ....................................................................................................................................36

REVISION HISTORY ..........................................................................................................................37

27-Jan-2014

1 Introduction
TM

The ZedBoard is an evaluation and development board based on the Xilinx Zynq -7000 All
Programmable SoC (AP SoC). Combining a dual Corex-A9 Processing System (PS) with 85,000
Series-7 Programmable Logic (PL) cells, the Zynq-7000 AP SoC can be targeted for broad use in
many applications. The ZedBoard’s robust mix of on-board peripherals and expansion
capabilities make it an ideal platform for both novice and experienced designers. The features
provided by the ZedBoard consist of:
•

•
•

Xilinx® XC7Z020-1CLG484C Zynq-7000 AP SoC
o Primary configuration = QSPI Flash
o Auxiliary configuration options
 Cascaded JTAG
 SD Card
Memory
o 512 MB DDR3 (128M x 32)
o 256 Mb QSPI Flash
Interfaces
o USB-JTAG Programming using Digilent SMT1-equivalent circuit
 Accesses PL JTAG
 PS JTAG pins connected through PS Pmod
o 10/100/1G Ethernet
o USB OTG 2.0
o SD Card
o USB 2.0 FS USB-UART bridge
o Five Digilent Pmod™ compatible headers (2x6) (1 PS, 4 PL)
o One LPC FMC
o One AMS Header
o Two Reset Buttons (1 PS, 1 PL)
o Seven Push Buttons (2 PS, 5 PL)
o Eight dip/slide switches (PL)
o Nine User LEDs (1 PS, 8 PL)
o DONE LED (PL)
On-board Oscillators
o 33.333 MHz (PS)
o 100 MHz (PL)
Display/Audio
o HDMI Output
o VGA (12-bit Color)
o 128x32 OLED Display
o Audio Line-in, Line-out, headphone, microphone
Power
o On/Off Switch
o 12V @ 5A AC/DC regulator
Software
o ISE® WebPACK Design Software
o License voucher for ChipScope™ Pro locked to XC7Z020

27-Jan-2014

Flash

QSPI

PMOD

ENET/
MDIO

Pmod

USB
OTG

PHY

USBOTG

USB
UART

USB
Cont

PS_GPIO

DDR3

Reset
33Mhz

USBUART

1 LED,
2 buttons

512Mbyte
DDR3 (x32)

Clk

DDR

PS_RST
PS_CLK

Processing System (PS)

Gbit
Enet

FMC

GPIO

Programmable Logic (PL)

Multiplexed I/O (MIO)

Pmods
8

FMC-LPC

GPIO (8 LEDs,
8 slide switches,
5 pushbuttons)

HdPhn Out
8

I2S/ACD

I2S Audio
Codec

Line Out
Line In
MIC In

HDMI

VGA

OLED

DONE
PROG
GPIO/VP/VN
JTAG

GCLK

HDMI
transmitter

VGA (12bit color)

128x32 OLED

PROG

Display

DONE LED

Type A
HDMI Out

XADC
USB
Cont
Clk

Primary JTAG

100Mhz

ZYNQ XC7Z020-CLG484

Figure 1 – ZedBoard Block Diagram

27-Jan-2014

1.1

Zynq Bank Pin Assignments

The following figure shows the Zynq bank pin assignments on the ZedBoard followed by a table
that shows the detailed I/O connections.

Figure 2 - Zynq Z7020 CLG484 Bank Assignments

27-Jan-2014

2 Functional Description
2.1

All Programmable SoC

The ZedBoard features a Xilinx Zynq XC7Z020-1CLG484 All Programmable SoC (AP SoC).
Initial ZedBoards were marked ‘Rev C’ and shipped with Engineering Sample "CES" grade
silicon. Later ‘Rev D’ shipments switched to production "C" grade silicon once those became
available. The Zynq-7000 AP SoC part markings indicate the silicon grade.

2.2

Memory

Zynq contains a hardened PS memory interface unit. The memory interface unit includes a
dynamic memory controller and static memory interface modules.

2.2.1 DDR3
The ZedBoard includes two Micron DDR3 128 Megabit x 16 memory components creating a 32bit interface, totaling 512 MB.
Earlier ZedBoards used Micron MT41J128M16HA-15E:D, but
As of August 2012, this device has been marked by Micron for end-of-life. There are several
options that Micron offers for a replacement. ZedBoard will likely migrate to the
MT41K128M16JT-125 device, although this is pending validation. The DDR3 is connected to the
hard memory controller in the Processor Subsystem (PS) as outlined in the Zynq datasheet.
The multi-protocol DDR memory controller is configured for 32-bit wide accesses to a 512 MB
address space. The PS incorporates both the DDR controller and the associated PHY, including
its own set of dedicated I/Os. DDR3 memory interface speeds up to 533MHz (1066Mbs) are
supported.
The DDR3 uses 1.5V SSTL-compatible inputs. DDR3 Termination is utilized on the ZedBoard.
The Zynq-7000 AP SoC and DDR3 have been placed close together keeping traces short and
matched.
DDR3 on the PS was routed with 50 ohm targeted trace impedance for single-ended signals, and
DCI resistors (VRP/VRN) as well as differential clocks set to 80 ohms. Each DDR3 chip needs its
own 240-ohm pull-down on ZQ. The Xilinx Zynq-7000 All Programmable SoC PCB Design and
Pin Planning Guide (UG933) recommends using 40 ohm trace impedance for DDR3 single-ended
signals, so designers looking to duplicate the ZedBoard design may want consider this in their
own board design. See the appropriate ZedBoard Errata document for more details.
DDR-VDDQ is set to 1.5V to support the DDR3 devices selected. DDR-VTT is the termination
voltage which is ½ DDR-VDDQ. DDR-VREF is a separate buffered output that is equal to ½
nominal DDR-VDDQ. The DDR-VREF is isolated to provide a cleaner reference for the DDR
level transitions.

27-Jan-2014

The PCB design guidelines outlined in Zynq datasheet must be followed for trace matching, etc.

Signal Name

DDR_CK_P
DDR_CK_N
DDR_CKE
DDR_CS_B
DDR_RAS_B
DDR_CAS_B
DDR_WE_B
DDR_BA[2:0]
DDR_A[14:0]
DDR_ODT
DDR_RESET_B
DDR_DQ[31:0]
DDR_DM[3:0]
DDR_DQS_P[3:0]
DDR_DQS_N[3:0]
DDR_VRP
DDR_VRN
DDR_VREF[1:0]

Table 1 - DDR3 Connections
Description
Zynq pin

Differential clock
output
Differential clock
output
Clock enable
Chip select
RAS row address
select
RAS column address
select
Write enable
Bank address
Address
Output dynamic
termination
Reset
I/O Data
Data mask
I/O Differential data
strobe
I/O Differential data
strobe
I/O Used to calibrate
input termination
I/O Used to calibrate
input termination
I/O Reference
voltage

DDR3 pin

V3
P6

K9
L2

R4
PS_DDR_BA[2:0]
PS_DDR_A[14:0]

L3
BA[2:0]
A[14:0]

F3
PS_DDR_[31:0]
PS_DDR_DM[3:0]

T2
DDR3_DQ pins
LDM/UDM x2

PS_DDR_DQS_P[3:0]

UDQS/LDQS

PS_DDR_DQS_N[3:0]

UDQS#/LDQS#

N/A

H7, P7

For best DDR3 performance, DRAM training is enabled for write leveling, read gate, and read
data eye options in the PS Configuration Tool in Xilinx Platform Studio (XPS) or the IP Editor in
Vivado. Two entries allow for DQS to Clock Delay and Board Delay information to be specified for
each of the four byte lanes. The tools will calculate these board training details based upon
specific trace lengths for certain DDR3 signals.
The PCB lengths are contained in the ZedBoard PCB trace length reports. The DQS to CLK
Delay and Board Delay values are calculated specific to the ZedBoard memory interface PCB
design. The Xilinx tools allow for up to 4 memory devices to be configured for DDR3 4x8 flyby
topology. Note that ZedBoard is configured for DDR3 2x16 flyby routing topology. The first two
clock trace midpoint values (CLK0 and CLK1) are used to represent the Micron device electrically
furthest from the 7Z020 (IC25) and the second two clock trace midpoint values (CLK2 and CLK3)
are used to represent the Micron device electrically closest to the 7Z020 (IC26). The worksheet
calculation results are shown in the following table.

27-Jan-2014

Pin Group

Length
(mm)

Table 2 - DDR3 Worksheet Calculations
Length Package
Total
Propagation Total
(mils)
Length
Length
Delay
Delay
(mils)
(mils)
(ps/inch)
(ns)

CLK0

55.77

2195.9

470

2665.9

160

0.427

CLK1

55.77

2195.9

470

2665.9

160

0.427

CLK2

41.43

1631.1

470

2101.1

160

0.336

CLK3

41.43

1631.1

470

2101.1

160

0.336

DQS0

51.00

2008.0

504

2512.0

160

0.402

0.025

DQS1

50.77

1998.8

495

2493.8

160

0.399

0.028

DQS2

41.59

1637.6

520

2157.6

160

0.345

-0.009

DQS3

41.90

1649.4

835

2484.4

160

0.398

-0.061

DQ[7:0]

50.63

1993.3

465

2458.3

160

0.393

0.410

DQ[15:8]

50.71

1996.4

480

2476.4

160

0.396

0.411

DQ[23:16]

40.89

1609.9

550

2159.9

160

0.346

0.341

DQ[31:24]

40.58

1597.8

780

2377.8

160

0.380

0.358

DQS to
CLK
Delay
(ns)

Board
Delay
(ns)

The DQS to CLK Delay fields in the PS7 DDR Configuration window should be populated using
the corresponding values from the previous table.
The configuration fields of the tool may not allow you to input a negative delay value, this is a
known problem with the 14.1 tools and scheduled for correction in the 14.2 tools release. In the
case of DQS2 and DQS3 fields for DQS to CLK Delay, simply enter a value of zero rather than
the negative delay values. This is an acceptable workaround since the calculated values are
relatively close to zero and the values provided in these fields are used as initial values for the
read/write training for DDR3. Keep in mind for LPDDR2 there is no write leveling, and for DDR2
there is no training whatsoever. In these memory use cases, the accuracy of the trace length info
is more important. This is covered in further detail in section 10.6.8 of the Xilinx Zynq TRM,
UG585.

Figure 3 - DQS to Clock Delay Settings
The Board Delay fields in the PS7 DDR Configuration window should be populated using the
corresponding values from the table above.

Figure 4 - DDR3 Board Delay Settings
2.2.2 SPI Flash
The ZedBoard features a 4-bit SPI (quad-SPI) serial NOR flash. The Spansion S25FL256S is
used on this board. The Multi-I/O SPI Flash memory is used to provide non-volatile code, and
data storage. It can be used to initialize the PS subsystem as well as configure the PL
subsystem (bitstream). Spansion provides Spansion Flash File System (FFS) for use after
booting the Zynq-7000 AP SoC.

27-Jan-2014

The relevant device attributes are:
• 256Mbit
• x1, x2, and x4 support
• Speeds up to 104 MHz, supporting Zynq configuration rates @ 100 MHz
o In Quad-SPI mode, this translates to 400Mbs
• Powered from 3.3V
The SPI Flash connects to the Zynq-7000 AP SoC supporting up to Quad-I/O SPI interface. This
requires connection to specific pins in MIO Bank 0/500, specifically MIO[1:6,8] as outlined in the
Zynq datasheet. Quad-SPI feedback mode is used, thus qspi_sclk_fb_out/MIO[8] is connected to
a 20K pull-up resistor to 3.3V. This allows a QSPI clock frequency greater than FQSPICLK2.
Note: Zynq only supports 24-bit addressing, however the full capacity of the 256Mb Flash can be
accessed via internal bank switching. As of now the S25FL256S is not supported in iMPACT.
Note: 14.x is required for in-direct QSPI Flash Programming.

Signal Name
DQ0
DQ1
DQ2
DQ3
SCK
CS
FB Clock

Table 3 – QSPI Flash Pin Assignment and Definitions
Zynq Pin
MIO
Description
Data0
Data1
Data2
Data3
Serial Data Clock
Chip Select
QSPI Feedback

A2 (Bank MIO0/500)
F6 (MIO Bank 0/500)
E4 (MIO Bank 0/500)
A3 (MIO Bank 0/500)
A4 (MIO Bank 0/500)
A1 (MIO Bank 0/500)
E5 (MIO Bank 0/500)

1:6

QSPI Pin
5
2
3
7
6
1
N/C

Note: The QSPI data and clock pins are shared with the Boot Mode jumpers.

27-Jan-2014

Two packages can be used on the ZedBoard; SO-16 and WSON. For the WSON package,
there is a heat sink slug under the package that is not connected to any signal on the PCB.

Figure 5 - Overlying Packages for SPI Flash

27-Jan-2014

2.2.3

SD Card Interface

The Zynq PS SD/SDIO peripheral controls communication with the ZedBoard SD Card (A 4GB
Class 4 card is included in the ZedBoard kit.) The SD card can be used for non-volatile external
memory storage as well as booting the Zynq-7000 AP SoC. PS peripheral sd0 is connected
through Bank 1/501 MIO[40-47], including, Card Detect and Write Protect.
The SD Card is a 3.3V interface but is connected through MIO Bank 1/501 (1.8V). Therefore, a
TI TXS02612 level shifter performs this translation. The TXS02612 is a 2-port SDIO port
expander with level translation. ZedBoard only makes use of one of these parts. TI offered an
alternative TXS0206 device, but the 0.4mm pitch of that device’s packaging was too fine for our
manufacturer.
Based on the Zynq TRM, host mode is the only mode supported.
The ZedBoard SD Card is connected through a 9-pin standard SD card connector, J12, TE
2041021-1. A Class 4 card or better is recommended.
Note: To use the SD Card, JP6 must be shorted.

Figure 6 - SD Card Interface

Signal
Name
CLK
CMD

Data[3:0]

CD
WP

Table 4 – SD Card Pin Assignment and Definitions
MIO
Level Shift
Description
Zynq Pin
Pin
E14 (MIO Bank
Clock
40
Pass-Thru
1/501)
Command
C8 ((MIO Bank 1/501)
41
Pass-Thru
MIO Bank 1/501
D0: D8
Data
42:45
Pass-Thru
D1: B11
D2: E13
D3: B9
B10 (MIO Bank
Card Detect
47
Pass-Thru
1/501)
D12 ((MIO Bank
Write Protect
46
Pass-Thru
1/501)

SD Card
Pin
5
2
Data Pins
7
8
9
1
CD
WP

27-Jan-2014

2.3

USB

2.3.1

USB OTG

Warning: After the design of the ZedBoard was complete, a timing incompatibility
between the TUSB1210 PHY and Zynq was discovered. The TUSB1210 is not
recommended for new designs with Xilinx Zynq. Please refer to the ZedBoard Errata for
more details.
ZedBoard implements one of the two available PS USB OTG interfaces. An external PHY with
an 8-bit ULPI interface is required. A TI TUSB1210 Standalone USB Transceiver Chip is used as
the PHY. The PHY features a complete HS-USB Physical Front-End supporting speeds of up to
480Mbs. This part is available in a 32-pin QFN package. VCCio for this device is 1.8V and
cannot be connected through level shifters. The PHY is connected to MIO Bank 1/501, which is
powered at 1.8V. Additionally the USB chip must clock the ULPI interface which requires an
oscillator. A Fox XPRESSO oscillator (767-26-31) is used on ZedBoard.
The external USB interface connects through a TE 1981584-1.
The usb0 peripheral is used on the PS, connected through MIO[28-39] in MIO Bank 1/501.
This USB port will not power the board. However, ZedBoard provides 5V when in Host or OTG
modes. REFCLK pin of TUSB1210 is tied to ground as the Zynq-7000 AP SoC will drive the
CLOCK input of this part.
Table 5 - USB OTG Pin Assignment and Definitions
TUSB1210
Pin
Data[7:0]
26
31
29
2
11
18
19

USB
Conn Pin
N/C
N/C
N/C
N/C
N/C
N/C
2
3

N/C

MIO Bank 1/501
Bank 34

27
L16

N/C
TPS2051

Signal Name

Description

Zynq Pin

OTG_Data[8:0]
OTG_CLOCK
OTG_DIR
OTG_STP
OTG_NXT
OTG_CS
DP
DM

USB Data lines
USB Clock
ULPI DIR output signal
ULPI STP input signal
ULPI NXT output signal
USB Chip Select
DP pin of USB Connector
DM pin of USB Connector
Identification pin of the
USB connector
Reset
VBus Output Control

MIO Bank 1/501
MIO Bank 1/501
MIO Bank 1/501
MIO Bank 1/501
MIO Bank 1/501

ID
OTG_RESET_B
OTG_VBUS_OC

N/C
N/C

MIO

28:39

See the Jumper Settings section for configuring the USB interface for Host, Device and OTG
mode. The jumpers control the Vbus supply as well.
2.3.2 USB-to-UART Bridge
The ZedBoard implements a USB-to-UART bridge connected to a PS UART peripheral. A
Cypress CY7C64225 USB-to-UART Bridge device allows connection to a host computer. The
USB/UART device connects to the USB Micro B connector, J14, (TE 1981584-1) on the board.
Only basic TXD/RXD connection is implemented. If flow control is required this can be added
through Extended MIO on a PL-Pmod™.
Cypress provides royalty-free Virtual COM Port (VCP) drivers which permit the CY7C64225 USBto-UART bridge to appear as a COM port to host computer communications application software
(for example, HyperTerm or Tera Term). Please refer to the CY7C64225 Setup Guide posted on
zedboard.org for detailed instructions for installing the driver.

27-Jan-2014

The UART 1 Zynq PS peripheral is accessed through MIO[48:49] in MIO Bank 1/501 (1.8V).
Since the CY7C64225 device requires either 3.3V or 5V signaling, a TI TXS0102 level shifter is
used to level shift between 3.3V and 1.8V.
This USB port will not power the board. Therefore, Vbus needs to be connected to 3.3V though a
1KΩ series resistor. The Wake pin, pin 22, connects to GND. A 24Ω series resistor was placed
on each of the data lines, D+ and D-.
Table 6 – CY7C6 Connections
UART
Function in
Zynq
TX, data out
RX, data in

Zynq Pin

MIO

D11 (MIO Bank
1/501)
C14 (MIO Bank
1/501)

48:49

Schematic Net
Name

CY7C6 Pin

UART Function
in CY7C64225

USB_1_RXD

RXD, data in

USB_1_TXD

TXD, data out

Figure 7 – USB-UART Bridge Interface

2.3.3 USB-JTAG
The ZedBoard provides JTAG functionality based on the Digilent USB High Speed JTAG Module,
SMT1 device. This USB-JTAG circuitry is fully supported and integrated into Xilinx ISE tools,
including iMPACT, ChipScope, and SDK Debugger. Designers who want to re-use this circuit on
their board can do so by acquiring these modules from Avnet.
http://www.em.avnet.com/en-us/design/drc/Pages/Digilent-JTAG-SMT1-Surface-MountProgramming-Module.aspx
The JTAG is available through a Micro B USB connector, J17, TE 1981568-1. TCK has a series
termination resistor, 20-30Ω, to prevent signal integrity issues.
For the JTAG Chain setup, please refer to the Configuration section.

27-Jan-2014

2.3.4

USB circuit protection

All USB data lines, D+/-, are protected with a TE SESD0402Q2UG-0020-090.

USB
Con
n

D+
D-

Level
Shifter

Figure 8 – ESD Protection

2.4
2.4.1

Display and Audio
HDMI Output

An Analog Devices ADV7511 HDMI Transmitter provides a digital video interface to the
ZedBoard. This 225MHz transmitter is HDMI 1.4- and DVI 1.0-compatible supporting 1080p60
with 16-bit, YCbCr, 4:2:2 mode color.
The ADV7511 supports both S/PDIF and 8-channel I2S audio. The S/PDIF can carry compressed
audio including Dolby® Digital, DTS®, and THX®. There is an independent DPDIF input and
output. The I2S interface is not connected on ZedBoard. Analog Devices offers Linux drivers
and reference designs illustrating how to interface to this device.
The HMDI Transmitter has 25 connections to Bank 35 (3.3V) of the Zynq-7000 AP SoC:

27-Jan-2014

Signal Name
HDP
HD-INT
HD-SCL
HD-SDA
HD-CLK

HD-VSYNC
HD-HSYNC

HD-DE

HD_D[15:0]

HD-SPDIF
HD-SPDIFO

Table 7 - HDMI Interface Connections
Description
Zynq pin
Hot Plug Detect signal input
N/C
Interrupt signal output
W16
I2C Interface. Supports CMOS
AA18
logic levels from 1.8V to 3.3V
Y16
Video Clock Input. Supports
typical CMOS logic levels from
1.8V up to 3.3V
Vertical Sync Input (Not required
if using embedded syncs)
Horizontal Sync Input (Not
required if using embedded
syncs)
Data Enable signal input for
Digital Video (Not required if
using embedded syncs)
Video Data Input

Sony/Philips Digital Interface
Audio Input
Sony/Philips Digital Interface
Audio Output

ADV7511 pin
30
45
55

W18

56
79

W17

V17

U16

Bank 35
D0: Y13
D1: AA12
D2: AA14
D3: Y14
D4: AB15
D5: AB16
D6: AA16
D7: AB17
D8: AA17
D9: Y15
D10: W13
D11: W15
D12: V15
D13: U17
D14: V14
D15: V13
U15

88
87
86
85
84
83
82
81
80
78
74
73
72
71
70
69
10

Y18

27-Jan-2014

Figure 9 - HDMI Video Interface Timing
The HDMI transmitter connects externally via a HDMI Type A connector, J9, TE 1903015-1.
Circuit protection for the HDMI interface is provided by a Tyco Electronics SESD0802Q4UG.

27-Jan-2014

2.4.2 VGA Connector
The ZedBoard also allows 12-bit color video output through a through-hole VGA connector, TE 41734682-2. Each color is created from resistor-ladder from four PL pins.

Figure 10 - DB15

VGA Pin

Signal

Table 8 - VGA Connections
Description

Zynq Pin
V20, U20, V19, V18

RED

Red video

GREEN

Green video

BLUE

Blue video

ID2/RES

formerly Monitor ID bit 2

GND

Ground (HSync)

RED_RTN

Red return

GREEN_RTN

Green return

BLUE_RTN

Blue return

KEY/PWR

formerly key

GND

Ground (VSync)

ID0/RES

formerly Monitor ID bit 0

ID1/SDA

formerly Monitor ID bit 1

HSync

Horizontal sync

VSync

Vertical sync

Y19

ID3/SCL

formerly Monitor ID bit 3

AB22, AA22, AB21, AA21
Y21, Y20, AB20, AB19

AA19

27-Jan-2014

2.4.3

I2S Audio Codec

An Analog Devices ADAU1761 Audio Codec provides integrated digital audio processing to the
Zynq-7000 AP SoC. It allows for stereo 48KHz record and playback. Sample rates from 8KHz to
96KHz are supported. Additionally, the ADAU1761 provides digital volume control. The Codec
can be configured using Analog Devices SigmaStudio™ for optimizing audio for specific
acoustics, numerous filters, algorithms and enhancements. Analog Devices provides Linux
drivers for this device.
http://www.analog.com/en/content/cu_over_sigmastudio_graphical_dev_tool_overview/fca.html
The Codec interface to the Zynq-7000 AP SoC consists of the following connections:

Signal Name
AC-ADR0
AC-ADR1
AC-MCLK
AC-GPIO2
AC-GPIO3
AC-GPIO0
AC-GPIO1
AC-SDA
AC-SCK

Table 9 - CODEC Connections
Description
Zynq pin
I2C Address Bit 0/SPI Latch
AB1
Signal
I2C Address Bit 1/SPI Data
Y5
Input
Master Clock Input
AB2
Digital Audio Bit Clock
AA6
Input/Output
Digital Audio Left-Right Clock
Y6
Input/Output
Digital Audio Serial-Data DAC
Y8
Input
Digital Audio Serial Data ADC
AA7
Output
I2C Serial Data interface
AB5
I2C Serial Data interface
AB4

ADAU1761 pin
3
30
2
28
29
27
26
31
32

The Codec connects to the following connectors:
Table 10 - External Codec Connections
3.5mm Audio (Mic In) Pink

1734152-5

3.5mm Audio (Line In) Light Blue

1734152-6

3.5mm Audio (Line Out) Lime

1734152-4

3.5mm Audio (Headphone) Black

1734152-7

27-Jan-2014

2.4.4

OLED

An Inteltronic/Wisechip UG-2832HSWEG04 OLED Display is used on the ZedBoard. This
provides a 128x32 pixel, passive-matrix, monochrome display. The display size is 30mm x
11.5mm x 1.45mm.

Pin Number
Power Supply

Symbol

Table 11 - OLED Connections
Zynq Pin

Function

VDD

U12

Power Supply for Logic

VSS

N/C

Ground of OEL System

VCC

N/C

Power Supply for OEL Panel

IREF

N/C

Current Reference for Brightness Adjustment

VCOMH

N/C

Voltage Output High Level for COM Signal

VBAT

U11

Power Supply for DC/DC Converter Circuit

3/4
1/2

C1P / C1N
C2P / C2N

N/C

Positive Terminal of the Flying Inverting Capacitor
Negative Terminal of the Flying Boost Capacitor

RES#

Power Reset for Controller and Driver

CS#

N/C

Chip Select – Pulled Down on Board

D/C#

U10

Data/Command Control

SCLK

AB12

Serial Clock Input Signal

SDIN

AA12

Serial Data Input Signal

2.5

Clock sources

Driver

DC/DC Converter

Interface

The Zynq-7000 AP SoC’s PS subsystem uses a dedicated 33.3333 MHz clock source, IC18, Fox
767-33.333333-12, with series termination. The PS infrastructure can generate up to four PLLbased clocks for the PL system. An on-board 100 MHz oscillator, IC17, Fox 767-100-136,
supplies the PL subsystem clock input on bank 13, pin Y9.

2.6

Reset Sources

2.6.1 Power‐on Reset (PS_POR_B)
The Zynq PS supports external power-on reset signals. The power-on reset is the master reset of
the entire chip. This signal resets every register in the device capable of being reset. ZedBoard
drives this signal from a comparator that holds the system in reset until all power supplies are
valid. Several other IC’s on ZedBoard are reset by this signal as well.

27-Jan-2014

2.6.2 Program Push Button Switch
A PROG push switch, BTN6, toggles Zynq PROG_B. This initiates reconfiguring the PLsubsection by the processor.
2.6.3 Processor Subsystem Reset
Power-on reset, labeled PS_RST/BTN7, erases all debug configurations. The external system
reset allows the user to reset all of the functional logic within the device without disturbing the
debug environment. For example, the previous break points set by the user remain valid after
system reset. Due to security concerns, system reset erases all memory content within the PS,
including the OCM. The PL is also reset in system reset. System reset does not re-sample the
boot mode strapping pins.

2.7

User I/O

2.7.1 User Push Buttons
The ZedBoard provides 7 user GPIO push buttons to the Zynq-7000 AP SoC; five on the PL-side
and two on the PS-side.
Pull-downs provide a known default state, pushing each button connects to Vcco.
Table 12 - Push Button Connections
Signal Name
Subsection
Zynq pin
BTNU
PL
T18
BTNR
PL
R18
BTND
PL
R16
BTNC
PL
P16
BTNL
PL
N15
PB1
PS
D13 (MIO 50)
PB2
PS
C10 (MIO 51)

2.7.2 User DIP Switches
The ZedBoard has eight user dip switches, SW0-SW7, providing user input. SPDT switches
connect the I/O through a 10kΩ resistor to the VADJ voltage supply or GND.
Table 13 - DIP Switch Connections
Signal Name
Zynq pin
SW0
F22
SW1
G22
SW2
H22
SW3
F21
SW4
H19
SW5
H18
SW6
H17
SW7
M15

27-Jan-2014

2.7.3 User LEDs
The ZedBoard has eight user LEDs, LD0 – LD7. A logic high from the Zynq-7000 AP SoC I/O
causes the LED to turn on. LED’s are sourced from 3.3V banks through 390Ω resistors.
Table 14 - LED Connections
Signal Name
Subsection
Zynq pin
LD0
PL
T22
LD1
PL
T21
LD2
PL
U22
LD3
PL
U21
LD4
PL
V22
LD5
PL
W22
LD6
PL
U19
LD7
PL
U14
LD9
PS
D5 (MIO7)

2.8

10/100/1000 Ethernet PHY

The ZedBoard implements a 10/100/1000 Ethernet port for network connection using a Marvell
88E1518 PHY. This part operates at 1.8V. The PHY connects to MIO Bank 1/501 (1.8V) and
interfaces to the Zynq-7000 AP SoC via RGMII. The RJ-45 connector is a TE Connectivity
1840750-7 featuring integrated magnetics. The RJ-45 has two status indicator LEDs that indicate
traffic and valid link state.
A high-level block diagram of one 10/100/1000 Ethernet interface is shown in the following figure.
Marvell 88E1518 PHY

TD_P

control_tx

TD_N

gtxclk

RD_P
RD_N

Receive

XC7Z020

RJ45
Connector

clk_tx
10/100/1000
Magnetics

Transmit

data_tx[3:0]

data_rx[3:0]
clk_rx
control_rx
Crystal
125Mhz

phy_reset

LEDs

Figure 11 - 10/100/1000 Ethernet Interface
Zynq requires a voltage reference for RGMII interfaces. Thus PS_MIO_VREF, F8, is tied to 0.9V,
half the bank voltage of MIO Bank 1/501.

27-Jan-2014

Signal Name
RX_CLK
RX_CTRL
RXD[3:0]
TX_CLK
TX_CTRL
TXD[3:0]
MDIO
MDC

Table 15 – Ethernet PHY Pin Assignment and Definitions
Description
Zynq pin
MIO
Receive Clock
A14
Receive Control
D7
Receive Data
RXD0: E11
RXD1: B7
RXD2: F12
RXD3: A13
16:27
Transmit Clock
D6
Transmit Control
F11
Transmit Data
TXD0: E9
TXD1: A7
TXD2: E10
TXD3: A8
Management Data
C12
52:53
Management Clock
D10

88E1510 pin
40
37
38
39
41
42
47
2
44
45
48
1
5
4

The datasheet for the Marvell 88E1518 is not available publicly. An NDA is required for this
information. Please contact your local Avnet or Marvell representative for assistance.

2.9

Expansion Headers

2.9.1

LPC FMC Connector

A single low-pin count (LPC) FMC slot is provided on the ZedBoard to support a large ecosystem
of plug-in modules. The LPC FMC exposes 68 single-ended I/O, which can be configured as 34
differential pairs. The FMC interface spans over two PL I/O banks, banks 34 and 35. To meet
the FMC spec, these banks are powered from an adjustable voltage set by jumper, J18.
Selectable voltages include 1.8V, default, and 2.5V. It is also possible to set Vadj to 3.3V. Since
3.3V could potentially be the most damaging voltage setting for Vadj, this is not available with the
default board hardware. To set Vadj to 3.3V, solder a short across the 3V3 pads at J18 or solder
in an additional 1x2 header. The FMC pin out can be copied from the Master UCF, see
ZedBoard.org.
WARNING: Before attaching a FMC Card, ensure the correct voltage is selected on jumper, J18.
Failure to do so may result in damage to the FMC card and/or the ZedBoard.
Note, the following LPC FMC connections guidelines were followed:
 CLK_#_M2C
– 50 ohm single-ended impedance
– Less than 10mil skew in P/N pair
– Connected to GC (Global Clock) preferential or MRCC (Multi-Region) if not
available
– No length matching to any other feature
 LA bus
– 50 ohm single-ended impedance
– Less than 10mil skew in P/N pair
– Less than 100mil length skew across all bits in a bus
• No restriction between LA, HA or HB
– LA Bus 0:16 to be located in one bank
– LA Bus 17:33 to be located in one bank
– CC Pairs 0, 17 to be placed on MRCC pins
– CC Pairs 1, 18 to be placed on SRCC pins
• HB_06_CC optional placed on clock pin if available
 To conserve Zynq pins, GA[1:0] were removed and connected to GND.

27-Jan-2014

2.9.2 Digilent Pmod™ Compatible Headers (2x6)
The ZedBoard has five Digilent Pmod™ compatible headers (2x6). These are right-angle, 0.1”
female headers that include eight user I/O plus 3.3V and ground signals as show in the figure
below.
Four Pmod connectors interface to the PL-side of the Zynq-7000 AP SoC. These will connect to
Bank 13 (3.3V). One Pmod, JE1, connects to the PS-side on MIO pins [0,9-15] in MIO Bank
0/500 (3.3V). Uses for this Pmod include PJTAG access (MIO[10-13]) as well as nine other
hardened MIO peripherals (SPI, GPIO, CAN, I2C, UART, SD, QSPI, Trace, Watchdog).
The four PL Pmod connectors are placed in adjacent pairs on the board edge such that the
clearance between Pin 6 of header #1 and Pin 1 of header #2 is 10mm.
Two of the Pmods, JC1 and JD1, are aligned in a dual configuration and have their I/O routed
differentially to support LVDS running at 525Mbs.
All Pmod data lines, 8 per connector, are protected with two 4-channel TE SESD1004Q4UG0020-090.
FPGA I/O

FPGA I/O

4
5

3.3V

FPGA I/O

10
11
12

3.3V

Figure 12 - Pmod Connections

A couple links to Pmod examples are provided:
• http://www.em.avnet.com/en-us/design/drc/Pages/Digilent-PmodWiFi-802-11bgnWiFi-Interface.aspx
• http://www.em.avnet.com/en-us/design/drc/Pages/Digilent-Pmod-RS232-SerialConverter-and-Interface.aspx

27-Jan-2014

Pmod

JA1

Pmod

JC1
Differential

Signal
Name
JA1
JA2
JA3
JA4
JA7
JA8
JA9
JA10
Signal Name
JC1_N
JC1_P
JC2_N
JC2_P
JC3_N
JC3_P
JC4_N
JC4_P
Pmod

JE1
MIO Pmod

Table 16 - Pmod Connections
Pmod
Zynq pin
Signal Name
Y11
AA11
Y10
AA9
AB11
AB10
AB9
AA8
Zynq pin
AB6
AB7
AA4
Y4
T6
R6
U4
T4
Signal Name
JE1
JE2
JE3
JE4
JE7
JE8
JE9
JE10

JB1

Pmod

JD1
Differential

Zynq pin
A6
G7
B4
C5
G6
C4
B6
E6

Zynq pin

JB1
JB2
JB3
JB4
JB7
JB8
JB9
JB10

W12
W11
V10
W8
V12
W10
V9
V8

Signal Name
JD1_N
JD1_P
JD2_N
JD2_P
JD3_N
JD3_P
JD4_N
JD4_P

Zynq pin
W7
V7
V4
V5
W5
W6
U5
U6

MIO
MIO13
MIO10
MIO11
MIO12
MIO0
MIO9
MIO14
MIO15

2.9.3 Agile Mixed Signaling (AMS) Connector, J2
The XADC header provides analog connectivity for analog reference designs, including AMS
daughter cards like Xilinx’s AMS Evaluation Card.
The analog header is placed close to the LPC FMC header as shown. Both analog and digital IO
can be easily supported for a plug in card. This allows the analog header to be easily connected
to the FMC card using a short ribbon cable as shown. The analog header can also be used
“stand alone” to support the connection of external analog signals.
The pin out has been chosen to provide tightly coupled differential analog pairs on the ribbon
cable and to also provide AGND isolation between channels. The plug in cards which will
facilitate a number of reference designs have not yet been designed so this pin out must provide
a reasonable degree of freedom while also keeping resource requirements as minimal as
possible.

27-Jan-2014

The ZedBoard AMS header is comparable with similar connectors on the Xilinx KC705 and
ZC702 boards. Any AMS plug-in cards built for those boards should be compatible with
ZedBoard as well.

Figure 13 - Analog Header Pin out

The following anti-aliasing filters were used for the XADC inputs:
- VP/VN
- VAUX0P/VAUX0N
- VAUX8P/VAUX8N

Figure 14 - Anti-Aliasing Filters for XADC Inputs

27-Jan-2014

Table 17 - Analog Header Pin Out
Name

VP/VN

VAUX0P/VAUX0N

Description

Requirement

XADC
Header

Zynq Pin

Two pins required. Dedicated
pins on the 7 series package.

1V peak-topeak input

XADC-VN-R : M12

This is the dedicated analog
input channel for the ADC(s).

maximum

XADC-VP-R : L11

Two pins required. Auxiliary
analog input channel 0. Two
dedicated channels needed for
simultaneous sampling
applications. Should also

1V peak-topeak input
maximum
6
3

XADC-AD0N-R : E16
XADC-AD0P-R : F16

simultaneous sampling
applications. Should also
support use as IO inputs by
disconnection of anti-alias cap
see

7
8

XADC-AD8N-R : D17
XADC-AD8P-R : D16

Two pins required. Access to

XADC-DXN : N12

thermal Diode

XADC-DXP : N11

Three pins required. Analog
ground reference GNDADC.
Analog channel isolation

4
5
10

support use as IO inputs by
disconnection of anti-alias cap
see
Two pins required. Auxiliary
analog input channel 8. Two
dedicated channels needed for
VAUX8P/VAUX8N

DXP/DXN

AGND

VCCADC

VREF

AV_5V

1V peak-topeak input
maximum

One pin. This is the analog 1.8V
supply for XADC.

1.8V ±5%
@150mA max

One pin. This is the 1.25V
reference from the board.

1.25V ±0.2%
50ppm/ºC
@5mA max

Filtered 5V supply from board.

5V ±5%
@150mA max

GPIO

General Purpose I/O

Vadj

Adjustable Voltage, set by J18

Voltage set by
Vadj

G0: 18
G1: 17
G2: 20
G3: 19

H15
R15
K15
J15

1.8V, 2.5V,
3.3V

27-Jan-2014

2.10 Configuration Modes
Zynq-7000 AP SoC devices use a multi-stage boot process that supports both non-secure and
secure boot (note that secure boot is not supported for CES silicon.) The PS is the master of the
boot and configuration process. The following table shows the Zynq configuration modes. Upon
reset, the device mode pins are read to determine the primary boot device to be used: NOR,
NAND, Quad-SPI, SD Card or JTAG.
By default, the ZedBoard uses the SD Card configuration mode. The boot mode pins are
MIO[8:2] and are used as follows:
• MIO[2]/Boot_Mode[3] sets the JTAG mode
• MIO[5:3]/Boot_Mode[2:0] select the boot mode
• MIO[6]/Boot_Mode[4] enables the internal PLL
• MIO[8:7]/Vmode[1:0] are used to configure the I/O bank voltages, however these are
fixed on ZedBoard and not configurable
The ZedBoard provides jumpers for MIO[6:2]. These are 1x3 jumpers connected as shown
below. All mode pins can be pulled high or low through a 20 KΩ resistor.

Figure 15 - Configuration Mode Jumpers
These jumpers allow users to change the mode options, including using cascaded JTAG
configuration as well as using the internal PLL.
As noted above, the VMODE pins are strapped permanently to set Bank 500 and 501 voltages to
3.3V and 1.8V. These are not jumper selectable.

27-Jan-2014

The PS boot mode selections are shown in the table below, default setting highlighted in yellow:
Table 18 – ZedBoard Configuration Modes
Xilinx TRM

MIO[6]

MIO[5]

MIO[4]

MIO[3]

MIO[2]

Boot_Mode[4]

Boot_Mode[0]

Boot_Mode[2]

Boot_Mode[1]

Boot_Mode[3]

JTAG Mode
Cascaded
JTAG
Independent
JTAG

0
1
Boot Devices
0
0
1
0
1
1
PLL Mode

JTAG
Quad-SPI
SD Card
PLL Used
PLL
Bypassed

0
0
0

0
1
Bank Voltages
MIO Bank 500
MIO Bank 501

3.3V
1.8V

Expected configuration time using a 50MB/s QSPI flash is 250ms.
PUDC_B is pulled high on ZedBoard but can be pulled low via JP5. This active-low input enables
internal pull-ups during configuration on all SelectIO pins
A push button labeled “PROG” is connected to the Zynq PROG pin, T11, and pulled up. Pushing
the button connects PROG to ground. Pushing this button will clear the PL configuration
memory, effectively resetting the entire PL subsection. The PS is responsible for reconfiguring
the PL. Zynq will not automatically reconfigure the PL as in standard FPGAs. The user software
application must reprogram the PL. An interrupt will indicate a change in the devcfg.INT_STS
register and the configuration pin status can be read from the devcfg.STATUS register. When
configuration is complete, a blue LED, LD12, labeled DONE, will light.

2.10.1 JTAG
As an alternative to using the onboard USB-JTAG interface, the ZedBoard provides traditional
Platform Cable JTAG connector, J15, for use with Xilinx Platform Cables and Digilent JTAG HS1
Programming Cables. The JTAG Chain is constructed as follows:

Figure 16 - ZedBoard JTAG Chain

27-Jan-2014

ZedBoard automatically adds the FMC into the JTAG chain when an FMC card is plugged into
the board via the FMC-PRSNT signal.

2.11 Power
2.11.1 Primary Power Input
The board’s primary input is through a 12V barrel jack. A compatible AC/DC converter will have a
2.5mm inner diameter, 5.5mm outer diameter, center positive connection.
The total power budget is based on 4A from an AC/DC wall wart supply. This rail is protected
with a TE 0603SFF600F/24-2.
A 10mΩ, 1W current sense resistor exists in series with the 12V input power supply. Header J21
straddles this resistor to measure the voltage across this resistor for calculating ZedBoard power.
Power is the measured voltage squared divided by the 10mΩ resistance.
2.11.2 On/Off Switch
ZedBoard includes an On/Off switch, SW8, to gate 12V. . When SW8 is in the OFF position, 12V
is disconnected from the board.
2.11.3 Regulators
The following Maxim power solution provides the power rails of the ZedBoard.

Figure 17 - Maxim Power Solution

27-Jan-2014

The table below shows the minimum required voltage rails, currents, and tolerances.
Table 19 - TPS65708 Connections
Voltage (V)

Current (A)

Tolerance

1.0 (Vccint)

1.3

5.00%

1.5 (Vccoddr)

1.5

5.00%

1.8 (Vccaux)

0.8

5.00%

1.8, 2.5, 3.3
(jumper adjustable, 2.5V
default) (Vadj)

5.00%

3.3 (Vcco/FMC/Pmod)

5.00%

1.8 (analog) (Vccadc)

0.15

5.00%

1.25 reference (Vrefp)

0.005

0.2%, 50ppm/ºC

0.75 (DDR3 Vtt)

1.5

5.00%

5.0 (Filtered for XADC)

0.15

5.00%

2.11.4 Sequencing
Sequencing for the power supplies follows the recommendations for the Zynq device. PS and PL
INT and AUX supplies are tied together on the ZedBoard platform to create a low cost design.
The following diagram illustrates the supply sequencing:
5V
1V Vccint
1.8V XADC
1.8V Vccaux
3.3V Vcco
Vadj (1.8/2.5/3.3)
1.5V Vccoddr
0.75V Vtt
1.25V Vref

Figure 18 - Power Sequencing
In addition to the sequencing, a power on reset circuit is used to hold the board in reset until all
power supplies have reached their regulation point.

27-Jan-2014

2.11.5 Power Good LED
A green status LED, LD13, indicates when power is good on the board. Power Good is wired
with the Resets and PROG to prevent operation of the board when power is not good.
2.11.6 Power Estimation
The Power estimation chart is shown below.
Table 20 – Current Usage Estimations, in mA
Feature

Part Number

MFG

Zynq-7000 AP SoC PS
Zynq-7000 AP SoC PL

Z7020-CLG484
Z7020-CLG484
MT41K128M16HA15E:D

Xilinx
Xilinx

DDR3
DDR3 Termination
QSPI Flash
QSPI Flash
10/100/1000 PHY
10/100/1000 PHY
USB 2.0 OTG PHY
HDMI Transmitter
Audio Codec
OLED
Clock
USB JTAG
UART to USB
SD Card
PS User LED (green)
PL User LEDs (green)
x8
PS User PB x2
PL User PBs x5
PL User Slide Switches
x8
Status LEDs (amber)
x4?
DONE LED (blue)
PS Pmod
PL Pmod #1
PL Pmod #2
PL Pmod #3
PL Pmod #4
FMC-LPC

Bank

Micron

1.0V

1.5V

1.8V

600
1200

250

150
300

VCCO_DDR

Vadj

3.3V
150
50

425
360

S25FL256S Vcc
S25FL256S Vio
88E1518 internal
88E1518 Vddo
TUSB1210
ADV7511
ADAU1761
UG-2832HSWEG04
F4100
SMT1
CY7C64225

Spansion
Spansion
Marvell
Marvell
TI
ADI
ADI
Univision
Fox
Digilent
Cypress

100
2
50

VCCO_MIO0
72

63
27
30
181

VCCO_MIO1
VCCO_MIO1

30
0
58
28
40
110
26
100
5

VCCO_MIO1
VCCO_MIO1
VCCO_MIO0

40
VCCO_MIO0

0
0
0
20
5

TE 5-534206-6
TE 5-534206-6
TE 5-534206-6
TE 5-534206-6
TE 5-534206-6

TE
TE
TE
TE
TE

VCCO_MIO0
3000
2000

Total

1872

1035

751

2000

3814

1.0

1.5

1.8

2.5

3.3

27-Jan-2014

2.11.7 Testing
The power circuitry has been tested to verify compliance with the Zynq power requirements, such
as:
• Tolerance
o 1.0V Vccint  0.95 to 1.05V
o Vccaux  +/- 5%
o Vcco  +/-5%
• Ramp time
o 0.20 to 50ms
o In-rush current must be controlled so the power circuitry is not overloaded at
start-up
• Monotonicity
o No negative dips in Vccint or Vccaux power-up ramps
• Sequencing
o Verify sequencing responds as expected based on design
• Refer to Zynq Datasheet for the latest requirements
2.11.8 Probes
Two ground test point are available on the board, J3 and J4. This allows easy access to attach
ground leads of two scope probes to the board without having to locate GND pins on a header.

27-Jan-2014

Zynq-7000 AP SoC Banks

The following figure and table show Zynq CLG484 I/O bank assignments on the Zynq board.

Figure 19 - Zynq I/O Banks

27-Jan-2014

3.1

Zynq-7000 AP SoC Bank Voltages
Table 21 - Zynq Bank Voltage Assignments

PS-Side
Bank

Voltage (default)

MIO Bank 0/500

3.3V

MIO Bank 1/501

1.8V

DDR

1.5V

PL-Side
Bank0

3.3V

Bank 13

3.3V

Bank 33

3.3V

Bank 34

Vadj (2.5V)

Bank 35

Vadj (2.5V)

Note: Banks 34 and 35 are powered from an adjustable voltage rail. Jumper, J18, selects this
voltage. Selectable voltages include 1.8V, 2.5V and 3.3V. The 3.3V jumper was intentionally
unpopulated on ZedBoard as these banks primarily connect to the FMC interface and many FMC
cards are only 1.8V and 2.5V compatible. Connecting 3.3V to these cards can damage them, so
leaving this jumper unpopulated reduces the risk of damaging FMC cards.

27-Jan-2014

4 Jumper Settings
Table 22 - Jumper Settings
Ref Designator

Description

Default Setting

JP1

Microphone Input Bias

Open – No Electret
Microphone

JP2

Vbus 5V Enable

Open – 5V
Disconnected

JP3

USB Vbus Capacitor
Setting

Open – Device
Mode

JP4

CFGBVS Select

Not Populated

JP5

PUDC Select

Not Populated

JP6

PS_MIO0 Pull-Down

Short

Boot_Mode[3]/MIO[2]

GND – Cascaded
JTAG

JP7

JP8
JP9
JP10

Boot_Mode[0]/MIO[3]
Boot_Mode[1]/MIO[4]
Boot_Mode[2]/MIO[5]

110 – SD Card

JP11

Boot_Mode[4]/MIO[6]

GND – PLL Used

JP12

XADC Ferrite Bead
Disable

Open

JP13

JTAG PS-RST

Open

Vadj Select

1.8V

J18

Function
Short to enable Bias
Voltage for Electret
Microphone. Right
Channel only.
Short to enable 5V
output to USB OTG
Connector, J13, for
either Host or OTG
modes.
Short for Host mode
(>120uF).
Open for Device or OTG
modes (4.7uF).
Pre-configuration I/O
standard type for the
dedicated configuration
bank 0. Vcco_0 is 3.3V,
Connected to 3.3V
through a 10K resistor.
This jumper connects to
GND and should NOT
be used.
Active Low input enables
internal pull-ups during
configuration on
all SelectIO pins.
Connected to Vadj
through 10K resistor.
Install for SD Card boot
on CES silicon.
JTAG Mode. GND
cascades PS and PL
JTAG chains. VCC
makes JTAG chains
independent.
Boot Device Select
See Zynq Configuration
Modes
PLL Select. GND uses
PS PLLs. VCC
bypasses internal PS
PLLs
Short bypasses XADCGND ferrite bead
connection to board
GND.
Short connects JTAG
PROG-RST to PS
Reset.
Selects Vadj (1.8V, 2.5V,
or 3.3V)

27-Jan-2014

Figure 20 - ZedBoard Jumper Map

27-Jan-2014

5 Mechanical
The ZedBoard measures 6.3”x6.3”.

Figure 21 - ZedBoard Mechanical

27-Jan-2014

6 Revision History

Rev date

Rev #

8/1/12
8/2/12

1.0
1.1

8/14/12

1.2

8/15/12
8/30/12

1.3
1.4

9/4/12

1.5

9/5/12
1/17/13

1.6
1.7

1/18/13

1.8

1/29/13

1.9

10/2/13

2.0

11/1/13
1/27/14

2.1
2.2

Reason for change
Initial ZedBoard User’s Guide
Mapped Configuration Mode Table to match ZedBoard layout
Added MIO Pins and Peripheral Tables; Updated Reset Section;
Updated Block Diagram
Updated Part Package numbering; Matched Xilinx Trademarks
Updated Board Images to Rev. C.1; Updated DDR3 section
Corrected package information in ZedBoard Block Diagram (fig. 1);
Added note regarding connecting multiple Pmods
Fixed error in Pmod Pinout Table
Added TI USB OTG PHY design advisory notice
Added LD9 to docs; Updated Default Jumper Table; Updated
Configuration Modes Table
Replaced RJ-45 184808-7 (obsolete) with 1840750-7
Removed ‘ES’ designation from Zynq part number. Corrected DDR3
IC25/IC26 placement description with IC26 being closest to the
Zynq. Removed references to the Xilinx Answer Record for DDR
training calculations as these are now included in the Xilinx tools.
Corrected reference to JE1’s MIO usage. Added MIO to Table 16.
Updated DDR3 trace impedance used vs. UG933 recommendation.

27-Jan-2014

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