Realtek Semiconductor RTL8187 802.11b/g RTL8187 miniCard User Manual Realtek RTL8187L DataSheet 1 2

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RTL8187L
802.11b/g RTL8187 miniCard
Rev. 1.2
06 September 2005
Track ID: JATR-1076-21
RTL8187L
Datasheet
COPYRIGHT
©2005 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied,
including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in
this document or in the product described in this document at any time. This document could include
technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are
trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document is intended for the software engineer’s reference and provides detailed programming
information.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide. In that event, please contact your
Realtek representative for additional information that may help in the development process.
REVISION HISTORY
Revision
1.0
1.1
Release Date
2004/10/22
2005/04/25
1.2
2005/09/06
Wireless LAN Network Interface Controller
Summary
First release.
Revised data transaction content.
Added offset 8 information (Table 27, page 23, and Table 28, page 23).
Added RoHS declaration (see last 2 pages).
Added lead (Pb)-free and package identification information on page 4.
Corrected section 14 Mechanical Dimensions, page 34.
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Table of Contents
1.
GENERAL DESCRIPTION ...............................................................................................................................................1
2.
FEATURES ..........................................................................................................................................................................2
3.
SYSTEM APPLICATIONS ................................................................................................................................................3
4.
BLOCK DIAGRAM ............................................................................................................................................................3
5.
PIN ASSIGNMENTS...........................................................................................................................................................4
5.1.
6.
LEAD (PB)-FREE PACKAGE IDENTIFICATION ...................................................................................................................4
PIN DESCRIPTIONS ..........................................................................................................................................................5
6.1. USB TRANSCEIVER INTERFACE ......................................................................................................................................5
6.2. EEPROM INTERFACE .....................................................................................................................................................5
6.3. POWER PINS ....................................................................................................................................................................5
6.4. LED INTERFACE..............................................................................................................................................................6
6.5. ATTACHMENT UNIT INTERFACE ......................................................................................................................................6
6.5.1.
RTL8225 RF Chipset ..............................................................................................................................................6
6.5.2.
RTL8255 RF Chipset ..............................................................................................................................................7
6.6. CLOCK AND OTHER PINS .................................................................................................................................................8
7.
CPU ACCESS TO ENDPOINT DATA..............................................................................................................................9
7.1.
7.2.
8.
CONTROL TRANSFER .......................................................................................................................................................9
BULK TRANSFER .............................................................................................................................................................9
USB REQUEST ..................................................................................................................................................................10
8.1.
8.2.
8.3.
8.4.
8.5.
8.6.
8.7.
8.8.
8.9.
8.10.
8.11.
8.12.
8.13.
8.14.
8.15.
8.16.
9.
GET DESCRIPTOR-DEVICE .............................................................................................................................................10
GET DESCRIPTOR-DEVICE QUALIFIER (HIGH SPEED)....................................................................................................10
GET DESCRIPTOR-CONFIGURATION ..............................................................................................................................11
GET DESCRIPTOR-STRING INDEX 0 ...............................................................................................................................11
GET DESCRIPTOR-STRING INDEX 1 ...............................................................................................................................12
GET DESCRIPTOR-STRING INDEX 2 ...............................................................................................................................12
GET DESCRIPTOR-STRING INDEX 3 ...............................................................................................................................13
GET DESCRIPTOR-STRING INDEX 4 ...............................................................................................................................13
GET DESCRIPTOR-STRING INDEX 5 ...............................................................................................................................14
GET DESCRIPTOR-OTHER SPEED CONFIGURATION....................................................................................................14
SET ADDRESS ............................................................................................................................................................15
SET INTERFACE 0 ......................................................................................................................................................15
SET FEATURE DEVICE ...............................................................................................................................................15
CLEAR FEATURE DEVICE ..........................................................................................................................................16
SET CONFIG 0............................................................................................................................................................16
SET CONFIG 1............................................................................................................................................................16
EEPROM (93C46 OR 93C56) CONTENTS ....................................................................................................................17
9.1.
9.2.
10.
EEPROM REGISTERS SUMMARY ..................................................................................................................................20
EEPROM POWER MANAGEMENT REGISTERS SUMMARY .............................................................................................20
USB PACKET BUFFERING ........................................................................................................................................21
10.1.
10.2.
TRANSMIT BUFFER MANAGER ..................................................................................................................................21
RECEIVE BUFFER MANAGER .....................................................................................................................................21
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10.3.
11.
PACKET RECOGNITION ..............................................................................................................................................21
FUNCTIONAL DESCRIPTION ..................................................................................................................................22
11.1.
TRANSMIT & RECEIVE OPERATIONS..........................................................................................................................22
11.1.1. Transmit ...............................................................................................................................................................22
11.1.2. Receive .................................................................................................................................................................25
11.2.
LOOPBACK OPERATION .............................................................................................................................................27
11.3.
TX ENCAPSULATION (WITH RTL8187L INTERNAL BASEBAND PROCESSOR)............................................................27
11.4.
RX DECAPSULATION (WITH RTL8187L INTERNAL BASEBAND PROCESSOR) ...........................................................27
11.5.
LED FUNCTIONS .......................................................................................................................................................28
11.5.1. Link Monitor.........................................................................................................................................................28
11.5.2. Infrastructure Monitor .........................................................................................................................................28
11.5.3. Rx LED .................................................................................................................................................................28
11.5.4. Tx LED .................................................................................................................................................................29
11.5.5. Tx/Rx LED ............................................................................................................................................................29
11.5.6. LINK/ACT LED ....................................................................................................................................................30
12.
APPLICATION DIAGRAM .........................................................................................................................................31
13.
ELECTRICAL CHARACTERISTICS........................................................................................................................32
13.1.
TEMPERATURE LIMIT RATINGS .................................................................................................................................32
13.2.
DC CHARACTERISTICS ..............................................................................................................................................32
13.3.
AC CHARACTERISTICS ..............................................................................................................................................33
13.3.1. Serial EEPROM Interface Timing (93C46(64*16)/93C56(128*16))...................................................................33
14.
MECHANICAL DIMENSIONS ...................................................................................................................................34
14.1.
15.
MECHANICAL DIMENSIONS NOTES............................................................................................................................35
ORDERING INFORMATION .....................................................................................................................................36
List of Tables
TABLE 1. USB TRANSCEIVER INTERFACE .....................................................................................................................................5
TABLE 2. EEPROM INTERFACE ....................................................................................................................................................5
TABLE 3. POWER PINS ...................................................................................................................................................................5
TABLE 4. LED INTERFACE.............................................................................................................................................................6
TABLE 5. ATTACHMENT UNIT INTERFACE .....................................................................................................................................6
TABLE 6. RTL8255 RF CHIPSET....................................................................................................................................................7
TABLE 7. CLOCK AND OTHER PINS ................................................................................................................................................8
TABLE 8. GET DESCRIPTOR-DEVICE ............................................................................................................................................10
TABLE 9. GET DESCRIPTOR- DEVICE QUALIFIER (HIGH SPEED) ..................................................................................................10
TABLE 10. GET DESCRIPTOR-CONFIGURATION .............................................................................................................................11
TABLE 11. GET DESCRIPTOR-STRING INDEX 0 ..............................................................................................................................11
TABLE 12. GET DESCRIPTOR-STRING INDEX 1 ..............................................................................................................................12
TABLE 13. GET DESCRIPTOR-STRING INDEX 2 ..............................................................................................................................12
TABLE 14. GET DESCRIPTOR-STRING INDEX 3 ..............................................................................................................................13
TABLE 15. GET DESCRIPTOR-STRING INDEX 4 ..............................................................................................................................13
TABLE 16. GET DESCRIPTOR-STRING INDEX 5 ..............................................................................................................................14
TABLE 17. GET DESCRIPTOR-OTHER SPEED CONFIGURATION ......................................................................................................14
TABLE 18. SET ADDRESS ..............................................................................................................................................................15
TABLE 19. SET INTERFACE 0 .........................................................................................................................................................15
Wireless LAN Network Interface Controller
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TABLE 20. SET FEATURE DEVICE ..................................................................................................................................................15
TABLE 21. CLEAR FEATURE DEVICE .............................................................................................................................................16
TABLE 22. SET CONFIG 0 ..............................................................................................................................................................16
TABLE 23. SET CONFIG 1 ..............................................................................................................................................................16
TABLE 24. EEPROM (93C46 OR 93C56) CONTENTS ....................................................................................................................17
TABLE 25. EEPROM REGISTERS SUMMARY ................................................................................................................................20
TABLE 26. EEPROM POWER MANAGEMENT REGISTERS SUMMARY ............................................................................................20
TABLE 27. TX DESCRIPTOR FORMAT ............................................................................................................................................22
TABLE 28. TX STATUS DESCRIPTOR ..............................................................................................................................................23
TABLE 29. RX DESCRIPTOR FORMAT ............................................................................................................................................25
TABLE 30. RX STATUS DESCRIPTOR..............................................................................................................................................25
TABLE 31. TEMPERATURE LIMIT RATINGS ....................................................................................................................................32
TABLE 32. DC CHARACTERISTICS .................................................................................................................................................32
TABLE 33. EEPROM ACCESS TIMING PARAMETERS ....................................................................................................................33
TABLE 34. ORDERING INFORMATION ............................................................................................................................................36
List of Figures
FIGURE 1.
FIGURE 2.
FIGURE 3.
FIGURE 4.
FIGURE 5.
FIGURE 6.
FIGURE 7.
FIGURE 8.
BLOCK DIAGRAM ..........................................................................................................................................................3
PIN ASSIGNMENTS.........................................................................................................................................................4
RX LED ......................................................................................................................................................................28
TX LED ......................................................................................................................................................................29
TX/RX LED ................................................................................................................................................................29
LINK/ACT LED.........................................................................................................................................................30
APPLICATION DIAGRAM ..............................................................................................................................................31
SERIAL EEPROM INTERFACE TIMING ........................................................................................................................33
Wireless LAN Network Interface Controller
Track ID: JATR-1076-21 Rev. 1.2
RTL8187L
Datasheet
1. General Description
The Realtek RTL8187L is a low-profile highly integrated cost-effective Wireless LAN USB 2.0 network
interface controller that integrates a USB 2.0 PHY, SIE (Serial Interface Engine), 8051 MCU, a Wireless
LAN MAC, and a Direct Sequence Spread Spectrum/OFDM baseband processor onto one chip. It provides
USB high speed (480Mbps), and full speed (12Mbps), and supports 4 endpoints for transfer pipes. To
reduce protocol overhead, the RTL8187L supports Short InterFrame Space (SIFS) burst mode to send
packets back-to-back. A protection mechanism prevents collisions among 802.11b nodes. The RTL8187L
fully complies with IEEE 802.11a/b/g specifications.
Direct Sequence Spread Spectrum (DSSS), Complementary Code Keying (CCK), and Orthogonal
Frequency Division Multiplexing (OFDM) baseband processing are implemented to support all IEEE
802.11a, 802.11b, and 802.11g data rates. Differential phase shift keying modulation schemes, DBPSK and
DQPSK with data scrambling capability, are available, along with complementary code keying to provide
data rates of 1, 2, 5.5, and 11Mbps, with long or short preamble. A high-speed Fast Fourier Transform
(FFT)/Inverse Fast Fourier Transform (IFFT), combined with BPSK, QPSK, 16QAM and 64QAM
modulation of the individual sub-carriers, provides data rates of 6, 9, 12, 18, 24, 36, 48 and 54Mbps, with
rate-compatible punctured convolutional coding with a coding rate of 1/2, 2/3, and 3/4.
An enhanced signal detector, an adaptive frequency domain equalizer, and a soft-decision Viterbi decoder
are built-in to alleviate severe multipath effects. Efficient IQ-imbalance calibration, DC offset, phase noise,
frequency offset, and timing offset compensation reduce radio frequency front-end impairments. Selectable
digital transmit and receiver FIR filters are provided to meet the requirements of transmit spectrum masks,
and to reject adjacent channel interference, respectively. Both in the transmitter and receiver,
programmable scaling in the digital domain trades the quantization noise against the increased probability
of clipping. Robust signal detection, symbol boundary detection, and channel estimation perform well at
the minimum sensitivity.
The RTL8187L supports fast receiver Automatic Gain Control (AGC) and antenna diversity functions, and
an adaptive transmit power control function to obtain better performance in the analog portions of the
transceiver. It also has on-chip digital-to-analog converters and analog-to-digital converters for analog I
and Q inputs and outputs, transmit TSSI and receiver RSSI inputs, and transmit and receiver AGC outputs.
The RTL8187L is highly integrated and requires no ‘glue’ logic or external memory. It keeps network
maintenance costs low and eliminates usage barriers.
Wireless LAN Network Interface Controller
Track ID JATR-1076-21 Rev. 1.2
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Datasheet
2. Features
„
128-Pin LQFP and 128-pin LQFP Lead
(Pb)-Free package
„
State machine implementation without
external memory (RAM, flash) requirement
„
Complies with IEEE 802.11a/b/g standards
„
Supports descriptor-based buffer
management
„
Integrated Wireless LAN MAC and Direct
Sequence Spread Spectrum/OFDM
Baseband Processor in one chip
„
Enhanced signal detector, adaptive frequency
domain equalizer, and soft-decision Viterbi
decoder to alleviate severe multipath effects
„
OFDM with BPSK, QPSK, 16QAM and
64QAM modulations and demodulations
supported with rate compatible punctured
convolutional coding with coding rate of 1/2,
2/3, and 3/4
„
Efficient IQ-imbalance calibration, DC
offset, phase noise, frequency offset and
timing offset compensation reduce analog
front-end impairments
„
Selectable digital transmit and receiver FIR
filters provided to meet transmit spectrum
mask requirements and to reject adjacent
channel interference
„
Programmable scaling both in transmitter
and receiver to trade quantization noise
against the increased probability of clipping
„
Fast receiver Automatic Gain Control (AGC)
& antenna diversity functions
„
Hardware-based IEEE 802.11i
encryption/decryption engine, including
64-bit/128-bit WEP, TKIP, and AES
„
Processing Gain compliant with FCC
„
On-Chip A/D and D/A converters for I/Q
Data, AGC, and Adaptive Power Control
„
Supports both transmit and receive Antenna
Diversity
„
Data rates of 1, 2, 5.5, 6, 9, 11, 12, 18, 24, 36,
48, and 54Mbps
„
Supports Wi-Fi alliance WPA and WPA2
security
„
Supports 40MHz OSC as the internal clock
source. The frequency deviation of the OSC
must be within 25 PPM on IEEE 802.11g and
20 PPM on IEEE 802.11a
„
Contains two large independent transmit and
receive FIFO buffers
„
Advanced power saving mode when the
LAN and wakeup function are not used
„
Uses 93C46 (64*16-bit EEPROM) or 93C56
(128*16-bit EEPROM) to store resource
configuration and ID parameter data
„
LED pins for various network activity
indications
„
Two GPIO pins supported
„
IEEE 802.11g protection mechanisms for
both RTS/CTS and CTS-to-self
„
Burst-mode support for dramatically
enhanced throughput
„
DSSS with DBPSK and DQPSK, CCK
modulations and demodulations supported
with long and short preamble
Wireless LAN Network Interface Controller
Track ID JATR-1076-21 Rev. 1.2
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Datasheet
„
„
Supports digital loopback capability on both
ports
Supports 4 endpoints:
‹
64-Byte buffer for control endpoint
„
Scatter and gather operation
‹
512-Byte buffer for bulk IN endpoint
„
Complies with USB Specification 2.0
‹
Two 512-Byte buffers for bulk OUT
endpoint
‹
„
Supports Full-speed (12Mbps) and
High-speed (480Mbps)
Embedded standard 8051 CPU with
enhanced features:
‹
Four cycles per instruction
‹
Variable clock speed cuts power
consumption
„
3.3V and 1.8V power supplies required
„
5V tolerant I/Os
„
0.18µm CMOS process
3. System Applications
„
USB Dongle WLAN adapter
„
Embedded WLAN solution in notebook, desktop, mobile phone, and motherboard
Wireless LAN Network Interface Controller
Track ID JATR-1076-21 Rev. 1.2
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Datasheet
4. Block Diagram
MAC
EEPROM
Interface
Serial
Control
LED Driver
RTS, CTS,
ACK Frame
Generator
D-
S I E + Register
D+
WEP/
TKIP/
AES
Checksum
Logic
CCA/
NAV
Engine
FIFO
Control
Logic
FIFO
Frame Type
Discriminator
Interrupt
Control
Logic
Frame Length
Register
Power and TX/RX Timing Control Logic
Radio and
Synthesizer
Control
Transmit/
Receive
Logic
Interface
From BBP
MAC/BBP
Interface
BBP, TX Section
MAC/BBP
Interface
From
MAC
Scrambler
TXI
DAC
TXQ
DAC
TXAGC
TX AGC
Control
TX State
Machine
Register
DAC
Digital
Filter
Coding
ADC
TXDET
ADC
RXI
ADC
RXQ
BBP, RX Section
MAC/BBP
Interface
Descrambler
Register
RXAGC
DAC
Clear Channel
Assessment/
Signal Quality
To MAC
From
MAC
Decoding
RX AGC
Control
ADC
RX State
Machine
Antenna
Diversity
Control
RSSI
ANTSEL
ANTSELB
Figure 1. Block Diagram
Wireless LAN Network Interface Controller
Track ID JATR-1076-21 Rev. 1.2
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Datasheet
5. Pin Assignments
Figure 2. Pin Assignments
5.1. Lead (Pb)-Free Package Identification
Lead (Pb)-free package is indicated by an ‘L’ in the location marked ‘T’ in Figure 2.
Wireless LAN Network Interface Controller
Track ID JATR-1076-21 Rev. 1.2
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Datasheet
6. Pin Descriptions
In order to reduce pin count, and therefore size and cost, some pins have multiple functions. In such cases,
the functions are separated with a ‘/’ symbol. Refer to the Pin Assignments diagram on page 4 for a
graphical representation.
The following signal type codes are used in the tables:
I: Input.
S/T/S: Sustained Tri-State.
O: Output
O/D: Open Drain.
T/S: Tri-State bi-directional input/output pin.
6.1. USB Transceiver Interface
Table 1. USB Transceiver Interface
Symbol
HSDP
HSDM
FSDP
FSDM
RUP
RREF
Type
I/O
I/O
I/O
I/O
N/A
N/A
Pin No
26
24
27
25
28
31
Description
High speed USB D+ signal
High speed USB D- signal
Full speed USB D+ signal
Full speed USB D- signal
External pull-up resistor (1.5kW) for D+ line.
External Reference. Requires 1% precision 6.25K resistor to ground
6.2. EEPROM Interface
Table 2. EEPROM Interface
Symbol
EESK
EEDI
EEDO
EECS
Type
I/O
Pin No
51
39
36
47
Description
EESK in 93C46 (93C56) programming or auto-load mode.
EEDI in 93C46 (93C56) programming or auto-load mode.
EEDO in 93C46 (93C56) programming or auto-load mode.
EEPROM Chip Select.
93C46 (93C56) chip select.
6.3. Power Pins
Table 3. Power Pins
Symbol
VDD33
AVDD
VDD
Type
GND
AGND
Pin No
40, 59, 78, 93, 111
2, 9, 22, 29, 32, 127
44, 53, 72, 82, 90, 96,
105, 115
41, 45, 52, 60, 73, 80,
83, 91, 110
3, 10, 21, 23, 30, 123,
126, 128
Wireless LAN Network Interface Controller
Description
+3.3V (Digital).
+3.3V (Analog).
+1.8V.
Ground (Digital).
Ground (Analog).
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Datasheet
6.4. LED Interface
Table 4. LED Interface
Symbol
LED0, 1
Type
Pin No
48, 56
Description
LED Pins (Active low)
LEDS1~0
00
01
10
11
LED0
TX/RX
TX/RX
TX
LINK/ACT
LED1
Infrastructure
LINK
RX
Infrastructure
During power down mode, the LED signals are logic high.
6.5. Attachment Unit Interface
6.5.1. RTL8225 RF Chipset
Table 5. Attachment Unit Interface
Symbol
RIFSCK
Type
Pin No
57
I/O
61
58
77
108
LNA_HL
ANTSEL
88
87
ANTSELB
95
TRSW
TRSWB
VCOPDN
A_PAPE
B_PAPE
RFTXEN
RFRXEN
GPIO0
GPIO1
GPIO2
GPIO3
104
103
49
85
107
102
113
67
68
69
70
RIFSD
RFLE
CALEN
CALMODE
Description
Serial Clock Output.
For the RTL8225 RF chipset, all operation mode switching and register setting is
done via a 4-wire serial interface.
Serial Data Input/Output.
Serial Enable control.
Serial Read/Write control.
Receiver Output.
I and Q channel AC coupling high-pass corner frequency selection. The output
function of this pin is not used in the RTL8225 RF chipset.
Not used in the RTL8225 RF chipset.
Antenna Select.
The antenna detects signal change states as the receiver switches from antenna to
antenna during the acquisition process in antenna diversity mode. This is a
complement for ANTSELB for differential drive of antenna switches.
Antenna Select B.
The antenna detects signal change states as the receiver switches from antenna to
antenna during the acquisition process in the antenna diversity mode. This is a
complement for ANTSEL for differential drive of antenna switches.
Transmit/Receive path select.
The TRSW select signal controls the direction of the Transmit/Receive switch.
Output Pin as shutdown mode select digital input.
2.4GHz Transmit Power Amplifier Power Enable.
Not used in the RTL8225 RF chipset.
Not used in the RTL8225 RF chipset.
Not used in the RTL8225 RF chipset.
General purpose input/output pin.
General purpose input/output pin.
General purpose input/output pin.
General purpose input/output pin.
Wireless LAN Network Interface Controller
Track ID JATR-1076-21 Rev. 1.2
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Datasheet
Symbol
GPIO4
GPIO5
VREFO
VRP
VRN
RXIP
RXIN
RXQP
RXQN
RXAGC
TXAGC
RSSI
TSSI0
TSSI1
TXQP
TXQN
TXIP
TXIN
TXQTP
TXQTN
TXITP
TXITN
Type
Pin No
100
94
118
119
120
121
122
124
125
11
12
14
13
15
16
17
18
Description
General purpose input/output pin.
General purpose input/output pin.
Not used in the RTL8225 RF chipset.
Not used in the RTL8225 RF chipset.
Not used in the RTL8225 RF chipset.
Receive (Rx) In-phase Analog Data.
Receive (Rx) Quadrature-phase Analog Data.
Not used in the RTL8225 RF chipset.
Not used in the RTL8225 RF chipset.
Analog Input to the Receive Power A/D Converter for Receive AGC Control.
Input to the Transmit Power A/D Converter for 2.4GHz Transmit AGC Control.
Not used in the RTL8225 RF chipset.
Not used in the RTL8225 RF chipset.
Not used in the RTL8225 RF chipset.
Transmit (TX) Quadrature-phase Analog Data.
Transmit (TX) In-phase Analog Data.
6.5.2. RTL8255 RF Chipset
Table 6. RTL8255 RF Chipset
Symbol
RIFSCK
Type
Pin No
57
RIFSD
RFLE
CALEN
CALMODE
61
58
77
108
LNAHL
ANTSEL
ANTSELB
88
87
95
TRSW
TRSWB
VCOPDN
APAPE
BPAPE
104
103
49
85
107
Description
Serial Clock Output.
For the RTL8255 RF chipset, all operation mode switching and register setting is
done via a 3-wire serial interface.
Serial Data Input/Output.
Serial Enable control.
Not used in the RTL8255 RF chipset.
Receiver Output.
I and Q channel AC coupling high-pass corner frequency selection. The output
function of this pin is not used in the RTL8255 RF chipset.
Not used in the RTL8255 RF chipset.
Antenna Select.
The antenna detects signal change states as the receiver switches from antenna to
antenna during the acquisition process in antenna diversity mode.
Transmit/Receive path select.
The TRSW select signal controls the direction of the Transmit/Receive switch.
Not used in the RTL8255 RF chipset.
2.4GHz Transmit Power Amplifier Power Enable.
5GHz Transmit Power Amplifier Power Enable.
Wireless LAN Network Interface Controller
Track ID JATR-1076-21 Rev. 1.2
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Datasheet
Symbol
RFTXEN
RFRXEN
GPIO[0]
GPIO[1]
GPIO[2]
GPIO[3]
GPIO[4]
GPIO[5]
VREFO
VRP
VRN
RXIP
RXIN
RXQP
RXQN
RXAGC
TXAGC
RSSI
TSSI0
TSSI1
TXQP
TXQN
TXIP
TXIN
TXQTP
TXQTN
TXITP
TXITN
Type
Pin No
102
113
67
68
69
70
100
94
118
119
120
121
122
124
125
11
12
14
13
15
16
17
18
Description
Not used in the RTL8255 RF chipset.
Not used in the RTL8255 RF chipset.
General purpose input/output pin.
General purpose input/output pin.
General purpose input/output pin.
General purpose input/output pin.
General purpose input/output pin.
General purpose input/output pin.
Not used in the RTL8255 RF chipset.
Not used in the RTL8255 RF chipset.
Not used in the RTL8255 RF chipset.
Receive (Rx) In-phase Analog Data.
Receive (Rx) Quadrature-phase Analog Data.
Not used in the RTL8255 RF chipset.
Not used in the RTL8255 RF chipset.
Analog Input to the Receive Power A/D Converter for Receive AGC Control.
Input to the Transmit Power A/D Converter for 2.4GHz Transmit AGC Control.
Input to the Transmit Power A/D Converter for 5GHz Transmit AGC Control.
Transmit (TX) Quadrature-phase Analog Data.
Transmit (TX) In-phase Analog Data.
Not used in the RTL8255 RF chipset.
Not used in the RTL8255 RF chipset.
6.6. Clock and Other Pins
Table 7. Clock and Other Pins
Symbol
R15K
XI
Type
I/O
Pin No
20
Wireless LAN Network Interface Controller
Description
This pin must be pulled low by a 15K Ω resistor.
40MHz OSC Input.
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RTL8187L
Datasheet
7. CPU Access to Endpoint Data
7.1. Control Transfer
Control transfers configure and send commands to a device. Because they are so important, they employ
extensive USB error checking. The host reserves a portion of each USB frame for control transfers. Control
transfers consist of two or three stages. The SETUP stage contains eight bytes of USB control data. An
optional DATA stage contains more data, if required. The STATUS stage allows the device to indicate
successful completion of a control operation.
7.2. Bulk Transfer
Bulk data is bursty, traveling in packets of 8, 16, 32, or 64 bytes at full speed, or at 512 bytes at high speed.
Bulk data has guaranteed accuracy due to an automatic retry mechanism for erroneous data. The host
schedules bulk packets when there is available bus time.
Wireless LAN Network Interface Controller
Track ID JATR-1076-21 Rev. 1.2
RTL8187L
Datasheet
8. USB Request
8.1. Get Descriptor-Device
Table 8. Get Descriptor-Device
Setup Transaction
BmReq
80
bReq
06
wValueL
00
wValueH
01
wIndexL
00
wIndexH
00
wLengthL
Lengh_L
wLengthH
Length_H
DATA3
02
81
DATA4
00
00
DATA5
00
01
DATA6
00
01
DATA7
40
02
DATA3
01
81
DATA4
00
00
DATA5
00
01
DATA6
00
01
DATA7
40
02
High Speed Data Transaction
DATA0
12
DA
03
DATA1
01
0B
01
DATA2
00
87
Full Speed Data Transaction
DATA0
12
DA
03
DATA1
01
0B
01
DATA2
10
87
8.2. Get Descriptor-Device Qualifier (High Speed)
Table 9. Get Descriptor- Device Qualifier (High Speed)
Setup Transaction
BmReq
80
bReq
06
wValueL
00
wValueH
06
wIndexL
00
wIndexH
00
wLengthL
Lengh_L
DATA2
00
DATA3
02
DATA4
00
DATA5
00
DATA6
00
wLengthH
Length_H
Data Transaction
DATA0
0A
01
DATA1
06
00
Wireless LAN Network Interface Controller
10
DATA7
40
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RTL8187L
Datasheet
8.3. Get Descriptor-Configuration
Table 10. Get Descriptor-Configuration
Setup Transaction
BmReq
80
bReq
06
wValueL
00
wValueH
02
wIndexL
00
wIndexH
00
wLengthL
Lengh_L
wLengthH
Length_H
DATA3
00
00
05
02
02
DATA4
01
00
81
02
00
DATA5
01
03
02
00
02
DATA6
04
00
00
02
00
DATA7
80
00
02
00
DATA3
00
00
05
02
02
DATA4
01
00
81
02
40
DATA5
01
03
02
40
00
DATA6
00
00
40
00
00
DATA7
E0
00
00
00
High Speed Data Transaction
DATA0
09
FA
00
00
07
DATA1
02
09
05
07
05
DATA2
27
04
07
05
03
Full Speed Data Transaction
DATA0
09
01
00
00
07
DATA1
02
09
05
07
05
DATA2
27
04
07
05
03
8.4. Get Descriptor-String Index 0
Table 11. Get Descriptor-String Index 0
Setup Transaction
BmReq
80
bReq
06
wValueL
00
wValueH
03
wIndexL
00
wIndexH
00
wLengthL
Lengh_L
DATA2
09
DATA3
04
DATA4
DATA5
DATA6
wLengthH
Length_H
Data Transaction
DATA0
04
DATA1
03
Wireless LAN Network Interface Controller
11
DATA7
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RTL8187L
Datasheet
8.5. Get Descriptor-String Index 1
Table 12. Get Descriptor-String Index 1
Setup Transaction
BmReq
80
bReq
06
wValueL
01
wValueH
03
wIndexL
09
wIndexH
04
wLengthL
Lengh_L
DATA2
52
74
DATA3
00
00
DATA4
65
65
DATA5
00
00
DATA6
61
6B
wLengthH
Length_H
Data Transaction
DATA0
10
6C
DATA1
03
00
DATA7
00
00
8.6. Get Descriptor-String Index 2
Table 13. Get Descriptor-String Index 2
Setup Transaction
BmReq
80
bReq
06
wValueL
02
wValueH
03
wIndexL
09
wIndexH
04
wLengthL
Lengh_L
DATA2
52
31
57
6C
20
20
70
DATA3
00
00
00
00
00
00
00
DATA4
54
38
59
65
4C
41
74
DATA5
00
00
00
00
00
00
00
DATA6
4C
37
72
73
41
64
65
wLengthH
Length_H
Data Transaction
DATA0
3A
38
20
65
73
4E
61
72
DATA1
03
00
00
00
00
00
00
00
Wireless LAN Network Interface Controller
12
DATA7
00
00
00
00
00
00
00
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RTL8187L
Datasheet
8.7. Get Descriptor-String Index 3
Table 14. Get Descriptor-String Index 3
Setup Transaction
BmReq
80
bReq
06
wValueL
03
wValueH
03
wIndexL
09
wIndexH
04
wLengthL
Lengh_L
DATA2
30
34
30
DATA3
00
00
00
DATA4
30
63
30
DATA5
00
00
00
DATA6
65
30
30
wLengthH
Length_H
Data Transaction
DATA0
1A
30
30
31
DATA1
03
00
00
00
DATA7
00
00
00
8.8. Get Descriptor-String Index 4
Table 15. Get Descriptor-String Index 4
Setup Transaction
BmReq
80
bReq
06
wValueL
04
wValueH
03
wIndexL
09
wIndexH
04
wLengthL
Lengh_L
DATA2
57
6C
20
77
20
64
DATA3
00
00
00
00
00
00
DATA4
69
65
4E
6F
43
DATA5
00
00
00
00
00
DATA6
72
73
65
72
61
wLengthH
Length_H
Data Transaction
DATA0
2C
65
73
74
6B
72
DATA1
03
00
00
00
00
00
Wireless LAN Network Interface Controller
13
DATA7
00
00
00
00
00
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RTL8187L
Datasheet
8.9. Get Descriptor-String Index 5
Table 16. Get Descriptor-String Index 5
Setup Transaction
BmReq
80
bReq
06
wValueL
05
wValueH
03
wIndexL
09
wIndexH
04
wLengthL
Lengh_L
DATA2
42
2D
42
2D
2C
6B
54
DATA3
00
00
00
00
00
00
00
DATA4
75
49
75
4F
42
2D
DATA5
00
00
00
00
00
00
DATA6
6C
4E
6C
55
75
4F
wLengthH
Length_H
Data Transaction
DATA0
34
6B
2C
6B
54
6C
55
DATA1
03
00
00
00
00
00
00
DATA7
00
00
00
00
00
00
8.10. Get Descriptor-Other Speed Configuration
Table 17. Get Descriptor-Other Speed Configuration
Setup Transaction
BmReq
80
bReq
06
wValueL
00
wValueH
07
wIndexL
00
wIndexH
00
wLengthL
Lengh_L
wLengthH
Length_H
DATA3
00
00
05
02
02
DATA4
01
00
81
02
00
DATA5
01
03
02
00
02
DATA6
04
00
00
02
00
DATA7
80
00
02
00
DATA3
00
00
05
02
02
DATA4
01
00
81
02
40
DATA5
01
03
02
40
00
DATA6
00
00
40
00
00
DATA7
E0
00
00
00
High Speed Data Transaction
DATA0
09
FA
00
00
07
DATA1
02
09
05
07
05
DATA2
27
04
07
05
03
Full Speed Data Transaction
DATA0
09
01
00
00
07
DATA1
02
09
05
07
05
DATA2
27
04
07
05
03
Wireless LAN Network Interface Controller
14
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RTL8187L
Datasheet
8.11. Set Address
Table 18. Set Address
Setup Transaction
BmReq
bReq
00
05
Note: No data transaction.
wValueL
addrL
wValueH
addrH
wIndexL
00
wIndexH
00
wLengthL
00
wLengthH
00
wIndexH
00
wLengthL
00
wLengthH
00
wIndexH
00
wLengthL
00
wLengthH
00
8.12. Set Interface 0
Table 19. Set Interface 0
Setup Transaction
BmReq
bReq
01
0B
Note: No data transaction.
wValueL
00
wValueH
00
wIndexL
00
8.13. Set Feature Device
Table 20. Set Feature Device
Setup Transaction
BmReq
bReq
00
03
Note: No data transaction.
wValueL
01
Wireless LAN Network Interface Controller
wValueH
00
wIndexL
00
15
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Datasheet
8.14. Clear Feature Device
Table 21. Clear Feature Device
Setup Transaction
BmReq
bReq
00
01
Note: No data transaction.
wValueL
01
wValueH
00
wIndexL
00
wIndexH
00
wLengthL
00
wLengthH
00
wIndexH
00
wLengthL
00
wLengthH
00
wIndexH
00
wLengthL
00
wLengthH
00
8.15. Set Config 0
Table 22. Set Config 0
Setup Transaction
BmReq
bReq
00
09
Note: No data transaction.
wValueL
00
wValueH
02
wIndexL
00
8.16. Set Config 1
Table 23. Set Config 1
Setup Transaction
BmReq
bReq
00
09
Note: No data transaction.
wValueL
01
Wireless LAN Network Interface Controller
wValueH
00
wIndexL
00
16
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RTL8187L
Datasheet
9. EEPROM (93C46 or 93C56) Contents
The RTL8187L supports the attachment of an external EEPROM. The 93C46 is a 1Kbit EEPROM (the
93C56 is a 2Kbit EEPROM). The EEPROM interface provides the ability for the RTL8187L to read from,
and write data to, an external serial EEPROM device. If the EEPROM is not present, the RTL8187L
initialization uses default values for the Operational Registers. Software can read and write to the
EEPROM using “bit-bang” accesses via the 9346CR Register.
Although it is actually addressed by words, its contents are listed below by bytes for convenience. After the
initial power on or auto-load command in the 9346CR, the RTL8187L performs a series of EEPROM read
operations from the 93C46 (93C56).
Note: It is suggested to obtain Realtek approval before changing the default settings of the EEPROM.
Table 24. EEPROM (93C46 or 93C56) Contents
Bytes
00h
01h
Contents
87h
81h
02h-03h
04h-05h
06h
07h
08h
09h-0Ah
0Bh
VID
DID
ChannelPlan
EnergyDetThr
RFParm
Version
Options function
Description
These 2 bytes contain the ID code word for the RTL8187L. The RTL8187L will load
the contents of the EEPROM into the corresponding location if the ID word (8187h) is
correct.
USB Vendor ID.
USB Device ID.
Channel Plan: Map of channels to be scanned.
Energy detection threshold.
RF specific parameter.
The version of EEPROM content.
Bit0: Timeout function.
0: Disable RTL8187L’s USB timeout mechanism.
1: Enable RTL8187L’s USB timeout mechanism.
Bit1: USB remote wake up function.
0: There is no remote wake up feature for the RTL8187L.
1: There is a remote wake up feature for the RTL8187L.
Bit2:
0: The RTL8187L’s remote wake-up is based on the WLAN’s wake-up signal
1: The RTL8187L’s remote wake-up is push-button based.
Bit3: USB Status stage.
1: Bypass the check setup interrupt procedure of 8051 when host sends set_address
command.
Bit4: SelfloopbackISR function.
1: The UTM self loopback will be initialized by internal 8051.
0Ch
RFChipID
Bit7:
1: The power control signal to AFE will be auto controlled by suspendm.
RF Chip ID.
The identifier of the RF chip.
Wireless LAN Network Interface Controller
17
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RTL8187L
Datasheet
Bytes
0Dh
Contents
CONFIG3
0Eh~13h
MAC Address
14h
15h
CONFIG1
16h~17h
18h
CRC
CONFIG2
19h
CONFIG4
1Ah~1Dh
ANA_PARM
1Eh
TESTR
1Fh
20h
OFDM_TxPower
OFDM_TxPower
OFDM_TxPower
OFDM_TxPower
OFDM_TxPower
OFDM_TxPower
OFDM_TxPower
OFDM_TxPower
OFDM_TxPower
OFDM_TxPower
10
OFDM_TxPower
11
OFDM_TxPower
12
CCK_TxPower1
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
Description
RTL8187L Configuration register 3.
Operational register FF59h.
MAC Address.
After the auto-load command or a hardware reset, the RTL8187L loads MAC
Addresses to IDR0~IDR5 of the I/O registers of the RTL8187L.
Reserved.
RTL8187L Configuration register 1.
Operational register FF52h.
16-bit CRC value of EEPROM content.
RTL8187L Configuration register 2.
Operational register FF53h.
RTL8187L Configuration register 4.
Operational register FF5Ah.
Analog Parameter for the RTL8187L.
Operational registers of the RTL8187L are from FF54h to FF57h.
Reserved. Do not change this field without Realtek approval.
RTL8187L Test Mode Register.
Operational register FF5Bh.
Reserved. Do not change this field without Realtek approval.
Reserved.
Transmit Power Level for 802.11a-defined channel_ID 36
(Center frequency=5180MHz).
Transmit Power Level for 802.11a-defined channel_ID 40
(Center frequency=5200MHz).
Transmit Power Level for 802.11a-defined channel_ID 44
(Center frequency=5220MHz).
Transmit Power Level for 802.11a-defined channel_ID 48
(Center frequency=5240MHz).
Transmit Power Level for 802.11a-defined channel_ID 52
(Center frequency=5260MHz).
Transmit Power Level for 802.11a-defined channel_ID 56
(Center frequency=5280MHz).
Transmit Power Level for 802.11a-defined channel_ID 60
(Center frequency=5300MHz).
Transmit Power Level for 802.11a-defined channel_ID 64
(Center frequency=5320MHz).
Transmit Power Level for 802.11a-defined channel_ID 149
(Center frequency=5745MHz).
Transmit Power Level for 802.11a-defined channel_ID 153
(Center frequency=5765MHz).
Transmit Power Level for 802.11a-defined channel_ID 157
(Center frequency=5785MHz).
Transmit Power Level for 802.11a-defined channel_ID 161
(Center frequency=5805MHz).
Transmit Power Level for 802.11b(g)-defined channel_ID 1
(center frequency=2412MHz).
Wireless LAN Network Interface Controller
18
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RTL8187L
Datasheet
Bytes
2Dh
Contents
CCK_TxPower2
2Eh
CCK_TxPower3
2Fh
CCK_TxPower4
30h
CCK_TxPower5
31h
CCK_TxPower6
32h-35h
ANA_PARM2
36h
CCK_TxPower11
37h
CCK_TxPower12
38h
CCK_TxPower13
39h
CCK_TxPower14
3Ah-6Bh
6Ch-79h
7Ah
Manufacture String
Product String
CCK_TxPower7
7Bh
CCK_TxPower8
7Ch
CCK_TxPower9
7Dh
CCK_TxPower10
Description
Transmit Power Level for 802.11b(g)-defined channel_ID 2
(center frequency=2417MHz).
Transmit Power Level for 802.11b(g)-defined channel_ID 3
(center frequency=2422MHz).
Transmit Power Level for 802.11b(g)-defined channel_ID 4
(center frequency=2427MHz).
Transmit Power Level for 802.11b(g)-defined channel_ID 5
(center frequency=2432MHz).
Transmit Power Level for 802.11b(g)-defined channel_ID 6
(center frequency=2437MHz).
Reserved: Do not change this field without Realtek approval.
Analog Parameter1 for the RTL8187L: Operational registers of the RTL8187L are
from FF60h to FF63h.
Transmit Power Level for 802.11b(g)-defined channel_ID 11
(center frequency=2462MHz).
Transmit Power Level for 802.11b(g)-defined channel_ID 12
(center frequency=2467MHz).
Transmit Power Level for 802.11b(g)-defined channel_ID 13
(center frequency=2472MHz).
Transmit Power Level for 802.11b(g)-defined channel_ID 14
(center frequency=2484MHz).
Manufacture String and Product String:Those bits specify both manufacturer’s
information and device’s information for the USB standard request.
Maximum two strings total length are 50 bytes.
Reserved.
Transmit Power Level for 802.11b(g)-defined channel_ID 7
(center frequency=2442MHz).
Transmit Power Level for 802.11b(g)-defined channel_ID 8
(center frequency=2447MHz).
Transmit Power Level for 802.11b(g)-defined channel_ID 9
(center frequency=2452MHz).
Transmit Power Level for 802.11b(g)-defined channel_ID 10
(center frequency=2457MHz).
Wireless LAN Network Interface Controller
19
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RTL8187L
Datasheet
9.1. EEPROM Registers Summary
Table 25. EEPROM Registers Summary
Address
Name
FF00hIDR0 – IDR5
FF05h
FF52h
FF53h
FF54hFF57h
CONFIG1
CONFIG2
Type
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
W*
LEDS1
LEDS1
LEDS0
LEDS0
LWACT
LWACT
LCK
W*
PAPE
_sign
PAPE
_sign
LWPTN
LWPTN
LANWake
R/W*
ANA_PARM R/W**
FF59h
CONFIG3
FF5Ah
CONFIG4
W*
W*
PAPE
_time
PAPE
_time
32-bit Read Write
PARM_En
PARM_En
Magic
Magic
LWPME
LWPME
8-bit Read Write
FF5Bh
TESTR
FF60hANA_PARM2 R/W
32-bit Read Write
FF63h
FFD8h
CONFIG5 R/W**
Note 1: Registers marked 'W*' can be written only if bits EEM1=EEM0=1.
Note 2: Registers marked 'W**' can be written only if bits EEM1:0=[1:1] and
CONFIG3= 0.
9.2. EEPROM Power Management Registers Summary
Table 26. EEPROM Power Management Registers Summary
Configuration
Space Offset
52h
53h
Name
Type
PMC
Bit7
Bit6
Bit5
Bit4
Bit3
Aux_I_b1 Aux_I_b0
DSI Reserved PMECLK
PME_D3cold PME_D3hot PME_D2 PME_D1 PME_D0
Wireless LAN Network Interface Controller
20
Bit2
Bit1
Bit0
D2
Version
D1 Aux_I_b2
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RTL8187L
Datasheet
10. USB Packet Buffering
The RTL8187L incorporates two independent FIFOs for transferring data to/from the system interface and
from/to the network. The FIFOs provide temporary storage of data, freeing the host system from the
real-time demands of the network.
The way in which the FIFOs are emptied and filled is controlled by the FIFO threshold values in the
Receive Configuration registers. These values determine how full or empty the FIFOs must be before the
device requests the bus. Once the RTL8187L requests the bus, it will attempt to empty or fill the FIFOs as
allowed by the respective MXDMA settings in the Transmit Configuration and Receive Configuration
registers.
10.1. Transmit Buffer Manager
The buffer management scheme used on the RTL8187L allows quick, simple, and efficient use of the frame
buffer memory. The buffer management scheme uses separate buffers and descriptors for packet
information. This allows effective transfers of data to the transmit buffer manager by simply transferring
the descriptor information to the transmit queue.
The Tx Buffer Manager DMA’s packet data from system memory and places it in the 3.5KB transmit FIFO,
and pulls data from the FIFO to send to the Tx MAC. Multiple packets may be present in the FIFO,
allowing packets to be transmitted with Short InterFrame (SIF) space. Additionally, once the RTL8187L
requests the bus, it will attempt to fill the FIFO as allowed by the MXDMA setting.
The Tx Buffer Manager process also supports priority queuing of transmit packets. It handles this by
drawing from two separate descriptor lists to fill the internal FIFO. If packets are available in the high
priority queues, they will be loaded into the FIFO before those of low priority.
10.2. Receive Buffer Manager
The Rx Buffer Manager uses the same buffer management scheme as used for transmits. The Rx Buffer
Manager retrieves packet data from the Rx MAC and places it in the 4KB receive data FIFO, and pulls data
from the FIFO for DMA to system memory. The receive FIFO is controlled by the FIFO threshold value in
RXFTH. This value determines the number of long words written into the FIFO from the MAC unit before
a DMA request for system memory occurs. Once the RTL8187L gets the bus, it will continue to transfer the
long words from the FIFO until the data in the FIFO is less than one long word, or has reached the end of the
packet, or the max DMA burst size is reached, as set in MXDMA.
10.3. Packet Recognition
The Rx packet filter and recognition logic allows software to control which packets are accepted, based on
destination address and packet type. Address recognition logic includes support for broadcast, multicast
hash, and unicast addresses. The packet recognition logic includes support for WOL and programmable
pattern recognition.
Wireless LAN Network Interface Controller
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RTL8187L
Datasheet
11. Functional Description
11.1. Transmit & Receive Operations
The RTL8187L supports a new descriptor-based buffer management that will significantly lower host CPU utilization. The
RTL8187L supports transmit descriptor and receive descriptor in memory. Each OUT packet contains 3-double-word transmit
descriptors and each IN packet contains 4-double-word receive descriptors.
11.1.1. Transmit
Tx Descriptor Format
Table 27. Tx Descriptor Format
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RSVD
RATE_
FALL
BACK_
LIMIT
(4 bits)
C M S
TXRATE
RTSRATE T O P
(4 bits)
(4 bits) S R L
E E C
N F P
N RSVD
Length (15 bits)
(3 bits)
AGC (8 bits)
Wireless LAN Network Interface Controller
9 8 7 6 5 4 3 2 1 0
TPKTSIZE (12 bits)
RTSDUR (16 bits)
RETRY_LIMIT (8 bits)
22
Offset 0
Offset 4
CWMAX CWMIN Offset 8
(4 bits)
(4 bits)
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RTL8187L
Datasheet
Table 28. Tx Status Descriptor
Offset#
Bit#
31:28
Symbol
RSVD
27:24
TXRATE
23
RTSEN
22:19
RTSRATE
18
CTSEN
Description
Reserved.
Tx Rate.
These four bits indicate the current frame’s transmission rate.
Bit 27
Bit 26
Bit 25
1Mbps
2Mbps
5.5Mbps
11Mbps
6Mbps
9Mbps
12Mbps
18Mbps
24Mbps
36Mbps
48Mbps
54Mbps
Reserved
All other combinations
Bit 24
RTS Enable.
Set to 1 indicates that an RTS/CTS handshake shall be performed at the
beginning of any frame exchange sequence where the frame is of type Data or
Management, the frame has a unicast address in the Address1 field, and the
length of the frame is greater than RTSThreshold.
RTS Rate.
These four bits indicate the RTS frame’s transmission rate before transmitting the
current frame and will be ignored if the RTSEN bit is set to 0.
Bit 22
Bit 21
Bit 20
Bit 19
1Mbps
2Mbps
5.5Mbps
11Mbps
6Mbps
9Mbps
12Mbps
18Mbps
24Mbps
36Mbps
48Mbps
54Mbps
Reserved
All other combinations
CTS Enable.
Both RTSEN and CTSEN set to 1 indicates that the CTS-to-Self protection
mechanism will be used.
Wireless LAN Network Interface Controller
23
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RTL8187L
Datasheet
Offset#
Bit#
17
16
15
14:12
11:0
TPKTSIZE
31
LENGEXT
30:16
Length
15:0
RTSDUR
31:28
27:25
24
23:16
15:8
7:4
3:0
RATE_FALL
BACK_LIMIT
RSVD
ANTENNA
AGC
RETRY_LIMIT
CWMAX
CWMIN
Symbol
MOREFRAG
Description
More Fragment.
This bit is set to 1 in all data type frames that have another fragment of the current
packet to follow.
SPLCP
Short Physical Layer Convergence Protocol format.
When set, this bit indicates that a short PLCP preamble will be added to the
header before transmitting the frame.
NO_ENCRYPT No Encryption.
This packet will be sent out without encryption even if Tx encryption is enabled.
RSVD
Reserved.
Transmit Packet Size.
This field indicates the number of bytes required to transmit the frame.
Length Extension.
This bit is used to supplement the Length field (bits 30:16, offset 4). This bit will
be ignored if the TXRATE is set to 1Mbps, 2Mbps, or 5.5Mbps.
PLCP Length.
The PLCP length field indicates the number of microseconds required to transmit
the frame.
RTS Duration.
These bits indicate the RTS frame’s duration field before transmitting the current
frame and will be ignored if the RTSEN bit is set to 0.
Data Rate Auto Fallback Limit.
Reserved.
Tx Antenna.
Tx AGC.
Retry Count Limit.
Maximum Contention Window.
Minimum Contention Window.
Wireless LAN Network Interface Controller
24
Track ID JATR-1076-21 Rev. 1.2
RTL8187L
Datasheet
11.1.2. Receive
Rx Descriptor Format
Table 29. Rx Descriptor Format
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7
RSVD
RSVD (6 bits)
R M P B R P C
S RXRATE S A A A E W R
V (4 bits) V R M R S R C
M 3
G 2
AGC (8 bits)
6 5 4 3 2 1 0
Offset 0
Frame_Length (12 bits)
Offset 4
RSSI
(7 bits)
TSFTL
TSFTH
SQ
(8 bits)
Offset 8
Offset 12
Table 30. Rx Status Descriptor
Offset#
Bit#
31:28
Symbol
RSVD
Description
Reserved.
27
DMAF
26
FOVF
25
SPLCP
24
RSVD
RX DMA Fail.
When set, this packet will be dropped by software.
FIFO Overflow.
When set, this bit indicates that the receive FIFO was exhausted before this
packet was fully received.
Short Physical Layer Convergence Protocol format.
When set, this bit indicates that a short PLCP preamble was added to the current
received frame.
Reserved.
Wireless LAN Network Interface Controller
25
Track ID JATR-1076-21 Rev. 1.2
RTL8187L
Datasheet
Offset#
Bit#
23:20
Symbol
RXRATE
19
18
RSVD
MAR
17
PAM
16
BAR
15
RES
14
PWRMGT
13
CRC32
12
ICV
11:0
Frame_Length
Description
Rx Rate.
These four bits indicate the current frame’s receiving rate.
Bit 23
Bit 22
Bit 21
Bit 20
1Mbps
2Mbps
5.5Mbps
11Mbps
6Mbps
9Mbps
12Mbps
18Mbps
24Mbps
36Mbps
48Mbps
54Mbps
Reserved
All other combinations
Reserved.
Multicast Address Packet Received.
When set, this bit indicates that a multicast packet was received.
Physical Address Matched.
When set, this bit indicates that the destination address of this Rx packet matches
the value in the RTL8187L’s ID registers.
Broadcast Address Received.
When set, this bit indicates that a broadcast packet was received. BAR and MAR
will not be set simultaneously.
Receive Error.
Valid if DMAF=0
Receive Power Management Packet.
When set, this bit indicates that the Power Management bit is set on the received
packet.
CRC32 Error.
When set, this bit indicates that a CRC32 error has occurred on the received
packet. A CRC32 packet can be received only when RCR_ACRC32 is set.
Integrity Check Value Error.
When set, this bit indicates that an ICV error has occurred on the received packet.
A ICV packet can be received only when RCR_AICV is set.
This bit indicates the received packet length including CRC32, in bytes.
31:26
25
24
23:16
15
RSVD
WAKEUP
DECRYPTED
AGC
ANTENNA
Reserved.
The received packet is a unicast wakeup packet.
The received packet has been decrypted.
The AGC of the received packet.
The received packet is received through this antenna.
14:8
RSSI
Received Signal Strength Indicator.
The RSSI is a measure of the RF energy received by the PHY.
Wireless LAN Network Interface Controller
26
Track ID JATR-1076-21 Rev. 1.2
RTL8187L
Datasheet
Offset#
Bit#
7:0
Symbol
SQ
31:0
TSFTL
Description
Signal Quality.
The SQ is a measure of the quality of BAKER code lock, providing an effective
measure during the full reception of a PLCP preamble and header.
A snapshot of the TSFTR’s least significant 32 bits.
12
31:0
TSFTH
A snapshot of the TSFTR’s most significant 32 bits.
11.2. Loopback Operation
Loopback mode is normally used to verify that the logic operations have performed correctly. In loopback
mode, the RTL8187L takes frames from the transmit descriptor and transmits them up to internal Rx logic.
The loopback function does not apply to an external PHYceiver.
11.3. Tx Encapsulation (With RTL8187L Internal Baseband
Processor)
While operating in Tx mode, the RTL8187L encapsulates the frames that it transmits according to the
Differential Binary Phase Shift Keying (DBPSK) for 1Mbps, Differential Quaternary Phase Shift Keying
(DQPSK) for 2Mbps, and Complementary Code Keying (CCK) for 5.5Mbps and 11Mbps modulators. The
changes to the original packet data are as follows:
1. The PLCP preamble is always transmitted as the DBPSK waveform and used by the receiver to achieve
initial PN synchronization.
2. The PLCP header can be configured to be either DBPSK or DQPSK and includes the necessary data
fields of the communications protocol to establish the physical layer link.
3. The MAC frame can be configured for DBPSK, DQPSK, or CCK.
11.4. Rx Decapsulation (With RTL8187L Internal Baseband
Processor)
The RTL8187L continuously monitors the network when reception is enabled. When activity is recognized
it starts to process the incoming data. After detecting receive activity on the channel, the RTL8187L starts
to process the PLCP preamble and header based on the mode of operation.
The RTL8187L checks CRC16 and CRC32, then reports if CRC16 or CRC32 has errors. When using the
40-bit WEP and 104-bit WEP module for decryption, the RTL8187L also checks the Integrity Check Value
(ICV) and reports if the ICV has errors.
Wireless LAN Network Interface Controller
27
Track ID JATR-1076-21 Rev. 1.2
RTL8187L
Datasheet
11.5. LED Functions
The RTL8187L supports 2 LED signals in 4 configurable operation modes. The following sections describe
the different LED actions.
11.5.1. Link Monitor
The Link Monitor senses the link integrity. Whenever link status is established, the specific link LED pin is
driven low.
11.5.2. Infrastructure Monitor
The Infrastructure Monitor senses the link integrity of an Infrastructure network. Whenever Link OK in
Infrastructure network status is established, the specific Infrastructure LED pin is driven low.
11.5.3. Rx LED
Blinking of the Rx LED indicates that receive activity is occurring.
Power On
LED = High
Receiving
Packet?
No
Yes
LED = High for (100 +- 10) ms
LED = Low for (12 +- 2) ms
Figure 3. Rx LED
Wireless LAN Network Interface Controller
28
Track ID JATR-1076-21 Rev. 1.2
RTL8187L
Datasheet
11.5.4. Tx LED
Blinking of the Tx LED indicates that transmit activity is occurring.
Power On
LED = High
Transmitting
Packet?
No
Yes
LED = High for (100 +- 10) ms
LED = Low for (12 +- 2) ms
Figure 4. Tx LED
11.5.5. Tx/Rx LED
Blinking of the Tx/Rx LED indicates that both transmit and receive activity is occurring.
Power On
LED = High
Tx/Rx Packet?
No
Yes
LED = High for (100 +- 10) ms
LED = Low for (12 +- 2) ms
Figure 5. Tx/Rx LED
Wireless LAN Network Interface Controller
29
Track ID JATR-1076-21 Rev. 1.2
RTL8187L
Datasheet
11.5.6. LINK/ACT LED
Blinking of the LINK/ACT LED indicates that the RTL8187L is linked and operating properly. If this LED
is high for extended periods it indicates that a link problem exists.
Power On
LED = High
No
Link?
Yes
LED = Low
No
Tx/Rx packet?
Yes
LED = High for (100 +- 10) ms
LED = Low for (12 +- 2) ms
Figure 6. LINK/ACT LED
Wireless LAN Network Interface Controller
30
Track ID JATR-1076-21 Rev. 1.2
RTL8187L
Datasheet
12. Application Diagram
Main/Aux. Power
Regulators
Power 3.3V, 1.8V
LED
External
ROM/RAM
Power 3.3V, 1.8V
Power 3.3V, 1.8V
RTL8187L
Antenna
External
RF
Devices
Base
Band
40MHz
Clock
D+
MAC
SIE
EEPROM
D-
Power 3.3V
Figure 7. Application Diagram
Wireless LAN Network Interface Controller
31
Track ID JATR-1076-21 Rev. 1.2
RTL8187L
Datasheet
13. Electrical Characteristics
13.1. Temperature Limit Ratings
Table 31. Temperature Limit Ratings
Parameter
Storage temperature
Operating temperature
Minimum
-55
-10
Maximum
+125
70
Units
°C
°C
13.2. DC Characteristics
Table 32. DC Characteristics
Symbol
VDD33
VDD18
Voh
Vol
Vih
Vil
Iin
Ioz
Icc
Parameter
Conditions
Minimum
3.3V Supply Voltage
3.0
1.8V Supply Voltage
1.7
Minimum High Level Output
Ioh = -8mA
0.9 * Vcc
Voltage
Maximum Low Level Output
Iol = 8mA
Voltage
Minimum High Level Input Voltage
0.5 * Vcc
Maximum Low Level Input Voltage
-0.5
Input Current
Vin =Vcc or GND
-1.0
Tri-State Output Leakage Current
Vout =Vcc or GND
-10
Average Operating Supply Current
Iout = 0mA,
Wireless LAN Network Interface Controller
32
Typical
3.3
1.8
Maximum
3.6
1.9
Vcc
Units
0.1 * Vcc
Vcc+0.5
0.3 * Vcc
1.0
10
460
µA
µA
mA
Track ID JATR-1076-21 Rev. 1.2
RTL8187L
Datasheet
13.3. AC Characteristics
13.3.1. Serial EEPROM Interface Timing (93C46(64*16)/93C56(128*16))
EESK
EECS
EEDI
tcs
(Read)
An
A2
A1
A0
(Read)
EEDO High Impedance
Dn
D1
D0
EESK
EECS
EEDI
tcs
(Write)
An
...
A0
Dn
...
D0
(Write)
EEDO High Impedance
BUSY
READY
twp
tsk
EESK
tskh
EECS
tcss
tdis
tcsh
tskl
tdih
EEDI
tdos
tdoh
EEDO (Read)
EEDO
tsv
STATUS VALID
(Program)
Figure 8. Serial EEPROM Interface Timing
Table 33. EEPROM Access Timing Parameters
Symbol
tcs
twp
tsk
tskh
tskl
tcss
tcsh
tdis
tdih
tdos
tdoh
tsv
Parameter
Minimum CS Low Time
Write Cycle Time
SK Clock Cycle Time
SK High Time
SK Low Time
CS Setup Time
CS Hold Time
DI Setup Time
DI Hold Time
DO Setup Time
DO Hold Time
CS to Status Valid
Wireless LAN Network Interface Controller
9346/9356
9346/9356
9346/9356
9346/9356
9346/9356
9346/9356
9346/9356
9346/9356
9346/9356
9346/9356
9346/9356
9346/9356
33
Minimum
1000/250
Typical
Maximum
10/10
4/1
1000/500
1000/250
200/50
0/0
400/50
400/100
2000/500
2000/500
1000/500
Units
ns
ms
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
Track ID JATR-1076-21 Rev. 1.2
RTL8187L
Datasheet
14. Mechanical Dimensions
See the Mechanical Dimensions notes on the next page.
Wireless LAN Network Interface Controller
34
Track ID JATR-1076-21 Rev. 1.2
RTL8187L
Datasheet
14.1. Mechanical Dimensions Notes
Symbol
A1
A2
D1
E1
L1
Θ
Dimension in inch
Min Typical Max
0.063
0.002
0.053 0.055 0.057
0.005 0.007 0.009
0.004
0.006
0.624 0.630 0.636
0.547 0.551 0.555
0.016 BSC
0.624 0.630 0.636
0.547 0.551 0.555
0.018 0.024 0.030
0.039 REF
0°
3.5°
7°
Dimension in
Min Typical
0.05
1.35
1.40
0.13
0.18
0.09
15.85 16.00
13.90 14.00
0.40 BSC
15.85 16.00
13.90 14.00
0.45
0.60
1.00 REF
0°
3.5°
Wireless LAN Network Interface Controller
Note:
1.Dimension b does not include dambar
protrusion/intrusion.
2.Controlling dimension: Millimeter
3.General appearance spec. should be based
on final visual inspection spec.
mm
Max
1.60
1.45
0.23
0.20
16.15
14.10
TITLE: 128LD LQFP ( 14x14x1.4 mm*2 ) PACKAGE OUTLINE
-CU L/F, FOOTPRINT 2.0 mm
LEADFRAME MATERIAL:
APPROVE
DOC. NO. 530-ASS-P004
VERSION 1
PAGE
OF
CHECK
DWG NO. LQ128 - 2
DATE
MAY. 13.2002
REALTEK SEMICONDUCTOR CORP.
16.15
14.10
0.75
7°
35
Track ID JATR-1076-21 Rev. 1.2
RTL8187L
Datasheet
15. Ordering Information
Table 34. Ordering Information
Part Number
RTL8187L
RTL8187L-LF
Package
128-pin LQFP
RTL8187L with Lead (Pb)-Free package
Status
MP
MP
Realtek Semiconductor Corp.
Headquarters
No. 2, Industry East Road IX, Science-based
Industrial Park, Hsinchu, 300, Taiwan, R.O.C.
Tel: 886-3-5780211 Fax: 886-3-5776047
www.realtek.com.tw
Wireless LAN Network Interface Controller
36
Track ID JATR-1076-21 Rev. 1.2
Federal Communication Commission Interference Statement
This equipment has been tested and found to comply with the limits for a Class B digital
device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide
reasonable protection against harmful interference in a residential installation. This
equipment generates, uses and can radiate radio frequency energy and, if not installed and
used in accordance with the instructions, may cause harmful interference to radio
communications. However, there is no guarantee that interference will not occur in a
particular installation. If this equipment does cause harmful interference to radio or
television reception, which can be determined by turning the equipment off and on, the
user is encouraged to try to correct the interference by one of the following measures:
Reorient or relocate the receiving antenna.
Increase the separation between the equipment and receiver.
Connect the equipment into an outlet on a circuit different from that to which the
receiver is connected.
Consult the dealer or an experienced radio/TV technician for help.
FCC Caution: Any changes or modifications not expressly approved by the party
responsible for compliance could void the user's authority to operate this equipment.
This device complies with Part 15 of the FCC Rules. Operation is subject to the following
two conditions: (1) This device may not cause harmful interference, and (2) this device
must accept any interference received, including interference that may cause undesired
operation.
This device and its antenna(s) must not be co-located or operating in conjunction with
any other antenna or transmitter.
This device is intended only for OEM integrators under the following conditions:
OEM integrator is still responsible for testing their end product for any additional
compliance requirements required with this module installed (for example, digital device
emissions, PC peripheral requirements, etc.).
IMPORTANT NOTE: In the event that these conditions can not be met (for example
certain laptop configurations or co-location with another transmitter), then the FCC
authorization is no longer considered valid and the FCC ID can not be used on the final
product. In these circumstances, the OEM integrator will be responsible for re-evaluating
the end product (including the transmitter) and obtaining a separate FCC authorization.
Without Co-located
The antenna (s) used for this transmitter must not be co-located or operating in
conjunction with any other antenna or transmitter.
Modular Approval
OEM integrator is still responsible for testing their end product for any additional
compliance requirements required with this module installed (for example, digital device
emissions, PC peripheral requirements, etc.).
IMPORTANT NOTE: In the event that these conditions can not be met (for example
certain laptop configurations or co-location with another transmitter), then the FCC
authorization is no longer considered valid and the FCC ID can not be used on the final
product. In these circumstances, the OEM integrator will be responsible for re-evaluating
the end product (including the transmitter) and obtaining a separate FCC authorization.
Modular OEM Integrator Notice
End Product Labeling
This transmitter module is authorized only for use in device where the antenna may be
installed such that 20 cm may be maintained between the antenna and users. The final
end product must be labeled in a visible area with the following: “Contains TX FCC ID:
TX2-RTL8187”.
IC Radiation Exposure Statement:
"Operation is subject to the following two conditions: (1) this device may not cause
interference, and (2) this device must accept any interference, including interference that
may cause undesired operation of the device."
OEM integrator is still responsible for testing their end product for any additional
compliance requirements required with this module installed (for example, digital device
emissions, PC peripheral requirements, etc.).
IMPORTANT NOTE: In the event that these conditions can not be met (for example
certain laptop configurations or co-location with another transmitter), then the FCC
authorization is no longer considered valid and the FCC ID can not be used on the final
product. In these circumstances, the OEM integrator will be responsible for re-evaluating
the end product (including the transmitter) and obtaining a separate FCC authorization.
This transmitter module is authorized only for use in device where the antenna may be
installed such that 20 cm may be maintained between the antenna and users. The final
end product must be labeled in a visible area with the following: “Contains TX IC ID:
6317A–RTL8187”.
This device has been designed to operate with an antenna having a maximum gain of
[3.00] dBi. Antenna having a higher gain is strictly prohibited per regulations of
Industry Canada. The required antenna impedance is 50 ohms."
List of antennas below:
Ant. Type PIFA
1.
Connector IPEX
Ant. Type PIFA
3.
Connector IPEX
Ant. Type PIFA
5.
Connector IPEX
Ant. Type PIFA
7.
Connector IPEX
Ant. Type PIFA
9.
Connector IPEX
11 Ant. Type PIFA
. Connector IPEX
13 Ant. Type PIFA
. Connector IPEX
15 Ant. Type PIFA
. Connector IPEX
17 Ant. Type PIFA
. Connector IPEX
19 Ant. Type PIFA
. Connector IPEX
21 Ant. Type PIFA
. Connector IPEX
PK
Gain(dBi)
Model
DQ661500301
No.
PK
2.39
Gain(dBi)
Model
AR830WIPI02A
No.
PK
0.78
Gain(dBi)
WDAN-QMA6002
Model
-DF
No.
PK
0.3
Gain(dBi)
Model
AAFJ5050002LF0
No.
PK
1.97
Gain(dBi)
Model
ARMK8WIPI02A
No.
PK
2.37
Gain(dBi)
AAFA5050004LQ
Model
No.
PK
2.57
Gain(dBi)
Model
B0785028000003
No.
PK
2.55
Gain(dBi)
Model
AR621WIPI02D
No.
PK
2.49
Gain(dBi)
Model
ARK8MWIPI01B
No.
PK
2.86
Gain(dBi)
AAFQ5050002LK
Model
No.
PK
0.74
Gain(dBi)
Model
MA6002
No.
Ant. Type
2.
PK
PIFA Gain(dBi) 2.32
Connector IPEX Model No. MA6001
Ant. Type
4.
PK
PIFA Gain(dBi) 2.11
Connector IPEX Model No. AR320WIPI02B
Ant. Type
6.
PK
PIFA Gain(dBi) 1.1
Connector IPEX Model No. DQ661500115
Ant. Type
8.
PK
PIFA Gain(dBi) 2.57
Connector IPEX Model No. AR620WIPI02C
PK
10 Ant. Type PIFA Gain(dBi) 1
. Connector IPEX Model No. ARMK8WIPI02A
PK
12 Ant. Type PIFA Gain(dBi) 2.11
. Connector IPEX Model No. AR320WIPI01B
PK
14 Ant. Type PIFA Gain(dBi) 2.21
. Connector IPEX Model No. AR330WIPI01D
PK
16 Ant. Type PIFA Gain(dBi) 2.48
. Connector IPEX Model No. ARW62WIPI01G
PK
18 Ant. Type PIFA Gain(dBi) 0.46
. Connector IPEX Model No. AAFQ5050001L
K0
PK
20 Ant. Type PIFA Gain(dBi) 2.45
. Connector IPEX Model No. B012502800000
PK
22 Ant. Type PIFA Gain(dBi) 0.03
. Connector IPEX Model No. W340UA1
To reduce potential radio interference to other users, the antenna type and its gain
should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not
more than that permitted for successful communication.
Installation Guide__
Realtek RTL8187 + RTL8225-VF (Z2)
802.11 b/g miniCard
Date: 2006/06/06
Version: 1.0
This document is subject to change without notice. The document
contains Realtek confidential information and must not be disclosed
to any third party without appropriate NDA.
Installation Description
This module is to be installed only by the professionals.
When IRF303JU/IRF303U2is installed in a product, we shall consider the following points;
1. Since RTL8187 miniCard owns its FCC ID Number/IC Number, we shall affix an exterior
label on the outside of the product if the FCC ID/IC Number is not visible. The exterior label
shall use wording such as either “Contains Transmitter Module FCC ID: TX2-RTL8187/IC
Number: 6317A-RTL8187”or “Contains FCC ID: TX2-RTL8187/ IC Number: 6317A-RTL8187”.
2. RTL8187 miniCard complies with requirements of sub-sections 15.203, 15.205, 15.207,
15.247 and 15.407 in FCC Rules Part 15. We shall installRTL8187 miniCard in accordance
with their requirements. RTL8187 miniCard complies with requirements of the sub-section
2.1091. When installers install RTL8187 miniCard into a product, they shall ensure that the
public is not exposedto radio frequency energy levels in excess of the Commission’s
guidelines in accordance with the sub-section 15.247(e)(i) and 15.407(f) in FCC Rules Part 15.

---

Source Exif Data:

File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.5
Linearized                      : No
Page Mode                       : UseOutlines
XMP Toolkit                     : 3.1-701
About                           : uuid:98da98bd-5fb9-4dde-a09a-97d231fc0e67
Producer                        : Acrobat Distiller 6.0.1 (Windows)
Creator Tool                    : Acrobat PDFMaker 6.0 for Word
Modify Date                     : 2006:08:08 10:03:40+08:00
Create Date                     : 2005:09:05 18:42:58+08:00
Metadata Date                   : 2006:08:08 10:03:40+08:00
Document ID                     : uuid:cdad0d8b-b140-4469-a294-b4a7d7860838
Instance ID                     : uuid:8a14c5e5-55d0-4bf3-8f66-2030ba6ff14b
Format                          : application/pdf
Title                           : Realtek RTL8187L DataSheet 1.2
Creator                         : Realtek RTL8187L DataSheet 1.2
Description                     : Realtek RTL8187L DataSheet 1.2
Has XFA                         : No
Page Count                      : 47
Page Layout                     : SinglePage
Subject                         : Realtek RTL8187L DataSheet 1.2
Author                          : Realtek RTL8187L DataSheet 1.2
Keywords                        : Realtek, RTL8187L, DataSheet, 1.2

EXIF Metadata provided by EXIF.tools