Realtek Semiconductor RTL8187B 802.11b/g RTL8187B miniCard User Manual Realtek RTL8187B DataSheet 1 0

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RTL8187B-GR
WIRELESS LAN NETWORK INTERFACE
CONTROLLER
DATASHEET
Rev. 1.0
09 October 2006
Track ID: JATR-1076-21
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com.tw
RTL8187B
Datasheet
COPYRIGHT
©2006 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied,
including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in
this document or in the product described in this document at any time. This document could include
technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are
trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document is intended for the software engineer’s reference and provides detailed programming
information.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide. In that event, please contact your
Realtek representative for additional information that may help in the development process.
REVISION HISTORY
Revision
1.0
Release Date
2006/10/09
Wireless LAN Network Interface Controller
Summary
First release.
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RTL8187B
Datasheet
Table of Contents
1.
GENERAL DESCRIPTION ...............................................................................................................................................1
2.
FEATURES ..........................................................................................................................................................................2
3.
SYSTEM APPLICATIONS ................................................................................................................................................3
4.
BLOCK DIAGRAM ............................................................................................................................................................4
5.
PIN ASSIGNMENTS...........................................................................................................................................................5
5.1.
6.
GREEN PACKAGE AND VERSION IDENTIFICATION ...........................................................................................................5
PIN DESCRIPTIONS ..........................................................................................................................................................6
6.1. USB TRANSCEIVER INTERFACE ......................................................................................................................................6
6.2. EEPROM INTERFACE .....................................................................................................................................................6
6.3. POWER PINS ....................................................................................................................................................................6
6.4. LED INTERFACE..............................................................................................................................................................7
6.5. ATTACHMENT UNIT INTERFACE ......................................................................................................................................7
6.5.1.
RTL8225 RF Chipset ..............................................................................................................................................7
6.5.2.
RTL8255 RF Chipset ..............................................................................................................................................8
6.6. CLOCK AND OTHER PINS .................................................................................................................................................9
7.
CPU ACCESS TO ENDPOINT DATA............................................................................................................................10
7.1.
7.2.
8.
CONTROL TRANSFER .....................................................................................................................................................10
BULK TRANSFER ...........................................................................................................................................................10
USB REQUEST ..................................................................................................................................................................11
8.1.
8.2.
8.3.
8.4.
8.5.
8.6.
8.7.
8.8.
8.9.
8.10.
8.11.
8.12.
8.13.
8.14.
8.15.
8.16.
9.
GET DESCRIPTOR-DEVICE .............................................................................................................................................11
GET DESCRIPTOR-DEVICE QUALIFIER (HIGH SPEED)....................................................................................................11
GET DESCRIPTOR-CONFIGURATION ..............................................................................................................................12
GET DESCRIPTOR-STRING INDEX 0 ...............................................................................................................................13
GET DESCRIPTOR-STRING INDEX 1 ...............................................................................................................................13
GET DESCRIPTOR-STRING INDEX 2 ...............................................................................................................................13
GET DESCRIPTOR-STRING INDEX 3 ...............................................................................................................................14
GET DESCRIPTOR-STRING INDEX 4 ...............................................................................................................................14
GET DESCRIPTOR-STRING INDEX 5 ...............................................................................................................................15
GET DESCRIPTOR-OTHER SPEED CONFIGURATION....................................................................................................15
SET ADDRESS ............................................................................................................................................................16
SET INTERFACE 0 ......................................................................................................................................................16
SET FEATURE DEVICE ...............................................................................................................................................16
CLEAR FEATURE DEVICE ..........................................................................................................................................17
SET CONFIG 0............................................................................................................................................................17
SET CONFIG 1............................................................................................................................................................17
EEPROM (93C46 OR 93C56) CONTENTS ....................................................................................................................18
9.1.
9.2.
10.
EEPROM REGISTERS SUMMARY ..................................................................................................................................21
EEPROM POWER MANAGEMENT REGISTERS SUMMARY .............................................................................................21
USB PACKET BUFFERING ........................................................................................................................................22
10.1.
10.2.
TRANSMIT BUFFER MANAGER ..................................................................................................................................22
RECEIVE BUFFER MANAGER .....................................................................................................................................22
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10.3.
11.
PACKET RECOGNITION ..............................................................................................................................................22
FUNCTIONAL DESCRIPTION ..................................................................................................................................23
11.1.
TRANSMIT & RECEIVE OPERATIONS..........................................................................................................................23
11.1.1. Transmit ...............................................................................................................................................................23
11.1.2. Receive .................................................................................................................................................................27
11.2.
RX COMMAND ...........................................................................................................................................................29
11.3.
LOOPBACK OPERATION .............................................................................................................................................29
11.4.
TX ENCAPSULATION (WITH RTL8187B INTERNAL BASEBAND PROCESSOR)............................................................29
11.5.
RX DECAPSULATION (WITH RTL8187B INTERNAL BASEBAND PROCESSOR) ...........................................................30
11.6.
QOS FUNCTIONS .......................................................................................................................................................30
11.7.
CONTENTION-BASED ADMISSION CONTROL FUNCTIONS ...........................................................................................30
11.8.
DURATION FIELD PROCESSING ..................................................................................................................................31
11.9.
LED FUNCTIONS .......................................................................................................................................................31
11.9.1. Link Monitor.........................................................................................................................................................31
11.9.2. Infrastructure Monitor .........................................................................................................................................31
11.9.3. Rx LED .................................................................................................................................................................32
11.9.4. Tx LED .................................................................................................................................................................33
11.9.5. Tx/Rx LED ............................................................................................................................................................33
11.9.6. LINK/ACT LED ....................................................................................................................................................34
12.
APPLICATION DIAGRAM .........................................................................................................................................35
13.
ELECTRICAL CHARACTERISTICS........................................................................................................................36
13.1.
TEMPERATURE LIMIT RATINGS .................................................................................................................................36
13.2.
DC CHARACTERISTICS ..............................................................................................................................................36
13.3.
AC CHARACTERISTICS ..............................................................................................................................................37
13.3.1. Serial EEPROM Interface Timing (93C46(64*16)/93C56(128*16))...................................................................37
14.
MECHANICAL DIMENSIONS ...................................................................................................................................38
14.1.
15.
MECHANICAL DIMENSIONS NOTES............................................................................................................................39
ORDERING INFORMATION .....................................................................................................................................39
List of Tables
TABLE 1. USB TRANSCEIVER INTERFACE .....................................................................................................................................6
TABLE 2. EEPROM INTERFACE ....................................................................................................................................................6
TABLE 3. POWER PINS ...................................................................................................................................................................6
TABLE 4. LED INTERFACE.............................................................................................................................................................7
TABLE 5. ATTACHMENT UNIT INTERFACE .....................................................................................................................................7
TABLE 6. RTL8255 RF CHIPSET....................................................................................................................................................8
TABLE 7. CLOCK AND OTHER PINS ................................................................................................................................................9
TABLE 8. GET DESCRIPTOR-DEVICE ............................................................................................................................................11
TABLE 9. GET DESCRIPTOR- DEVICE QUALIFIER (HIGH SPEED) ..................................................................................................11
TABLE 10. GET DESCRIPTOR-CONFIGURATION .............................................................................................................................12
TABLE 11. GET DESCRIPTOR-STRING INDEX 0 ..............................................................................................................................13
TABLE 12. GET DESCRIPTOR-STRING INDEX 1 ..............................................................................................................................13
TABLE 13. GET DESCRIPTOR-STRING INDEX 2 ..............................................................................................................................13
TABLE 14. GET DESCRIPTOR-STRING INDEX 3 ..............................................................................................................................14
TABLE 15. GET DESCRIPTOR-STRING INDEX 4 ..............................................................................................................................14
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TABLE 16. GET DESCRIPTOR-STRING INDEX 5 ..............................................................................................................................15
TABLE 17. GET DESCRIPTOR-OTHER SPEED CONFIGURATION ......................................................................................................15
TABLE 18. SET ADDRESS ..............................................................................................................................................................16
TABLE 19. SET INTERFACE 0 .........................................................................................................................................................16
TABLE 20. SET FEATURE DEVICE ..................................................................................................................................................16
TABLE 21. CLEAR FEATURE DEVICE .............................................................................................................................................17
TABLE 22. SET CONFIG 0 ..............................................................................................................................................................17
TABLE 23. SET CONFIG 1 ..............................................................................................................................................................17
TABLE 24. EEPROM (93C46 OR 93C56) CONTENTS ....................................................................................................................18
TABLE 25. EEPROM REGISTERS SUMMARY ................................................................................................................................21
TABLE 26. EEPROM POWER MANAGEMENT REGISTERS SUMMARY ............................................................................................21
TABLE 27. TX DESCRIPTOR FORMAT ............................................................................................................................................23
TABLE 28. TX STATUS DESCRIPTOR ..............................................................................................................................................24
TABLE 29. RX DESCRIPTOR FORMAT ............................................................................................................................................27
TABLE 30. RX STATUS DESCRIPTOR..............................................................................................................................................28
TABLE 31. TX BEACON INTERRUPT ...............................................................................................................................................29
TABLE 32. TX CLOSE DESCRIPTOR................................................................................................................................................29
TABLE 33. TEMPERATURE LIMIT RATINGS ....................................................................................................................................36
TABLE 34. DC CHARACTERISTICS .................................................................................................................................................36
TABLE 35. EEPROM ACCESS TIMING PARAMETERS ....................................................................................................................37
TABLE 36. ORDERING INFORMATION ............................................................................................................................................39
List of Figures
FIGURE 1.
FIGURE 2.
FIGURE 3.
FIGURE 4.
FIGURE 5.
FIGURE 6.
FIGURE 7.
FIGURE 8.
BLOCK DIAGRAM ..........................................................................................................................................................4
PIN ASSIGNMENTS.........................................................................................................................................................5
RX LED ......................................................................................................................................................................32
TX LED ......................................................................................................................................................................33
TX/RX LED ................................................................................................................................................................33
LINK/ACT LED.........................................................................................................................................................34
APPLICATION DIAGRAM ..............................................................................................................................................35
SERIAL EEPROM INTERFACE TIMING ........................................................................................................................37
Wireless LAN Network Interface Controller
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RTL8187B
Datasheet
1. General Description
The Realtek RTL8187B is a low-profile highly integrated cost-effective Wireless LAN USB 2.0 network
interface controller that integrates a USB 2.0 PHY, SIE (Serial Interface Engine), 8051 MCU, a Wireless
LAN MAC, and a Direct Sequence Spread Spectrum/OFDM baseband processor onto one chip. It provides
USB high speed (480Mbps), and full speed (12Mbps), and supports 9 endpoints for transfer pipes. To
reduce protocol overhead, the RTL8187B supports Short InterFrame Space (SIFS) burst mode to send
packets back-to-back. A protection mechanism prevents collisions among 802.11b nodes. The RTL8187B
fully complies with IEEE 802.11a/b/g, WMM, 802.11e, and CCX specifications.
To reduce protocol overhead, the RTL8187B supports Short InterFrame Space (SIFS) burst mode to send
packets back-to-back. A protection mechanism prevents collisions among 802.11b nodes.
Direct Sequence Spread Spectrum (DSSS), Complementary Code Keying (CCK), and Orthogonal
Frequency Division Multiplexing (OFDM) baseband processing are implemented to support all IEEE
802.11a, 802.11b, and 802.11g data rates. Differential phase shift keying modulation schemes, DBPSK and
DQPSK with data scrambling capability, are available, along with complementary code keying to provide
data rates of 1, 2, 5.5, and 11Mbps, with long or short preamble. A high-speed Fast Fourier Transform
(FFT)/Inverse Fast Fourier Transform (IFFT), combined with BPSK, QPSK, 16QAM and 64QAM
modulation of the individual sub-carriers, provides data rates of 6, 9, 12, 18, 24, 36, 48 and 54Mbps, with
rate-compatible punctured convolutional coding with a coding rate of 1/2, 2/3, and 3/4.
An enhanced signal detector, an adaptive frequency domain equalizer, and a soft-decision Viterbi decoder
are built-in to alleviate severe multipath effects. Efficient IQ-imbalance calibration, DC offset, phase noise,
frequency offset, and timing offset compensation reduce radio frequency front-end impairments. Selectable
digital transmit and receiver FIR filters are provided to meet the requirements of transmit spectrum masks,
and to reject adjacent channel interference, respectively. Both in the transmitter and receiver,
programmable scaling in the digital domain trades the quantization noise against the increased probability
of clipping. Robust signal detection, symbol boundary detection, and channel estimation perform well at
the minimum sensitivity.
The RTL8187B supports fast receiver Automatic Gain Control (AGC) and antenna diversity functions, and
an adaptive transmit power control function to obtain better performance in the analog portions of the
transceiver. It also has on-chip digital-to-analog converters and analog-to-digital converters for analog I
and Q inputs and outputs, transmit TSSI and receiver RSSI inputs, and transmit and receiver AGC outputs.
The RTL8187B keeps network maintenance costs low and eliminates usage barriers. The RTL8187B is
highly integrated and requires no ‘glue’ logic or external memory.
The installation for antenna is fixed as vertical polarization.
Wireless LAN Network Interface Controller
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Datasheet
2. Features
„
128-Pin LQFP with ‘Green’ package
„
State machine implementation without
external memory (RAM, flash) requirement
„
Complies with IEEE 802.11a/b/g standards
„
Supports descriptor-based buffer
management
„
Integrated Wireless LAN MAC and Direct
Sequence Spread Spectrum/OFDM
Baseband Processor in one chip
„
Enhanced signal detector, adaptive frequency
domain equalizer, and soft-decision Viterbi
decoder to alleviate severe multipath effects
„
OFDM with BPSK, QPSK, 16QAM and
64QAM modulations and demodulations
supported with rate compatible punctured
convolutional coding with coding rate of 1/2,
2/3, and 3/4
„
Efficient IQ-imbalance calibration, DC
offset, phase noise, frequency offset and
timing offset compensation reduce analog
front-end impairments
„
Selectable digital transmit and receiver FIR
filters provided to meet transmit spectrum
mask requirements and to reject adjacent
channel interference
„
Programmable scaling both in transmitter
and receiver to trade quantization noise
against the increased probability of clipping
„
Processing Gain compliant with FCC
„
On-Chip A/D and D/A converters for I/Q
Data, AGC, and Adaptive Power Control
„
Fast receiver Automatic Gain Control (AGC)
& antenna diversity functions
„
Supports both transmit and receive Antenna
Diversity
„
Complies with WMM, 802.11e, and CCX
specifications
„
Data rates of 1, 2, 5.5, 6, 9, 11, 12, 18, 24, 36,
48, and 54Mbps
„
Complies with 802.11h, 802.11i, 802.11j
specifications
„
Supports 40MHz OSC as the internal clock
source. The frequency deviation of the OSC
must be within 25 PPM on IEEE 802.11g and
20 PPM on IEEE 802.11a
„
Hardware-based IEEE 802.11i
encryption/decryption engine, including
64-bit/128-bit WEP, TKIP, and AES
„
IEEE 802.11g protection mechanisms for
both RTS/CTS and CTS-to-self
„
Supports Wi-Fi alliance WPA and WPA2
security
„
Burst-mode support for dramatically
enhanced throughput
„
Contains two large independent transmit and
receive FIFO buffers
„
DSSS with DBPSK and DQPSK, CCK
modulations and demodulations supported
with long and short preamble
„
Advanced power saving mode when the
LAN and wakeup function are not used
Wireless LAN Network Interface Controller
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Datasheet
„
„
LED pins for various network activity
indications
„
Six GPIO pins supported
„
Supports digital loopback capability on both
ports
„
„
„
Uses 93C46 (64*16-bit EEPROM) or 93C56
(128*16-bit EEPROM) to store resource
configuration and ID parameter data
„
Embedded standard 8051 CPU with
enhanced features:
‹
Four cycles per instruction
‹
Variable clock speed cuts power
consumption
Supports 9 endpoints:
‹
64-Byte buffer for control endpoint
‹
Two 512-Byte buffers for bulk IN
endpoint
‹
Seven 512-Byte buffers for bulk OUT
endpoint
Scatter and gather operation
Complies with USB Specification 2.0
‹
Supports Full-speed (12Mbps) and
High-speed (480Mbps)
„
3.3V and 1.5V power supplies required
„
5V tolerant I/Os
„
0.15µm CMOS process
3. System Applications
„
USB Dongle WLAN adapter
„
Embedded WLAN solution in notebook, desktop, mobile phone, and motherboard
Wireless LAN Network Interface Controller
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Datasheet
4. Block Diagram
MAC
EEPROM
Interface
Radio and
Synthesizer
Control
Serial
Control
LED Driver
RTS, CTS,
ACK Frame
Generator
D-
S I E + Register
D+
WEP/
TKIP/
AES
Checksum
Logic
CCA/
NAV
Engine
FIFO
Control
Logic
FIFO
Frame Type
Discriminator
Interrupt
Control
Logic
Frame Length
Register
Power and TX/RX Timing Control Logic
Transmit/
Receive
Logic
Interface
From BBP
MAC/BBP
Interface
BBP, TX Section
MAC/BBP
Interface
From
MAC
Scrambler
TXI
DAC
TXQ
DAC
TXAGC
TX AGC
Control
TX State
Machine
Register
DAC
Digital
Filter
Coding
ADC
TXDET
ADC
RXI
ADC
RXQ
BBP, RX Section
MAC/BBP
Interface
Descrambler
DAC
Clear Channel
Assessment/
Signal Quality
To MAC
From
MAC
Decoding
Register
RX AGC
Control
ADC
RX State
Machine
Antenna
Diversity
Control
RXAGC
RSSI
ANTSEL
ANTSELB
Figure 1. Block Diagram
Wireless LAN Network Interface Controller
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Datasheet
5. Pin Assignments
Figure 2. Pin Assignments
5.1.
Green Package and Version Identification
Green package is indicated by a ‘G’ in the location marked ‘T’ in Figure 2.
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Datasheet
6. Pin Descriptions
In order to reduce pin count, and therefore size and cost, some pins have multiple functions. In such cases,
the functions are separated with a ‘/’ symbol. Refer to the Pin Assignments diagram on page 5 for a
graphical representation.
The following signal type codes are used in the tables:
I: Input.
S/T/S: Sustained Tri-State.
O: Output
O/D: Open Drain.
T/S: Tri-State bi-directional input/output pin.
6.1.
USB Transceiver Interface
Table 1. USB Transceiver Interface
Symbol
HSDP
HSDM
RREF
6.2.
Type
I/O
I/O
N/A
Pin No
26
24
31
Description
High speed USB D+ signal
High speed USB D- signal
External Reference. Requires 1% precision 6.25K resistor to ground
EEPROM Interface
Table 2. EEPROM Interface
Symbol
EESK
EEDI
EEDO
EECS
6.3.
Type
I/O
Pin No
51
39
36
47
Description
EESK in 93C46 (93C56) programming or auto-load mode.
EEDI in 93C46 (93C56) programming or auto-load mode.
EEDO in 93C46 (93C56) programming or auto-load mode.
EEPROM Chip Select. 93C46 (93C56) chip select.
Power Pins
Table 3. Power Pins
Symbol
VCC3
AVDD
VCCK
Type
GNDK
AGND
Pin No
40, 59, 78, 93, 111
2, 9, 22, 29, 127
44, 53, 72, 82, 90, 105,
115
41, 45, 52, 60, 73, 80,
83, 91, 92, 106, 110,
116
3, 10, 21, 23, 30, 123,
126
Wireless LAN Network Interface Controller
Description
+3.3V (Digital).
+3.3V (Analog).
+1.5V.
Ground (Digital).
Ground (Analog).
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Datasheet
6.4.
LED Interface
Table 4. LED Interface
Symbol
LED0, 1
Type
Pin No
48, 56
Description
LED Pins (Active low)
LEDS1~0
00
01
10
11
LED0
TX/RX
TX/RX
TX
LINK/ACT
LED1
Infrastructure
LINK
RX
Infrastructure
During power down mode, the LED signals are logic high.
6.5.
Attachment Unit Interface
6.5.1.
RTL8225 RF Chipset
Table 5. Attachment Unit Interface
Symbol
RIFSCK
Type
Pin No
57
I/O
61
58
77
108
LNA_HL
ANTSEL
88
87
ANTSELB
95
TRSW
TRSWB
VCOPDN
A_PAPE
B_PAPE
RFTXEN
RFRXEN
GPIO0
GPIO1
GPIO2
GPIO3
104
103
49
85
107
102
113
67
68
69
70
RIFSD
RFLE
CALEN
CALMODE
Description
Serial Clock Output.
For the RTL8225 RF chipset, all operation mode switching and register setting is
done via a 4-wire serial interface.
Serial Data Input/Output.
Serial Enable control.
Serial Read/Write control.
Receiver Output.
I and Q channel AC coupling high-pass corner frequency selection. The output
function of this pin is not used in the RTL8225 RF chipset.
Not used in the RTL8225 RF chipset.
Antenna Select.
The antenna detects signal change states as the receiver switches from antenna to
antenna during the acquisition process in antenna diversity mode. This is a
complement for ANTSELB for differential drive of antenna switches.
Antenna Select B.
The antenna detects signal change states as the receiver switches from antenna to
antenna during the acquisition process in the antenna diversity mode. This is a
complement for ANTSEL for differential drive of antenna switches.
Transmit/Receive path select.
The TRSW select signal controls the direction of the Transmit/Receive switch.
Output Pin as shutdown mode select digital input.
2.4GHz Transmit Power Amplifier Power Enable.
Not used in the RTL8225 RF chipset.
Not used in the RTL8225 RF chipset.
Not used in the RTL8225 RF chipset.
General purpose input/output pin.
General purpose input/output pin.
General purpose input/output pin.
General purpose input/output pin.
Wireless LAN Network Interface Controller
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Datasheet
Symbol
GPIO4
GPIO5
VREFO
VRP
VRN
RXIP
RXIN
RXQP
RXQN
RXAGC
TXAGC
RSSI
TSSI0
TSSI1
TXQP
TXQN
TXIP
TXIN
TXQTP
TXQTN
TXITP
TXITN
6.5.2.
Type
Pin No
100
94
118
119
120
121
122
124
125
11
12
14
13
15
16
17
18
Description
General purpose input/output pin.
General purpose input/output pin.
Not used in the RTL8225 RF chipset.
Not used in the RTL8225 RF chipset.
Not used in the RTL8225 RF chipset.
Receive (Rx) In-phase Analog Data.
Receive (Rx) Quadrature-phase Analog Data.
Not used in the RTL8225 RF chipset.
Not used in the RTL8225 RF chipset.
Analog Input to the Receive Power A/D Converter for Receive AGC Control.
Input to the Transmit Power A/D Converter for 2.4GHz Transmit AGC Control.
Not used in the RTL8225 RF chipset.
Not used in the RTL8225 RF chipset.
Not used in the RTL8225 RF chipset.
Transmit (TX) Quadrature-phase Analog Data.
Transmit (TX) In-phase Analog Data.
RTL8255 RF Chipset
Table 6. RTL8255 RF Chipset
Symbol
RIFSCK
Type
Pin No
57
RIFSD
RFLE
CALEN
CALMODE
61
58
77
108
LNAHL
ANTSEL
ANTSELB
88
87
95
TRSW
TRSWB
VCOPDN
APAPE
BPAPE
104
103
49
85
107
Description
Serial Clock Output.
For the RTL8255 RF chipset, all operation mode switching and register setting is
done via a 3-wire serial interface.
Serial Data Input/Output.
Serial Enable control.
Not used in the RTL8255 RF chipset.
Receiver Output.
I and Q channel AC coupling high-pass corner frequency selection. The output
function of this pin is not used in the RTL8255 RF chipset.
Not used in the RTL8255 RF chipset.
Antenna Select.
The antenna detects signal change states as the receiver switches from antenna to
antenna during the acquisition process in antenna diversity mode.
Transmit/Receive path select.
The TRSW select signal controls the direction of the Transmit/Receive switch.
Not used in the RTL8255 RF chipset.
2.4GHz Transmit Power Amplifier Power Enable.
5GHz Transmit Power Amplifier Power Enable.
Wireless LAN Network Interface Controller
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Datasheet
Symbol
RFTXEN
RFRXEN
GPIO[0]
GPIO[1]
GPIO[2]
GPIO[3]
GPIO[4]
GPIO[5]
VREFO
VRP
VRN
RXIP
RXIN
RXQP
RXQN
RXAGC
TXAGC
RSSI
TSSI0
TSSI1
TXQP
TXQN
TXIP
TXIN
TXQTP
TXQTN
TXITP
TXITN
6.6.
Type
Pin No
102
113
67
68
69
70
100
94
118
119
120
121
122
124
125
11
12
14
13
15
16
17
18
Description
Not used in the RTL8255 RF chipset.
Not used in the RTL8255 RF chipset.
General purpose input/output pin.
General purpose input/output pin.
General purpose input/output pin.
General purpose input/output pin.
General purpose input/output pin.
General purpose input/output pin.
Not used in the RTL8255 RF chipset.
Not used in the RTL8255 RF chipset.
Not used in the RTL8255 RF chipset.
Receive (Rx) In-phase Analog Data.
Receive (Rx) Quadrature-phase Analog Data.
Not used in the RTL8255 RF chipset.
Not used in the RTL8255 RF chipset.
Analog Input to the Receive Power A/D Converter for Receive AGC Control.
Input to the Transmit Power A/D Converter for 2.4GHz Transmit AGC Control.
Input to the Transmit Power A/D Converter for 5GHz Transmit AGC Control.
Transmit (TX) Quadrature-phase Analog Data.
Transmit (TX) In-phase Analog Data.
Not used in the RTL8255 RF chipset.
Not used in the RTL8255 RF chipset.
Clock and Other Pins
Table 7. Clock and Other Pins
Symbol
R15K
XI
EXTRSTB
Type
I/O
Pin No
20
32
Wireless LAN Network Interface Controller
Description
This pin must be pulled low by a 15K Ω resistor.
40MHz clock Input.
Pull high 3.3V. If pulled low, the whole chip will be reset.
Track ID: JATR-1076-21 Rev. 1.0
RTL8187B
Datasheet
7. CPU Access to Endpoint Data
7.1.
Control Transfer
Control transfers configure and send commands to a device. Because they are so important, they employ
extensive USB error checking. The host reserves a portion of each USB frame for control transfers. Control
transfers consist of two or three stages. The SETUP stage contains eight bytes of USB control data. An
optional DATA stage contains more data, if required. The STATUS stage allows the device to indicate
successful completion of a control operation.
7.2.
Bulk Transfer
Bulk data is bursty, traveling in packets of 8, 16, 32, or 64 bytes at full speed, or at 512 bytes at high speed.
Bulk data has guaranteed accuracy due to an automatic retry mechanism for erroneous data. The host
schedules transmission of bulk packets when there is available bus time.
Wireless LAN Network Interface Controller
10
Track ID: JATR-1076-21 Rev. 1.0
RTL8187B
Datasheet
8. USB Request
8.1.
Get Descriptor-Device
Table 8. Get Descriptor-Device
Setup Transaction
BmReq
80
bReq
06
wValueL
00
wValueH
01
wIndexL
00
wIndexH
00
wLengthL
Lengh_L
wLengthH
Length_H
DATA3
02
81
DATA4
00
00
DATA5
00
01
DATA6
00
01
DATA7
40
02
DATA3
01
81
DATA4
00
00
DATA5
00
01
DATA6
00
01
DATA7
40
02
High Speed Data Transaction
DATA0
12
DA
03
DATA1
01
0B
01
DATA2
00
87
Full Speed Data Transaction
DATA0
12
DA
03
8.2.
DATA1
01
0B
01
DATA2
10
87
Get Descriptor-Device Qualifier (High Speed)
Table 9. Get Descriptor- Device Qualifier (High Speed)
Setup Transaction
BmReq
80
bReq
06
wValueL
00
wValueH
06
wIndexL
00
wIndexH
00
wLengthL
Lengh_L
DATA2
00
DATA3
02
DATA4
00
DATA5
00
DATA6
00
wLengthH
Length_H
Data Transaction
DATA0
0A
01
DATA1
06
00
Wireless LAN Network Interface Controller
11
DATA7
40
Track ID: JATR-1076-21 Rev. 1.0
RTL8187B
Datasheet
8.3.
Get Descriptor-Configuration
Table 10. Get Descriptor-Configuration
Setup Transaction
BmReq
80
bReq
06
wValueL
00
wValueH
02
wIndexL
00
wIndexH
00
wLengthL
Length_L
wLengthH
Length_H
DATA3
00
00
05
04
02
00
02
00
07
05
DATA4
01
00
83
02
00
02
00
07
05
0C
DATA5
01
09
02
00
02
00
07
05
0B
02
DATA6
04
FF
00
02
00
07
05
0A
02
00
DATA7
80
FF
02
00
07
05
89
02
00
02
DATA3
00
00
05
04
02
40
00
00
07
05
DATA4
01
00
83
02
40
00
00
07
05
0C
DATA5
01
09
02
40
00
00
07
05
0B
02
DATA6
04
FF
40
00
00
07
05
0A
02
40
DATA7
80
FF
00
00
07
05
89
02
40
00
High Speed Data Transaction
DATA0
09
FA
FF
00
07
05
07
02
00
02
00
DATA1
02
09
02
07
05
06
02
00
02
00
DATA2
51
04
07
05
05
02
00
02
00
07
Full Speed Data Transaction
DATA0
09
FA
FF
00
07
05
07
02
40
00
00
DATA1
02
09
02
07
05
06
02
40
00
00
DATA2
51
04
07
05
05
02
40
00
00
07
Wireless LAN Network Interface Controller
12
Track ID: JATR-1076-21 Rev. 1.0
RTL8187B
Datasheet
8.4.
Get Descriptor-String Index 0
Table 11. Get Descriptor-String Index 0
Setup Transaction
BmReq
80
bReq
06
wValueL
00
wValueH
03
wIndexL
00
wIndexH
00
wLengthL
Lengh_L
DATA2
09
DATA3
04
DATA4
DATA5
DATA6
wLengthH
Length_H
Data Transaction
DATA0
04
8.5.
DATA1
03
DATA7
Get Descriptor-String Index 1
Table 12. Get Descriptor-String Index 1
Setup Transaction
BmReq
80
bReq
06
wValueL
01
wValueH
03
wIndexL
09
wIndexH
04
wLengthL
Lengh_L
DATA2
52
74
DATA3
00
00
DATA4
65
65
DATA5
00
00
DATA6
61
6B
wLengthH
Length_H
Data Transaction
DATA0
10
6C
8.6.
DATA1
03
00
DATA7
00
00
Get Descriptor-String Index 2
Table 13. Get Descriptor-String Index 2
Setup Transaction
BmReq
80
bReq
06
wValueL
02
wValueH
03
wIndexL
09
wIndexH
04
wLengthL
Lengh_L
DATA2
52
31
20
4E
6`
72
DATA3
00
00
00
00
00
DATA4
54
38
57
20
70
DATA5
00
00
00
00
00
DATA6
4C
37
4C
41
74
wLengthH
Length_H
Data Transaction
DATA0
2B
38
42
41
64
65
DATA1
03
00
00
00
00
00
Wireless LAN Network Interface Controller
13
DATA7
00
00
00
00
00
Track ID: JATR-1076-21 Rev. 1.0
RTL8187B
Datasheet
8.7.
Get Descriptor-String Index 3
Table 14. Get Descriptor-String Index 3
Setup Transaction
BmReq
80
bReq
06
wValueL
03
wValueH
03
wIndexL
09
wIndexH
04
wLengthL
Lengh_L
DATA2
30
34
30
DATA3
00
00
00
DATA4
30
63
30
DATA5
00
00
00
DATA6
65
30
30
wLengthH
Length_H
Data Transaction
DATA0
1A
30
30
31
8.8.
DATA1
03
00
00
00
DATA7
00
00
00
Get Descriptor-String Index 4
Table 15. Get Descriptor-String Index 4
Setup Transaction
BmReq
80
bReq
06
wValueL
04
wValueH
03
wIndexL
09
wIndexH
04
wLengthL
Lengh_L
DATA2
57
6C
20
77
20
64
DATA3
00
00
00
00
00
00
DATA4
69
65
4E
6F
43
DATA5
00
00
00
00
00
DATA6
72
73
65
72
61
wLengthH
Length_H
Data Transaction
DATA0
2C
65
73
74
6B
72
DATA1
03
00
00
00
00
00
Wireless LAN Network Interface Controller
14
DATA7
00
00
00
00
00
Track ID: JATR-1076-21 Rev. 1.0
RTL8187B
Datasheet
8.9.
Get Descriptor-String Index 5
Table 16. Get Descriptor-String Index 5
Setup Transaction
BmReq
80
bReq
06
wValueL
05
wValueH
03
wIndexL
09
wIndexH
04
wLengthL
Lengh_L
DATA2
55
48
65
6C
6E
74
DATA3
00
00
00
00
00
00
DATA4
53
53
72
20
76
65
DATA5
00
00
00
00
00
00
DATA6
42
20
69
43
65
72
wLengthH
Length_H
Data Transaction
DATA0
30
20
48
61
6F
72
8.10.
DATA1
03
00
00
00
00
00
DATA7
00
00
00
00
00
00
Get Descriptor-Other Speed Configuration
Table 17. Get Descriptor-Other Speed Configuration
Setup Transaction
BmReq
80
bReq
06
wValueL
00
wValueH
07
wIndexL
00
wIndexH
00
wLengthL
Lengh_L
DATA3
00
00
05
04
02
00
02
00
07
05
DATA4
01
00
83
02
00
02
00
07
05
0C
DATA5
01
09
02
00
02
00
07
05
0B
02
DATA6
04
FF
00
02
00
07
05
0A
02
00
wLengthH
Length_H
High Speed Data Transaction
DATA0
09
FA
FF
00
07
05
07
02
00
02
00
DATA1
07
09
02
07
05
06
02
00
02
00
DATA2
51
04
07
05
05
02
00
02
00
07
Wireless LAN Network Interface Controller
15
DATA7
80
FF
02
00
07
05
89
02
00
02
Track ID: JATR-1076-21 Rev. 1.0
RTL8187B
Datasheet
Full Speed Data Transaction
DATA0
09
FA
FF
00
07
05
07
02
40
00
00
8.11.
DATA1
07
09
02
07
05
06
02
40
00
00
DATA2
51
04
07
05
05
02
40
00
00
07
DATA3
00
00
05
04
02
40
00
00
07
05
DATA4
01
00
83
02
40
00
00
07
05
0C
DATA5
01
09
02
40
00
00
07
05
0B
02
DATA6
04
FF
40
00
00
07
05
0A
02
40
DATA7
80
FF
00
00
07
05
89
02
40
00
wIndexH
00
wLengthL
00
wLengthH
00
wIndexH
00
wLengthL
00
wLengthH
00
wIndexH
00
wLengthL
00
wLengthH
00
Set Address
Table 18. Set Address
Setup Transaction
BmReq
bReq
00
05
Note: No data transaction.
8.12.
wValueL
addrL
wValueH
addrH
wIndexL
00
Set Interface 0
Table 19. Set Interface 0
Setup Transaction
BmReq
bReq
01
0B
Note: No data transaction.
8.13.
wValueL
00
wValueH
00
wIndexL
00
Set Feature Device
Table 20. Set Feature Device
Setup Transaction
BmReq
bReq
00
03
Note: No data transaction.
wValueL
01
Wireless LAN Network Interface Controller
wValueH
00
wIndexL
00
16
Track ID: JATR-1076-21 Rev. 1.0
RTL8187B
Datasheet
8.14.
Clear Feature Device
Table 21. Clear Feature Device
Setup Transaction
BmReq
bReq
00
01
Note: No data transaction.
8.15.
wValueL
01
wValueH
00
wIndexL
00
wIndexH
00
wLengthL
00
wLengthH
00
wIndexH
00
wLengthL
00
wLengthH
00
wIndexH
00
wLengthL
00
wLengthH
00
Set Config 0
Table 22. Set Config 0
Setup Transaction
BmReq
bReq
00
09
Note: No data transaction.
8.16.
wValueL
00
wValueH
02
wIndexL
00
Set Config 1
Table 23. Set Config 1
Setup Transaction
BmReq
bReq
00
09
Note: No data transaction.
wValueL
01
Wireless LAN Network Interface Controller
wValueH
00
wIndexL
00
17
Track ID: JATR-1076-21 Rev. 1.0
RTL8187B
Datasheet
9. EEPROM (93C46 or 93C56) Contents
The RTL8187B supports the attachment of an external EEPROM. The 93C46 is a 1Kbit EEPROM (the
93C56 is a 2Kbit EEPROM). The EEPROM interface provides the ability for the RTL8187B to read from,
and write data to, an external serial EEPROM device. If the EEPROM is not present, the RTL8187B
initialization uses default values for the Operational Registers. Software can read and write to the
EEPROM using “bit-bang” accesses via the 9346CR Register.
Although it is actually addressed by words, its contents are listed below by bytes for convenience. After the
initial power on or auto-load command in the 9346CR, the RTL8187B performs a series of EEPROM read
operations from the 93C46 (93C56).
Note: It is suggested to obtain Realtek approval before changing the default settings of the EEPROM.
Table 24. EEPROM (93C46 or 93C56) Contents
Bytes
00h
01h
Contents
29h
81h
02h-03h
04h-05h
06h
07h
08h
09h
VID
DID
ChannelPlan
Reserved
Reserved
Version
0Ah
0Bh
0Ch
Tx Power Base
Reserved
RFChipID
0Dh
CONFIG3
0Eh~13h
MAC Address
14h
TxPower12
15h
CONFIG1
16h~17h
18h
CRC
CONFIG2
Description
These 2 bytes contain the ID code word for the RTL8187B. The RTL8187B will load
the contents of the EEPROM into the corresponding location if the ID word (8129h) is
correct.
USB Vendor ID.
USB Device ID.
Channel Plan: Map of channels to be scanned.
Bit [7:6] Interface Selection
00 : USB
01 : Mini Card
02 : Reserved
03 : Reserved
Bit [5:0] The EEPROM version.
Tx power of the serving base station.
RF Chip ID.
The identifier of the RF chip.
RTL8187B Configuration register 3.
Operational register FF59h.
MAC Address.
After the auto-load command or a hardware reset, the RTL8187B loads MAC
Addresses to IDR0~IDR5 of the I/O registers of the RTL8187B.
Transmit Power Level for 802.11b(g)-defined channel_ID 12
(center frequency=2467MHz).
RTL8187B Configuration register 1.
Operational register FF52h.
Bit[5:2] : USB receive sensitivity
16-bit CRC value of EEPROM content. Reserved for Software use.
RTL8187B Configuration register 2.
Operational register FF53h.
Wireless LAN Network Interface Controller
18
Track ID: JATR-1076-21 Rev. 1.0
RTL8187B
Datasheet
Bytes
19h
Contents
CONFIG4
1Ah~1Dh
ANA_PARM
1Eh
TESTR
1Fh
CONFIG5
20h
TxPower36
21h
TxPower40
22h
TxPower44
23h
TxPower48
24h
TxPower52
25h
TxPower56
26h
TxPower60
27h
TxPower64
28h
TxPower149
29h
TxPower153
2Ah
TxPower157
2Bh
TxPower161
2Ch
TxPower1
2Dh
TxPower2
2Eh
TxPower3
2Fh
TxPower4
30h
TxPower5
31h
TxPower6
Description
RTL8187B Configuration register 4.
Operational register FF5Ah.
Analog Parameter for the RTL8187B.
Operational registers of the RTL8187B are from 54h to 57h.
Reserved. Do not change this field without Realtek approval.
RTL8187B Test Mode Register.
Operational register FF5Bh.
Reserved. Do not change this field without Realtek approval.
RTL8187B Configuration register 5.
Operational register FFD8h.
Transmit Power Level for 802.11a-defined channel_ID 36
(Center frequency=5180MHz).
Transmit Power Level for 802.11a-defined channel_ID 40
(Center frequency=5200MHz).
Transmit Power Level for 802.11a-defined channel_ID 44
(Center frequency=5220MHz).
Transmit Power Level for 802.11a-defined channel_ID 48
(Center frequency=5240MHz).
Transmit Power Level for 802.11a-defined channel_ID 52
(Center frequency=5260MHz).
Transmit Power Level for 802.11a-defined channel_ID 56
(Center frequency=5280MHz).
Transmit Power Level for 802.11a-defined channel_ID 60
(Center frequency=5300MHz).
Transmit Power Level for 802.11a-defined channel_ID 64
(Center frequency=5320MHz).
Transmit Power Level for 802.11a-defined channel_ID 149
(Center frequency=5745MHz).
Transmit Power Level for 802.11a-defined channel_ID 153
(Center frequency=5765MHz).
Transmit Power Level for 802.11a-defined channel_ID 157
(Center frequency=5785MHz).
Transmit Power Level for 802.11a-defined channel_ID 161
(Center frequency=5805MHz).
Transmit Power Level for 802.11b(g)-defined channel_ID 1
(center frequency=2412MHz).
Transmit Power Level for 802.11b(g)-defined channel_ID 2
(center frequency=2417MHz).
Transmit Power Level for 802.11b(g)-defined channel_ID 3
(center frequency=2422MHz).
Transmit Power Level for 802.11b(g)-defined channel_ID 4
(center frequency=2427MHz).
Transmit Power Level for 802.11b(g)-defined channel_ID 5
(center frequency=2432MHz).
Transmit Power Level for 802.11b(g)-defined channel_ID 6
(center frequency=2437MHz).
Wireless LAN Network Interface Controller
19
Track ID: JATR-1076-21 Rev. 1.0
RTL8187B
Datasheet
Bytes
32h-35h
36h
37h
Contents
ANA_PARM2
Description
Analog Parameter 2 for RTL8187B.
Operational registers for the RTL8187B are 60h to 63h.
Reserved. Do not change this field without Realtek approval.
TxPower11
Transmit Power Level for 802.11b(g)-defined channel_ID 11
(center frequency=2462MHz).
Optional functions Bit[1:0]: Suspend pin behavior.
00b: Default pull high
01b: Default pill low
10b: Functions as a PME# signal
Bit[2]: USB remote wake up function.
0: No remote wake up feature for RTL8187B
1: Remote wake up feature for RTL8187B
Bit[3] : UART Support.
0: No UART interface support
1: UART interface support
Bit[5:4]: Response default serial number.
00b: Respond serial number from EEPROM
01b: Respond serial number from internal ROM, 00 E0 4C 00 00 01
Others : Reserved
38h
39h
3Ah-73h
74h-79h
7Ah
7Bh
7Ch
7Dh
7Eh
7Fh
Bit[6] : Device Power.
0: Bus power
1: Self power
TxPower13
Transmit Power Level for 802.11b(g)-defined channel_ID 13
(center frequency=2472MHz).
TxPower14
Transmit Power Level for 802.11b(g)-defined channel_ID 14
(center frequency=2484MHz).
Manufacture String Manufacture String and Product String:Those bits specify both manufacturer’s
information and device’s information for the USB standard request.
Product String
Maximum two strings total length are 58 bytes.
Reserved.
TxPower7
Transmit Power Level for 802.11b(g)-defined channel_ID 7
(center frequency=2442MHz).
TxPower8
Transmit Power Level for 802.11b(g)-defined channel_ID 8
(center frequency=2447MHz).
TxPower9
Transmit Power Level for 802.11b(g)-defined channel_ID 9
(center frequency=2452MHz).
TxPower10
Transmit Power Level for 802.11b(g)-defined channel_ID 10
(center frequency=2457MHz).
CustomerID
BIT[0-7]: CustomerID, 0x00 and 0xFF is reserved for Realtek.
SW Antenna
BIT[0:1]: 01b enables SW Antenna Diversity.
Diversity
BIT[2:3]: 01b is default antenna.
Wireless LAN Network Interface Controller
20
Track ID: JATR-1076-21 Rev. 1.0
RTL8187B
Datasheet
9.1.
EEPROM Registers Summary
Table 25. EEPROM Registers Summary
Address
Name
FF00hIDR0 – IDR5
FF05h
FF52h
FF53h
FF54hFF57h
CONFIG1
CONFIG2
Type
Bit7
Bit6
Bit5
W*
LEDS1
LEDS1
LEDS0
LEDS0
LCK
W*
Bit4
CONFIG3
FF5Ah
CONFIG4
Bit2
USB Receive Sensitivity
USB Receive Sensitivity
PAPE
_sign
PAPE
_sign
Bit0
W*
W*
PAPE
_time
PAPE
_time
32-bit Read Write
PARM_En
PARM_En
Magic
Magic
LWPME
LWPME
8-bit Read Write
LWPTN
LWPTN
LANWake
FF5Bh
TESTR
FF60hANA_PARM2 R/W
32-bit Read Write
FF63h
FFD8h
CONFIG5 R/W**
Note 1: Registers marked 'W*' can be written only if bits EEM1=EEM0=1.
Note 2: Registers marked 'W**' can be written only if bits EEM1:0=[1:1] and
CONFIG3= 0.
9.2.
Bit1
R/W*
ANA_PARM R/W**
FF59h
Bit3
EEPROM Power Management Registers Summary
Table 26. EEPROM Power Management Registers Summary
Configuration
Space Offset
52h
53h
Name
Type
PMC
Bit7
Bit6
Bit5
Bit4
Bit3
Aux_I_b1 Aux_I_b0
DSI Reserved PMECLK
PME_D3cold PME_D3hot PME_D2 PME_D1 PME_D0
Wireless LAN Network Interface Controller
21
Bit2
Bit1
Bit0
D2
Version
D1 Aux_I_b2
Track ID: JATR-1076-21 Rev. 1.0
RTL8187B
Datasheet
10. USB Packet Buffering
The RTL8187B incorporates two independent FIFOs for transferring data to/from the system interface and
from/to the network. The FIFOs provide temporary storage of data, freeing the host system from the
real-time demands of the network.
The way in which the FIFOs are emptied and filled is controlled by the FIFO threshold values in the
Receive Configuration registers. These values determine how full or empty the FIFOs must be before the
device requests the bus. Once the RTL8187B requests the bus, it will attempt to empty or fill the FIFOs as
allowed by the respective MXDMA settings in the Transmit Configuration and Receive Configuration
registers.
10.1.
Transmit Buffer Manager
The buffer management scheme used on the RTL8187B allows quick, simple, and efficient use of the frame
buffer memory. The buffer management scheme uses separate buffers and descriptors for packet
information. This allows effective transfers of data to the transmit buffer manager by simply transferring
the descriptor information to the transmit queue.
The Tx Buffer Manager DMA’s packet data from system memory and places it in the 3.5KB transmit FIFO,
and pulls data from the FIFO to send to the Tx MAC. Multiple packets may be present in the FIFO,
allowing packets to be transmitted with Short InterFrame (SIF) space. Additionally, once the RTL8187B
requests the bus, it will attempt to fill the FIFO as allowed by the MXDMA setting.
The Tx Buffer Manager process also supports priority queuing of transmit packets. It handles this by
drawing from two separate descriptor lists to fill the internal FIFO. If packets are available in the high
priority queues, they will be loaded into the FIFO before those of low priority.
10.2.
Receive Buffer Manager
The Rx Buffer Manager uses the same buffer management scheme as used for transmits. The Rx Buffer
Manager retrieves packet data from the Rx MAC and places it in the 4KB receive data FIFO, and pulls data
from the FIFO for DMA to system memory. The receive FIFO is controlled by the FIFO threshold value in
RXFTH. This value determines the number of long words written into the FIFO from the MAC unit before
a DMA request for system memory occurs. Once the RTL8187B gets the bus, it will continue to transfer the
long words from the FIFO until the data in the FIFO is less than one long word, or has reached the end of the
packet, or the max DMA burst size is reached, as set in MXDMA.
10.3.
Packet Recognition
The Rx packet filter and recognition logic allows software to control which packets are accepted, based on
destination address and packet type. Address recognition logic includes support for broadcast, multicast
hash, and unicast addresses. The packet recognition logic includes support for WOL and programmable
pattern recognition.
Wireless LAN Network Interface Controller
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RTL8187B
Datasheet
11. Functional Description
11.1.
Transmit & Receive Operations
The RTL8187B supports a new descriptor-based buffer management that will significantly lower host CPU utilization. The
RTL8187B supports transmit descriptor and receive descriptor in memory. Each OUT packet contains 3-double-word transmit
descriptors and each IN packet contains 4-double-word receive descriptors.
11.1.1. Transmit
Tx Descriptor Format
Table 27. Tx Descriptor Format
31 30 29 28
27 26 25 24 23
TXRATE
(4 bits)
D F L
M S S
22 21 20 19 18 17 16 15 14 13 12 11 10
R RTSRATE C M S N BSSID
T (4 bits) T O P O _NO
S R L _
E E C E
NF P N
Length (15 bits)
9 8 7 6 5 4 3 2 1 0
TPKTSIZE (12 bits)
RTSDUR (16 bits)
TX_BUFFER_ADDRESS
M RSVD
Frame_Length (12 bits)
I (3 bits)
NEXT_TX_DESCRIPTOR_ADDRESS
RATE_FALL RTS_RATE RSVD P N R RETRY_LIMIT (8 bits)
RTSAGC (8 bits)
BACK_LIMIT
_FALL
(4bits) I O T
(5 bits)
BACK_LIM
F _ _
IT (4 bits)
S A D
C B
DURATION (16 bits)
Offset 0
Offset 4
Offset 8
Offset 12
Offset 16
Offset 20
Wireless LAN Network Interface Controller
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RTL8187B
Datasheet
31 30 29 28
27 26 25 24 23
R SPC A
22 21 20 19 18 17 16 15 14 13 12 11 10
AGC (8 bits)
FRAG_QSIZE (16 bits)
RSVD
(4bits)
9 8 7 6 5 4 3 2 1 0
DELAY_BOUND (16 bits)
E BCKEY (6 bits)
TPC
_PO
LAR
ITY
Offset 24
HW
Leng
thSel
ect
Offset 28
Table 28. Tx Status Descriptor
Offset#
Bit#
31
Symbol
OWN
30
DMA OK
29
FS
28
LS
Wireless LAN Network Interface Controller
Description
Ownership.
When set, this bit indicates that the descriptor is owned by the NIC, and the
data relative to this descriptor is ready to be transmitted. When cleared, it
indicates that the descriptor is owned by the host system. The NIC clears this
bit when the relative buffer data is transmitted. In this case, OWN=1.
DMA OK.
Set by the driver, reset by the RTL8187B when TX DMA OK. If IMR’s
corresponding bit is set and the driver sets this bit, the RTL8187B resets this
bit and issues an interrupt right after DMA OK of the last segment (LS). If not,
the RTL8187B just resets this bit without asserting an interrupt.
First Segment Descriptor.
When set, this bit indicates that this is the first descriptor of a Tx packet, and
that this descriptor is pointing to the first segment of the packet.
Last Segment Descriptor.
When set, indicates that this is the last descriptor of a Tx packet, and this
descriptor is pointing to the last segment of the packet.
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Datasheet
Offset#
Bit#
27:24
Symbol
TXRATE
23
RTSEN
22:19
RTSRATE
18
CTSEN
17
MOREFRAG
16
SPLCP
Wireless LAN Network Interface Controller
Description
Tx Rate.
These five bits indicate the current frame’s transmission rate.
Bit 27
Bit 26
Bit 25
Bit 24
1Mbps
2Mbps
5.5Mbps
11Mbps
6Mbps
9Mbps
12Mbps
18Mbps
24Mbps
36Mbps
48Mbps
54Mbps
Reserved
All other combinations
RTS Enable.
Set to 1 indicates that an RTS/CTS handshake shall be performed at the
beginning of any frame exchange sequence where the frame is of type Data or
Management, the frame has an unicast address in the Address1 field, and the
length of the frame is greater than RTSThreshold.
RTS Rate.
These four bits indicate the RTS frame’s transmission rate before transmitting
the current frame and will be ignored if the RTSEN bit is set to 0.
Bit 22
Bit 21
Bit 20
Bit 19
1Mbps
2Mbps
5.5Mbps
11Mbps
6Mbps
9Mbps
12Mbps
18Mbps
24Mbps
36Mbps
48Mbps
54Mbps
Reserved
All other combinations
CTS Enable.
Both RTSEN and CTSEN set to 1 indicates that the CTS-to-self protection
mechanism will be used.
More Fragment.
This bit is set to 1 in all data type frames that have another fragment of the
current packet to follow.
Short Physical Layer Convergence Protocol format.
When set, this bit indicates that a short PLCP preamble will be added to the
header before transmitting the frame.
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RTL8187B
Datasheet
Offset#
Bit#
15
Symbol
NO_ENCRYPT
14:12
RSVD
11:0
TPKTSIZE
31
LENGEXT
30:16
Length
15:0
RTSDUR
12
12
12
12
31:0
31:16
15
14:12
11:0
TxBuff
DURATION
MIC_CAL
RSVD
Frame_Length
16
31:0
NTDA
20
31:27
20
26:23
20
22:19
20
18
PIFS
20
17
NO_ACM
20
16
RT_DB
20
15:8
RETRY_LIMIT
20
7:0
RTSAGC
24
31
RSVD
24
30:29
SPC
24
28
ANTENNA
24
27:20
AGC
Tx AGC.
24
19:16
RSVD
Reserved.
24
15:0
DELAY_BOUND
DELAY BOUND
Wireless LAN Network Interface Controller
26
Description
No Encryption.
This packet will be sent out without encryption even if Tx encryption is
enabled.
Reserved.
Transmit Packet Size.
This field indicates the number of bytes required to transmit the frame.
Length Extension.
This bit is used to supplement the Length field (bits 30:16, offset 4). This bit
will be ignored if the TXRATE is set to 1Mbps, 2Mbps, or 5.5Mbps.
PLCP Length: The PLCP length field indicates the number of microseconds
required to transmit the frame.
RTS Duration: These bits indicate the RTS frame’s duration field before
transmitting the current frame and will be ignored if the RTSEN bit is set to 0.
32-bit Transmit Buffer Address.
Time duration to send this packet plus SIFS and ACK
Enable MIC calculation.
Reserved.
Transmit Frame Length.
This field indicates the length in the Tx buffer, in bytes, to be transmitted.
32-bit Address of the Next Transmit Descriptor.
RATE_FALL
Data Rate Auto Fallback Limit.
BACK_LIMIT
RTS_RATE_FALL RTS/CTS Rate Auto Fallback Limit.
BACK_LIMIT
RSVD
Reserved.
Setting this bit will cause this frame be sent after PIFS
No admission control procedure.
This packet will be sent out without being restricted by admission control
procedures. For example, the management type frames shall be sent using the
access category AC_VO without being restricted by admission control
procedures.
Lifetime limited by RETRY_LIMIT (RT_DB=0) or DELAY_BOUND
(RT_DB=1).
Retry Count Limit.
Tx RTS AGC.
Reserved.
Short preamble count.
00: 10 bits
01: 12 bits
10: 14 bits
11: 16 bits
Tx Antenna.
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RTL8187B
Datasheet
Offset#
28
Bit#
31:16
Symbol
FRAG_QSIZE
28
15
ENPMPD
28
14
EN_BCKEY
28
13:8
BCKEY
Specify key to use in CAM for broadcast/multicast.
28
PT_EN
Enable Power Tracking.
28
TPC_EN
28
5:4
TPC_POLARITY
28
TPC_DESEN
28
1:0
HWLengthSelect
Description
Fragmentation Queue Size.
Upon sending the first frame of a fragmentation sequence, the driver writes the
queue size of the entire fragmentation exchange (including the first frame)
here. MAC uses this value when counting down TXOP. This field is valid
when TCR (0x40) duration processing fields are set to mode 1 or 2.
Enable Power Meter Pre-distortion Packet.
Enable broadcast/multicast key search when using Multiple BSSID
Enable TPC.
TPC Polarity Select.
00: Neither increment nor decrement.
01: Increment.
10: Decrement.
11: Reserved.
TPC Descriptor AGC Enable.
0: Use the value of register TPC_TXAGC_OFDM as 54MHz TXAGC Base.
1: Use the value of AGC in the same descriptor as 54MHz TXAGC Base.
HW Length Select.
00: No Encryption.
01: RC4 Encryption.
10: AES Encryption.
11: Reserved.
11.1.2. Receive
Rx Descriptor Format
Table 29. Rx Descriptor Format
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7
D F L
M S S
RSVD (11 bits)
Offset 0
U T
D O
R K
RTS RC
(7 bits)
Packet RC
(8 bits)
RSVD
TX_BUFFER_ADDRESS
MPDUExchangeTime (16 bits)
RSVD (4
Frame_Length (12 bits)
bits)
NEXT_TX_ DESCRIPTOR _ADDRESS
RSVD
RSVD
RSVD
Wireless LAN Network Interface Controller
1 0
27
Offset 4
Offset 8
Offset 12
Offset 16
Offset 20
Offset 24
Offset 28
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Datasheet
Table 30. Rx Status Descriptor
Offset#
Bit#
31
Symbol
OWN
Description
Ownership.
When set, this bit indicates that the descriptor is owned by the NIC. When clear, it
indicates that the descriptor is owned by the host system. The NIC clears this bit
when the related buffer data has been transmitted. In this case, OWN=0.
DMA Okay.
30
DMA_OK
29
FS
28
LS
27:17
RSVD
First Segment Descriptor.
When set, this bit indicates that this is the first descriptor of a Tx packet, and that
this descriptor is pointing to the first segment of the packet.
Last Segment Descriptor.
When set, this bit indicates that this is the last descriptor of a Tx packet, and that
this descriptor is pointing to the last segment of the packet.
Reserved.
16
UDR
FIFO underrun during transmission of this packet.
15
TOK
14:8
RTS RC
7:0
Packet RC
31:0
RSVD
Transmit (Tx) OK.
Indicates that a packet exchange sequence has completed successfully.
RTS Retry Count. The RTS RC’s initial value is 0. It indicates the number of
retries of RTS.
Packet Retry Count.
The RC’s initial value is 0. It indicates the number of retries before a packet was
transmitted properly.
Reserved.
31:0
TxBuff
32-bit Transmit Buffer Address.
12
31:16
12
15:12
12
11:0
Frame_Length
16
31:0
NTDA
Transmit Frame Length.
This field indicates the length in the Tx buffer, in bytes, to be transmitted.
32-bit Address of Next Transmit Descriptor.
20
31:0
RSVD
Reserved.
24
31:0
RSVD
Reserved.
28
31:0
RSVD
Reserved.
MPDUExchange MPDUExchangeTime corresponds to the just completed MPDU exchange. The
Time
MPDUExchangeTime equals the time required to transmit the MPDU sequence,
i.e., the time required to transmit the MPDU plus the time required to transmit the
expected response frame plus one SIFS.
RSVD
Reserved.
Wireless LAN Network Interface Controller
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Datasheet
11.2.
Rx Command
The RTL8187B supports an Rx command queue to feedback the Tx state and beacon interrupt . When the
Command Type (bit[31:30]) is set to 00b, it indicates Tx Beacon Interrupt. When set to 01b, it indicates Tx
Close Descriptor.
Table 31. Tx Beacon Interrupt
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Cmd
RSVD
Last Beacon CW
Type
Last Beacon TSF[31:0]
Table 32. Tx Close Descriptor
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Cmd
FS LS
Sequence No[11:0]
Type
RTS Retry Count[6:0]
Packet Retry Count[7:0]
MAC Used Time [15:0]
11.3.
Loopback Operation
Loopback mode is normally used to verify that the logic operations have performed correctly. In loopback
mode, the RTL8187B takes frames from the transmit descriptor and transmits them up to internal Rx logic.
The loopback function does not apply to an external PHYceiver.
11.4.
Tx Encapsulation (With RTL8187B Internal Baseband
Processor)
When operating in Tx mode, the RTL8187B encapsulates the frames that it transmits according to the
Differential Binary Phase Shift Keying (DBPSK) for 1Mbps, Differential Quaternary Phase Shift Keying
(DQPSK) for 2Mbps, and Complementary Code Keying (CCK) for 5.5Mbps and 11Mbps modulators. The
changes to the original packet data are as follows:
1. The PLCP preamble is always transmitted as the DBPSK waveform and used by the receiver to achieve
initial PN synchronization.
2. The PLCP header can be configured to be either DBPSK or DQPSK and includes the necessary data
fields of the communications protocol to establish the physical layer link.
3. The MAC frame can be configured for DBPSK, DQPSK, or CCK.
Wireless LAN Network Interface Controller
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Datasheet
11.5.
Rx Decapsulation (With RTL8187B Internal Baseband
Processor)
The RTL8187B continuously monitors the network when reception is enabled. When activity is recognized
it starts to process the incoming data. After detecting receive activity on the channel, the RTL8187B starts
to process the PLCP preamble and header based on the mode of operation.
The RTL8187B checks CRC16 and CRC32, then reports if CRC16 or CRC32 has errors. When using the
40-bit WEP and 104-bit WEP module for decryption, the RTL8187B also checks the Integrity Check Value
(ICV) and reports if the ICV has errors.
11.6.
QoS Functions
The RTL8187B supports WMM, WMM Scheduled Access, and IEEE 802.11e functions.
11.7.
Contention-based Admission Control Functions
Refer to Section 9.9.3 of the IEEE 802.11e specification for greater detail.
The ATL (Admitted Time Limit) is a statically set value which determines the maximum transmission time
a class can have.
Software keeps track of admitted time per access that requires admission control. Upon receipt of a
successful response frame, the non-AP QSTA adds the admitted time variable for the specified EDCAF to
the value contained in the Medium Time field of the TSPEC element. The non-AP QSTA then starts a
five-second timer. The non-AP QSTA shall update the value of used time:
A. At five second intervals
used_time = max ((used_time-admitted_time), 0)
B. After each successful or unsuccessful MPDU (re)transmission attempt,
used_time = used_time + MPDUExchangeTime
If the used_time reaches or exceeds the admitted time value, the corresponding EDCAF sets the
corresponding bit in the ACM_CONTROL register to 1. The corresponding EDCAF may then choose to
temporarily replace the EDCA parameters for the EDCAF with those specified for an access category of
lower priority, if no admission control is required for those access categories.
Wireless LAN Network Interface Controller
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RTL8187B
Datasheet
11.8.
Duration Field Processing
The RTL8187B supports three modes of duration field processing (selected via the DurProcMode bit in
each AC_XX_TXOPQueued register).
•
Mode 0: Software takes full control of duration field processing. MAC has nothing to do with it.
•
Mode 1: DMA reads the 2-byte DURATION value in the TX descriptor and adds it to the
AC_XX_TXOPQueued register.
•
Mode2: Hardware accumulates all the requested duration values of each EDCAF data queue and each
EDCAF FIFO and writes the value to each corresponding AC_XX_TXOPQueued register.
In Mode1 and Mode2, MAC decreases the value in the AC_XX_TXOPQueued register each time an
EDCAF packet is transmitted.
11.9.
LED Functions
The RTL8187B supports 2 LED signals in 4 configurable operation modes. The following sections describe
the different LED actions.
11.9.1. Link Monitor
The Link Monitor senses the link integrity. Whenever link status is established, the specific link LED pin is
driven low.
11.9.2. Infrastructure Monitor
The Infrastructure Monitor senses the link integrity of an Infrastructure network. Whenever Link OK in
Infrastructure network status is established, the specific Infrastructure LED pin is driven low.
Wireless LAN Network Interface Controller
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Datasheet
11.9.3. Rx LED
Blinking of the Rx LED indicates that receive activity is occurring.
Power On
LED = High
Receiving
Packet?
No
Yes
LED = High for (100 +- 10) ms
LED = Low for (12 +- 2) ms
Figure 3. Rx LED
Wireless LAN Network Interface Controller
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RTL8187B
Datasheet
11.9.4. Tx LED
Blinking of the Tx LED indicates that transmit activity is occurring.
Power On
LED = High
Transmitting
Packet?
No
Yes
LED = High for (100 +- 10) ms
LED = Low for (12 +- 2) ms
Figure 4. Tx LED
11.9.5. Tx/Rx LED
Blinking of the Tx/Rx LED indicates that both transmit and receive activity is occurring.
Power On
LED = High
Tx/Rx Packet?
No
Yes
LED = High for (100 +- 10) ms
LED = Low for (12 +- 2) ms
Figure 5. Tx/Rx LED
Wireless LAN Network Interface Controller
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RTL8187B
Datasheet
11.9.6. LINK/ACT LED
Blinking of the LINK/ACT LED indicates that the RTL8187B is linked and operating properly. If this LED
is high for extended periods it indicates that a link problem exists.
Power On
LED = High
No
Link?
Yes
LED = Low
No
Tx/Rx packet?
Yes
LED = High for (100 +- 10) ms
LED = Low for (12 +- 2) ms
Figure 6. LINK/ACT LED
Wireless LAN Network Interface Controller
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RTL8187B
Datasheet
12. Application Diagram
Main/Aux. Power
Regulators
Power 3.3V, 1.5V
LED
External
ROM/RAM
Power 3.3V, 1.5V
Power 3.3V, 1.8V
RTL8187B
Antenna
External
RF
Devices
Base
Band
40MHz
Clock
D+
MAC
SIE
EEPROM
D-
Power 3.3V
Figure 7. Application Diagram
Wireless LAN Network Interface Controller
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RTL8187B
Datasheet
13. Electrical Characteristics
13.1.
Temperature Limit Ratings
Table 33. Temperature Limit Ratings
Parameter
Storage temperature
Operating temperature
13.2.
Minimum
-55
-10
Maximum
+125
70
Units
°C
°C
DC Characteristics
Table 34. DC Characteristics
Symbol
Parameter
VDD33
VDD15
Conditions
Minimum
Typical
Maximum
Units
3.3V Supply Voltage
3.0
3.3
3.6
1.5V Supply Voltage
1.4
1.5
1.6
Vcc
0.1 * Vcc
Voh
Minimum High Level Output
Voltage
Ioh = -8mA
Vol
Maximum Low Level Output
Voltage
Iol = 8mA
Vih
Minimum High Level Input Voltage
0.5 * Vcc
Vcc+0.5
Vil
Maximum Low Level Input Voltage
-0.5
0.3 * Vcc
Iin
Input Current
Vin =Vcc or GND
-1.0
1.0
µA
Ioz
Tri-State Output Leakage Current
Vout =Vcc or GND
-10
10
µA
Icc
Average Operating Supply Current
Iout = 0mA
242
mA
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Wireless LAN Network Interface Controller
0.9 * Vcc
RTL8187B
Datasheet
13.3.
AC Characteristics
13.3.1. Serial EEPROM Interface Timing (93C46(64*16)/93C56(128*16))
EESK
EECS
EEDI
tcs
(Read)
An
A2
A1
A0
(Read)
EEDO High Impedance
Dn
D1
D0
EESK
EECS
EEDI
tcs
(Write)
An
...
A0
Dn
...
D0
(Write)
EEDO High Impedance
BUSY
READY
twp
tsk
EESK
tskh
EECS
tcss
tdis
tcsh
tskl
tdih
EEDI
tdos
tdoh
EEDO (Read)
EEDO
tsv
STATUS VALID
(Program)
Figure 8. Serial EEPROM Interface Timing
Table 35. EEPROM Access Timing Parameters
Symbol
tcs
twp
tsk
tskh
tskl
tcss
tcsh
tdis
tdih
tdos
tdoh
tsv
Parameter
Minimum CS Low Time
Write Cycle Time
SK Clock Cycle Time
SK High Time
SK Low Time
CS Setup Time
CS Hold Time
DI Setup Time
DI Hold Time
DO Setup Time
DO Hold Time
CS to Status Valid
Wireless LAN Network Interface Controller
9346/9356
9346/9356
9346/9356
9346/9356
9346/9356
9346/9356
9346/9356
9346/9356
9346/9356
9346/9356
9346/9356
9346/9356
37
Minimum
1000/250
Typical
Maximum
10/10
4/1
1000/500
1000/250
200/50
0/0
400/50
400/100
2000/500
2000/500
1000/500
Units
ns
ms
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
Track ID: JATR-1076-21 Rev. 1.0
RTL8187B
Datasheet
14. Mechanical Dimensions
See the Mechanical Dimensions notes on the next page.
Wireless LAN Network Interface Controller
38
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RTL8187B
Datasheet
14.1.
Symbol
A1
A2
D1
E1
L1
Θ
Mechanical Dimensions Notes
Dimension in inch
Min Typical Max
0.063
0.002
0.053 0.055 0.057
0.005 0.007 0.009
0.004
0.006
0.624 0.630 0.636
0.547 0.551 0.555
0.016 BSC
0.624 0.630 0.636
0.547 0.551 0.555
0.018 0.024 0.030
0.039 REF
0°
3.5°
7°
Dimension in
Min Typical
0.05
1.35
1.40
0.13
0.18
0.09
15.85 16.00
13.90 14.00
0.40 BSC
15.85 16.00
13.90 14.00
0.45
0.60
1.00 REF
0°
3.5°
mm
Max
1.60
1.45
0.23
0.20
16.15
14.10
16.15
14.10
0.75
7°
Note:
1.Dimension b does not include dambar
protrusion/intrusion.
2.Controlling dimension: Millimeter
3.General appearance spec. should be based
on final visual inspection spec.
TITLE: 128LD LQFP ( 14x14x1.4 mm*2 ) PACKAGE OUTLINE
-CU L/F, FOOTPRINT 2.0 mm
LEADFRAME MATERIAL:
APPROVE
DOC. NO. 530-ASS-P004
VERSION 1
PAGE
OF
CHECK
DWG NO. LQ128 - 2
DATE
MAY. 13.2002
REALTEK SEMICONDUCTOR CORP.
15. Ordering Information
Table 36. Ordering Information
Part Number
Package
RTL8187B-GR
128-pin LQFP with green package
Note: See page 5 for Green package identification.
Status
MP
Realtek Semiconductor Corp.
Headquarters
No. 2, Innovation Road II, Hsinchu Science Park,
Hsinchu 300, Taiwan.
Tel: 886-3-5780211 Fax: 886-3-5776047
www.realtek.com.tw
Wireless LAN Network Interface Controller
39
Track ID: JATR-1076-21 Rev. 1.0
Test Report
REALTEK SEMICONDUCTOR CORP.
Report No. : CE/2005/12075
NO. 2, INDUSTRY E. RD. IX, SCIENCE-BASED INDUSTRIAL Date
: 2005/01/20
PARK, HSINCHU 300, TAIWAN
Page
: 1 of 2
The following merchandise was (were) submitted and identified by the client as :
Type of Product
Style/Item No
Sample Received
Testing Date
LQFP (LF)
4C055S2
2005/01/13
2005/01/13 TO 2005/01/20
============================================================================
Test Result
- Please see the next page -
The content of this PDF file is in accordance with the original issued reports for reference only. This Test Report cannot be reproduced, except in full,
without prior written permission of the Company
SGS TAIWAN LIMITED
NO. 136-1, Wu Kung Road, WuKu Industrial Zone, Taipei county, Taiwan.
t(886-2) 22993939 f(886-2) 2299-3237 www.sgs.com.tw
Test Report
REALTEK SEMICONDUCTOR CORP.
Report No. : CE/2005/12075
NO. 2, INDUSTRY E. RD. IX, SCIENCE-BASED INDUSTRIAL Date
: 2005/01/20
PARK, HSINCHU 300, TAIWAN
Page
: 2 of 2
Test Result
PART NAME NO.1
MIXED BLACK PLASTIC BODY&SILVER COLORED
METAL-MIXED ALL PART
Test Item (s):
Unit
Method
MDL
PBBs(Polybrominated
biphenyls)(CAS NO:05953665-1)
0.0005
PBBEs(PBDEs)(Polybrominat
ed biphenyl ethers)
With reference to
USEPA3540 or USEPA3550.
Analysis was performed by
HPLC/DAD, LC/MS or
GC/MS. (prohibited by
2002/95/EC (RoHS),
83/264/EEC, and
76/769/EEC)
With reference to
USEPA3540 or USEPA3550.
Analysis was performed by
HPLC/DAD, LC/MS or
GC/MS. (prohibited by
2002/95/EC (RoHS),
83/264/EEC, and
76/769/EEC)
Result
No.1
N.D.
0.0005
N.D.
Test Item (s):
Unit
Method
MDL
Chromium VI (Cr+6)
ppm
As per US EPA 7196A and
US EPA 3060A.
Result
No.1
N.D.
Cadmium (Cd)
ppm
N.D.
Mercury (Hg)
ppm
N.D.
Lead (Pb)
ppm
ICP-AES after as per EN
1122, method B:2001 or
other acid digestion.
ICP-AES after as per US
EPA 3052 or other acid
digestion.
ICP-AES after as per US
EPA 3050B or other acid
digestion.
N.D.
NOTE： (1) N.D. = Not detected (
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Modify Date                     : 2007:02:05 16:27+08:00
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Metadata Date                   : 2007:02:05 16:27+08:00
Creator Tool                    : Acrobat PDFMaker 6.0 for Word
Format                          : application/pdf
Title                           : Realtek RTL8187B DataSheet 1.0
Description                     : Realtek RTL8187B DataSheet 1.0
Creator                         : Realtek RTL8187B DataSheet 1.0
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Subject                         : Realtek RTL8187B DataSheet 1.0
Author                          : Realtek RTL8187B DataSheet 1.0


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