Barrot Technology IVTI50E Bluetooth Module User Manual
IVT Corporation Bluetooth Module
User Manual
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| Document ID | 2010556 |
| Application ID | I/g7sE+Gu80BbqGHaaQ+6w== |
| Document Description | User Manual |
| Short Term Confidential | No |
| Permanent Confidential | No |
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| Document Type | User Manual |
| Display Format | Adobe Acrobat PDF - pdf |
| Filesize | 153.85kB (1923123 bits) |
| Date Submitted | 2013-07-08 00:00:00 |
| Date Available | 2013-07-08 00:00:00 |
| Creation Date | 2013-07-05 14:52:20 |
| Producing Software | Microsoft® Word 2010 |
| Document Lastmod | 2013-07-05 14:54:32 |
| Document Title | User Manual |
| Document Creator | Microsoft® Word 2010 |
| Document Author: | ivt |
oSy lei Blu Blu oSy lei Blu i50e Datasheet June 27, 2013 Version 1.9 oSy lei lu oSy i50e Datasheet oSy VERSION HISTORY REVISION 1.0 1.1 AMENDMENT lei Blu Initial version AUTHOR 2012-6-25 Wang Yuqiang Zhu Yong oSy Added certification, contact information, copyright ei 1.2 Revise chapter 2.1 1.3 Add chapter 2.5: add power DATE lue 2012-8-08 Niu Chong Huang Ruixue 2012-10-12 Li Li 2012-11-16 Li Li consumption when i50e works as master 1.4 Update i50e footprint. Refer to Figure oSy 2012-11-22 30. Wan Zhifu Li Li ei 1.5 Update format 1.6 Update PIN description. See Table 9. lue 2012-11-29 Li Li 2012-12-21 Li Li Change UART_CTS to CMOS Input, change UART_RX to CMOS Input oSy 1.7 Add package information 2013-3-4 Li Li 1.8 1. Update Figure2. 2013-4-2 Li Li lu 2. Add FCC, IC, CE certificate 1.8 Update designated antenna. 2013-4-16 Li Li 1.9 Update descrpitons. 2013-6-27 Li Li 2 / 58 i50e Datasheet Contents oSy Block Diagram and Descriptions ............................................................................................... 6 Electrical Characteristics ........................................................................................................... 8 lei 2.1 Absolute maximum ratings ............................................................................................... 8 2.2 Recommended Operating Conditions ............................................................................... 8 2.3 Terminal characteristics .................................................................................................... 8 2.4 Battery charger ................................................................................................................. 9 2.5 CODEC Characteristics ..................................................................................................... 10 2.6 Current Consumption ...................................................................................................... 11 2.7 Radio Characteristics and General Specifications ........................................................... 11 Blu oSy Pin Description ........................................................................................................................ 12 Power Management................................................................................................................ 19 Power Management Block .............................................................................................. 19 4.2 Battery Charger ............................................................................................................... 20 Blu Serial Interfaces ....................................................................................................................... 21 5.1 UART Interface ................................................................................................................ 21 5.1.1 UART Configuration While RESET is Active.............................................................. 23 5.1.2 UART Bypass Mode ................................................................................................. 23 5.2 lei 4.1 SPI Interface .................................................................................................................... 24 Audio Interfaces ...................................................................................................................... 24 6.1 6.1.1 6.2 oSy Audio Interface ................................................................................................................ 24 Audio Input and Output .......................................................................................... 25 lei Stereo Audio CODEC Interface ........................................................................................ 26 6.2.1 ADC .......................................................................................................................... 26 6.2.2 DAC .......................................................................................................................... 28 6.2.3 IEC 60958 Interface ................................................................................................. 30 6.2.4 Microphone Input ................................................................................................... 30 6.2.5 Line Input ................................................................................................................ 32 6.2.6 Output Stage ........................................................................................................... 33 Blu oSy 6.2.6.1 Mono Operation ...................................................................................................................... 34 6.2.6.2 Side Tone ................................................................................................................................. 34 6.2.6.3 Integrated Digital Filter ............................................................................................................ 34 lu 6.3 Digital Audio Interface (I2S) ............................................................................................ 34 6.4 PCM Interface.................................................................................................................. 38 6.4.1 PCM Interface Master/Slave ................................................................................... 38 6.4.2 Long Frame Sync ..................................................................................................... 39 3 / 58 i50e Datasheet 6.4.3 Short Frame Sync .................................................................................................... 40 6.4.4 Multi Slot Operation ................................................................................................ 40 6.4.5 GCI Interface............................................................................................................ 41 6.4.6 Slots and Sample Formats ....................................................................................... 41 6.4.7 Additional Features ................................................................................................. 42 6.4.8 PCM Configuration .................................................................................................. 42 oSy lei Software Stacks ....................................................................................................................... 43 7.1 Blu BlueSoleil Stack ............................................................................................................... 44 Enhanced Data Rate ................................................................................................................ 45 8.1 Enhanced Data Rate Baseband ....................................................................................... 45 8.2 Enhanced Data Rate _/4 DQPSK ...................................................................................... 45 8.3 8DQPSK ........................................................................................................................... 46 oSy Re-flow Temperature-time Profile .......................................................................................... 47 10 Reliability and Environmental Specification ........................................................................ 48 lei 10.1 Temperature test ............................................................................................................. 48 10.2 Vibration Test .................................................................................................................. 48 10.3 Desquamation Test .......................................................................................................... 48 10.4 Drop Test ......................................................................................................................... 48 10.5 Packaging Information..................................................................................................... 48 Blu 11 Layout and Soldering Considerations ...................................................................................... 49 11.1 Soldering Recommendations .......................................................................................... 49 11.2 Layout Guidelines ............................................................................................................ 49 oSy 12 Physical Dimensions ............................................................................................................ 50 13 Package ............................................................................................................................... 51 14 Certifications ....................................................................................................................... 54 lei 14.1 Bluetooth ......................................................................................................................... 54 14.2 CE 0700 ........................................................................................................................... 54 14.3 FCC .................................................................................................................................. 54 14.4 IC ..................................................................................................................................... 55 Blu 15 RoHS Statement with a List of Banned Materials................................................................ 56 16 Bluetooth Technology Best Developed Corporation ........................................................... 57 17 Contact Information ............................................................................................................ 57 18 Copyright ............................................................................................................................. 58 lu oSy 4 / 58 I50e Datasheet i50e DESCRIPTION oSy FEATURES ei BlueSoleil i50e is a Bluetooth 2.1 +EDR (Enhanced Data Rates) class 2module. It contains all the necessary elements from Bluetooth radio to antenna and a fully implemented protocol stack. BQB, KCC, TELEC Certification Industrial temperature range from -400C Integrated audio codec, acoustic echo cancellation algorithm powerful and easy-to-use BlueSoleil firmware. BlueSoleil enables users to access Bluetooth functionality with simple ASCII Support for 802.11 Coexistence 8Mbits or 16Mbits of Flash Memory Low power consumption RoHS Compliant oSy lei commands delivered to the module over serial interface - it's just like a Bluetooth Blu EDR to +850C By default i50e module is equipped with modem. Fully Qualified Bluetooth system v2.1 + Therefore, i50e provides an ideal solution APPLICATIONS for developers who want to integrate High quality stereo headsets Bluetooth wireless technology into their High quality mono headsets design. Hands-free car kits Wireless speakers IVI Bluetooth Solution Blu oSy lei lu oSy Figure 1 BlueSoleil i50e 5 / 58 i50e Datasheet 1 Block Diagram and Descriptions oSy BlueSoleil i50e’s block diagram is illustrated in Figure 2 below. lei Blu Blu oSy lei oSy Figure 2 i50e Block Diagram BC05-MM Blu lei The BlueCore05-MM is a single-chip radio and baseband IC for Bluetooth 2.4GHz systems. It provides a fully compliant Bluetooth system to v2.1+EDR of the specification for data and voice. BlueCore05-MM contains the Kalimba DSP co-processor with double the MIPS of BlueCore03-MM, supporting enhanced audio applications. BlueCore05-MM integrates a 16-bit stereo codec and it has a fully differential audio interface with a low noise microphone bias. Crystal The crystal oscillates at 16MHz. lu Flash oSy Flash memory is used for storing the Bluetooth protocol stack and Virtual Machine applications. It can also be used as an optional external RAM for memory-intensive applications. Balanced Filter Combined balun and filter changes the balanced input/output signal of the module to unbalanced signal of the antenna. The filter is a band pass filter (ISM band). 6 / 58 i50e Datasheet RF in/out PIN i50e does not integrate antenna. The customers can only connect external RF-transceiver antenna to pin 54.It is not a standard antenna jack or connector. And only the PCB antenna, which is the designated antenna, can be connected to this pin. The antenna gain is no more than 1dBi. The designated PCB antenna manufacture is Walsin Technology Corporation. The model of the designated PCB antenna is RFANT3216120A5T Series. Any modifications or changes to the external designated antenna without permission is prohibited. USB oSy lei Blu The USB interface is a full speed Universal Serial Bus (USB) interface for communicating with other compatible digital devices. I50e acts as a USB peripheral, responding to requests from a Master host controller such as a Personal Computer (PC). oSy Synchronous Serial Interface lei This interface is a synchronous serial port interface (SPI) for interfacing with other digital devices. The SPI port can be used for i50e debugging. It can also be used for programming the Flash memory. UART Blu This interface is a standard Universal Asynchronous Receiver Transmitter (UART) interface for communicating with other serial devices. UART is usually used to operate i50e by ASCII commands from MCU. oSy PCM / I2S / SPDIF Interface lei This interface is a bi-directional serial programmable audio interface supporting PCM, I2S and SPDIF formats. Blu Audio Interface The audio interface of i50e has fully differential inputs and outputs and a microphone bias output. A high-quality stereo audio Bluetooth application can be implemented with minimum amount of external components. Programmable I/O oSy i50e has a total of 14 digital programmable I/O terminals. These are controlled by the firmware running on the device. lu Reset I50e has a reset circuitry that is used to reset the module in the startup to ensure proper operation of the flash memory. Alternatively, the reset can be externally driven by using a i50e reset pin. 7 / 58 i50e Datasheet 2 Electrical Characteristics 2.1 Absolute maximum ratings oSy lei The module should not continuously run under extreme conditions. The absolute maximum ratings are summarized in Table 1 below. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability and cause permanent damage to the device. Blu Table 1 Absolute Maximum Ratings Min Max Storage temperature -40 85 Operating temperature Supply voltage -40 -0.3 85 3.6 Terminal voltages Vss-0.4 Blu Ec Vdd + 0.4 Unit stem °C °C 2.2 Recommended Operating Conditions Recommended operating conditions are summarized in Table 2 below. Table 2 Recommended Operating Conditions oSy Operating temperature Min -30 Typ 20 Max 85 Unit °C VDD_IO VDD_BAT 1.7 2.5 3.3 3.3 3.6 4.4 3.3 6.5 Vdd lei VDD_CHG Terminal voltages lu Bcharacteristics 2.3 Terminal oSy BlueSoleil i50e’s terminal characteristics are summarized in Table 3 below. Table 3 Terminal Characteristics lu I/O voltage levels VIL input logic level low VIH input logic level high VOL output logic level low VOH output logic level high Reset terminal VTH,res threshold voltage Min Typ Max Unit -0.4 0.7×Vdd 0.75×Vdd 0.8 Vdd + 0.4 0.2 VDD 0.64 0.85 1.5 8 / 58 i50e Datasheet RIRES input resistance 220 kΩ CIRES input capacitance Input and tri-state current with Strong pull-up 220 nF -100 Sy -40 eil Strong pull-down Weak pull-up Weak pull-down I/O pad leakage current LED driver pad Off current On resistance(Vpad) On resistance, pad enabled by battery charger(Vpad< 0.5V) 2.4 Battery charger Blu -10 µA 10 -5 40 -1 100 -0,2 µA µA 0,2 µA -1 µA 20 33 µA Ω 20 50 Ω oSy lei BlueSoleil i50e’s battery charger characteristics are summarized in Table 4 below. Table 4 Battery Charger Characteristic VDD_CHG Supply current (a) Min Typ. Max Unit 4.5 6.5 4.5 14 mA mA Battery trickle charge current (b) (c) Maximum setting Minimum setting mA Maximum battery fast charge current (d) (c) HeadrooTHD+N 16Ω load m = 0.3 V Headroom > 0.7 V (e) 140 mA 120 40 0.1 mA mA 35 2.9 mA eS Blu Minimum battery fast charge current (d) (c) oSy Headroom > 0.7 V Headroom = 0.3 V Trickle charge voltage threshold Float voltage (with correct trim value set), VFLOAT(f) Float voltage trim step size (f) Battery charge termination current, as a percentage of the fast charge current 4.2 4.23 50 mV 10 20 1.5 -5 3.9 3.7 0.22 200 mA μA mV il Supply current (a) Battery current Battery recharge hysteresis (g) VDD_CHG under-voltage VDD_CHG rising threshold VDD_CHG falling VDD_CHG - BAT_P lockout VDD_CHG rising oSy 4.17 100 9 / 58 i50e Datasheet threshold VDD_CHG falling Supply current Battery current 0.17 -1 1.5 mA μA oSy (a) Current into VDD_CHG - does not include current delivered to battery (I VDD_CHG - I BAT_P) (b) BAT_P < Float voltage lei (c) Charge current can be set in 16 equally spaced steps (d) Trickle charge threshold < BAT_P < Float voltage Blu (e) Where headroom = VDD_CHG - BAT_P (f) Float voltage can be adjusted in 15 steps. Trim setting is determined in production test and must be loaded into the battery charger by firmware during boot-up sequence (g) Hysteresis of (VFLOAT - BAT_P) for charging to restart 2.5 CODEC Characteristics Blu oSy lei BlueSoleil i50e’s battery charger characteristics are summarized in Table 5 and Table 6 below. Table 5 Stereo CODEC ADC Characteristics Parameter Conditions Resolution Input Sample Rate, Fsample Fsample lu THD+N 100kΩ load SNR (Load = 16Ω, 0dBFS input relative to digital silence) Stereo CODEC Digital to Analog Converter Parameter Conditions Resolution Input Sample Rate, Fsample Typ Max Unit 16 Bits oSy 8 kHz 11.025 kHz Signal to Noise 16 kHz Ratio, SNR 22.050 kHz 32 kHz 44.1 kHz Digital Gain Digital Gain Resolution = 1/32dB Analogue Gain Analogue Gain Resolution = 3dB Output voltage full scale swing (differential) Allowed Load ResistiveCapacitive fin = 1kHz B/W = 20Hz→20kHz A-Weighted THD+N < 1% 150mVpk-pk input Min 48 kHz -24 16(8) 95 95 95 95 95 95 750 21.5 -21 OC 500 dB dB dB dB dB dB dB dB mV rms Ω pF 95 0.01 dB Min Typ Max 16 Unit Bits 48 kHz oSy 10 / 58 i50e Datasheet Table 6 Stereo CODEC DAC Characteristics Parameters oSy Conditions Resolution Input Sample Rate, Fsample Min Typ Max Unit 16 Bits 44.1 kHz Fsample 8 kHz 82 dB 11.025 kHz 81 dB 16 kHz 22.050 kHz 80 79 dB dB 32 kHz 79 dB 78 dB -24 -3 21.5 42 dB dB mV rms 800 20 6.0 mV rms kHz kΩ 0.04 lei Blu fin = 1kHz B/W = 20Hz→20kHz A-Weighted THD+N < 1% 150mVpk-pk input Signal to Noise Ratio, SNR oSy 44.1 kHz Digital Gain Analogue Gain Digital Gain Resolution = 1/32dB Analogue Gain Resolution = 3dB ei Input full scale at maximum gain (differential) Input full scale at minimum gain (differential) 3dB Bandwidth Microphone mode input impedance THD+N (microphone input) @ 30mV rms input oSy 2.6 Current Consumption lei BlueSoleil i50’s current consumption is summarized in Table 7 below. Table 7 Current Consumption lu Operation Mode Inquiry and Page scan No data traffic after connecting mobile phone Stereo music traffic (e)SCO traffic, that is, hands-free Connection Type UART Rate (kbps) Average Unit mA 9.6 4.2 mA Slave Master Slave Master 9.6 115.2 9.6 115.2 Ec stem 30 28 34.7 29 oand General Specifications 2.7 Radio Characteristics Blu mA mA mA mA BlueSoleil i50’s radio characteristics and general specifications are summarized in Table 8 below. 11 / 58 i50e Datasheet Table 8 Radio Characteristics and General Specifications Specification Operating frequency range Lower quard band oSy (2400 ... 2483,5) MHz Upper quard band 2 MHz lei 3,5 MHz Blu Carrier frequency 2402 MHz ... 2480 MHz Modulation method GFSK (1 Mbps) P/4 DQPSK (2Mbps) Hopping 1600 hops/s, 1 MHz channel space Asynchronous, 723.2 kbps / 57.6 kbps GFSK Synchronous: 433.9 kbps / 433.9 kbps P/4 DQPSK Maximum data rate Blu Receiver IF frequency Transmission power RF input impedance Compliance Min Max ISM Band f = 2402 + k, k = 0...78 Asynchronous, 1448.5 kbps / 115.2 kbps Synchronous: 869.7 kbps / 869.7 kbps Asynchronous, 2178.1 kbps / 177.2 kbps Synchronous: 1306.9 kbps / 1306.9 kbps 8DQPSK Receiving signal range oSy Note lei -82 to -20 dBm Typical condition 1.5 MHz Center frequency -11 ... -9 dBm +1 ... +3 dBm oSy Bluetooth specification, version 2.0 + EDR 3 Pin Descriptionolei Bl USB specification USB specification, version 1.1 (USB 2.0 compliant) BlueSoleil i50e’s PIN description refers to Figure 3 and Table 9. lu oSy 12 / 58 i50e Datasheet oSy lei Blu oSy lei Figure 3 i50e PIN Diagram (Top View) Blu Table 9 PIN Definition PIN NO. Name Type AIO1 Bi-directional AIO0 Bi-directional RESET GND lu Function oSy Programmable input/output line lei Programmable input/output line CMOS Input with weak internal pull-up Reset if low. Input debounced so must be 5ms to cause a reset GND Ground PIO9 Bi-directional Programmable input/output line PIO10 Bi-directional Programmable input/output line PIO11 Bi-directional Programmable input/output line PIO12 Bi-directional Programmable input/output line PIO13 Bi-directional Programmable input/output line lu oSy 13 / 58 i50e Datasheet 10 PIO14 Bi-directional Programmable input/output line 11 PIO15 Bi-directional 12 GND GND 13 VDD_IO Power 14 VDD_USB Power 15 VDD_1.8V_OUT Power +1.8V power output 16 GND GND Ground 17 USB_DP Bi-directional 18 USB_DN Bi-directional USB Date minus 19 UART_RTS CMOS Output UART Request to Send (active low) 20 UART_CTS CMOS Input UART Clear to Send (active low) 21 UART_RX CMOS Input UART Data input 22 UART_TX CMOS Output 23 PCM_IN CMOS Input 24 PCM_SYNC Bi-directional Synchronous data Sync 25 PCM_CLK Bi-directional Synchronous data clock 26 PCM_OUT CMOS Output Synchronous data output 27 NC 28 NC 29 NC 30 NC lei oSy Blu Blu Programmable input/output line Ground +3.3V power supply Positive supply for UART/USB ports oSy lei Blu USB Date plus oSy lei UART Data output Synchronous data input lu oSy Used for manufactory Used for manufactory Used for manufactory Used for manufactory 14 / 58 i50e Datasheet 31 VRE_IN analogue Take high to enable Battery terminal +ve oSy Lithium ion/polymer battery positive 32 VDD_BAT 33 GND lei Blu GND terminal. Battery charger output and input to switch- mode regulator Ground 34 VDD_CHG Charger input Lithium ion/polymer battery charger input 35 LED1 Open drain output LED driver 36 LED0 Open drain output LED driver 37 GND GND Ground 38 SPK_L_N Analogue 39 SPK_L_P Analogue Speaker output positive , 40 SPK_R_N Analogue Speaker output negative , right 41 SPK_R_P Analogue Speaker output positive , right 42 GND GND 43 MIC_BIAS Analogue 44 MIC_B_P Analogue Microphone input positive , right 45 MIC_B_N Analogue Microphone input negative , right 46 MIC_A_P Analogue Microphone input positive , left 47 MIC_A_N Analogue Microphone input negative , left 48 GND GND Ground 49 PIO0 Bi-directional Programmable input/output line Blu oSy lei Blu Speaker output negative , left oSy lei Ground Microphone bias lu left oSy 15 / 58 i50e Datasheet 50 PIO1 Bi-directional 51 PIO2 Bi-directional 52 PIO3 Bi-directional 53 GND GND 54 RF I/O RF 55 GND GND Ground 56 PIO4 Bi-directional Programmable input/output line 57 PIO5 Bi-directional 58 PIO6 59 PIO7 60 PIO8 oSy lei Blu Blu Programmable input/output line Programmable input/output line Ground RF Interface oSy lei Programmable input/output line Bi-directional Programmable input/output line Bi-directional Programmable input/output line Bi-directional Programmable input/output line GND Blu oSy lei Connect GND pins to the ground plane of PCB. GND_S Programmable input/output line Analog Ground .Connect GND_S pin to the ground plane of PCB with ferrite bead. VDD_IO Supply voltage connection for the digital I/Os of the module. Supply voltage at this pin can vary between 1.8 V and 3.3 V. Output voltage swing at the digital terminals of i50e is 0 to VDD_IO. lu VDD_USB Positive supply for UART/USB ports. VDD_BAT oSy Input for an internal 1.8 V switched mode regulator combined with output of the internal battery charger. See chapter 4.2 for detailed description for the charger. When not powered from a battery, VDD_IO and VDD_BAT can be combined to a single 3.3 V supply voltage. 16 / 58 i50e Datasheet VRE_IN Enable pin for the internal 1,8 V regulator. This pin should be combined to a 3.3V supply voltage. VDD_CHG oSy lei Charger input voltage. The charger will start operating when voltage to this pin is applied. When the charger is not used, this pin should be left floating. See chapter 4.2 for detailed description of the charger. RESET Blu The RESET pin is an active low reset. A reset will be performed between 1.5 and 4.0ms following RESET being active. It is recommended that RESET be applied for a period greater than 5ms. PIO0 – PIO15 oSy lei Programmable digital I/O lines. All PIO lines can be configured through software to have either weak or strong pull-ups or pull-downs. Configuration for each PIO line depends on the application. Default configuration for unused PIO lines is low. Blu AIO0 – AIO1 AIOs can be used to monitor analogue voltages such as a temperature sensor for the battery charger. AIOs can also be configured to be used as digital I/Os. The voltage level at these pins is 0 V to 1.5 V. UART_RTS oSy lei CMOS output with weak internal pull-up. Can be used to implement RS232 hardware flow control where RTS (request to send) is active low indicator. UART interface requires external RS232 transceiver chip. UART_CTS Blu CMOS input with weak internal pull-down. Can be used to implement RS232 hardware flow control where CTS (clear to send) is active low indicator. UART interface requires external RS232 transceiver chip. UART_RXD lu oSy CMOS input with weak internal pull-down. UART_RXD is used to implement UART data transfer from another device to i50e. UART interface requires external RS232 transceiver chip. UART_TXD CMOS output with weak internal pull-up. TXD is used to implement UART data transfer from i50e to another device. UART interface requires external RS232 transceiver chip. PCM_OUT 17 / 58 i50e Datasheet CMOS output with weak internal pull-down. Used in PCM (pulse code modulation) interface to transmit digitized audio. The PCM interface is shared with the I2S interface. oSy PCM_IN CMOS input with weak internal pull-down. Used in PCM interface to receive digitized audio. The PCM interface is shared with the I2S interface. lei Blu PCM_CLK Bi-directional synchronous data clock signal pin with weak internal pull-down. PCM_CLK is used in PCM interface to transmit or receive CLK signal. When configured as a master, i50e generates clock signal for the PCM interface. When configured as a slave PCM_CLK is an input and receives the clock signal from another device. oSy PCM_SYNC A bi-directional synchronous data strobe with weak internal pull-down. When configured as a master, i50e generates SYNC signal for the PCM interface. When configured as a slave PCM_SYNC is an input and receives the SYNC signal from another device. USB_D+ Blu lei Bi-directional USB data line with a selectable internal 1.5 k pull-up implemented as a current source (compliant with USB specification v1.2) External series resistor is required to match the connection to the characteristic impedance of the USB cable. oSy USB_D- Bi-directional USB data line. External series resistor is required to match the connection to the characteristic impedance of the USB cable. RF Blu lei Connect external RF-transceiver antenna to this pin. MIC_B_N and MIC_B_P Right channel audio inputs. This dual audio input can be configured to be either single-ended or fully differential and programmed for either microphone or line input. Route differential pairs close to each other and use a solid dedicated audio ground plane for the audio signals. lu MIC_A_N and MIC_A_P oSy Left channel audio input. ESD protection and layout considerations similar to right channel audio should be used. SPK_B_N and SPK_B_P Right channel audio output. The audio output lines should be routed differentially to either the speakers or to the output amplifier, depending on whether or not a single-ended signal is 18 / 58 i50e Datasheet required. Use low impedance ground plane dedicated for the audio signals. SPK_A_N and SPK_A_P oSy Left channel audio output. The same guidelines apply to this section as discussed previously. lei MIC_BIAS Bias voltage output for a microphone. Use the same layout guidelines as discussed previously with other audio signals. LED0/1 Blu I50e includes a pad dedicated to driving LED indicators. This terminal may be controlled by firmware and it can also be set by the battery charger. The terminal is an open-drain output, so the LED must be connected from a positive supply rail to the pad in series with a current limiting resistor. It is recommended that the LED pad is operated with a pad voltage below 0.5V. In this case, the pad can be thought of as a resistor, RON. The resistance together with the external series resistor will set the current, ILED, in the LED. Value for the external series resistance can be calculated from the Equation 1. Blu oSy lei Equation 1 LED Series Resistor oSy Where VF is the forward voltage drop of the LED, ILED is the forward current of the LED and RON is on resistance (typically 20 Ω) of the LED driver. lei 4 Power Management 4.1 Power Management Blu Block BlueSoleil i50e contains an internal battery charger and a switch mode regulator that is mainly used for internal blocks of the module. See Figure 4 below. The module can be powered from a single 3.3 V supply provided that VDD_CHG is floating. Alternatively the module can be powered from a battery connected to VDD_BAT and using an external regulator for VDD_IO. 1.8 V to 3.3 V supply voltage for VDD_IO can be used to give desired signal levels for the digital interfaces of the module. USB, however, requires 3.3 V for proper operation and thus, when USB is in use, 3.3 V for VDD_IO is mandatory.AIO pins of the module use 1.8 V from the internal regulator and thus voltage level with these pins is within 0 V and 1.8 V. lu oSy VRE_IN is used to enable the on-chip regulator of i50e and should be taken high. 19 / 58 i50e Datasheet oSy lei Blu Blu oSy lei Figure 4 Power Management Block 4.2 Battery Charger oSy The battery charger is a constant current / constant voltage charger circuit, and is suitable for lithium ion/polymer batteries only. It shares a connection to the battery terminal, VDD_BAT, with the switch-mode regulator. Blu lei The constant current level can be varied to allow charging of different capacity batteries. I50e allows a number of different currents to be used in the battery charger hardware. Values written to PS key 0x039b CHARGER_CURRRENT in the range 1~15 specify the charger current from 40~135mA in even steps.Values outside the valid 0~15 range result in no change to the charging current. The default charging current (Key = 0) is nominally 40mA. Setting 0 is interpreted as “no-change” so will be ignored. The charger enters various states of operation as it charges a battery, including the following status: oSy Off: entered when the charger is disconnected. Trickle Charge: entered when the battery voltage is below 2.9V. Fast Charge - Constant Current: entered when the battery voltage is above 2.9V. Fast Charge - Constant Voltage: entered when the battery has reached Vfloat, the charger switches mode to maintain the cell voltage at Vfloatvoltage by adjusting the constant charge current. Standby: this is the state when the battery is fully charged and no charging takes place. lu 20 / 58 i50e Datasheet When a voltage is applied to the charger input terminal VDD_CHG, and the battery is not fully charged, the charger will operate and a LED connected to the terminal LED0 will illuminate. By default, until the firmware is running, the LED will pulse at a low-duty cycle to minimize current consumption. The battery charger circuitry auto-detects the presence of a power source, allowing the firmware to detect, using an internal status bit, when the charger is powered. Therefore, when the charger supply is not connected to VDD_CHG, the terminal must be left open circuit. The VDD_CHG pin, when not connected, must be allowed to float and not be pulled to a power rail. When the battery charger is not enabled, this pin may float to a low undefined voltage. Any DC connection will increase current consumption of the device. Capacitive components such as diodes, FETs, and ESD protection, may be connected. The battery charger is designed to operate with a permanently connected battery. If the application permits the charger input to be connected while the battery is disconnected, the VDD_BAT pin voltage may become unstable. This, in turn, may cause damage to the internal switch-mode regulator. Connecting a 470uF capacitor to VDD_BAT limits these oscillations thus preventing damage. oSy lei Blu oSy 5 Serial Interfaces lu 5.1 UART Interface oSy BlueSoleil I50e Universal Asynchronous Receiver Transmitter (UART) interface provides a simple mechanism for communicating with other serial devices using the RS232 standard. See Figure 5 below. The UART interface of i50e uses voltage levels of 0 to Vdd and thus external transceiver IC is required to meet the voltage level specifications of UART. Blu lei lu oSy Figure 5 i50e UART interface Table 10 Possible UART Settings 21 / 58 i50e Datasheet Parameters Possible Values 1200 baud (≤2%Error) Minimum Maximum Flow control Parity oSy 9600 baud (≤1%Error) Baud rate 3.0Mbaud (≤1%Error) lei Blu Number of stop bits Bits per channel RTS/CTS, none None, Odd, Even 1 or 2 Four signals are used to implement the UART function, as shown in Figure 5. When i50e is connected to another digital device, UART_RX and UART_TX transfer data between the two devices. The remaining two signals, UART_CTS and UART_RTS, can be used to implement RS232 hardware flow control where both are active low indicators. DTR, DSR and DCD signals can be implemented using PIO terminals of i50e. All UART connections are implemented using CMOS technology and have signaling levels of 0V and VDD. In order to communicate with the UART at its maximum data rate using a standard PC, an accelerated serial port adapter card is required for the PC. Blu oSy lei The UART interface is capable of resetting i50e upon reception of a break signal. A Break is identified by a continuous logic low (0V) on the UART_RX terminal, as shown in Figure 6. If tBRK is longer than the value, defined by the PS Key PSKEY_HOST_IO_UART_RESET_TIMEOUT, (0x1a4), a reset will occur. This feature allows a host to initialize the system to a known state. Also, i50e can emit a Break character that may be used to wake the Host. See Figure 6 below. Blu oSy lei Figure 6 Break Signal oSy Since UART_RX terminal includes weak internal pull-down, it can’t be left open unless disabling UART interface using PS_KEY settings. If UART is not disabled, a pull-up resistor has to be connected to UART_RX. UART interface requires external RS232 transceiver, which usually includes the required pull-up. lu Table 11 shows a list of commonly used Baud rates and their associated values for the Persistent Store Key PSKEY_UART_BAUD_RATE (0x204). There is no requirement to use these standard values. Any Baud rate within the supported range can be set in the Persistent Store Key according to the formula in Equation 2 below. 22 / 58 i50e Datasheet oSy Equation 2 Baud Rate Calculation Formula lei Blu Table 11 UART Baud Rates and Error Values Persistent store values Baud Rate 1200 Hex Error Dec 0x0005 1.73% 0x000a 10 1.73% 4800 0x0014 20 9600 19200 38400 0x0027 0x004f 0x009d 39 79 157 -0.82% 0.45% -0.18% 57600 76800 0x00ec 0x013b 263 315 0.03% 0.14% 472 0.03% 0x03b0 0x075f 0x0ebf 944 1887 3775 0.03% -0.02% 0.00% 1382400 0x161e 5662 -0.01% 1843200 2765800 0x1d7e 0x2c3d 7550 11325 2400 115200 230400 460800 921600 oSy ei lue 0x01d8 1.73% eSo stem Ec 0.00% 0.00% 5.1.1 UART Configuration While RESET is Active Blu The UART interface for i50e while the chip is being held in reset is tri-state. This will allow the user to daisy chain devices onto the physical UART bus. The constraint on this method is that any devices connected to this bus must tri-state when i50e reset is de-asserted and the firmware begins to run. 5.1.2 UART Bypass Mode lu oSy Alternatively, for devices that do not tri-state the UART bus, the UART bypass mode on i50e can be used. The default state of i50e after reset is de-asserted, this is for the host UART bus to be connected to the i50e UART, thereby allowing communication to i50e via the UART. In order to apply the UART bypass mode, a BCCMD command will be issued to i50e upon this, it will switch the bypass to PIO[7:4] as shown in Figure 7. Once the bypass mode has been invoked, i50e will enter the deep sleep state indefinitely. 23 / 58 i50e Datasheet In order to re-establish communication with i50e, the chip must be reset so that the default configuration takes affect. oSy It is important for the host to ensure a clean Bluetooth disconnection of any active links before the bypass mode is invoked. Therefore it is not possible to have active Bluetooth links while operating the bypass mode. lei The current consumption for a device in UART Bypass Mode is equal to the values quoted for a device in standby mode. See Figure 7 below. Blu Blu oSy lei Figure 7 UART Bypass Mode 5.2 SPI Interface Blu oSy lei The synchronous serial port interface (SPI) is for interfacing with other digital devices. The SPI port can be used for system debugging. It can also be used for programming the Flash memory. SPI interface is connected using the MOSI, MISO, CSB and CLK pins. SPI interface is only used for debugging and updating firmware. 6 Audio Interfaces 6.1 Audio Interface Blu oSy The audio interface circuit consists of the following components. Stereo audio CODEC 24 / 58 i50e Datasheet Dual audio inputs and outputs A configurable PCM, I2S or SPDIF interface oSy Figure 8 below outlines the functional blocks of the interface. The CODEC supports stereo playback and recording of audio signals at multiple sample rates with a resolution of 16-bit. The ADC and the DAC of the CODEC each contain two independent channels. Any ADC or DAC channel can be run at its own independent sample rate. lei Blu Blu oSy lei Figure 8 Audio Interface The interface for the digital audio bus shares the same pins as the PCM CODEC interface, which means that each of the audio buses are mutually exclusive in their usage. These alternative functions are summarized in Table 12 below. oSy Table 12 Alternative functions of the digital audio bus interface on the PCM interface PCM Interface PCM_OUT PCM_IN PCM_SYNC SPDIF Interface SPDIF_OUT SPDIF_IN PCM_CLK 6.1.1 Audio Input and Output I2S Interface SD_OUT SD_IN WS SCK oSy The audio input circuitry consists of a dual audio input that can be configured to be either single-ended or fully differential and programmed for either microphone or line input. It has an analogue and digital programmable gain stage for optimization of different microphones. lu Audio signals are very sensitive to noise caused by the Bluetooth radio and it is highly recommended to always use fully differential signals. The audio output circuitry consists of a dual differential class A-B output stage. 25 / 58 i50e Datasheet 6.2 Stereo Audio CODEC Interface oSy The main features of the interface are as follows. Stereo and mono analogue input for voice band and audio band Stereo and mono analogue output for voice band and audio band Support for stereo digital audio bus standards such as I2S Support for IEC-60958 standard stereo digital audio bus standards, e.g. S/PDIF and AES3/EBU Support for PCM interfaces including PCM master CODECs that require an external system clock lei Blu Blu oSy lei Blu oSy lei Figure 9 Stereo CODEC Audio Input and output Stages The stereo audio CODEC uses a fully differential architecture in the analogue signal path, which results in low noise sensitivity and good power supply rejection while effectively doubling the signal amplitude. It operates from a single power-supply of 1.5V and uses a minimum of external components. 6.2.1 ADC lu oSy The ADC consists of two second-order Sigma Delta converters allowing two separate channels that are identical in functionality, as shown in Figure 10. Each ADC supports the following sample rates: 26 / 58 i50e Datasheet 8kHz 11.025kHz 16kHz 22.05kHz 24kHz 32kHz 44.1kHz oSy lei Blu The ADC contains two gain stages for each channel, an analogue and a digital gain stage. The digital gain stage has a programmable selection value in the range of 0 to 15 with the associated ADC gain settings summarized in Table 13 below. There is also a high resolution digital gain mode that allows the gain to be changed in 1/32dB steps. Please contact IVT Corporation for more information. oSy lei Table 13 ADC Digital Gain Rate Selection Blu Gain Selection Value 3.5 9.5 12 15.5 10 11 oSy ADC Digital Gain Setting (dB) 12 13 14 15 lu 18 21.5 -24 -20.5 -18 -14.5 -12 -8.5 -6 oSy -2.5 The ADC analogue amplifier is a two-stage amplifier. The first stage of the analogue amplifier is responsible for selecting the correct gain for either microphone input or line input and, therefore, has two gain settings, one for the microphone and one for the line input. Refer to the chapter 6.2.4 and 6.2.5. In simple terms, the first stage amplifier has a selectable 24dB gain stage for the microphone and this creates the dual programmable gain required for the microphone or the line input. The equivalent block diagram for the two stages is shown in Figure 10 below. 27 / 58 i50e Datasheet oSy lei Blu Blu oSy lei Figure 10 ADC Analogue Amplifier Block Diagram The second stage of the analogue amplifier shown in Figure 10 has a programmable gain with seven individual 3dB steps. In simple terms, by combining the 24dB gain selection of the microphone input with the seven individual 3dB gain steps, the overall range of the analogue amplifier is approximately -3dB to 42dB in 3dB steps. The overall gain control of the ADC is controlled by a VM function. 6.2.2 DAC Blu oSy lei The DAC consists of two third-order Sigma Delta converters allowing two separate channels that are identical in functionality as shown in Figure 10 above. Each DAC supports the following samples rates: 8kHz 11.025kHz 16kHz 22.050kHz 24kHz 32kHz 44.1kHz 48kHz lu oSy The default setting for A2DP is 44.1 kHz and for HFP 8 kHz. 28 / 58 i50e Datasheet The DAC contains two gain stages for each channel: a digital and an analogue gain stage. The digital gain stage has a programmable selection value in the range of 0 to 15 with associated DAC gain settings. This is summarized in Table 14. There is also a high resolution digital gain mode that allows the gain to be changed in 1/32dB steps. Please contact IVT Corporation for more information. oSy lei Table 14 DAC Digital Gain Rate Selection Blu Gain Selection Value ADC Digital Gain Setting (dB) 3.5 9.5 12 ei lue 10 11 oSy 15.5 18 21.5 -24 -20.5 -18 -14.5 12 13 -12 -8.5 14 15 -6 -2.5 oSy lei The DAC analogue amplifier has a programmable gain with seven individual 3dB steps. The overall gain control of the DAC is controlled by a VM function. This setting is a combined function of the digital and analogue amplifier settings , therefore, for a 1V rms nominal digital output signal from the digital gain stage of the DAC, the following approximate output values of the analogue amplifier of the DAC can be expected: Blu Table 15 DAC Analogue Gain Rate Selection Analogue Gain Setting lu oSy DAC Gain Setting (dB) -3 -6 -9 -12 -15 -18 29 / 58 i50e Datasheet 6.2.3 IEC 60958 Interface oSy The IEC 60958 interface is a digital audio interface that uses bi-phase coding to minimize the DC content of the transmitted signal and allows the receiver to decode the clock information from the transmitted signal. The IEC 60958 specification is based on the two industry standards AES/EBU and the Sony and Philips interface specification SPDIF. The interface is compatible with IEC 60958-1, IEC 60958-3 and IEC 60958-4. lei Blu The SPDIF interface signals are SPDIF_IN and SPDIF_OUT and are shared on the PCM interface pins. The input and output stages of the SPDIF pins can interface either to a 75Ω Coaxial cable with an RCA connector. See Figure 11 below. Or there is an option to use an optical link that uses Toslink optical components. See Figure 12 below. Blu oSy lei oSy Figure 11 Example circuit for SPDIF interface (Co-Axial) Blu lei lu oSy Figure 12 Example circuit for SPDIF interface (Optical) 6.2.4 Microphone Input The audio-input is intended for use from 1μA@94dB SPL to about 10μA@94dB SPL. With biasing resistors R1 and R2 equal to 1kΩ, this requires microphones with sensitivity between about -40dBV and -60dBV. 30 / 58 i50e Datasheet The MIC_BIAS is like any voltage regulator and requires a minimum load to maintain regulation. The MIC_BIAS will maintain regulation within the limits 0.2~1.53 mA depending on the bias current setting. This means that if a microphone that sits below these limits is used, the microphone output must be pre-loaded with a large value resistor to ground. oSy lei MIC_BIAS line either is used as an enable signal for an external biasing regulator. The default setting for the bias current in i50e is 0.2 mA and it is recommended to use an external low noise biasing regulator for the best noise performance. The recommended microphone biasing circuitry is shown in Figure 13 below. Blu Blu oSy lei Blu oSy lei Figure 13 Recommended Microphone Biasing (left channel shown) The input impedance at AUDIO_IN_N_LEFT, AUDIO_IN_P_LEFT, AUDIO_IN_N_RIGHT and AUDIO_IN_P_RIGHT is typically 6.0kΩ. C1 and C2 should be 150nF if bass roll-off is required to limit wind noise on the microphone. R1 sets the microphone load impedance and is normally in a range of 1 to 2kΩ. R2, C3 and C4 improve the supply rejection by decoupling supply noise from the microphone. Values should be selected as required. R1 may be connected to a convenient supply, in which case the bias network is permanently enabled, or to the output of the biasing regulator which may be configured to provide bias only when the microphone is required. lu oSy The microphone bias provides a 4-bit programmable output voltage with a 4-bit programmable output current, shown in Table 16 and Table 17. Table 16 Voltage Output Step Output Step Typical Voltage Level (V) 1.71 1.76 31 / 58 i50e Datasheet 1.82 1.87 1.95 2.02 oSy lei Blu 10 11 12 2.10 2.18 2.32 2.43 2.56 2.69 2.9 13 3.08 oSy 14 3.33 15 Table 17 Current Output Step lu Output Step 3.57 lei Typical Current (mA) 0.199 0.284 0.336 0.419 0.478 oSy 0.529 0.613 ei 10 11 12 lue 0.754 0.809 0.862 0.948 1.004 13 1.091 14 15 1.142 1.229 lu 6.2.5 Line Input 0.672 oSy If the input analogue gain is set to less than 21dB, i50e automatically selects line input mode. In line input mode, the first stage of the amplifier is automatically disabled, providing additional power saving. In line input mode, the input impedance varies from 6kΩ-30kΩ, depending on the volume setting. Figure 14 and Figure 15 show two circuits for line input operation and show connections for either differential or single-ended inputs. 32 / 58 i50e Datasheet oSy lei Blu Figure 14 Differential input (left channel shown) Blu oSy lei Figure 15 Single ended input (left channel shown) 6.2.6 Output Stage The output digital circuitry converts the signal from 16-bit per sample, linear PCM of variable sampling frequency to a 2Mbits/s 5-bit multi-bit bit stream, which is fed into the analogue output circuitry. oSy lei The output circuit is comprised of a digital to analogue converter with gain setting and an output amplifier. Its class AB output stage is capable of driving a signal on both channels of up to 2Vpk-pk differential into a load of 16Ω. The output is available as a differential signal between AUDIO_OUT_N_LEFT and AUDIO_OUT_P_LEFT for the left channel. See Figure 16 below; and between AUDIO_OUT_N_RIGHT and AUDIO_OUT_P_RIGHT for the right channel. The output is capable of driving a speaker directly if its impedance is at least 8Ω at reduced output swing and if only one channel is connected or an external regulator is used. Blu lu oSy Figure 16 Speaker Output (left channel shown) The analogue gain of the output stage is controlled by a 3-bit programmable resistive divider, which sets the gain in steps of approximately 3dB. 33 / 58 i50e Datasheet The multi-bit bit stream from the digital circuitry is low pass filtered by a third order filter with a pole at 20 kHz. The signal is then amplified in the fully differential output stage, which has a gain bandwidth of typically 1MHz. 6.2.6.1 Mono Operation oSy lei Mono operation is a single-channel operation of the stereo CODEC. The left channel represents the single mono channel for audio in and audio out. In mono operation, the right channel is an auxiliary mono channel that may be used in dual mono channel operation. Blu With single mono, the power consumption can be reduced by disabling the other channel. 6.2.6.2 Side Tone oSy In some applications, it is necessary to implement a side tone. This involves feeding an attenuated version of the microphone signal to the earpiece. The BlueCore5.Multimedia External CODEC contains a side tone circuitry to do this. The side tone hardware is configured through the following PS Keys: Blu PSKEY_SIDE_TONE_ENABLE lei PSKEY_SIDE_TONE_GAIN PSKEY_SIDE_TONE_AFTER_ADC oSy PSKEY_SIDE_TONE_AFTER_DAC lei 6.2.6.3 Integrated Digital Filter TBA Blu 6.3 Digital Audio Interface (I2S) The digital audio interface supports the industry standard formats for I2S, left-justified (LJ) or right-justified (RJ). The interface shares the same pins as the PCM interface, which means that each audio bus is mutually exclusive in its usage. These alternative functions are summarized in Table 18 below. Figure 17 shows the timing diagram. lu oSy Table 18 Alternative Functions of the Digital Audio Bus Interface on the PCM Interface PCM Interface PCM_OUT PCM_IN PCM_SYNC PCM_CLK I2S Interface SD_OUT SD_IN WS SCK 34 / 58 i50e Datasheet oSy lei Blu Blu oSy lei oSy Figure 17 Digital Audio Interface Modes Table 19 below introduces the values for the PS Key (PSKEY_DIGITAL_AUDIO_CONFIG) that is used to set-up the digital audio interface. For example, to configure an I2S interface with 16-bit SD data set PSKEY_DIGITAL_CONFIG to 0x0406. Blu lei Table 19 PSKEY_DIGITAL_AUDIO_CONFIG Bit Mask D[0] 0x0001 CONFIG_JUSTIFY_FORMAT D[1] 0x0002 CONFIG_LEFT_JUSTIFY_DELAY D[2] 0x0004 D[3] 0x0008 Name Description 0 for left justified, 1 for right justified. oSy For left justified formats: 0 is MSB of SD data occurs in the first SCLK period following WS transition. 1 is MSB of SD data occurs in the second SCLK period. lu CONFIG_CHANNEL_POLARITY For 0, SD data is left channel when WS is high. For 1 SD data is right channel. CONFIG_AUDIO_ATTEN_EN For 0, 17 bit SD data is rounded down to 16 bits. For 1, the audio attenuation defined 35 / 58 i50e Datasheet in CONFIG_AUDIO_ATTEN is applied over 24 bits with saturated rounding. Requires CONFIG_16_BIT_CROP_EN to be 0. D[7:4] 0x00F0 CONFIG_AUDIO_ATTE D[9:8] 0x0300 CONFIG_JUSTIFY_RESOLUTION D[10] oSy Attenuation in 6 dB steps. lei Resolution of data on SD_IN, 00=16 bit, Blu 0x0400 01=20 bit, 10=24 bit, 11=Reserved. This is required for right justified format and with left justified LSB first. CONFIG_16_BIT_CROP_EN Blu For 0, 17 bit SD_IN data is rounded down to 16 bits. For 1 only the most significant 16 bits of data are received. oSy lei The internal representation of audio samples withinBlueCore5.Multimedia External is 16-bit and data on SD_OUT is limited to 16-bit per channel. Digital audio interface slave timing refers to Table 20 and Figure 18 below. Table 20 Digital Audio Interface Slave Timing Symbol Parameter Min Typ SCK Frequency WS Frequency tch tcl topd tssu tsh SCK high time SCK low time SCK to SD_OUT delay WS to SCK set-up time WS to SCK hold time 80 80 20 20 SD_IN to SCK set-up time SD_IN to SCK hole time 20 20 tisu tih eSo Blu Unit 6.2 96 MHZ kHz 20 -- ns ns ns ns ns ns ns stem Ec lu Max oSy 36 / 58 i50e Datasheet oSy lei Blu oSy lei Figure 18 Digital Audio Interface Slave Timing Blu Digital audio interface slave timing refers to Table 21 and Figure 19 below. Table 21 Digital Audio Interface Master Timing Symbol Parameter Min SCK Frequency WS Frequency topd tspd SCK to SD_OUT delay SCK to WS delay tisu tih SD_IN to SCK set-up time SD_IN to SCK hole time 20 20 Blu Typ Max lei oSy Unit 6.2 96 MHZ kHz 20 ns ns ns ns lu oSy 37 / 58 i50e Datasheet Figure 19 Digital Audio Interface Master Timing oSy 6.4 PCM Interface lei Pulse Code Modulation (PCM) is a standard method used to digitize audio (particularly voice) patterns for transmission over digital communication channels. Through its PCM interface, i50e has hardware support for continual transmission and reception of PCM data, thus reducing processor overhead for wireless headset applications. i50e offers a bi directional digital audio interface that routes directly into the baseband layer of the on chip firmware. It does not pass through the HCI protocol layer. Blu Hardware on i50e allows the data to be sent to and received from a SCO connection. Up to three SCO connections can be supported by the PCM interface at any one time. oSy i50e can operate as the PCM interface Master generating an output clock of 128, 256 or 512kHz.When configured as PCM interface slave it can operate with an input clock up to 2048kHz. i50e is compatible with a variety of clock formats, including Long Frame Sync, Short Frame Sync and GCI timing environments. Blu lei It supports 13 or 16-bit linear, 8-bit µ-law or A-law companded sample formats at 8k samples/s and can receive and transmit on any selection of three of the first four slots following PCM_SYNC. The PCM configuration options are enabled by setting the PS Key PS _KEY_PCM_CONFIG32 (0x1b3). i50e interfaces directly to PCM audio devices are follows: oSy Qualcomm MSM 3000 series and MSM 5000 series CDMA baseband devices OKI MSM7705 four channels A-law and µ-law CODEC lei Motorola MC145481 8-bit A-law and µ-law CODEC Blu Motorola MC145483 13-bit linear CODEC STW 5093 and 5094 14-bit linear CODECs BlueCore4-External is also compatible with the Motorola SSI™ interface 6.4.1 PCM Interface Master/Slave lu oSy When configured as the Master of the PCM interface, i50e generates PCM_CLK and PCM_SYNC. See Figure 20 below. 38 / 58 i50e Datasheet oSy lei Blu Figure 20 i50e as PCM Master When configured as the Slave of the PCM interface, i50e accepts PCM_CLK and PCM_SYNC. PCM_CLK rates up to 2048kHz are accepted. See Figure 21 below. Blu oSy lei oSy Figure 21 i50e as PCM slave 6.4.2 Long Frame Sync Blu lei Long Frame Sync is the name given to a clocking format that controls the transfer of PCM data words or samples. In Long Frame Sync, the rising edge of PCM_SYNC indicates the start of the PCM word. When i50e is configured as PCM Master, generating PCM_SYNC and PCM_CLK, then PCM_SYNC is 8-bits long. When BlueCore5 MM is configured as PCM Slave, PCM_SYNC may be from two consecutive falling edges of PCM_CLK to half the PCM_SYNC rate, i.e. 62.5µs long. oSy i50e samples PCM_IN on the falling edge of PCM_CLK and transmits PCM_OUT on the rising edge. PCM_OUT may be configured to be high impedance on the falling edge of PCM_CLK in the LSB position or on the rising edge. See Figure 22 below. lu 39 / 58 i50e Datasheet oSy lei Blu Figure 22 Long Frame Sync (shown with 8-bit Companded Sample) 6.4.3 Short Frame Sync oSy In Short Frame Sync the falling edge of PCM_SYNC indicates the start of the PCM word. PCM_SYNC is always one clock cycle long. See Figure 23 below. Blu lei oSy lei Figure 23 Short Frame Sync (shown with 16-bit Companded Sample) Blu As with Long Frame Sync, i50e samples PCM_IN on the falling edge of PCM_CLK and transmits PCM_OUT on the rising edge. PCM_OUT may be configured to be high impedance on the falling edge of PCM_CLK in the LSB position or on the rising edge. 6.4.4 Multi Slot Operation lu oSy More than one SCO connection over the PCM interface is supported using multiple slots. Up to three SCO connections can be carried over any of the first four slots. See Figure 24 below. 40 / 58 i50e Datasheet oSy lei Blu Figure 24 Multi Slot Operation with Two Slots and 8-bit Companded Samples 6.4.5 GCI Interface oSy lei i50e is compatible with the General Circuit Interface, a standard synchronous 2B+D ISDN timing interface. The two 64Kbps B channels can be accessed when this mode is configured. See Figure 25 below. Blu Blu oSy lei Figure 25 GCI Interface The start of frame is indicated by the rising edge of PCM_SYNC and runs at 8kHz. With i50e in Slave mode, the frequency of PCM_CLK can be up to 4.096MHz. 6.4.6 Slots and Sample Formats lu oSy i50e can receive and transmit on any selection of the first four slots following each sync pulse. Slot durations can be either 8 or 16 clock cycles. Duration’s of 8 clock cycles may only be used with 8-bit sample formats. Durations of 16 clocks may be used with 8, 13 or 16-bit sample formats. i50e supports 13-bit linear, 16-bit linear and 8-bit µ-law or A-law sample formats. The sample rate is 8ksamples/s. The bit order may be little or big Endian. When 16-bit slots are used, 41 / 58 i50e Datasheet the 3 or 8 unused bits in each slot may be filled with sign extension, padded with zeros or a programmable 3-bit audio attenuation compatible with some Motorola CODECs. See Figure 26 below. oSy lei Blu Figure 26 16-bit Slot with 13-bit Linear Sample and Audio Gain Selected 6.4.7 Additional Features oSy i50e has a mute facility that forces PCM_OUT to be 0. In Master mode, PCM_SYNC may also be forced to 0 while keeping PCM_CLK running which some CODECS use to control power down. 6.4.8 PCM Configuration Blu lei The PCM configuration is set using two PS Keys, PSKEY_PCM_CONFIG32 and PSKEY_PCM_LOW_JITTER_CONFIG. They are summarized in Table 22 and Table 23 below. The default for PSKEY_PCM_CONFIG32 key is 0x00800000 i.e. first slot following sync is active, 13-bit linear voice format, long frame sync and interface master generating 256kHz PCM_CLK from 4MHz internal clock with no tri-stating of PCM_OUT. Table 22 PSKEY_PCM_CONFIG32 Bit position Name SLAVE MODE EN SHORT SYNC EN SIGN EXTENDED EN Description Set to 0 0 selects Master mode with internal generation of PCM_CLK and PCM_SYNC. 1 selects Slave mode requiring externally generated PCM_CLK and PCM_SYNC. This should be set to 1 if 48M_PCM_CLK_GEN_EN (bit 11) is set. 0 selects long frame sync (rising edge indicates start of frame), 1 selects short frame sync (falling edge indicates start of frame). Set to 0 0 selects padding of 8 or 13-bit voice sample into a 16- bit slot by inserting extra LSBs, 1 selects sign extension. When padding is selected with 3-bit voice sample, the 3 padding bits are the audio gain setting; with 8-bit samples the 8 padding bits are zeroes. 0 transmits and receives voice samples MSB first, 1 uses LSB first. lu LSB FIRST EN oSy oSy 42 / 58 i50e Datasheet TX TRISTATE EN 0 drives PCM_OUT continuously, 1 tri-states PCM_OUT immediately after the falling edge of PCM_CLK in the last bit of an active slot, assuming the next slot is not active. oSy SYNC SUPPRESS EN GCI MODE EN 0 tristates PCM_OUT immediately after the falling edge of PCM_CLK in the last bit of an active slot, assuming the next slot is also not active. 1 tristates PCM_OUT after the rising edge of PCM_CLK. 0 enables PCM_SYNC output when master, 1 suppresses PCM_SYNC whilst keeping PCM_CLK running. Some CODECS utilize this to enter a low power state. 1 enables GCI mode. MUTE EN 10 1 forces PCM_OUT to 0. TX TRISTATE RISING EDGE EN lei Blu 48M PCM CLK GEN EN 11 Blu LONG LENGTH SYNC EN 12 [20:16] oSy 0 sets PCM_CLK and PCM_SYNC generation via DDS from internal 4 MHz clock, as for BlueCore4-External. 1 sets PCM_CLK and PCM_SYNC generation via DDS from internal 48 MHz clock. 0 sets PCM_SYNC length to 8 PCM_CLK cycles and 1 sets length to 16 PCM_CLK cycles. Only applies for long frame sync and with 48M_PCM_CLK_GEN_EN set to 1. Set to 0b00000. lei MASTER CLK RATE [22:21] Selects 128 (0b01), 256 (0b00), 512 (0b10) kHz PCM_CLK frequency when master and 48M_PCM_CLK_GEN_EN (bit 11) is low. ACTIVE SLOT [26:23] Default is 0001. Ignored by firmware [28:27] Selects between 13 (0b00), 16 (0b01), 8 (0b10) bit sample with 16 cycle slot duration 8 (0b11) bit sample 8 cycle slot duration. SAMPLE_FORMAT Blu oSy lei Table 23 PSKEY_PCM_LOW_JITTER_CONFIG Name CNT LIMIT CNT RATE SYNC LIMIT Bit position [12:0] [23:16] [31:24] Description oSy Sets PCM_CLK counter limit Sets PCM_CLK count rate. Sets PCM_SYNC division relative to PCM_CLK. 7 Softwarelu B Stacks i50e is supplied with Bluetooth v2.1 + EDR compliant stack firmware, which runs on the internal RISC microcontroller. The i50e software architecture allows Bluetooth processing and the 43 / 58 i50e Datasheet application program to be shared in different ways between the internal RISC microcontroller and an external host processor (if any). oSy 7.1 BlueSoleil Stack lei Blu Blu oSy lei lu oSy lei Figure 27 BlueSoleil Stack As illustrated in Figure 27 above, no host processor is required to run the Bluetooth protocol stack. All BlueSoleil stack layers, including application software, run on the internal RISC processor. oSy The host processor interfaces to BlueSoleil stack of i50e via one or more of the physical interfaces, which are also shown in the figure 27. The most common interfacing is done via UART interface using the ASCII commands supported by the BlueSoleil stack. With these ASCII commands the user can access Bluetooth functionality without paying any attention to the complexity, which lies in the Bluetooth protocol stack. lu The user may write applications code to run on the host processor to control BlueSoleil stack with ASCII commands and to develop Bluetooth powered applications. Please refer to BlueSoleil_I50e_Programming_Manual.pdf. 44 / 58 i50e Datasheet 8 Enhanced Data Rate oSy EDR has been introduced to provide 2x and optionally 3x data rates with minimal disruption to higher layers of the Bluetooth stack. CSR supports both of the new data rates, with i50e. lei Blu 8.1 Enhanced Data Rate Baseband At the baseband level EDR uses the same 1.6kHz slot rate as basic data rate and therefore the packets can be 1, 3, or 5 slots long as per the basic data rate. Where EDR differs from the basic data rate is that in the same 1MHz symbol rate 2 or 3bits are used per symbol, compared to 1bit per symbol used by the basic data rate. To achieve the increase in number of bits symbol, two new modulation schemes have been introduced as summarized in Table 24 presented below and the modulation schemes are explained in the further sections. Table 24 Data Rate Schemes Blu oSy lei Although the EDR uses new packets Link establishment and management are unchanged and still use Basic Rate packets. lei 8.2 Enhanced Data Rate _/4 DQPSK Blu oSy 4 DQPSK includes the following features. 4-state Differential Phase Shift Keying. 2 bits determine phase shift between consecutive symbols. See Table 25 below. S/4 rotation avoids phase shift of S, which would cause large amplitude variation. Raised Cosine pulse shaping filter to further reduce side band emissions. lu oSy Table 25 2 bits Determine Phase Shift Between Consecutive Symbols 45 / 58 i50e Datasheet 8.3 8DQPSK oSy 8DQPSK includes the following features. 8-state Differential Phase-Shift Keying. See Figure 28 below. Three bits determine phase shift between consecutive symbols. See Table 26 below. lei Blu Table 26 3 bits Determine Phase Shift between Consecutive Symbols Blu oSy lei Blu oSy lei lu Figure 28 8DQPSK oSy 46 / 58 i50e Datasheet 9 Re-flow Temperature-time Profile oSy The re-flow profiles are illustrated in Figure 29 and Figure 30 below. lei Temp.(0C) Blu 40+20/-15s 2300C~2450C 2170C oSy 1500C~1900C Blu lei 90+30/-30s Time(S) Figure 29 Typical Lead-Free Re-flow Solder Profile Blu 2170C oSy lei lu 2420C oSy Figure 30 Typical Lead-free Re-flow 47 / 58 i50e Datasheet The soldering profile depends on various parameters according to the use of different solder and material. The data here is given only for guidance on solder re-flow. i50e will withstand up to two re-flows to a maximum temperature of 245°C. oSy lei 10 Reliability and Environmental Specification 10.1 Temperature Blu test Put the module in demo board which uses exit power supply, power on the module and oSy connect to mobile. Then put the demo in the ‐40℃ space for 1 hour and then move to +85℃ space within 1minute, after 1 hour move back to ‐40℃ space within 1 minute. This is 1 cycle. The cycles are 32 times and the units have to pass the testing. Blu 10.2 Vibration Test lei The module is being tested without package. The displacement requests 1.5mm and sample is vibrated in three directions(X,Y,Z). Vibration frequency set as 0.5G, a sweep rate of 0.1 octave/min from 5Hz to 100Hz last for 90 minutes each direction. Vibration frequency set as 1.5G, a sweep rate of 0.25 octave/min from 100Hz to 500Hz last for 20 minutes each direction. 10.3 Desquamation Test Blu oSy lei Use clamp to fix the module, measure the pull of the component in the module, make sure the module`s soldering is good. 10.4 Drop Test oSy Free fall the module (condition built in a wrapper which can defend ESD) from 150cm height to cement ground, each side twice, total twelve times. The appearance will not be damaged and all functions OK. 10.5 Packaging Information leil Blu After unpacking, the module should be stored in environment as follows. Temperature: 25℃ ± 2℃ 48 / 58 i50e Datasheet Humidity: <60% No acidity, sulfur or chlorine environment oSy The module must be used in four days after unpacking. lei 11 Layout and Soldering Considerations 11.1 Soldering BluRecommendations i50e is compatible with industrial standard reflow profile for Pb-free solders. The reflow profile used is dependent on the thermal mass of the entire populated PCB, heat transfer efficiency of the oven and particular type of solder paste used. oSy lei IVT Corporation will give following recommendations for soldering the module to ensure reliable solder joint and operation of the module after soldering. Since the profile used is process and layout dependent, the optimum profile should be studied case by case. Thus following recommendation should be taken as a starting point guide. Blu Avoid using more than one flow. Reliability of the solder joint and self-alignment of the component are dependent on the solder volume. Minimum of 150um stencil thickness is recommended. Aperture size of the stencil should be 1:1 with the pad size. oSy lei A low residue, “no clean” solder paste should be used due to low mounted height of the component Blu 11.2 Layout Guidelines Audio Layout oSy Route audio lines as differential pairs. The positive and negative signals should run parallel and close to each other until they are converted to single-ended signals. Use dedicated audio ground plane for entire audio section. lu Layout for i50e RF pin The RF pin includes the signal pin surrounded by GND contact. It is important to make sure there is a good GND contact for the RF pin. 50 ohm trace is used to trace the RF signal to a SMA connector or similar. GND stitching vias must be used to avoid radiated emissions from the corners of the PCB. 49 / 58 i50e Datasheet oSy lei Blu lu oSy lei Figure 31 Recommended Layout 12 Physical Dimensions oSy lei BlueSoleil i50e’s dimension is 21mm(L)x13.5mm(W)x2.5mm(H). Blu lu oSy 50 / 58 i50e Datasheet oSy lei Blu Blu oSy lei oSy Figure 32 i50e Footprint 13 Package Blu lei BlueSoleil i50e package information is summarized in Figure 33 and Figure 34 below. lu oSy 51 / 58 i50e Datasheet oSy lei Blu Blu oSy lei oSy lei Figure 33 Reel Information Blu lu oSy 52 / 58 i50e Datasheet oSy lei Blu Blu oSy lei Blu oSy lei lu oSy Figure 34 Tape Information 53 / 58 i50e Datasheet 14 Certifications oSy i50e is compliant to the following specifications. lei 14.1 Bluetooth Blu BlueSoleil i50e module is qualified as a Bluetooth controller subsystem and it fulfills all the mandatory requirements of Bluetooth 2.1 + EDR core specification. If not modified in any way, it is a complete Bluetooth entity, containing software and hardware functionality as well as the whole RF-part excluding the antenna. This practically translates to that if the module is used without modification of any kind, it does not need any Bluetooth approval work for evaluation on what needs to be tested. I50e Qualified Design ID (QDID): I50e qualified listing details: Blu oSy lei B017206 https://www.bluetooth.org/tpg/QLI_viewQDL.cfm?qid=17206 I50e PICS details: https://www.bluetooth.org/tpg/showCorePICS.cfm?3A000A5A005C5043535E5214403B0C0 D0E2405022413010E57503F202A5A705A564050 oSy I50e End Product Detail: lei https://www.bluetooth.org/tpg/EPL_Detail.cfm?ProductID=15034 Blu 14.2 CE 0700 Hereby, IVT Corporation declares that this device is in compliance with the essential requirements and other relevant provisions of Directive 1999/5/EC. lu 14.3 FCC oSy Host manufacturer: IVT Corporation Limited Host Brand name: BlueSoleil Host model number: i50e FCC ID: S78-IVTI50E 54 / 58 i50e Datasheet 14.4 IC oSy Host manufacturer: IVT Corporation Host Brand name: BlueSoleil Host model number: i50e lei Blu IC: 11004A-IVTI50E The limited modular approval is based on conditions established in the application such as car audio system, into which the module can be installed. The modular is integrated into the host mainboard according to the schematic application. See Figure 35 below. Blu oSy lei Blu oSy lei Figure 35 Schematic Application The output power of this device is less than 20mW. The SAR test is not required. The host manufacture can only connect the external designated PCB antenna to pin 54. When using the host, ensure that the antenna of the host is at least 20cm away from all persons. oSy This device complies with Industry Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device. lu This device complies with Part 15 of the FCC Rules and with RSS-210 of Industry Canada. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio 55 / 58 i50e Datasheet exempts de licence. L'exploitation est autorisée aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement. oSy lei This Class B digital apparatus complies with Canadian ICES-003. Blu Cet appareil numérique de la classe B est conforme à la norme NMB-003 du Canada. NOTE: The manufacturer is not responsible for any radio or TV interference caused by unauthorized modifications or changes to this equipment. Such modifications or changes could void the user’s authority to operate the equipment. NOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures: Blu oSy lei - Reorient or relocate the receiving antenna. oSy - Increase the separation between the equipment and receiver. -Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. Blu lei -Consult the dealer or an experienced radio/TV technician for help. 15 RoHS Statement with a List of Banned Materials lu oSy i50e meets the requirements of Directive 2002/95/EC of the European Parliament and of the Council on the Restriction of Hazardous Substance (RoHS). The following banned substances are not present in i50e, which is compliant with RoHS: Cadmium Lead 56 / 58 i50e Datasheet Mercury Hexavalent chromium PBB (Polybrominated Bi-Phenyl) PBDE (PolybrominatedDiphenyl Ether) oSy 16 Bluetooth Technology Best Developed Corporation oSy IVT Corporation is one of Bluetooth technology BEST developed together which is authenticated by The Bluetooth SIG. See Figure 36 below. Blu lei oSy lei Figure 36 IVT is One of Bluetooth Technology BEST Developed Together Blu 17 Contact Information Contact: Mr. Zhu Yong Mobile: +86 18910255873 Tel: +86 10 82898219 lu Fax: +86 10 62963059 oSy Email: embedded@ivtcorporation.com Address: IVT Corporation. 5/F, Fa Zhan Building No.12, Shang Di Xin Xi Road, Beijing, 100085 P.R. China Company Site: www.ivtcorporaiton.com Support: support@ivtcorporation.com 57 / 58 i50e Datasheet oSy 18 Copyright lei Copyright © 1999-2013 IVT Corporation Blu All rights reserved. IVT Corporation assumes no responsibility for any errors which may appear in the specification. Furthermore, IVT Corporation reserves the right to alter the hardware, software, and/or specifications detailed here at any time without notice and does not make any commitment to update the information contained here. oSy BlueSoleil is a registered trademark of IVT Corporation for Bluetooth production. lei The Bluetooth trademark is owned by the Bluetooth SIG Inc., USA and is licensed to IVT Corporation. Blu All other trademarks listed herein are owned by their respective owners. Blu oSy lei lu oSy 58 / 58
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