Hanbit Electronics HANBIT-CFC Internet Phone User Manual

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Date Submitted	2001-12-12 00:00:00
Date Available	2001-12-12 00:00:00
Creation Date	2001-11-02 09:32:44
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Document Title	Users Manual
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Document Author:	歯김정순

Version 1.0
HANBit
CFC-xxxSx Series
Compact Flash Card
Min.16MB ~ Max.512MB, ATA/IDE Interface Mode,
Support 3 power save mode, 3.3V/5.0V Operating Part No. CFCxxxSx
1. PRODUCT OVERVIEW
GENERAL DESCRIPTION
The CFCxxxSx series CompactFlash card is a flash technology based with ATA interface flash
memory card. It is constructed with flash disk controller chip and NAND-type (Samsung) flash memory
device. The CompactFlash card operates in both 3.3-Volt and 5.0-Volt power supplies. It comes in
capacity of 16, 32, 64, 96, 128, 192, 256, 384 MB and up to 512 MB formatted for type-I card.
By optimizing flash memory management, the life of this card can be extended to its maximum level.
Because the ECC function is included, the correctness of data transfer between the card and the mobile
device can be guaranteed. The power down and sleep modes of the card can ensure longer life of the
batteries in the mobile devices. It is a perfect choice of solid-state mass-storage cards for battery backup
handheld devices such as Digital Camera, Audio Player, PDA, GPS, or the applications which require high
environment tolerance with high performance sustained write speed.
FEATURES
ATA / True IDE compatible host interface
ATA command set compatible
Very high performance, very low power consumption
Automatic error correction
Support 3 power save mode : stop/idle/active
Support for CIS implemented with 256 bytes of attribute memory
Support for 8 or 16 bit host transfers
3.3V/5.0V operation voltage
Host data transfer rate : 20MB/s
Flash data transfer rate : 10MB/s
Host Interface bus width : 8/16 bit Access
Flash Interface bus width : 8 bit Access
Capacity : Min. 16MB ~ Max. 512MB
MTBF : 1,000,000 hours, minimum 30,000 insertions
Operating vibration : 15G peak to peak maximum
Operating shock : 1,000G maximum
PRODUCT SPECIFICATIONS
Capacities :
1/1
HANBit Electronics Co., Ltd.
Version 1.0
HANBit
CFC-xxxSx Series
16, 32, 48, 64, 96, 128, 192, 256, 384 and up to 512 MB (formatted)
System Compatibility :
Please refer to the compatibility list of index.
Performance :
Data Transfer Rates :
To/from Flash memory :
To/from host :
Sustained write :
Sustained read :
up to 4.2 MB/s in ATA PIO mode 4
up to 12.4 MB/s
up to 20MB/s
up to 2.9MB/s in ATA PIO mode 4
up to 5.62MB/s in ATA PIO mode 4
Operating Voltage : 3.3V / 5.0V ± 10%
Power consumption :
Read mode
Write mode
Stop mode
30 mA (typ), 40 mA (Max)
30 mA (typ), 40 mA (Max)
30 µA (typ)
Environment conditions :
Operating temperature
Storage temperature
Relative humidity
0°C to + 65°C
- 20°C to + 70°C
95%(Max)
Dimension :
Weight
Length
Width
Thickness
Capacity dependent
36.4 ± 0.15 mm (1.433 ± 0.006 in.)
42.8 ± 0.10 mm (1.685 ± 0.004 in.)
3.3 mm ± 0.10 mm (0.130 ± 0.004 in.)
2/2
HANBit Electronics Co., Ltd.
Version 1.0
HANBit
CFC-xxxSx Series
ELECTRICAL SPECIFICATIONS
Table 1.1 Absolute Maximum Ratings
Symbol
VDD
VIN
IIN
TSTG
Parameter
Supply voltage
Input voltage
DC input current
Storage temperature
Ratings
- 0.3 to + 7.0
- 0.3 to + 7.0
- 10
- 20 to + 85
Unit
mA
°C
Ratings
4.75 to 5.25
3.0 to 3.6
- 20 to +70
Unit
°C
Table 1.2 Recommended Operating Conditions
Symbol
VDD
Ta
Parameter
DC Supply voltage
5V
3.3V
Storage temperature
Table 1.3 DC Characteristics
(Ta=0°C to 70°C, VDD=3.0 to 5.3V)
Symbol
Parameter
IDD
Operating Current
Ids
Stop Current
VDD
High Level Output Voltage
VDD
Low Level Output Voltage
3/3
Min.
Typ.
30
50
Max.
70
150
2.4
0.4
Unit
mA
µA
HANBit Electronics Co., Ltd.
Version 1.0
HANBit
CFC-xxxSx Series
PHYSYCAL SPECIFICATION
Note: The optional notched configuration was shown in the CF Specification
Rev. 1.0. In specification Rev. 1.2, the notch was removed for ease of tooling.
This optional configuration can be used but it is not recommended.
Figure 1.1 Type I CompactFlash Storage Card Dimensions
4/4
HANBit Electronics Co., Ltd.
Version 1.0
HANBit
CFC-xxxSx Series
Electrical Interface
Physical Description
The host is connected to the CompactFlash Storage Card or CF+ Card using a standard 50-pin
connector. The connector in the host consists of two rows of 25 male contacts each on 50 mil
(1.27 mm) centers.
Pin Assignments and Pin Type
The signal/pin assignments are listed in Table 4. Low active signals have a “-” prefix. Pin types are
Input, Output or Input/Output. Section 4.3 defines the DC characteristics for all input and output
type structures.
Electrical Description
The CompactFlash Storage Card functions in three basic modes:
1) PC Card ATA using I/O Mode
2) PC Card ATA using Memory Mode
3) True IDE Mode
Which is compatible with most disk drives. CompactFlash Storage Cards are required to support
all three modes. The CF Cards normally function in the first and second modes, however they can
optionally function in True IDE mode. The configuration of the CompactFlash Card will be
controlled using the standard PCMCIA configuration registers starting at address 200h in the
Attribute Memory space of the storage card or for True IDE Mode, pin 9 being grounded. The
configuration of the CF Card will be controlled using configuration registers starting at the address
defined in the configuration Tuple (CISTPL_CONFIG) in the Attribute Memory space of the CF
Card.
Signal description describes the I/O signals. Signals whose source is the host are designated as
inputs while signals that the CompactFlash Storage Card sources are outputs. The CompactFlash
Storage Card logic levels conform to those specified in the PCMCIA Release 2.1 specification.
Each signal has three possible operating modes:
1) PC Card Memory mode
2) PC Card I/O mode
3) True IDE
True IDE mode is required for CompactFlash Storage cards. All outputs from the card are totem
pole except the data bus signals that are bi-directional tri-state.
2. PIN INFORMATION
5/5
HANBit Electronics Co., Ltd.
Version 1.0
HANBit
CFC-xxxSx Series
PIN ASSIGNMENTS AND PIN TYPE
Table 2.1 Pin Assignment and Pin type
PC Card Memory Mode
PC Card I/O Mode
True IDE Mode
Pin
Signal
Pin
Type
Function
Pin
Signal
Pin
Type
Function
Pin
Signal
Pin
Type
Function
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
GND
D03
D04
D05
D06
D07
-CE1
A10
-OE
A09
A08
A07
VCC
A06
A05
A04
A03
A02
A01
A00
D00
D01
D02
WP
-CD2
-CD1
D111
D121
D131
D141
D151
-CE21
-VS1
-IORD
-IOWR
-WE
DC
I/O
I/O
I/O
I/O
I/O
DC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Ground
I1Z, OZ3
I1Z, OZ3
I1Z, OZ3
I1Z, OZ3
I1Z, OZ3
I3U
I1Z
I3U
I1Z
I1Z
I1Z
Power
I1Z
I1Z
I1Z
I1Z
I1Z
I1Z
I1Z
I1Z, OZ3
I1Z, OZ3
I1Z, OZ3
OT3
Ground
Ground
I1Z, OZ3
I1Z, OZ3
I1Z, OZ3
I1Z, OZ3
I1Z, OZ3
I3U
Ground
I3U
I3U
I3U
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
GND
D03
D04
D05
D06
D07
-CE1
A10
-OE
A09
A08
A07
VCC
A06
A05
A04
A03
A02
A01
A00
D00
D01
D02
-IOIS16
-CD2
-CD1
D111
D121
D131
D141
D151
-CE21
-VS1
-IORD
-IOWR
-WE
DC
I/O
I/O
I/O
I/O
I/O
DC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Ground
I1Z, OZ3
I1Z, OZ3
I1Z, OZ3
I1Z, OZ3
I1Z, OZ3
I3U
I1Z
I3U
I1Z
I1Z
I1Z
Power
I1Z
I1Z
I1Z
I1Z
I1Z
I1Z
I1Z
I1Z, OZ3
I1Z, OZ3
I1Z, OZ3
OT3
Ground
Ground
I1Z, OZ3
I1Z, OZ3
I1Z, OZ3
I1Z, OZ3
I1Z, OZ3
I3U
Ground
I3U
I3U
I3U
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
GND
D03
D04
D05
D06
D07
-CS0
A10
-ATA SEL
A092
A082
A072
VCC
A062
A052
A042
A032
A02
A01
A00
D00
D01
D02
-IOIS16
-CD2
-CD1
D111
D121
D131
D141
D151
-CS11
-VS1
-IORD
-IOWR
-WE3
DC
I/O
I/O
I/O
I/O
I/O
DC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Ground
I1Z, OZ3
I1Z, OZ3
I1Z, OZ3
I1Z, OZ3
I1Z, OZ3
I3U
I1Z
I3U
I1Z
I1Z
I1Z
Power
I1Z
I1Z
I1Z
I1Z
I1Z
I1Z
I1Z
I1Z, OZ3
I1Z, OZ3
I1Z, OZ3
OT3
Ground
Ground
I1Z, OZ3
I1Z, OZ3
I1Z, OZ3
I1Z, OZ3
I1Z, OZ3
I3U
Ground
I3U
I3U
I3U
6/6
HANBit Electronics Co., Ltd.
Version 1.0
HANBit
CFC-xxxSx Series
PC Card Memory Mode
Pin
Signal
37 RDY/BSY
38
VCC
39
-CSEL
40
-VS2
41 RESET
42 -WAIT
43 -INPACK
44
-REG
45
BVD2
46
BVD1
47
D081
48
D091
49
D101
50
GND
PC Card I/O Mode
True IDE Mode
Pin
Type
Function
Pin
Signal
Pin
Type
Function
Pin
DC
I/O
I/O
I/O
I/O
I/O
DC
OT1
Power
I2Z
Open
I2Z
OT1
OT1
I3U
I1U, OT1
I1U, OT1
I1Z, OZ3
I1Z, OZ3
I1Z, OZ3
Ground
37
38
39
40
41
42
43
44
45
46
47
48
49
50
IREQ
VCC
-CSEL
-VS2
RESET
-WAIT
-INPACK
-REG
-SPKR
-STSCHG
D081
D091
D101
GND
DC
I/O
I/O
I/O
I/O
I/O
DC
OT1
Power
I2Z
Open
I2Z
OT1
OT1
I3U
I1U, OT1
I1U, OT1
I1Z, OZ3
I1Z, OZ3
I1Z, OZ3
Ground
37
INTRQ
38
VCC
39
-CSEL
40
-VS2
41 -RESET
42
IORDY
43 -INPACK
44
-REG3
45
-DASP
46 -PDIAG
47
D081
48
D091
49
D101
50
GND
Signal
Pin
Type
Function
DC
I/O
I/O
I/O
I/O
I/O
DC
OZ1
Power
I2U
Open
I2Z
ON1
OZ1
I3U
I1U, ON1
I1U, ON1
I1Z, OZ3
I1Z, OZ3
I1Z, OZ3
Ground
Note : 1. These signals are required only for 16bit access and not required when
installed in 8-bit systems. Devices should allow for 3-state signals not to consume current.
2. Should be grounded by the host.
3. Should be tied to VCC by the host.
4. Optional required for PCMCIA Storage Cards.
Signal Descriptions
7/7
HANBit Electronics Co., Ltd.
Version 1.0
HANBit
CFC-xxxSx Series
Table 2.2 Signal Descriptions
Signal Name
Dir. Pin
A10 - A0
(PC Card Memory Mode)
8,10,11,1
2,14,15,1
6,
17,18,
19,20
A10 - A0
(PC Card I/O Mode)
A2 - A0
(True IDE Mode)
BVD1
(PC Card Memory Mode)
Description
These address lines along with the -REG signal are used to select the
following: The I/O port address registers within the CompactFlash Storage
Card or CF+ Card, the memory mapped port address registers within the
CompactFlash Storage Card or CF+ Card, a byte in the card's information
structure and its configuration control and status registers.
This signal is the same as the PC Card Memory Mode signal.
18,19,
20
I/O
46
In True IDE Mode only A[2:0] are used to select the one of eight registers in
the Task File, the remaining address lines should be grounded by the host.
This signal is asserted high as BVD1 is not supported.
-STSCHG
(PC Card I/O Mode)
Status Changed
This signal is asserted low to alert the host to changes in the RDY/-BSY and
Write Protect states, while the I/O interface is configured. Its use is
controlled by the Card Config and Status Register.
-PDIAG
(True IDE Mode)
BVD2
(PC Card Memory Mode)
In the True IDE Mode, this input / output is the Pass Diagnostic signal in the
Master / Slave handshake protocol.
This signal is asserted high as BVD2 is not supported.
I/O
45
-SPKR
(PC Card I/O Mode)
This line is the Binary Audio output from the card. If the Card does not
support the Binary Audio function, this line should be held negated.
-DASP
(True IDE Mode)
-CD1, -CD2
(PC Card Memory Mode)
In the True IDE Mode, this input/output is the Disk Active/Slave Present
signal in the Master/Slave handshake protocol.
These Card Detect pins are connected to ground on the CompactFlash
Storage Card or CF+ Card. They are used by the host to determine that the
CompactFlash Storage Card or CF+ Card is fully inserted into its socket.
26,25
This signal is the same for all modes.
-CD1, -CD2
(PC Card I/O Mode)
-CD1, -CD2
(True IDE Mode)
-CE1, -CE2
(PC Card Memory Mode)
Card Enable
This signal is the same for all modes.
7,32
-CE1, -CE2
(PC Card I/O Mode)
Card Enable
This signal is the same as the PC Card Memory Mode signal.
In the True IDE Mode CS0 is the chip select for the task file registers while
CS2 is used to select the Alternate Status Register and the Device Control
Register.
-CS0, -CS1
(True IDE Mode)
Signal Name
-CSEL
(PC Card Memory Mode)
These input signals are used both to select the card and to indicate to the
card whether a byte or a word operation is being performed. -CE2 always
accesses the odd byte of the word. –CE1 accesses the even byte or the Odd
byte of the word depending on A0 and -CE2. A multiplexing scheme based
on A0, -CE1, -CE2 allows 8 bit hosts to access all data on D0-D7.
Dir.
Pin
39
Description
This signal is not used for this mode.
-CSEL
(PC Card I/O Mode)
This signal is not used for this mode.
-CSEL
This internally pulled up signal is used to configure this device as a Master
8/8
HANBit Electronics Co., Ltd.
Version 1.0
HANBit
CFC-xxxSx Series
(True IDE Mode)
D15 - D00
(PC Card Memory Mode)
I/O
D15 - D00
(PC Card I/O Mode)
31,30,
29,28,
27,49,
48,47,
6,5,4,
3,2,
or a Slave when configured in the True IDE Mode.
When this pin is grounded, this device is configured as a Master.
When the pin is open, this device is configured as a Slave.
These lines carry the Data, Commands and Status information between the
host and the controller. D00 is the LSB of the Even Byte of the W ord. D08 is
the LSB of the Odd Byte of the Word.
This signal is the same as the PC Card Memory Mode signal.
23,22,
D15 - D00
(True IDE Mode)
GND
(PC Card Memory Mode)
GND
(PC Card I/O Mode)
GND
(True IDE Mode)
-INPACK
( PC Card Memory Mode)
21
--
1,50
In True IDE Mode, all Task File operations occur in byte mode on the low
order bus D00-D07 while all data transfers are 16 bit using D00-D15.
Ground.
This signal is the same for all modes.
This signal is the same for all modes.
43
This signal is not used in this mode.
-INPACK
( PC Card I/O Mode)
Input Acknowledge
The Input Acknowledge signal is asserted by the CompactFlash Storage
Card or CF+ Card when the card is selected and responding to an I/O read
cycle at the address that is on the address bus. This signal is used by the
host to control the enable of any input data buffers between the
CompactFlash Storage Card or CF+ Card and the CPU.
-INPACK
(True IDE Mode)
-IORD
(PC Card Memory Mode)
In True IDE Mode this output signal is not used and should not be
connected at the host.
This signal is not used in this mode.
34
-IORD
(PC Card I/O Mode)
This is an I/O Read strobe generated by the host. This signal gates I/O data
onto the bus from the CompactFlash Storage Card or CF+ Card when the card
is config ured to use the I/O interface.
-IORD
(True IDE Mode)
-IOWR
(PC Card Memory Mode)
In True IDE Mode, this signal has the same function as in PC
Card I/O Mode.
This signal is not used in this mode.
35
-IOWR
(PC Card I/O Mode)
The I/O Write strobe pulse is used to clock I/O data on the Card Data bus
into the CompactFlash Storage Card or CF+ Card controller registers when
the CompactFlash Storage Card or CF+ Card is configured to use the I/O
interface. The clocking will occur on the negative to posit ive edge of the
signal (trailing edge).
In True IDE Mode, this signal has the same function as in PC Card I/O Mode.
-IOWR
(True IDE Mode)
Signal Name
-OE
(PC Card Memory Mode)
-OE
(PC Card I/O Mode)
Dir.
Pin
Description
This is an Output Enable strobe generated by the host interface. It is used to
read data from the CompactFlash Storage Card or CF+ Card in Memory Mode
and to read the CIS and configuration registers.
In PC Card I/O Mode, this signal is used to read the CIS and configuration
registers.
9/9
HANBit Electronics Co., Ltd.
Version 1.0
HANBit
CFC-xxxSx Series
-ATA SEL
(True IDE Mode)
RDY/-BSY
(PC Card Memory Mode)
To enable True IDE Mode this input should be grounded by the host.
37
I/O Operation – After the CompactFlash Storage Card or CF+ Card has been
configured for I/O operation, this signal is used as -Interrupt Request. This
line is strobed low to generate a pulse mode interrupt or held low for a level
mode interrupt.
-IREQ
( PC Card I/O Mode)
INTRQ
(True IDE Mode)
-REG
(PC Card Memory mode)
Attribute Memory Select
In Memory Mode this signal is set high when the CompactFlash Storage
Card or CF+ Card is ready to accept a new data transfer operation and held
low when the card is busy. The Host memory card socket must provide a
pull-up resistor.
At power up and at Reset, the RDY/ -BSY signal is held low(busy) until the
CompactFlash Storage Card or CF+ Card has completed its power up or reset
function. No access of any type should be made to the CompactFlash
Storage Card or CF+ Card during this time. The RDY/ -BSY signal is held high
(disabled from being busy) whenever the following condition is true: The
CompactFlash Storage Card or CF+ Card has been powered up with +RESET
continuously disconnected or asserted.
In True IDE Mode signal is the active high Interrupt Request to the host.
44
This signal is used during Memory Cycles to distinguish between Common
Memory and Register (Attribute) Memory accesses. High for Common
Memory, Low for Attribute Memory.
-REG
(PC Card I/O Mode)
The signal must also be active (low) during I/O Cycles when the I/O address
is on the Bus.
-REG
(True IDE Mode)
In True IDE Mode this input signal is not used and should be
connected to VCC by the host.
RESET
(PC Card Memory Mode)
41
When the pin is high, this signal Resets the CompactFlash Storage Card or
CF+ Card. The CompactFlash Storage Card or CF+ Card is Reset only at
power up if this pin is left high or open from power-up. The CompactFlash
Storage Card or CF+ Card is also Reset when the Soft Reset bit in the Card
Configuration Option Register is set.
RESET
(PC Card I/O Mode)
This signal is the same as the PC Card Memory Mode signal.
-RESET
(True IDE Mode)
In the True IDE Mode this input pin is the active low hardware
reset from the host.
VCC
(PC Card Memory Mode)
--
13,38
+5 V, +3.3 V power.
VCC
(PC Card I/O Mode)
This signal is the same for all modes.
VCC
(True IDE Mode)
This signal is the same for all modes.
Signal Name
-VS1
-VS2
(PC Card Memory Mode)
-VS1
-VS2
Dir.
Pin
Description
33,40
Voltage Sense Signals. -VS1 is grounded so that the CompactFlash Storage
Card or CF+ Card CIS can be read at 3.3 volts and -VS2 is reserved by
PCMCIA for a secondary voltage.
This signal is the same for all modes.
10 / 10
HANBit Electronics Co., Ltd.
Version 1.0
HANBit
CFC-xxxSx Series
(PC Card I/O Mode)
-VS1
-VS2
(True IDE Mode)
-WAIT
(PC Card Memory Mode)
This signal is the same for all modes.
42
-WAIT
(PC Card I/O Mode)
IORDY
(True IDE Mode)
-W E
(PC Card Memory Mode)
The -WAIT signal is driven low by the CompactFlash Storage
Card or CF+ Card to signal the host to delay completion of a
memory or I/O cycle that is in progress.
This signal is the same as the PC Card Memory Mode signal.
In True IDE Mode this output signal may be used as IORDY.
36
This is a signal driven by the host and used for strobing memory write data to
the registers of the CompactFlash Storage Card or CF+ Card when the card is
configured in the memory interface mode. It is also used for writing the
configuration registers.
-W E
(PC Card I/O Mode)
In PC Card I/O Mode, this signal is used for writing the configuration
registers.
-W E
(True IDE Mode)
WP
(PC Card Memory Mode)
Write Protect
In True IDE Mode this input signal is not used and should be
connected to VCC by the host.
Memory Mode - The CompactFlash Storage Card or CF+ Card does not have
a write protect switch. This signal is held low after the completion of the reset
initialization sequence.
24
-IOIS16
( PC Card I/O Mode)
I/O Operation - When the CompactFlash Storage Card or CF+ Card is
configured for I/O Operation Pin 24 is used for the -I/O Selected is 16 Bit Port
(-IOIS16) function. A Low signal indicates that a 16 bit or odd byte only
operation can be performed at the addressed port.
-IOIS16
(True IDE Mode)
In True IDE Mode this output signal is asserted low when this
device is expecting a word data transfer cycle.
11 / 11
HANBit Electronics Co., Ltd.

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