Intel Mobile Communications 104001 Wireless Bluetooth module User Manual rok104001 ds a7 v55 rok104001 ds a7 v55

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Data Sheet, DS3, June, 2003
R O K 104 001
B l u e t o o t h TM S y s t e m M o d u l e
Wireless Solutions
N e v e r
s t o p
t h i n k i n g .
ROK 104 001
Revision History:
2003-06-16
DS3
Previous Version:
2003-05-16
DS2
Page
Subjects (major changes since last revision)
Updated Information on FCC and R&TTE Approval,
Updated section 3.6.8 on Power Management 2003-June
Document has been updated: 2003-May
Document’s layout has been changed: 2003-Feb.
For questions on technology, delivery and prices please contact the Infineon
Technologies Offices in Germany or the Infineon Technologies Companies and
Representatives worldwide: see our webpage at http://www.infineon.com.
Edition 2003-06-16
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2003.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as warranted
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide
(www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
ROK 104 001
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Reference documents for ECP firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1
2.2
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Definition and Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1
3.2
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.3
3.3.1
3.3.1.1
3.4
3.4.1
3.4.2
3.4.3
3.4.4
3.5
3.5.1
3.5.2
3.5.3
3.5.4
3.5.5
3.6
3.6.1
3.6.2
3.6.3
3.6.4
3.6.5
3.6.5.1
3.6.5.2
3.6.5.3
3.6.6
3.6.7
3.6.8
3.7
3.7.1
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Design Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Radio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Baseband . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Regulation Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Module HW Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Host Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Other Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCM Voice Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Antenna . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bluetooth Module Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM & HCI Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Host Controller Interface (HCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Link Manager (LM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Antenna . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Shielding / EMC Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCB Design Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pad Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Spurious Emissions Measurement . . . . . . . . . . . . . . . . . . . . . . . . . .
Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Additional Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Management Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Assembly Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Solder Paste . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Sheet
11
11
12
12
12
12
13
13
13
13
13
14
14
14
14
16
16
16
17
17
17
18
19
19
19
19
20
20
21
22
23
23
23
23
24
24
DS1, 2003-02-01
ROK 104 001
3.7.2
3.7.3
3.7.4
3.8
3.9
Soldering Profile . . . . . . . . . . . . . . . . . . . . . . . .
Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FCC Modular Approval . . . . . . . . . . . . . . . . . . . . .
R&TTE Approval . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1
4.2
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.1
5.2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Module Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Reel Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.1
6.2
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Pinout (bottom view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Footprint, Land View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Data Sheet
...............
...............
...............
...............
...............
24
25
25
25
26
DS1, 2003-02-01
BluetoothTM System Module
ROK 104 001
Preliminary Data
Overview
The Bluetooth 1.1 System Module ROK 104 001 is a
complete FCC and R&TTE type approved product for
fast implementation and cuts your time-to-market. It is a
compact and cost effective radio/baseband module that
can be implemented in any kind of electronic device. The
module includes a baseband processor with 4 Mbit Flash
memory, a radio solution, interfaces to antenna and
application, supporting circuitry, together with basic
Bluetooth software for signaling at HCI level (Host Controller Interface) or ECP level
(Embedded Communication Platform).
The antenna filter is specially designed for applications in a GSM environment such as
inside a mobile phone. The ROK104001 also has a very high threshold for high signal
levels in-band, which makes it very suitable to be in an IEEE 802.11b environment.
As the ROK 104 001 is a generic product, it can be used for many different types of
applications that require Bluetooth capability such as
•
•
•
•
•
Computers and peripherals
Handheld devices and accessories
Inustrial and medical sensors
Access points and home base stations
Applications where short time-to-market is required
Type
Package
ROK 104 001
LGA-87
Data Sheet
DS2, 2003-05-16
ROK 104 001
Overview
1.1
•
•
•
•
•
•
•
•
•
•
•
Key Features
A small and complete class 2 Bluetooth system
Forms full Bluetooth functionality with only the addition of an antenna
Point to multipoint, 7 slaves for HCI firmware and 3 slaves for ECP firmware
Power management: PARK, SNIFF & HOLD as well as system power saving
Excellent high signal level performance in-band
Exceptional out-band blocking in all GSM bands
Multiple interfaces UART, PCM, bi-directional serial interface/GPIO
Capability of embedded solutions
Qualified to Bluetooth spec. 1.1
FCC and R&TTE type approved
Supports all Bluetooth profiles
1.2
•
•
•
•
ECI
ECI
ECI
ECI
Reference documents for ECP firmware
Protocol Specification
Driver User Manual
Driver Release Notes
Firmware Release Notes
These documents can be provided through your Infineon Technologies sales contact.
Data Sheet
DS2, 2003-05-16
ROK 104 001
Pin Description
Pin Description
2.1
Pin Configuration
ERA00099
Figure 1
Data Sheet
ROK 104 001, Bottom View
DS2, 2003-05-16
ROK 104 001
Pin Description
2.2
Pin Definition and Function
Table 1
Pin Definition and Function
Pin
Symbol
Type 1 )
Description
G0-2
GND
Power
Mechanical connection to ground
G3-4
N.C.
G5-7
GND
H0
N.C.
H1
GND
Power
Mechanical connection to ground
H2
D-
BD, PHY, IOP2
USB data pin (USB function is not supported)
H3
D+
BD, PHY, IOP2
USB data pin (USB function is not supported)
H4
ON
DI, Power
When tied to VDD , the module is HW enabled
H5
GND
Power
Ground
H6
GND
Power
Mechanical connection to ground
H7
N.C.
Mechanical connection - treat as no connect. Pad required.
J0
N.C.
Mechanical connection - treat as no connect. Pad required.
J1
UART2Tx
DO, IOP1
Tx data from UART 2 - not supported by HCI FW
J2
UART2CTS
DIU, IOP1
Flow control signal, Clear To Send data to UART 2 - not supported by
HCI FW
J3
UART1CTS
DIU, IOP2
Flow control signal, Clear To Send data to UART 1
J4
VDDIO
Power
External supply rail to the input / output ports
J5
VDD
Power
Supply Voltage
J6
GND
Power
Ground
J7
N.C.
Mechanical connection - treat as no connect. Pad required.
K0
N.C.
Mechanical connection - treat as no connect. Pad required.
K1-2
N.C.
Not connected
K3
UART1RTS
DO, IOP2
Flow control signal, Request To Send data from UART 1
K4
UART1Tx
DO, IOP2
Tx data from UART 1
K5
N.C.
K6
GND
K7
N.C.
Mechanical connection - treat as no connect. Pad required.
L0
N.C.
Mechanical connection - treat as no connect. Pad required.
L1
PCMRx
BDU, IOP2 (input
default)
PCM receive data (default)
L2
PCMSYNC
BD, IOP2
PCM data sampling rate
L3
WAKEUP
DO, IOP2
Indicates that the module wants to be attached (USB function is not
supported)
L4
GND
Power
Ground
L5
N.C.
Data Sheet
Mechanical connection - treat as no connect. Pad required.
Power
Mechanical connection to ground
Mechanical connection - treat as no connect. Pad required.
Not connected
Power
Signal ground
Not connected
DS2, 2003-05-16
ROK 104 001
Pin Description
Table 1
Pin Definition and Function (cont’d)
Pin
Symbol
Type 1 )
Description
L6
GND
Power
Ground
L7
N.C.
M0
GND
Power
Mechanical connection to ground
M1
PCMCLK
BD, IOP2
PCM clock that sets the PCM data rate
M2
EXTINT
DID, IOP1
External interrupt for embedded purposes
M3
UART1Rx
DIU, IOP2
Receive data to UART 1
M4
N.C.
M5
PWRAVAIL
DID, IOP1
Indicates whether external power is available; used in conjunction
with PWRFAIL - not supported by HCI FW
M6
N.C. - VTP4
DO
Not connected - vendor test point #4
M7
GND
Power
Mechanical connection to ground
N0
N.C.
N1
PCMTx
BD, IOP2 (output PCM transmit data (default)
default)
N2
UART2Rx
DIU, IOP1
Receive data to UART 2 - not supported by HCI FW
N3
GPIOB5
BD, IOP2
General purpose signal #5 input / default output for embedded
purposes
N4
GPIOB4
BD, IOP1
General purpose signal #4 input / default output for embedded
purposes
N5
UART2RTS
DO, IOP1
Flow control signal, Request To Send data from UART 2 - not
supported by HCI FW
N6
N.C. - VTP3
DI
Not connected -vendor test point #3
N7
VDD-RFDIG
AO
Output from internal regulator connected to digital section of the radio.
Shall be connected to a minimum capacitance of 2.2µF.
P0
N.C.
P1
GPIOB3
BD, IOP1
General purpose signal #3 input / default output for embedded
purposes
P2
EXTSYS
WAKEUP
DI, IOP1
Can be used as an external interrupt to control the EBC - for
embedded purposes
P3
SERIALCLK
BD3, IOP1
Bidirectional serial interface / GPIO clock signal
P4
DETACH
DIU, IOP2
Indicates that the USB host wants to detach the module (USB function
is not supported)
P5
N.C. - VTP2
DO
Not connected - vendor test point #2
P6
GPIOB6
BD, IOP1
General purpose signal #6 input / default output for embedded
purposes
P7
N.C.
R0
N.C. - VTP5
AO
Not connected - vendor test point (VDD_DIG) #5
R1-2
GND
Power
Ground
R3
RESET
DI, IOP1
Reset signal, active low (must be fed from an open drain output)
Data Sheet
Mechanical connection - treat as no connect. Pad required.
Not connected
Mechanical connection - do not connect
Mechanical connection - treat as no connect. Pad required.
Mechanical connection - treat as no connect. Pad required.
DS2, 2003-05-16
ROK 104 001
Pin Description
Table 1
Pin Definition and Function (cont’d)
Pin
Symbol
Type 1 )
Description
R4
GPIOB2
BD, IOP1
General purpose signal #2 input / default output for embedded
purposes
R5
PWRFAIL
DIU, IOP1
Indicates a poer fail condition; used in conjunction with PWRAVAIL not supported by HCI FW
R6
GPIOB7
BD, IOP1
General purpose signal #7 input / default output for embedded
purposes
R7
N.C.
Mechanical connection - treat as no connect. Pad required.
T0
N.C.
Mechanical connection - treat as no connect. Pad required.
T1
GND
Power
Ground
T2
ANT
BD, RF
50 Ω antenna connection
T3
GND
Power
Ground
T4
N.C.
Not connected
T5
N.C. - VTP1
Not connected - vendor test point #1
T6
SERIALDATA BD, IOP1
Serial interface - data signal
T7
N.C.
Mechanical connection - treat as no connect. Pad required.
V0-1
GND
Power
(V2)
V3-7
Mechanical connection to ground
(No pad)
GND
1) AO
BD
BDU
DI
DIU
DID
DO
GND
IOP1
IOP2
POW
PHY
RF
Power
Mechanical connection to ground
= Analogue output pad
= Bi-directional pad
= Bi-directional pad with pull-up
= Input pad
= Input pad with pull-up
= Input pad with pull-down
= Digital Output
= VSS power supply pad
= IO group VDD_DIG power supply pad
= IO group VDD_IO power supply pad
= Core power supply pad
= USB transceiver pad shared with UART1 RI and DCD pins (USB function is not supported)
= Radio Frequency pad
Data Sheet
10
DS2, 2003-05-16
ROK 104 001
Functional Description
Functional Description
3.1
Functional Block Diagram
Only required for PM s top mode function
PBM 990 80
UART1RxD
UART1TxD
UART1RTS
UART1CTS
Voltage
Regulation
UART2RxD
UART2TxD
UART2RTS
UART2CTS
PCMRx
PCMTx
PCMCLK
PCMSYNC
SERIALCLK
SERIALDATA
V DDIO
VDD _RFDIG
UART1
UART2
Embedded
Control
PCM
Loop
Filter
Antenna
Filter
Radio Control
Ra dio
ASIC
13 MHz
Crys tal
Figure 2
GPIOB2
GPIOB3
GPIOB4
GPIOB5
GPIOB6
GPIOB7
PWRFAIL
PWRAVAIL
RESET
EBC
(ARM7)
Serial
Interface
>1 µF
2.2 µF
EXTINT
EXTSYSWAKEUP
Shall be
positioned
as close
as possible
to mod ule.
Flash
Memory
DETACH
ON
VDD
RxBa lun
ANT
Antenna
Switch
TxBalun
Block Diagram
The ROK 104 001 is a complete Bluetooth module that has been specified and designed
according to the Bluetooth System v1.1. Its implementation is based on a high-
Data Sheet
11
DS2, 2003-05-16
ROK 104 001
Functional Description
performance integrated radio IC working with the baseband controller PBM 990 80, with
integrated flash memory and surrounding secondary components.
ROK 104 001 consists of three major parts; a baseband controller, firmware, and a radio.
Multi slot data and voice packets are supported. Communication between the module
and the host controller is carried out on UART and PCM interfaces. ROK 104001 is
compliant with BT version 1.1 and is a Class 2 BT Module. ROK 104 001 is tested
according to R&TTE and FCC type approval requirements.
3.2
Design Sections
ROK 104 001 has five major design sections. Figure 2 illustrates the interaction of the
various sections. The functionality of each section will be briefly explained.
3.2.1
Radio
The radio functionality is achieved by an Infineon Technologies Radio IC, a short-range
microwave frequency radio transceiver for Bluetooth communication links based on
RFCMOS technology.
3.2.2
Baseband
The baseband functionality is achieved by using Infineon Technologies PBM 990 80,
providing the baseband functionality and Flash memory. The baseband contains a
Bluetooth core (EBC); an ARM 7 processor, I/O ports (PCM and UART) and RAM
memory. Firmware is downloaded into the flash memory. The interfaces that are
implemented on the baseband chip are UART, PCM and serial clock interface (bidirectional serial interface / GPIO).
PBM 990 80 provides the link-setup and control routines for the layers above.
Furthermore, PBM 99080 also provides Bluetooth security like encryption,
authentication and key management.
Please refer to the PBM 990 80 data sheet for further information regarding baseband
functionallity.
3.2.3
Voltage Regulation Section
There are three inputs to the voltage regulation section (VDD, V DD_IO , ON). VDD can be
fed with 3.1 V to 4.75 V. The power regulator on the module creates 2.7 V regulated
supply.
A separate power supply rail (VDD_IO ) is provided for the I/O ports, UART and PCM.
VDD_IO can either be connected to V DD or to a dedicated supply rail, which is the same as
the logical interface of the host.
The ON input is the only signal that is required to activate the module.
Data Sheet
12
DS2, 2003-05-16
ROK 104 001
Functional Description
3.2.4
Crystal Oscillator
An internal crystal oscillator supplies radio IC and Baseband with a stable frequency. No
external oscillator or crystal is required.
3.2.5
Flash Memory
ROK 104 001 is delivered with 4 Mbit Flash memory. Firmware (F/W), in terms of link
manager and applicable upper layer stack parts, resides in the Flash and is available as
image file formats.
3.3
Module HW Interfaces
3.3.1
Host Interfaces
To enable a host system to access the Bluetooth radio link, a Host Controller Interface
(HCI) has been defined. The host system controls and distributes data to and from the
Bluetooth Link Manager with a set of commands. These commands are carried
physically on either the UART or USB interface (not supported by firmware).
3.3.1.1
UARTs
The UART implemented on the baseband is an industry standard and supports the
following baud rates: 300, 600, 900, 1200, 1800, 2400, 4800, 9600, 19200, 38400,
57600, 115200, 230400, 460800 and 921600 bits/s. 128-byte FIFOs are associated with
the UART1.
Four signals will be provided for the UART interface. TxD & RxD are used for data flow,
and RTS & CTS shall be used for flow control. The module is a DCE.
There are two on-chip UART interfaces, UART1 and UART2.
UART1 has 128-byte FIFOs and full modem control support and is used for data in and
out transmission at bit rates up to 921 kbit/s. UART1 is setup to a DTE configuration.
UART2 has 16-byte FIFOs and is used for control and/or boot.
Start-detect and Auto-baud functionality is available for both UARTs.
Data Sheet
13
DS2, 2003-05-16
ROK 104 001
Functional Description
Table 2
HCI Default Settings UART1, UART2
Speed
57600 bit/s
Data bit
8 bit
Stop bit
One
Parity
None
Flow
CTS/RTS
Note: These settings can be changed from the HCI level using Ericsson specific
commands. For HCI and ECP firmware, UART2 is disabled since UART1 is
default.
3.4
Other Interfaces
3.4.1
Serial Interface
The bi-directional serial interface / GPIO interface function is based on software using
two GPIO’s. The interface has a capacity of handling approximately 100 kbit/s.
A master serial I/F is available on the module. This is used to control external serial
interface devices. The controls of the serial interface pins are performed by Ericsson
specific HCI commands available in the FW implementation. See Application Note. This
enables application in a stand-alone ROK 104 001 module to also control other devices
via the serial interface.
3.4.2
General Purpose I/O
The ROK 104 001 architecture supports up to 8 General Purpose I/O’s. 2 GPIO’s are
default, that is used as the serial interface.
3.4.3
PCM Voice Interface
Uses the standard PCM interface, which has a sample rate of 8 kHz (PCMSYNC). The
PCM I/F can be set in master or slave mode (providing or receiving the PCMSYNC and
PCMCLK).
PCM clock (PCMCLK) is variable between 200kHz and 2.048 MHz in slave mode.
During the master mode, the PCMCLK is set at 2 MHz. PCM data can be linear PCM
(13-16bit), µ-Law (8 bit) or A-Law (8 bit).
Over the air the encoding is programmable to be CVSD, A-Law or µ-Law.
Data Sheet
14
DS2, 2003-05-16
ROK 104 001
Functional Description
The PCM line interface can act either as slave or master. When the PCM line interface
is slave the frequency range of PCMCLK (in) is 200 kHz to 2.048 MHz. When the PCM
line interface is master PCMCLK (out) is always 2 MHz.
Each PCM symbol on the PCMTx or PCMRx line is organized as an 8 or 16-bit sequence
of bits, arriving synchronous to PCMCLK in (if the PCM line interface is slave) or
PCMCLK out (if the PCM line interface is master). The symbol starts with its most
significant bit arriving after a positive edge on the PCMCLK in (or out), one clock cycle
after a PCMSYNC in (or out) positive transition. The symbol is then transferred by one
bit each PCMCLK in (or out) clock cycle until the least significant bit is transferred. The
EBC then samples the arriving bit at falling edges of PCMCLK in (or out).
The PCM symbols are transmitted bit by bit starting with the MSB, one clock cycle after
a positive edge on the PCMCLK in (if the PCM line interface is slave) or PCMCLK out (if
the PCM line interface is master), one clock cycle after a PCMSYNC (in or out) positive
transition. The rest of the bits are then transferred by one bit each PCMCLK (in or out)
cycle, and are synchronized with the rising edge of this clock.
Continuous
PCM clock
tPCH
t PCL
Continuous
PCM clock
PCMCLK out
t PSH
tPSV
Delayed PCM sync
PCMSYNC out
t PDOV
PCMX out
MSB
MSB-1
D1
D0
MSB
MSB-1
D1
D0
0, 1 or Z
tPDIS
PCMX in
0, 1 or Z
tPDIH
Figure 3
Data Sheet
PCM Master Mode Timing Diagram
15
DS2, 2003-05-16
ROK 104 001
Functional Description
Continuous
PCM clock
tPCH
t PCL
Continuous
PCM clock
PCMCLK in
tPSS
PCMSYNC in
t PSH
tPSW
t PDOV
PCMX out
MSB
MSB-1
D1
D0
MSB
MSB-1
D1
D0
0, 1 or Z
tPDIS
PCMX in
0, 1 or Z
tPDIH
Figure 4
3.4.4
PCM Slave Mode Timing Diagram
Antenna
The ANT pin should be connected to a 50 Ω antenna interface, thereby supporting the
best signal strength performance, VSWR should not be higher than 2:1. Infineon
Technologies can recommend application specific antennas.
3.5
Software
The Bluetooth link is partitioned into a hardware part and a software part. The software
relates to the Bluetooth protocol stack. Depending on the level of integration, there will
be two different firmware models available, including hardware specific drivers for the
Bluetooth core, UARTs, GPIO and bidirectional serial interface / GPIO. The level of
integration follows the two main scenarios:
•
•
LM & HCI firmware for HCI based applications, where the upper layer stack is
integrated in a host processor external to the ROK 104001
Embedded Communication Platform (ECP) where LM and upper layer Bluetooth
stack resides in the ROK 104001, communicating with an external host processor
through an easy to use ECI-interface (Embedded Communication Interface). For
further documentation on ECP and ECI, please refer to ECI-driver documentation.
3.5.1
Firmware
The module includes firmware for the host controller interface, HCI, and the link
manager, LM. The FW resides in the Flash and is available in load format (*.mfl) and in
binary format (*.bin).
Data Sheet
16
DS2, 2003-05-16
ROK 104 001
Functional Description
3.5.2
Bluetooth Module Stack
The Host Controller Interface (HCI) handles the communication by the transport layer
through the UART interface with the host. The Baseband and radio provide a secure and
reliable radio link for higher layers. The following sections describe the Bluetooth module
stack in more detail, see also Figure 5. It is implemented in accordance with and
complies with the Specification of the Bluetooth System v1.1.
HCI
Audio
Link Manager
Baseband
Radio
ERA00103
Figure 5
3.5.3
HW/HCI FW Parts Included in the Bluetooth Module from Infineon
LM & HCI Firmware
In this configuration the customer will access the LM through a Host Controller Interface
(HCI) protocol distributed over UART.
3.5.4
Host Controller Interface (HCI)
The HCI provides a uniform command I/F to the Baseband and Link Manager and also
to HW status registers. The HCI I/F is accessed through UART. There are three different
types of HCI packets:
•
•
•
HCI command packet - from host to Bluetooth module HCI
HCI event packets - from Bluetooth module HCI to host
HCI data packets - going both ways
It is not necessary to make use of all different commands and events for an application.
If the application is aimed at a pre-specified profile, the capabilities of such a profile are
necessary to adjust to - see Specification of the Bluetooth System v1.1. Profiles and
Application Note
a) With the HCI UART Transport Layer on top of HCI, the module will communicate with
a host through the UART I/F. The PCM I/F is also available for communicating voice.
Please refer to the Specification of the Bluetooth System v1.1 part H: 1-4 for in-depth
information regarding the HCI and different transport layers.
Data Sheet
17
DS2, 2003-05-16
ROK 104 001
Functional Description
UART
HCI
LM
PBM 990 80
UAR T
Running:
• LM
• HCI
OS : OS E
Host System
Controller
Running:
• Host Stack
• Application
OS:Customer
PBM 990 80
ERA00104
Figure 6
3.5.5
Host Controller Interface
Link Manager (LM)
The Link Manager in each Bluetooth module can communicate with another Link
Manager by using the Link Manager Protocol (LMP) which is a peer to peer protocol, see
Figure 7. The LMP messages have the highest priority and are used for link-setup,
security, control and power saving modes. The receiving Link Manager filters out the
message and does not need to acknowledge the message to the transmitting LM due to
the reliable link provided by the Baseband and radio. LM to LM communication can take
place without actions taken by the host. Discovery of features at other Bluetooth enabled
devices nearby can be found and saved for later use by the host. Please refer to the
Specification of the Bluetooth System v1.1 part C for in-depth information regarding the LMP.
Data Sheet
18
DS2, 2003-05-16
ROK 104 001
Functional Description
LM
LMP
LM
LC
LC
RF
RF
Physical layer
ERA00105
Figure 7
Link Manager
3.6
Design Guidelines
3.6.1
Power-up Sequence
There is no need for a power up sequence if VDD , ON and V DD_IO are tied together. A
power up sequence, if used, shall be applied accordingly: GND, VDD_IO supply rail, V DD
supply; and finally the ON signal should be applied in order to initiate the internal
regulator.
The power-down sequence is similar to the power-up procedure but in the reverse
format. Therefore, the disconnection of the signals shall be as follows: ON, VDD, V DD_IO ,
and finally GND.
3.6.2
RESET
The assignment of the RESET input is to generate a reset signal to ROK 104 0 0 1 .
During power-up the reset signal is set ‘low’ so that power supply glitches are avoided.
Therefore, no reset input is required after power-up.
3.6.3
Power
There are three inputs to the Voltage Management section (V DD, V DD_IO , ON). VDD is the
supply voltage that is typically 3.3 V.
A separate power supply rail (VDD_IO ) is provided for the I/O ports, UART and PCM.
VDD_IO can either be connected to V DD or to a dedicated supply rail, which is the same as
the logical interface of the host. The ON signal is controlling the internal regulators on or off.
Data Sheet
19
DS2, 2003-05-16
ROK 104 001
Functional Description
An input capacitor whose capacitance is > 1 µF is required between the VDD supply and
ground (the amount of capacitance may be increased without limit), see Figure 2. This
capacitor must be located as close as possible to the VDD pad returned to a clean
analogue ground. Any good quality ceramic, tantalum, or film capacitor may be used at
the input.
Important: Tantalum capacitors can suffer catastrophic failure due to surge current when
connected to a low-impedance source of power (like a battery or very large capacitor). If
a Tantalum capacitor is used at the input, it must be guaranteed by the manufacturer to
have a surge current rating sufficient for the application.
There are no requirements for ESR on the input capacitor, but tolerance and
temperature coefficient must be considered when selecting the capacitor to ensure that
the capacitance will be > 1 µF over the entire operating temperature range.
3.6.4
Antenna
The antenna output routing should be 50 Ω (VSWR ≤ 2:1) all the way to the antenna in
order to maintain the radio performance listed in this data sheet. For the routing
underneath the module, the modules ground plane should be considered. The type
approval for FCC and R&TTE have been done with an antenna gain of 1.6dBi.
3.6.5
Shielding / EMC Requirements
The module has its own RF shielding and is approved according to the standards by FCC
and R&TTE. If the approval number is not visible on the outside when the module is
utilised in the final product, an exterior label must state that there is a transmitter module
inside the product (see Section 3.8).
ROK 104 001
Route 1/GND
GND
Route 2
GND
GND vias
Figure 8
Data Sheet
GND vias
Side view of a recommended layout for a 4 layer PCB
20
DS2, 2003-05-16
ROK 104 001
Functional Description
Although the module has its own shielding extra precautionsregarding layout routing
should be taken. It is strongly recommended that all the routing from the module shall be
encapsulated between GND layers. Refer to figure 8 for an example with a 4-layer PCB.
ROK
104 001
3mm
GND vias
Figure 9
Top view of a recommended layout
Additionally, GND vias can be positioned around the module and its surrounding
components so that any high frequency signal cannot effect any other part of the
application board. This also protects the module from high frequency components that
could be positioned in the near vicinity. It is recommended to have a distance of 3 mm
between the earth vias. Refer to figure 9 as an example.
3.6.5.1
PCB Design Rules
As can be seen from figure10, the GND vias that surround the module should not have
a large impact of the ability to route the signals to the module.
Data Sheet
21
DS2, 2003-05-16
ROK 104 001
Functional Description
Total Thickness of PCB
Via hole ø
Catch Pad ø (Internal Layers)
GND vias distance
No. of possible
tracks between
GND vias
10
11
Figure 10
3.6.5.2
Maximum track
width for 1.6mm
thick PCB
767
460
329
256
209
177
153
135
121
110
100
1,6
0,3
0,7
3,2
0,6
1,2
Maximum track
width for 3.2mm
thick PCB
600
360
257
200
164
138
120
106
95
86
78
mm
mm
mm
mm
um
um
um
um
um
um
um
um
um
um
um
Typical PCB layout design rules
Pad Size
It is recommended that the pads on the PCB should have a diameter of 0.7 - 0.9 mm.
The surface finish on the PCB pads should be Nickel/Gold or a flat Tin/Lead surface or
OSP (Organic Surface Protection).
Data Sheet
22
DS2, 2003-05-16
ROK 104 001
Functional Description
3.6.5.3
Spurious Emissions Measurement
Level [dBm]
-45
-50
-55
-60
-65
-70
-75
-80
1G
MES
LIM
LIM
3.6.6
2G
3G
Frequency [Hz]
VLB030214-9_pre PK
EN 300328 RX 1-12G
EN 300328 RX 1-12G2
4G
5G
6G
7G
Peak Limit (dBm)
Limit_2=(Peak Limit)-6 (dBm)
Ground
Ground should be distributed with very low impedance as a ground plane. Connect all
GND pins to the ground plane.
3.6.7
Additional Decoupling
A capacitor whose capacitance of 2.2 µF is required between the VDD_RFDIG output and
ground, see block diagram Figure 2. This capacitor must be located as close as possible
to the VDD_RFDIG pad and returned to a clean analogue ground. Any good quality ceramic,
tantalum, or film capacitor may be used at the input.
3.6.8
Power Management Stop Mode
Note that from revision R2C of HCI-firmware and from R3B-revision of ECP-firmware,
the Power Management stop mode is disabled by default. In order to enable this
function, the 'HCI Command Store In Flash' has to be used (User ID: 131& Flash Data:
0001).
In order to utilize the power management stop mode features in the firmware; a schottky
diode must be assembled between the DETACH pad and the EXTSYSWAKEUP pad,
Data Sheet
23
DS2, 2003-05-16
ROK 104 001
Functional Description
see block diagram Figure 2. The cathode shall be assembled to DETACH and the
anode to EXTSYSWAKEUP.
Power management stop mode is disabled by grounding the DETACH pin. A ‘high’
logical level will enable power management; a pull-up resistor is assembled on the
module.
3.7
Assembly Guidelines
3.7.1
Solder Paste
The ROK 104001 module is made for surface mounting with land grid array (LGA)
solder joints. To assemble the module, solder paste (eutectic Tin/Lead) must be printed
at the target surface. Preferred solder paste height is 100 - 127 µm (4 - 5 mil).
3.7.2
Soldering Profile
It must be noted that the module should not be allowed to be hanging upside down in the
reflow operation. This means that the module has to be assembled on the side of the
PCB that is soldered last. The reflow process should be a regular surface mount
soldering profile (full convection strongly preferred), the ramp-up should not be higher
than 3°C/s and with a peak temperature of 210 - 225°C during 10 - 20 seconds. Max
sloping rate should not be higher than 4°C/s (see example of reflow profile in Figure 1 1).
Data Sheet
24
DS2, 2003-05-16
ROK 104 001
Functional Description
Temperature Profile
250
°C
ERA00106
10-20 s
200
183°C
60-125 s
120 s max.
150
100
Max. rising 3°C/s
Max. sloping 4°C/s
50
50
100
150
200
250
Figure 11
3.7.3
Eutectic SnPb-Solder Profile
Placement
The recommended pickup coordinates for the ROK 104001 shield is based on a nozzle
with inner diameter 2 mm and outer diameter 3.17 mm. The center of the shield is the
origin of coordinates, (0,0) for (x,y), giving the pickup coordinates (-1 mm,0) for (x,y).
3.7.4
Storage
Keep the component in its dry pack when not yet using the reel. After removal from the
dry pack ensure that the modules are soldered onto the PCB within 48 hours.
3.8
FCC Modular Approval
This device complies with part 15 of the FCC Rules. Operation is subject to the following
two conditions: (1) This device may not cause harmful interference, and (2) this device
must accept any interference received, including interference that may cause undesired
operation.
Changes or modifications not expressly approved by the party responsible for
compliance could void the user’s authority to operate the equipment.
Data Sheet
25
DS2, 2003-05-16
ROK 104 001
Functional Description
The modular transmitter is labeled with its own FCC ID number, but, if the FCC ID is not
visible when the module is installed inside another device, then the outside of the device
into which the module is installed must also display a label referring to the enclosed
module. The exterior label can use wording such as the following: “Contains Transmitter
Module FCC ID: Q23104001” or “Contains FCC ID: Q23104001”. Any similar wording
that expresses the same meaning may be used.
When reusing the Modular Approval, antenna related measurements might need to be
redone.The antenna used for modular approval was a max 1.6dBi half-wave antenna
from gigAnt (PCB Swivel 6076019). When using an other antenna a class II permissive
change will be needed.
3.9
R&TTE Approval
This device complies with the requirements in the European Union and EFTA according
to the following test specifications:
EN 300 328
EN 60950 and EU standard
EN 301 489 -1/17
The R&TTE Approval for the ROK 104001-device is valid in the 19 member states of EU
and EFTA. The R&TTE-organizations of respective member state must be given 4
weeks of notice before a product based on this approval is allowed to be released to
market. Each state has its specific form to be filled in and submitted, for the respective
R&TTE organization to respond to. In the absence of any response within four weeks,
the product is allowed to be released to the market.
Data Sheet
26
DS2, 2003-05-16
ROK 104 001
Electrical Characteristics
Electrical Characteristics
4.1
Absolute Maximum Ratings
Table 3
Absolute Maximum Ratings
Parameter
Symbol
Values
Unit
min.
max.
-40
+125
°C
Maximum temperature
-40
+85
°C
Operating temperature
-20
+75
°C
-0.3
5.25
-0.3
4.75
V DD_IO
-0.8
3.6
IO voltage range
V IOP1
-0.3
+2.8
IO voltage range
V IOP2
-0.3
V DD_IO
Temperature
T Stg
Storage temperature
Power Supply
1)
V DD
Supply voltage (921k baud rate with turbo ON and V DD
Supply voltage
ECP firmware)
I/O Supply voltage
Baseband Digital I/Os
+ 0.3
Input clamp current VI < V SSIO or VI > V DDIO
I IC
-20
+20
mA
Output clamp current VO < V SSIO or V O > VDDIO
I OC
-20
+20
mA
10
NA
15
15
dBm
dBm
Antenna Port
Matching on ANT pad (VSWR)
Input RF power
- In-band
- Out of band
1) VDDIO supply voltage must be powered on prior to or simultaneously as the VDD supply voltage. Deviations
from this power up sequence might damage the device.
Data Sheet
27
DS2, 2003-05-16
ROK 104 001
Electrical Characteristics
4.2
Table 4
DC Specifications
DC Specifications
Unless otherwise noted, the specification applies for HCI firmware
TAmb = -20 to +75°C, 3.10 < VDD < 4.75 V, ON = 3.3V, VSWR ≤ 21)
Parameter
Note/ Test
Condition
Symbol
Values
min.
typ.
Unit
max.
Digital Inputs
Low level input
voltage, digital
input
VIL_IOP1
Guaranteed
input low except V
IL_IOP2
ON signal
ON signal only
High level input
voltage, digital
input
RESET#2)
Guaranteed
input high
except ON
signal
ON signal only
Input pin internal
pull-up resistor
Input pin internal
pull-down resistor
VSSIO - 0.3
VSSIO - 0.3
0.85
VIL
VIH_IOP1
VIH_IOP
0.4
1.96
2.8
0.7 x VDD_IO
VDD_IO + 0.3 V
VIH
1.4
VDD
0.3 x VDD_IO V
(internal resistor RPU
on baseband
chip)
30
50
80
kΩ
(internal resistor R
PD
on baseband
chip)
10
20
40
Ω
Digital Outputs
Low level output
voltage
I OL = 800 µA
VOL
High level output
voltage
I OH = -800 µA
VOH_IOP1 2.4
VOH_IOP2 VDD_IO - 0.1
V SSIO + 0.1 V
2.8
VDD_IO
Current Consumption
Input leakage cur- VI = VSSIO
rent, any digital in- V = V
DDIO
put or bidirectional
pin in input mode
-1
+1
µA
Output leakage
current, tri-state
-1
+1
µA
HW Shutdown
Data Sheet
VO = VSSIO
VO = VDDIO
3)
65
28
µA
DS2, 2003-05-16
ROK 104 001
Electrical Characteristics
Table 4
DC Specifications (cont’d)
Unless otherwise noted, the specification applies for HCI firmware
TAmb = -20 to +75°C, 3.10 < VDD < 4.75 V, ON = 3.3V, VSWR ≤ 21)
Parameter
Note/ Test
Condition
Symbol
Values
min.
typ.
Unit
max.
Idle state with stop during first 4 s.
mode4)
after 4 s.
1100
µA
270
µA
Page Scan with
stop mode5)
mA
Inquiry and Page
Scan with stop
mode5)
mA
during first 4 s.
1100
µA
after 4 s.
270
µA
4.2
mA
4.2
mA
93
100
mA
mA
921600bps
with TURBO
on8)
125
mA
I CC_IO
mA
Hold mode5)
Park mode
Sniff mode
5)
6)
7)
Connection Mode
57600bps
460800bps
or 921600bps
with TURBO
off 8)
VDDIO supply
1) Parameter errors may occur if VSWR > 2.
2) RESET# signal must be fed from an open drain output.
3) Current consumption is based upon where the ‘ON’ signal is low and ‘VDDIO’ is grounded.
4) After HCI command.
5) Inquiry and page mode current is measured during 1.28 s.
6) Sniff max & min interval: 1.28 s; Sniff attempt & Timeout: 19.375 ms.
7) Average current consumption measured during DH5 packet whilst in remote loop back configuration.
8) The HCI command turbo on has a typical throughput of 610 kbit/s but when the turbo command is off the baud
rate is reduced to 510 kbit/s.
Data Sheet
29
DS2, 2003-05-16
ROK 104 001
Electrical Characteristics
Table 5
Timing Performance
Type
Parameter/
Condition
Symbol
Rise time
Fall time
tr
tr
Rise time
tR
tF
Values
min. typ.
Unit
max.
Digital input pins
requirements1)
All digital input and bidirectional input pins2)
10
ns
10
ns
3.5
20
ns
3.5
15
ns
Digital output pins
characteristics1)
All digital output and bidirectional output pins 2)
CLOAD = 25 pF
Fall time
CLOAD = 25 pF
System
fSYS_CLK
Clock frequency
Clock frequency tolerance
3)
13.0000
-20
Start-up time from power on
RESET# signal duration 4)
Sink current >
1 mA
MHz
+20
ppm
250
ms
ms
1) Static data - All baseband input and bi-directional pins can be connected to any external driving circuit before
turning on the supply, without damaging the device. However, it cannot be guaranteed that ROK 104001 does
not load the external driver in this case, unless the baseband core supply voltage is completely discharged
prior to this event.
2) Rise and fall times are measured between 10 % to 90 % of the VDDIO level.
3) Tolerance for the system clock takes into account aging effects of the crystal.
4) RESET# signal must be fed from an open drain output.
Data Sheet
30
DS2, 2003-05-16
ROK 104 001
Electrical Characteristics
Table 6
ACL Packets
Parameter
Condition
Values
min.
Symmetric transfer rate
Asymmetric transfer rate
Forward mode
Unit
typ.
max.
DM1 packet
108
108
kb/s
DH1 packet
172
172
kb/s
DM3 packet
258
258
kb/s
DH3 packet
390
390
kb/s
DM5 packet
286
286
kb/s
DH5 packet
433
433
kb/s
DM1 packet
108
108
kb/s
DH1 packet
172
172
kb/s
DM3 packet
387
387
kb/s
DH3 packet
585
585
kb/s
477
477
kb/s
610
723
kb/s
DM5 packet
DH5 packet
1)
Asymmetric transfer rate
DM1 packet
108
108
kb/s
Reverse mode
DH1 packet
172
172
kb/s
DM3 packet
54
54
kb/s
DH3 packet
86
86
kb/s
DM5 packet
36
36
kb/s
DH5 packet
57
57
kb/s
1) The HCI command turbo on has a typical throughput of 610 kbit/s but when the turbo command is off the baud
rate is reduced to 510 kbit/s. HCI turbo on command is only valid during 921k UART baud rate.
Table 7
SCO Packets
Parameter
Condition
Values
min.
Maximum transfer rate
Data Sheet
typ.
Unit
max.
HV1 packet
64.0
kb/s
HV2 packet
64.0
kb/s
HV3 packet
64.0
kb/s
DV packet
57.6
kb/s
31
DS2, 2003-05-16
ROK 104 001
Electrical Characteristics
Table 8
PCM interface Requirements and Characteristics
Parameter
Symbol
Values
min. typ.
Unit
max.
PCM Master mode (PCMCLK and PCMSYNC are outputs)
PCM clock frequency
f PC
2000
PCM clock high period
t PCH
200
ns
PCM clock low period
t PCL
200
ns
PCMSYNC pulse valid from PCMCLK rising edge t PSV
PCMSYNC pulse hold time from PCMCLK falling t PSH
edge
PCMX data out valid from PCMCLK rising edge
kHz
100
200
ns
ns
t PDOV
100
ns
PCMX data in setup time to PCMCLK falling edge t PDIS
100
ns
PCMX data in hold time from PCMCLK falling
edge
100
ns
t PIDH
PCM Slave mode (PCMCLK and PCMSYNC are inputs)
PCM clock frequency
f PC
200
2048
kHz
PCM clock high period
t PCH
200
ns
PCM clock low period
t PCL
200
ns
PCMSYNC setup time to PCMCLK falling edge
t PSS
100
ns
PCMSYNC hold time from PCMCLK falling edge t PSH
100
ns
PCMSYNC pulse width
t PSW
1/fPC
ns
PCMX data out valid from PCMCLK rising edge
t PDOV
100
ns
PCMX data in setup time to PCMCLK falling edge t PDIS
100
ns
PCMX data in hold time from PCMCLK falling
edge
100
ns
Table 9
t PIDH
RF Specifications
Parameter
Condition
Values
min.
typ.
Unit
max.
General
Frequency range
2.402
Double sided IF bandwidth
Data Sheet
2.480 GHz
32
MHz
DS2, 2003-05-16
ROK 104 001
Electrical Characteristics
Table 9
RF Specifications (cont’d)
Parameter
Condition
Values
min.
Antenna load
typ.
Unit
max.
Ω
50
VSWR
Rx mode
2:1
VSWR 1)
Tx mode
2:1
DH1 Connection
160 kHz deviation
w.r.t. BER < 0.1 %
-75
Receiver Performance
Sensitivity level
Max input level
RSSi accuracy
-71
dBm
-20
+13
Pin = -40 dBm
-6
+6
dB
Pin = -60 dBm
-6
+6
dB
C/Ico-channel2) 3)
dBm
12
14
dB
2) 3)
-3
dB
2) 4)
-35
-30
dB
-50
-30
dB
-20
-9
dB
-30
-20
dB
C/I1MHz
C/I2MHz
C/I>3MHz2) 4)
C/Iimage
2) 4)
Adjacent (1 MHz) interference to
inband image frequency
C/Iimage+/-1MHz2) 4)
Out-of-band blocking
30-1850 MHz
+5
+15
dBm
1850-1910 MHz
+4
+15
dBm
1911-2000 MHz
+9
dBm
2001-2399 MHz
-27
-8
dBm
2484-2999 MHz
-27
-9
dBm
3.0-12.75 GHz
-10
+3
dBm
-39
-30
dBm
2) 5)
Intermodulation rejection
Spurious emissions
30 MHz to 1 GHz
-57
dBm
1 GHz to 12.75 GHz
-47
dBm
Transmitter Performance
Frequency deviation
140
160
175
kHz
Tx power
-4
+1
+4
dBm
Initial frequency error
-75
75
kHz
20 dB bandwidth
Data Sheet
with peak detector
33
1000 kHz
DS2, 2003-05-16
ROK 104 001
Electrical Characteristics
Table 9
RF Specifications (cont’d)
Parameter
Condition
Values
min.
Tx carrier drift 2402 to 2482 MHz
Tx carrier drift 2480 to 2402 MHz
Spurious emissions
max.
1 slot (366 µs)
-25
25
kHz
3 slots (1598 µs)
-40
40
kHz
5 slots (2862 µs)
-40
40
kHz
1 slot (366 µs)
-25
25
kHz
3 slots (1598 µs)
-40
40
kHz
5 slots (2862 µs)
-40
40
kHz
-20
20
kHz
+2 MHz
-20
dBm
-2 MHz
-20
dBm
+3 MHz
-40
dBm
-3 MHz
-40
dBm
+4 MHz
-40
dBm
-4 MHz
-40
dBm
+13 MHz
-40
dBm
-13 MHz
-40
dBm
30 MHz - 1 GHz
-36
dBm
1 GHz - 12.75 GHz
-30
dBm
1.8 GHz - 1.9 GHz
-47
dBm
5.15 GHz - 5.3 GHz
-47
dBm
Drift rate
Adjacent channel power
typ.
Unit
1) During the Tx mode, the VSWR specification states the limits that are acceptable before any other RF
parameters are strongly affected, i.e. frequency deviation and drift.
2) Specification only valid for normal test conditions TAMB = 15 - 35 C.
3) Carrier signal level of -60 dBm, interferer Bluetooth modulated.
4) Carrier signal level of -67 dBm, interferer Bluetooth modulated.
5) Carrier: -64 dBm @ 2441 MHz, 1s t interferer: CW @ 2446 MHz, 2n d interferer: BT mod. @ 2451 MHz.
Data Sheet
34
DS2, 2003-05-16
ROK 104 001
Marking
Marking
5.1
Module Marking
Each module shall be marked with the following information printed on the shield.
Table 10
Marking
Description
1:
Infineon logotype
2:  Product number with suffix and revision state acc to
purchase order
3: 
Batch number
4: 
Manufacturing year (yy), week (ww) and factory code (2)
5:
Bluetooth logotype.
6:
CE-logo.
7:FCC ID: Q23104001
FCC No.
Data Sheet
35
DS2, 2003-05-16
ROK 104 001
Marking
Figure 12
5.2
Module Marking
Reel Marking
The reel, reel box and dry pack has a label with the following information:
•
•
•
•
•
•
•
•
Infineon product number with revision
Customer product number with revision
Quantity
Reel-ID. (Batch No)
Factory code
Manufacturing date
Country of origin
Infineon logotype
1-6 above is also printed in BAR-code format
Data Sheet
36
DS2, 2003-05-16
ROK 104 001
Package Outlines
Package Outlines
2 max.
15.5 ±0.2
10.5 ±0.2
0.8 typ.
1.4
1.27
1.27
0.805
Figure 13
ERA00108
ROK 104 001 Mechanical Dimensions (maximum values) and
Footprint, Bottom View
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.
Data Sheet
37
Dimensions in mm
DS2, 2003-05-16
ROK 104 001
Package Outlines
6.1
Pinout (bottom view)
Please refer to Figure 4 for the positioning of each pad.
Table 11
7 GND
N.C.
N.C.
N.C.
VDD_RF GND
DIG
N.C.
N.C.
N.C.
N.C.
6 GND
SERIAL
DATA
GPIOB7
GPIOB6
N.C. VTP3
GND
GND
GND
GND GND
5 GND
N.C. VTP1
PWRFAIL N.C. VTP2
N.C.
N.C.
VD D
GND GND
4 GND
N.C.
GPIOB2
DETACH GPIOB4
N.C.
GND
UART1Tx
VDDIO
ON
N.C.
3 GND
GND
RESET
SERIAL
CLK
UART1Rx WAKEUP UART1RTS UART1CTS D+
N.C.
ANT
GND
EXTSYS UART2Rx EXTINT
WAKEUP
1 GND
GND
GND
GPIOB3
0 GND
N.C.
6.2
N.C. VTP4
UART2RTS PWRAV
AIL
GPIOB5
PCMSYNC N.C.
UART2CTS D-
GND
GND
PCMTX
PCMCLK PCMRx
N.C.
UART2Tx GND GND
N.C. - VTP5 N.C.
N.C.
GND
N.C.
N.C.
N.C.
N.C.
GND
Footprint, Land View
Pad Size: ø0.8 mm
Pitch: 1.27 mm
ERA00109
G0
Figure 14
Data Sheet
ROK 104 001 Mechanical Dimensions of Footprint,
Land Pattern View (seen from above the component)
38
DS2, 2003-05-16
ROK 104 001
Ordering Information
Ordering Information
Please contact Infineon Technologies for further information.
Packaging
The modules will be delivered in a tape & reel and dry pack, protecting them from ESD
and mechanical shock.
The tape width is 24 mm and the pitch is 12 mm. The diameter of the reel is 13 inches
and it contains 1500 modules.
Abbreviations
ASIC
- Application Specific Integrated Circuit
BER
- Bit Error Rate
CMOS
- Complementary Metal Oxide Semiconductor
DCE
- Data Circuit terminating Equipment
HCI
- Host Controller Interface
IC
- Integrated Circuit
ISM
- Industrial Scientific and Medical
LGA
- Land Grid Array
PCB
- Printed Circuit Board
PCM
- Pulse Code Modulation
Rx
- Receive
SIG
- Special Interest Group
Tx
- Transmit
UART
- Universal Asynchronous Receiver Transmitter
USB
- Universal Serial Bus
Data Sheet
39
DS2, 2003-05-16

---

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Title                           : rok104001-ds_a7_v55.book(rok104001-ds_a7_v55.fm)
Creator                         : wikman

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