LG Electronics USA LEO3-BAND13 LTE User Equipment User Manual
LG Electronics USA LTE User Equipment Users Manual
Users Manual
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| Document ID | 1114075 |
| Application ID | vKC0xa7GeHL+uEauulSzLw== |
| Document Description | Users Manual |
| Short Term Confidential | No |
| Permanent Confidential | No |
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| Document Type | User Manual |
| Display Format | Adobe Acrobat PDF - pdf |
| Filesize | 192.26kB (2403219 bits) |
| Date Submitted | 2009-05-21 00:00:00 |
| Date Available | 2009-11-16 00:00:00 |
| Creation Date | 2009-05-11 13:37:02 |
| Producing Software | doPDF Ver 6.0 Build 259 (Windows XP x32) |
| Document Lastmod | 2009-05-19 16:15:14 |
| Document Title | Microsoft Word - LTEPF-UE-HWRB3RB-MAN-004-UE RF Band13 HW Manual.doc |
| Document Creator | Microsoft Word - LTEPF-UE-HWRB3RB-MAN-004-UE RF Band13 HW Manual.doc |
| Document Author: | frank.lee |
FCC ID : BEJLEO3-BAND13 ATTACHMENT E. - User Manual - HCT CO., LTD. SAN 136-1, AMI-RI, BUBAL-EUP, ICHEON-SI, KYOUNGKI-DO, 467-701, KOREA TEL:+82 31 639 8517 FAX:+82 31 639 8525 www.hct.co.kr Report No. : HCT-RF09-0512 1/1 Updated File Rev. BAND13 RF board manual Written by Reviewed by Granted by Title Type LEO3 RF (Band13) Hardware Manual Managed by Manual ABSTRACT This document is a hardware RF board manual for LTE user equipment platform. Contents of this document are the description of each blocks and usage directions. It is recommended to peruse this manual before operating RF Board. HISTORY Rev Status Date Author Contents KEY WORDS 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Mobile Communication Technology Research Lab. 533 Hogye-dong, Dongan-gu, Anyang-shi, Kyongki-do, KOREA 33 34 35 36 37 38 ©Copyright, 2009 By LG Electronics Inc. All rights reserved. No part of this document may be reproduced in any way, or by any means, without the express written permission of LG Electronics Inc. LGE Proprietary MCTR Lab. Updated File Rev. BAND13 RF board manual 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 [Notice] 1. The product described in this manual may be modified without prior notice for reliability, functionality or design improvement. 2. Information contained in this manual is correct and reliable, but LG shall not be held responsible for damage due to the use of information, product or circuit or infringement of property rights or other rights. 3. This manual does not grant users the property rights and other rights of the third party or LG Electronics Inc. 4. No part of this manual may be transcribed or duplicated without the written permission of LG Electronics Inc. 5. The appearance of the product shown in this manual may slightly differ from that of the actual product. LGE Proprietary ii MCTR Lab. Updated File Rev. BAND13 RF board manual 10 11 12 13 14 15 16 17 18 19 20 CONTENTS 1 Introduction................................................................................................................................ １ 1.1 Scope ..................................................................................................................................... １ 1.2 Terminology............................................................................................................................ １ 2 Features and Photograph........................................................................................................... ２ 2.1 Features ................................................................................................................................. ２ 2.2 Photograph of the LEO3 RF board .......................................................................................... ２ 3 Block Diagram and Description .................................................................................................. ４ 3.1 Block Diagram ........................................................................................................................ ４ 3.2 Block Description .................................................................................................................... ４ 3.2.1 RX Blocks................................................................................................................... ４ 3.2.2 TX Blocks ................................................................................................................... ５ 3.2.3 Common Blocks ......................................................................................................... ５ 4 Interface .................................................................................................................................... ７ 4.1 Power supply .......................................................................................................................... ７ 4.2 Digital I/Q Data & Sampling Cock ........................................................................................... ８ 4.3 SPI ......................................................................................................................................... ８ 4.4 Control signals (GPIO’s).......................................................................................................... ９ 4.5 LEDs....................................................................................................................................... ９ 5 Placement Map....................................................................................................................... １０ 21 LGE Proprietary iii MCTR Lab. Updated File Rev. BAND13 RF board manual FIGURES Figure 1: Photograph of LEO3 RF ................................................................................................... ３ Figure 2: RF Block Diagram (For RX/TX) ........................................................................................ ４ Figure 3: Diagrams of Power supply................................................................................................ ７ Figure 4: Diagrams of Data & Clock Signal Interface....................................................................... ８ Figure 5: Diagram of SPI interface .................................................................................................. ９ Figure 7: Top placement map of LEO3 RF (Band13).................................................................... １０ 10 11 12 13 14 TABLES Table 1: List of SPI programmable devices ..................................................................................... ８ 15 16 LGE Proprietary iv MCTR Lab. Updated File Rev. BAND13 RF board manual Introduction 1.1 Scope This RF board is intended for radio frequency part of LTE user equipment platform to develop and verify LTE user equipment modem. This RF board is connected to 3rd version of LTE user equipment platform (LEO3) as the form of daughter board. This document intends to describe the brief architecture and usages of the board designed as RF part of LEO3 platform. 10 11 1.2 Terminology 12 13 14 15 16 17 18 19 20 21 22 23 24 ADC AFC DAC LO LTE LVDS MISO PA RF SAW UE VGA LGE Proprietary Analog to Digital Converter Automatic Frequency Compensation Digital to Analog Converter Local Oscillator Long Term Evolution Low-Voltage Differential Signaling Multi-In Single-Out Power Amplifier Radio Frequency Surface Acoustic Wave User Equipment Variable Gain Amplifier １ MCTR Lab. Updated File Rev. BAND13 RF board manual Features and Photograph 2.1 Features 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 2.2 Supporting RF band: BAND-13 Transmitting Frequency band: 777 ~ 787 MHz (10MHz) Receiving Frequency band: 746 ~ 756 MHz (10MHz) 2-Receive path and 1-Transmit path (MISO) +6V dc main power supply 19.2 MHz reference clock Transceiver Two chips transceiver solution by Infineon SMARTiLTE ICs(PMB_LTE_v093) Triple-band operation Three programmable LTE RF bandwidths: 5,10,20MHz Supply voltage rage from 2.7 ~ 3.0V nd Optional 2 supply voltage from 1.71 ~ 3.0V On-chip LDO Different power-down modes 3-wire bus programmable 10-bit ADC and DAC support 61.44 MHz for AD conversion 122.88 MHz for DA conversion Additional 16-bit HKDAC for Tx VGC and AFC Photograph of the LEO3 RF board 26 LGE Proprietary ２ MCTR Lab. Updated File Rev. BAND13 RF board manual Figure 1: Photograph of LEO3 RF - Mechanical size of board is 170 (W) X 170 (H) mm LGE Proprietary ３ MCTR Lab. Updated File Rev. BAND13 RF board manual Block Diagram and Description 3.1 Block Diagram 1.4-1.6V 1.71-3.0V 2.7-3.0V 2.7-3.0V 1.4-1.6V 1.71-3.0V 2.7-3.0V 2.7-3.0V Figure 2: RF Block Diagram (For RX/TX) 10 11 3.2 Block Description 12 13 3.2.1 RX Blocks 14 15 16 17 Two receive paths, RX0 path and RX1 path, are designed for MISO technology to increase the receiving data throughput. Both of receiving paths have the same structure and consist of the following transceivers and anything else analog devices. 18 19 20 21 LNA - This LNA is used for each receiving path LNA has the fixed 14dB gain at range of Band13 22 23 24 25 26 27 28 29 30 Transceiver (RX section) - LNA2 with three programmable gain steps - Complete analog baseband path without external components - Three programmable baseband channel filter bandwidths - Separate RX PGC 3-wire bus operation possible - Performance RX Total Gain : 2~80dB Gain step: 1dB LGE Proprietary ４ MCTR Lab. Updated File Rev. BAND13 RF board manual Gain switching time: under 6 us LNA2 Gain: 0/-6/-12 dB Gain deviation: +/-3 dB NFDSB:12dB – 42dB IP1dB: -15dBm 10 11 12 ADC - Dual 10-bit, 150MSPS analog-to-digital converter - 10-bit dedicated for each I/Q data - A/D clock speed: 61.44MHz - Two’s complement data formatting - Internal fixed reference mode (the input span is 2 Vp-p) 13 14 15 16 RX PLL - A Module type consisting of PLL and VCO - Programmalbe by 3 wire serial interface, SPI 17 18 19 3.2.2 TX Blocks 20 21 22 23 24 In transmit path, it is connected to a duplexer linked to ANT0. The transmitting data from LEO3 platform is the dedicated 10-bit digital signals for each I/Q via DAC. And its signaling uses LVDS system for high speed data transmitting. Refer to the block diagram at section 2.3. The transmit data pass through the following devices. 25 26 27 28 Level Translator - High speed data level conversion, LVDS-to-CMOS 29 30 31 32 33 34 DAC - Dual 10-bit, 125MSPS digital-to-analog converter - 10-bit dedicated for each I/Q data - D/A clock speed: 122.88MHz - Offset binary data formatting 35 36 37 38 39 40 41 42 43 44 45 Transceiver (TX section) - RF VGA’s with >85dB gain range - Three programmable baseband filter bandwidths - Performance POUTmax: 3~7dBm POUTmin: -77dBm TXGC range:0.5V ~ 2.2V Gain switching time:10usec NTX: -136dBm/Hz Carrier suppression:26dB 46 47 48 49 50 Digital Attenuator - Single 10 dB Step - Control voltage: -8.5V≤Vc≤+8V - Low Loss: 0.3 dB @ 900 MHz 51 52 53 54 Power Amplifier - Operating frequency: 1,710 ~ 1,785MHz - Max output power: 28.5dBm 55 56 57 58 3.2.3 Common Blocks 59 LGE Proprietary ５ MCTR Lab. Updated File Rev. BAND13 RF board manual VCTCXO - AFC supported by the external gain control voltage - Generating reference clock for transceiver 1st and 2nd respectively - Generating reference clock for RX PLL - Generating baseband clocks as the reference clock source 10 11 12 16-bit HKDAC for AFC and TX VGC control - Dual channel 16-bit DAC - Programmable by 3 wire serial interface, SPI - Its analog output voltage level functions the following: 1) AFC support 2) VGA gain control at transmit path LGE Proprietary ６ MCTR Lab. Updated File Rev. BAND13 RF board manual Interface The RF board for interfacing with LEO3 platform has 3 units of high speed 120pin connector. One of them has the role for main power supply, 6V. The others make the interface between RF to baseband (LEO3 platform) such as data transmitting and receiving, programming the SPI device, transmitting control signals, supplying A/D or D/A clock, monitoring the status and etc. 4.1 Power supply 10 11 12 13 Figure 3: Diagrams of Power supply 14 LGE Proprietary ７ MCTR Lab. Updated File Rev. BAND13 RF board manual 4.2 Digital I/Q Data & Sampling Cock Figure 4: Diagrams of Data & Clock Signal Interface 10 4.3 SPI 11 12 13 14 15 16 17 18 There are 3 programmable devices on RF board by using 3 wire SPI interface. 3 units SPI blocks exist on the interface with baseband platform. They are listed at Table 1 (Also refer to block diagram at Figure 5). st nd At this list, 1 transceiver and 2 transceiver consist of each SPI0 and SPI1. Also 16-bit HKDAC has the dedicated by SPI2. It can be possible by using a dedicated chip select signal for each device with LLDM software. When selecting one of them, a dedicated chip select signal enables its device to program. 19 20 SPI Device st 1 Transceiver nd Transceiver 21 16bit-HKDAC 22 SPI block SPI0 SPI1 SPI2 23 SPI data bit 16 24 25 Table 1: List of SPI programmable devices 26 LGE Proprietary ８ MCTR Lab. Updated File Rev. BAND13 RF board manual Figure 5: Diagram of SPI interface 4.4 Control signals (GPIO’s) 10 11 For control the RF blocks, the control signals from LEO3 platform are connected as the below. 12 13 14 15 16 17 18 19 20 21 22 BS(1)_IDLE: Enables the LDOs and LED for a self-Indicator TX_ON: Enables the LDOs at transmit path and transmit block at 1st Transceiver (Including turns on LED for a self-indicator) PA_R0 : Controls the power mode of transmitter block (Including D-attenuator) PA_EN : Enables PA LNA_EN0: Enables the LNA of antenna0 path (At the 1st transceiver) LNA_EN1: Enables the LNA of antenna1 path (At the 2nd transceiver) TCXO_ON: Enables the LDO for source clock (VC-TCXO) st GPIO_SLEEPB(0): Enables the 1 transceiver (Via Master on signal) GPIO_SLEEPB(1): Enables the 2nd transceiver (Via Master on signal) 23 24 25 4.5 LEDs 26 27 28 29 30 To indicate PLL lock status of 1st transceiver(LD_RFIC0), 2nd transceiver(LD_RFIC1) and RX PLL, three LEDs are present on the board. When locked at the frequency by setting the SPI from LEO3, LD output of each Transceiver and RX PLL turns on these LEDs. Anything else, there are two more LEDs(D4032 D403) for TX_ON and IDLE. 31 32 LGE Proprietary ９ MCTR Lab. Updated File Rev. BAND13 RF board manual Placement Map Figure 6: Top placement map of LEO3 RF (Band13) LGE Proprietary １０ MCTR Lab. Updated File BAND13 RF board manual Notice OEM integrators and installers are instructed that the phrase. This device contains Warning: Exposure to Radio Frequency Radiation The radiated output power of this device is far below the FCC radio frequency exposure limits. Nevertheless, the device should be used in such a manner that the potential for human contact during normal operation is minimized. In order to avoid the possibility of exceeding the FCC radio frequency exposure limits, human proximity to the antenna should not be less than 20cm during normal operation. The gain of the antenna for 3GPP-Band13(777~787MHz) must not exceed -2.3 dBi. The antenna(s) used for this transmitter must not be co-located or operating in conjunction with any other antenna or transmitter. LGE Proprietary １1 MCTR Lab. Updated File Written by Rev. LEO3 Platform Board Manual.doc 2009/05/08 Reviewed by Granted by Title Type LEO3 Platform Board Manual 1.0 Managed by Manual ABSTRACT HISTORY Rev Status Date Author Contents KEY WORDS ©Copyright, 2009 By LG Electronics Inc. All rights reserved. No part of this document may be reproduced in any way, or by any means, without the express written permission of LG Electronics Inc LGE Proprietary MCTR Lab. Updated File 10 11 12 13 14 15 16 17 18 19 20 Rev. LEO3 Platform Board Manual.doc 2009/05/08 1.0 CONTENTS 1 Introduction................................................................................................................................ １ 1.1 Scope ..................................................................................................................................... １ 1.2 Terms and Definitions ............................................................................................................. １ 2 Key Features and Pictures of the Platform ................................................................................. １ 2.1 Key Features .......................................................................................................................... １ 2.1.1 L1000 ......................................................................................................................... １ 2.1.2 Memory ...................................................................................................................... ２ 2.1.3 Other peripherals........................................................................................................ ２ 2.2 Pictures and Placement of the Platform .................................................................................. ２ 2.2.1 Pictures of LEO3 Platform .......................................................................................... ２ 2.2.2 Placement Map........................................................................................................... ３ 3 Power Supplies.......................................................................................................................... ４ 3.1 Main Board Power................................................................................................................... ４ 3.2 RF Board Power ..................................................................................................................... ４ 3.3 L1000...................................................................................................................................... ４ 3.4 Other Peripherals.................................................................................................................... ４ 4 Switch Setting............................................................................................................................ ４ 5 LED Monitor............................................................................................................................... ７ 6 Image Downloading ................................................................................................................... ７ 21 LGE Proprietary ii MCTR Lab. Updated File Rev. LEO3 Platform Board Manual.doc 2009/05/08 1.0 FIGURES Figure 1. LEO3 Platform (Top Side) ................................................................................................ ２ Figure 2. LEO3 Platform (Bottom Side)........................................................................................... ３ Figure 3. LEO3 Platform Board Layout............................................................................................ ３ LGE Proprietary iii MCTR Lab. Updated File Rev. LEO3 Platform Board Manual.doc 2009/05/08 1.0 TABLES Table 1. DIP switch setting for L1000 boot configuration ................................................................. ５ Table 2. DIP switch setting for manual IRQ generation.................................................................... ５ Table 3. DIP switch setting for LED_DEBUG................................................................................... ６ Table 4. DIP switch setting for Ethernet PHY................................................................................... ６ Table 5. Jumper setting for UART signal connection ....................................................................... ７ LGE Proprietary iv MCTR Lab. Updated File 2009/05/08 10 11 12 13 14 15 16 17 18 Rev. LEO3 Platform Board Manual.doc 1.0 Introduction 1.1 Scope This document describes briefly the board level operations, key features and the environment of the LEO3 Platform Rev.A / Rev.B. The purpose of this platform is the verification of LG LTE ASIC, namely ‘L1000’, and the evaluation of LG UE system performance. The further details about the characteristics and functions of L1000 are available on other documents. LEO3 platform consists of a core board, a main board, an RF board and application boards. For the core board, two types of ‘MOC-D’ and ‘MDC-D’ are available on the LEO3 platform. With the ‘MOC-D’ board, it is possible to implement and perform the functionalities of ‘Mobile Platform’ with additional application boards. In case of there being no application boards, also is it possible to implement and perform the functionalities of ‘Data Card’ with USB cables. With the ‘MDC-D’ board, it is possible to implement and perform the functionalities of ‘Data Card’ the same as ‘MOC-D’ without application boards. And is it possible to probe and capture the signals (raw data) out of the modem part with the external DSP Bus I/F and Ethernet MAC. But it will be focused on MOC-D only without application board in this document. Although this platform is built with some boards, it will be described on the baseband board without application and RF board. 19 20 21 1.2 Terms and Definitions 22 LTE: Long Term Evolution M-DDR: Mobile DDR MOC-D: Modem Only Core - D MDC-D: Modem and DSP Core – D GMII: Gigabit Media Independent Interace DM: Diagnostic Monitoring 23 24 25 26 27 28 29 30 31 Key Features and Pictures of the Platform 32 33 2.1 Key Features 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 2.1.1 · · · · · · · · · · · · · · · · · · · · · · · L1000 ARM1136JF-S with 307.2MHz core clock 32kB I-Cache/ 32kB D-Cache 32kB I-TCM/ 16kB D-TCM 64kB SRAM 128kB Boot ROM 16-channel DMA with 64bit AHB interface 64bit/32bit AHB interface with 153.6MHz 32bit M-DDR SDRAM controller with 153.6MHz (up to 2Gb) 8bits NAND Flash controller 2 port USB 2.0 HS device controller (Host interface/DM interface) 20-GPIOs with interrupt capability 1-channel I2C 1-channel UART 3-channel 4wire SPIs for RF control 1-channel general 3wire SPI 1-channel general 4wire SPI 19.2MHz reference clock 48MHz clock for USB/UART/I2C/Timer 122.88MHz DAC / 61.44MHz ADC clock 32.768kHz RTC clock 1 Tx antenna interface with 10bit I/Q 2 Rx antenna interface with 10bit I/Q External hardwire boot configuration LGE Proprietary １ MCTR Lab. Updated File · Rev. LEO3 Platform Board Manual.doc 2009/05/08 1.0 Debugger port (JTAG + ETM11) 2.1.2 · · Memory MCP with 2Gb 8bit NAND flash / DDR333 1Gb 32bit M-DDR 64Mb Serial NOR flash (4wire SPI) 2.1.3 · · · · · · · · · Other peripherals PMIC for evaluation and feasibility check 2-USB connectors LVDS drivers for 10bit I/Q Tx signal and DAC clock Application board interface (unavailable in this document) 1-channel SIM connector 1-channel 4bit SDIO connector (only available for MDC-D core board) JTAG/ETM 11 debug ports for ARM (ETM clock with 76.8MHz) JTAG debug port for DSP (only available for MDC-D core board) 1-Gigabit Ethernet (GMII mode) connector for DSP (only available for MDC-D core board) RF interface with connector (bottom side) Reset switch for global hardware reset 15 LEDs and 2 DIP-switches for debug 5 LEDs for Ethernet mode monitor (only available for MDC-D core board) 8 LEDs for DSP GPIO (only available for MDC-D core board) 2 DIP-switches for boot configuration setting 10 11 12 13 14 15 16 17 · · · · · · 18 19 20 21 22 23 24 25 26 2.2 Pictures and Placement of the Platform 27 28 2.2.1 Pictures of LEO3 Platform 29 30 +12V 31 Power SW. SIM L1000 JTAG ETM11 USB UART DIP SW. 32 Figure 1. LEO3 Platform (Top Side) 33 LEDs 34 LGE Proprietary ２ LEDs MCTR Lab. Updated File 2009/05/08 Rev. LEO3 Platform Board Manual.doc 1.0 Rx1 ANT Rx0/ Tx ANT Figure 2. LEO3 Platform (Bottom Side) 2.2.2 Placement Map Figure 3. LEO3 Platform Board Layout LGE Proprietary ３ MCTR Lab. Updated File 2009/05/08 Rev. LEO3 Platform Board Manual.doc 1.0 Power Supplies 3.1 Main Board Power Main external power is supplied from DC input jack on the upper left corner of the baseband platform board. The regular input voltage is 12V. For this platform, an external power adaptor ‘CLG-60-12’ from Mean Well is provided with maximum current rating of 5A. 10 11 12 13 3.2 RF Board Power The RF board power is supplied from the mian board RF connector. The regular RF board input voltage is 6V, which is regulated from the main board power so an additional power supply for RF board is not required. 14 15 16 3.3 · · · · 17 18 19 20 L1000 Core Power - +1.2V Memory controller / Flash controller power - +1.8V I/O Power - +2.8V USB Power - +3.3V 21 22 3.4 Other Peripherals L1000 I/O power - +2.8V LVDS driver Power - +3.3V Reset Power - +2.8V SIM L/T Output Power - +1.8V / +3.0V Ethernet Transceiver Analog Power - +1.8V / +2.5V (only available for MDC-D core board) · Ethernet I/O Power - +3.3V (only available for MDC-D core board) · DSP Core Power - +1.25V (only available for MDC-D core board) · DSP Memory Controller Power - +1.8V (only available for MDC-D core board) · · · · · 23 24 25 26 27 28 29 30 31 32 33 34 Switch Setting 35 36 37 38 Configuration and control settings are done by 5-DIP switches (SW4, SW5, SW6, SW7, SW8) and 2 jumpers (J3, J4). The assignments of each signal and their descriptions are in the following tables. 39 LGE Proprietary ４ MCTR Lab. Updated File 2009/05/08 Rev. LEO3 Platform Board Manual.doc 1.0 SW7 No. Name JTAG_CFG(0) Defaul ON JTAG_CFG(1) OFF EPI_MODE ON USB_MODE OFF PWR_CUT_MODE OFF REFCLK_SEL OFF NAND_CFG(0) OFF NAND_CFG(1) OFF No. Name MODE(0) Defaul ON MODE(1) OFF MDOE(2) OFF MODE(3) OFF Description JTAG_CFG[1:0] [OFF:OFF] No JTAG [OFF:ON] ARM Only [ON:OFF] CC5 Only [ON:ON] ARM-CC5 *ON: High, OFF: Low [OFF] Dedicated Address/Data EPI I/O [ON] Muxed Address/Data EPI I/O *ON: HIgh, OFF: Low [OFF] UTMI mode [ON] ULPI mode *ON: High OFF: Low [OFF] Power cut disable [ON] Power cut enable *ON: High, OFF: Low [OFF] On-board VCTCXO 19.2MHz [ON] RF board 19.2MHz *ON: High, OFF: Low (Rev.A) *ON: Low, OFF: High (Rev.B) [ON] 4byte address [OFF] 5byte address *ON: Low, OFF: High [ON] Small block (1page: 512byte + 16byte) [OFF] Large block (1page 2048byte +64byte) *ON: Low, OFF: High SW8 Description MODE[2:0] [OFF:OFF:OFF] Undefined [OFF:OFF:ON] NAND boot [OFF:ON:OFF] Serial Flash boot [OFF:ON:ON] EPI boot [ON:OFF:OFF] SDIO boot [ON:OFF:ON] USB boot [ON:ON:OFF] Serial Flash boot (for debug) [ON:ON:ON] Test *ON: High, OFF: Low [OFF] Secure Boot disable [ON] Secure Boot enable *ON: High OFF: Low Table 1. DIP switch setting for L1000 boot configuration LGE Proprietary ５ MCTR Lab. Updated File 2009/05/08 Rev. LEO3 Platform Board Manual.doc 1.0 SW6 No. Name IRQ(0) Defaul OFF IRQ(1) OFF IRQ(2) OFF IRQ(3) OFF Description [OFF] Low level [ON] High level *ON: High, OFF: Low [OFF] High level (Rev.A), Low level (Rev.B) [ON] Low level (Rev.A), High level (Rev.B) *ON: High, OFF: Low (Rev.A) *ON: Low, OFF: High (Rev.B) [OFF] High level [ON] Low level *ON: Low, OFF: High [OFF] High level [ON] Low level *ON: Low, OFF: High Table 2. DIP switch setting for manual IRQ generation LGE Proprietary ６ MCTR Lab. Updated File 2009/05/08 Rev. LEO3 Platform Board Manual.doc 1.0 * Caution) Please, be careful to switch ‘ON” for the SW5. Switching ‘ON’ should be done only when the corresponding GPIO directions have defined as ‘Input’. Otherwise (if defined as ‘Output’), it would be possible for the L1000 to have a damage. SW5 No. Name LED_DEBUG(0) Defaul OFF LED_DEBUG(1) OFF LED_DEBUG(2) OFF LED_DEBUG(3) OFF LED_DEBUG(4) OFF LED_DEBUG(5) OFF LED_DEBUG(6) OFF LED_DEBUG(7) OFF Description Corresponding to GPIO(0) of [OFF] Low level [ON] High level *ON: High, OFF: Low Corresponding to GPIO(1) of [OFF] Low level [ON] High level *ON: High, OFF: Low Corresponding to GPIO(2) of [OFF] Low level [ON] High level *ON: High, OFF: Low Corresponding to GPIO(3) of [OFF] Low level [ON] High level *ON: High, OFF: Low Corresponding to GPIO(4) of [OFF] Low level [ON] High level *ON: High, OFF: Low Corresponding to GPIO(5) of [OFF] Low level [ON] High level *ON: High, OFF: Low Corresponding to GPIO(6) of [OFF] Low level [ON] High level *ON: High, OFF: Low Corresponding to GPIO(7) of [OFF] Low level [ON] High level *ON: High, OFF: Low L1000 L1000 L1000 L1000 L1000 L1000 L1000 L1000 Table 3. DIP switch setting for LED_DEBUG * SW4 is not available for MOC-D core board LGE Proprietary ７ MCTR Lab. Updated File 2009/05/08 Rev. LEO3 Platform Board Manual.doc 1.0 SW4 No. Name D_PHYAD(1) D_PHYAD(2) D_PHYAD(3) D_PHYAD(4) D_ETH_MAN_MDIX Defaul OFF OFF OFF OFF OFF D_ETH_MULTI_EN ON D_ETH_MDIX_EN OFF DSP_PWRDOWN OFF Description D_PHYAD[4:1] [OFF] Ethernet PHY address value 1 [ON] Ethernet PHY address value 0 *ON: Low, OFF: High [OFF] Cross-over line mode [ON] Straight lien mode *ON: Low, OFF: High [OFF]: Multiple node (master) [ON]: Single node (slave) *ON: Low, OFF: High [OFF]: Enable auto MDIX [ON]: Disable auto MDIX (set by D_ETH_MAN_MDIX) *ON: Low, OFF: High [OFF]: DSP clock / reset enable [ON]: DSP clock / reset disable *ON: Low, OFF: High Table 4. DIP switch setting for Ethernet PHY LGE Proprietary ８ MCTR Lab. Updated File Rev. LEO3 Platform Board Manual.doc 2009/05/08 1.0 Jumper No. J3 J4 Name UART_CTS/ UART_RTS UART_RXD/ UART_TXD Default 1-2 connection 3-4 connection 1-2 connection 3-4 connection [1-2, [1-3, [1-2, [1-3, 3-4] 2-4] 3-4] 2-4] Description for the cross UART cable for the straight UART cable for the cross UART cable for the straight UART cable Table 5. Jumper setting for UART signal connection 10 11 LED Monitor In the platform board, 15 LEDs are provided for the L1000 debug monitoring such as crash debug, timing check, interrupt flag, status of L1000 etc. The definition of monitor is not given yet for each LED explicitly. (TBD) The LEDs for LED_DEBUG[0:7] and the LEDs for IRQ[0:3] are located lower left-hand corner of the main board. The LEDs for STATUS[0:2] are located lower right-hand corner of the main board. All of them are indicated with white silkscreen printing on the main board respectively. 12 13 14 15 16 17 Image Downloading If the other boot modes than ‘JTAG Boot’ such as ‘NAND Flash Boot’, ‘NOR Flash Boot’ are to be used, they require the related image downloading into NAND flash or NOR flash. For further information about the image downloading including the other boot load with USB or SDIO, refer to other related documents. 18 LGE Proprietary ９ MCTR Lab.
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