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| Document Title | L506 hardware design |
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/$+DUGZDUH'HVLJQ
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LTE Module Series
Version： V1.0
Date： 2016-09-13
&RS\ULJKW 6KDQJKDL 0RELOHWHN &RPPXQLFDWLRQ /WG
Shanghai Mobiletek Communication Ltd
L506 Hardware Design
Notice
Some features of the product and its accessories described herein rely on the software installed,
capacities and settings of local network, and therefore may not be activated or may be limited by local
network operators or network service providers.
Thus, the descriptions herein may not exactly match the product or its accessories which you purchase.
Shanghai Mobiletek Communication Ltd reserves the right to change or modify any information or
specifications contained in this manual without prior notice and without any liability.
Copyright
This document contains proprietary technical information which is the property of Shanghai Mobiletek
Communication Ltd. copying of this document and giving it to others and the using or communication
of the contents thereof, are forbidden without express authority. Offenders are liable to the payment of
damages. All rights reserved in the event of grant of patent or the registration of a utility model or
design. All specification supplied herein are subject to change without notice at any time.
DISCLAIMER
ALL CONTENTS OF THIS MANUAL ARE PROVIDED “AS IS”. EXCEPT AS REQUIRED BY
APPLICABLE LAWS, NO WARRANTIES OF ANY KIND, EITHER EXPRESS OR IMPLIED,
INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
AND FITNESS FOR A PARTICULAR PURPOSE, ARE MADE IN RELATION TO THE
ACCURACY, RELIABILITY OR CONTENTS OF THIS MANUAL.
TO THE MAXIMUM EXTENT PERMITTED BY APPLICABLE LAW, IN NO EVENT SHALL
SHANGHAI MOBILETEK COMMUNICATION LTD BE LIABLE FOR ANY SPECIAL,
INCIDENTAL, INDIRECT, OR CONSEQUENTIAL DAMAGES, OR LOSS OF PROFITS,
BUSINESS, REVENUE, DATA, GOODWILL SAVINGS OR ANTICIPATED SAVINGS
REGARDLESS OF WHETHER SUCH LOSSES ARE FORSEEABLE OR NOT.
Copyright © Shanghai Mobiletek Communication Ltd
L506 Hardware Design
Version History
Date
Version Description of change
2016-09-13
V1.0
Initial
Copyright © Shanghai Mobiletek Communication Ltd
Author
L506 Hardware Design
1 About this document
1.1Applicable scope
This document describes the L506 series 4G LTE LCC Module (hereinafter referred to as L506),
the basic specifications, product electrical characteristics, design guidance and hardware interface
development guidance. Users need to follow this documentation requirements and guidance for
design.
This document applies only to L506 products in the application development.
1.2 Writing purpose
This document provides the design and development basis for the product users. By reading this
document, users can have a whole understanding of the product, the technical parameters of the
product have a clear understanding, and can be used in this document to complete the development
of Internet access functions.
This hardware development document not only provides the product functional features and
technical parameters, but also provides product reliability testing and related testing standards,
business functions to achieve process, RF performance indicators and user circuit design guidance.
1.3 Support and reference documents list
In addition to the hardware development documentation, we also provide a guide to the
development board based on this product manual and software development instruction manual, 1-1 is
supported as a list.
Table 1-1 support document list
No.
Documents
《L506 AT Command User Guide》
《L506_SPEC.docx》
《L506 EVB User Manual》
《L506 Schematic checklist》
《L506 Layout checklist》
《L506_Reference Design_V3.pdf》
《L506_V1_DECAL.sch》
Copyright © Shanghai Mobiletek Communication Ltd
L506 Hardware Design
《L506_V3_DECAL.PCB》
1.4 Terms and Abbreviations
Table 1-2 is the Document relative Terms and Abbreviations。
Table 1-2 Terms and Abbreviations
Abbreviation
Descriptions
ESD
Electro-Static discharge
USB
Universal Serial Bus
UART
Universal Asynchronous Receiver Transmitter
SDCC
Secure Digital Card Controller
USIM
Universal Subscriber Identification Module
SPI
Serial Peripheral Interface
I2C
Inter-Integrated Circuit
PCM
Pulse-coded Modulation
I/O
Input/output
LED
Light Emitting Diode
GPIO
General-purpose Input/Output
WCDMA
Wideband Code Division Multi Access
UMTS
Universal Mobile Telecommunication System
HSDPA
High Speed Downlink Packet Access
HSUPA
High Speed Uplink Packet Access
AGPS
Assisted Global Positioning System
BER
Bit Error Rate
DL
Downlink
COEX
WLAM/LTE-ISM coexistence
SMPS
Switched-mode power supplies
LTE
Long Term Evolution
FDD
Frequency Division Duplexing
TDD
Time Division Duplexing
Copyright © Shanghai Mobiletek Communication Ltd
L506 Hardware Design
DPCH
Dedicated Physical Channel
DPCH_Ec
Average energy per PN chip for DPCH. DPCH
Copyright © Shanghai Mobiletek Communication Ltd
L506 Hardware Design
2 Product Overview
L506 is a series module and design for global market, It include standard series and LD series.
User can choose the module based on the wireless network configuration. In this document, the
supported radio band is described in the following items. This product is a LCC interface of 4G
wireless internet module, with the high speed, small size, light weight, high reliability can be widely
used in various products and devices with wireless internet access:
Table 2-1 L506 series module type correspond band
Support band
WCDMA
LTE-FDD
GNSS
L506
UMTS850
●
UMTS1900
●
FDD_LTE B2
●
FDD_LTE B4
●
FDD_LTE B5
●
FDD_LTE B13
●
FDD_LTE B17
●
GPS L1 BAND
●
GLONASS
●
BEIDOU
●
Table 2-2 Differences list between L506A standard series and
L506 LD series
Feature
L506 Standard series
L506 LD series
Voice
YES
NO
GNSS
YES
NO
Diversity reception
YES
NO
Data transmission specifications
LTE-FDD
- Uplink up to 50Mbps,
- Downlink up to 150Mbps
Copyright © Shanghai Mobiletek Communication Ltd
L506 Hardware Design
HSPA+
- Uplink up to 5.76 Mbps,
- Downlink up to 42 Mbps
UMTS
- Uplink/Downlink up to 384Kbps
Interface
SUB2.0
UART
USIM (3V/1.8V)
GPIO
ADC
SDIO
PCM
SPI
I2C
NETLIGHT
POWER KEY
RESET
Dimensions（L×W×H）:30mm×30mm×2.8mm
Figure 2-1
TOP VIEW
Product Physical Map
BOTTOM VIEW
2.1 Package Dimensions
The product module is 87-PIN LCC package module, in addition to signal pin, also contains many
special heat welding disc to improve joint performance, mechanical strength and heat dissipation
Copyright © Shanghai Mobiletek Communication Ltd
L506 Hardware Design
performance, the heat release welding disc 12 and uniform distribution in the bottom of the PCB.
Package size is 30 x 30 mm, the height is 2.8 mm. Pin 1 position from the bottom of the belt angle
welding plate to identify, the missing corner where the direction of the corresponding module angle
pad, figure 2-2 is the product dimension type map:
(a)Top Dimensions (Unit mm)
Copyright © Shanghai Mobiletek Communication Ltd
(b)Top Detail (Unit mm)A
L506 Hardware Design
(c)Bottom Dimensions (Unit mm)
Note: antenna feed point in actual use of the customers don't need (PCB assembly, the stencil
file).
(d)Bottom Detail B (Unit mm)
Copyright © Shanghai Mobiletek Communication Ltd
L506 Hardware Design
(e)Bottom Detail C (Unit mm)
Copyright © Shanghai Mobiletek Communication Ltd
L506 Hardware Design
(e)Side view Dimensions(Unit mm)
Figure 2-2 Module Dimensions
2.2 Product Function Outline
2.2.1 Hardware Diagram
This product mainly includes the following signal group：USB Interface signal、USIM card
Interface signal、I2C Interface signal、UART Interface signal、PCM Interface signal、UART
Interface signal、SPI interface、Module startup、Module control signal、Power supply and ground.
Copyright © Shanghai Mobiletek Communication Ltd
L506 Hardware Design
2.2.2 Radio frequency function
RF
Function Overview：
Five-Band FDD-LTE B2/B4/B5/B13/B17
Dual-Band UMTS/HSDPA/HSPA+ B2/B5
GPS/BEIDOU/GLONASS
The operating frequency range of the transmitter is shown in table 2-2.
Table 2-3 RF frequency band
Working band
Upstream band（Uplink）
Downlink frequency（Downlink）
WCDMA B5
824 MHz~849 MHz
869 MHz~894 MHz
WCDMA B2
1850 MHz — 1910 MHz
1930 MHz — 1990MHz
FDD_LTE B2
1850 MHz — 1910 MHz
1930 MHz — 1990MHz
FDD_LTE B4
1710 MHz~1755 MHz
2110 MHz~2155 MHz
FDD_LTE B5
824 MHz~849 MHz
869 MHz~894 MHz
FDD_LTE B13
777 MHz~787 MHz
746 MHz~756 MHz
FDD_LTE B17
704 MHz~716 MHz
734 MHz~746 MHz
GPS L1 BAND
--
1574.4 ～1576.44 MHz
GLONASS
--
1598 ～1606 MHz
BEIDOU B1
--
1559.05 ～1563.14 MHz
Copyright © Shanghai Mobiletek Communication Ltd
L506 Hardware Design
Table 2-4 Conducted transmission power
Working Band
Max Power
Min Power
WCDMA B5
22.5dBm +/-1dB
<-50dBm
WCDMA B2
23dBm +/-1dB
<-50dBm
FDD_LTE B2
22dBm +/-1dB
<-40dBm
FDD_LTE B4
22dBm +/-1dB
<-40dBm
FDD_LTE B5
22dBm +/-1dB
<-40dBm
FDD_LTE B13
21dBm +/-1dB
<-40dBm
FDD_LTE B17
21dBm +/-1dB
<-40dBm
Table 2-5 Conducted receive sensitivity
Receive sensitivity(Typical)
Receive sensitivity(MAX)
WCDMA B2
< -108dBm
3GPP
WCDMA B5
< -109dBm
3GPP
ID NQ
EN
TI
AL
Working Band
Table 2-6 Reference sensitivity (QPSK)
Channel bandwidth
E-UTRA Band
1.4 MHz
3 MHz
5 MHz
10 MHz
15 MHz
20 MHz
Duplex Mode
-102.2
-99.7
-100
-97.2
-96.2
-95
FDD
-102.2
-99.7
-98
-95
-94.2
-93
FDD
-102.2
-99.7
-98
-95
--
--
FDD
13
--
--
-100.2
-97.2
--
--
FDD
17
--
--
-97
-94
--
--
FDD
CO
Copyright © Shanghai Mobiletek Communication Ltd
L506 Hardware Design
3 Interface Description
3.1 PIN Definition
3.1.1 Pin I/O parameter definition
The I/O parameter definition of the product is shown in table 3-1.
Table 3-1 I/O parameter definitions
Pin attribute symbol
Description
PI
Power input PIN
PO
Power output PIN
AI
Analog input
AIO
Analog signal input/output PIN
I/O
Digital signal input/output PIN
DI
Digital signal input
DO
Digital signal output
DOH
Digital output with high level
DOL
Digital output with low level
PD
Pull down
PU
Pull up
AO
Analog output
3.1.2 Pin Map
L506 haver different version, and the correspond pin definition show as special mark (* mark or
#mark) in the pin map. In the different hardware version the corresponding pin have differential
using, detail description show as below chart. All hardware interfaces which connect L506 to
customers’ application platform are through 87 pins pads (Metal half hole). Figure 3-1 is L506
outline diagram.
Copyright © Shanghai Mobiletek Communication Ltd
GND
VBAT
GND
BOOT_CFG1
62
61
87
GND
65
VBAT
RTS
66
63
CTS
67
64
RI
DCD
70
RXD
TXD
71
68
DTR
72#
69#
PCM_IN
PCM_OUT
73
PCM_SYNC
75
74
GND
PCM_CLK
76
GND
78
77
GND
GNSS_ANT
79
COEX3
80
86
L506 Hardware Design
85
GND
PWRKEY
SPI_MISO
SPI_MOSI
11
12
USB_DP
13
GND
14
USB_ID
16
USIM_DATA
17
FLIGHTMODE
53
USIM_DET
52#
GPIO_1/
WAKEUP_OUT
51
NETLIGHT
50#
GPIO_2/
WAKEUP_IN
49
STATUS
48
SD1_DET
47
ADC1
46
ADC2
45#
GPIO_0
44
VDD_EXT
43
GND
42*
USIM_CLK
19
USIM_VDD
20
41
GND
82
MAIN_ANT
38
39
VBAT
VBAT
83
37
GND
40
36*
SDC1_CLK
GND
35*
COEX1
34*
P_CLK
33*
SDC1_DATA0
VREG_L2_1V8
32*
29*
SDC1_DATA1
SDC1_CMD
28#
GPIO_3
31*
27*
SDC1_DATA2
SDC1_DATA3
26
30*
25
SD_CLK
81
SD_DATA3
GND
SCL
54
18
24
USIM_RST
SDA
55
15
SD_DATA2
VDD_1V8
23
USB_DN
L506 LCC
TOP
22
USB_VBUS
10
SD_DATA1
GND
GND
56
SD_DATA0
SPI_CS
GND
57
21
SPI_CLK
58
SD_CMD
GND
AUX_ANT
84#
RESET
GND
59
COEX2
GND
BOOT_CFG0
60
Figure 3-1 Pin Map View (Top View)
Note: 1.
#flag pin in Figure 3-1 stand for multi-function pin. Detail description show as in
corresponding function description.
3.1.3 PIN Definition and function description
Table 3-2 Pin definition
Pin No.
Pin description
Pin No.
Pin description
GND
GND
PWRKEY
RESET
Copyright © Shanghai Mobiletek Communication Ltd
L506A Hardware Design
GND
SPI_CLK
SPI_MISO
SPI_MOSI
SPI_CS
10
GND
11
USB_VBUS
12
USB_DN
13
USB_DP
14
GND
15
VDD_1V8
16
USB_ID
17
USIM_DATA
18
USIM_RST
19
USIM_CLK
20
USIM_VDD
21
SD_CMD
22
SD_DATA0
23
SD_DATA1
24
SD_DATA2
25
SD_DATA3
26
SD_CLK
27*
SDC1_DATA2
28#
GPIO_3
29*
SDC1_DATA1
30*
31*
SDC1_DATA3
32*
SDC1_CMD
33*
SDC1_DATA0
34*
VREG_L2_1V8
35*
32K_SLEEP_CLK
36*
SDC1_CLK
37
GND
38
VBAT
39
VBAT
40
GND
41
GND
42*
43
GND
44
VDD_EXT
45#
GPIO_0
46
ADC2
47
ADC1
48
SD1_DET
49
STATUS
50#
GPIO_2/WAKEUP_IN
51
NETLIGHT
52#
GPIO_1/WAKEUP_OUT
53
USIM_DET
54
FLIGHTMODE
55
SCL
56
SDA
57
GND
58
GND
59
AUX_ANT
60
GND
61
GND
62
VBAT
63
VBAT
64
GND
65
GND
66
RTS
67
CTS
68
RXD
Copyright © Shanghai Mobiletek Communication Ltd
L506 Hardware Design
69#
RI
70
DCD
71
TXD
72#
DTR
73
PCM_OUT
74
PCM_IN
75
PCM_SYNC
76
PCM_CLK
77
GND
78
GND
79
GNSS_ANT
80
GND
81
GND
82
MAIN_ANT
83
COEX1
84
COEX2#
85
BOOT_CFG0
86
COEX3
87
BOOT_CFG1
Table 3-3 Pin Function Description
Power interface
Pin Name
Pin No.
I/O
Description
Content
Power supply voltage,
VBAT
38,39,62,63
PI
VBAT=3.4V~4.2V.
The power supply
for system Maximum
load current must
above 2A.
Module
VDD_1V8
15
PO
LDO
output
power ,1.8V
output,
Max
current
150mA,
For I/O, MCP, SLIC,
If not use keep it
open.
sensors.
Module
VDD_EXT
44
PO
LDO
output
power, 2.85V output,
Max current 300mA.
Only
,40,41,43,57,5
VDD. If not use
keep it open.
Ground.
8,60,61,64,65,
77,78,80,81
System Control
Pin Name
Pin No.
I/O
PWRKEY
DI
RESET
DI
Description
System power on/off
input, active low.
System reset input,
active low.
Copyright © Shanghai Mobiletek Communication Ltd
for
external SD Card
1,2,5,10,14,37
GND
use
Content
L506 Hardware Design
The input signal, used
FLIGHTMODE
54
DI, PU
to control the system
Pull
UP
to
into flight mode, H:
VDD_1V8（PIN 15）
flight mode; L: normal
with 10K resistor
mode
Module status(GPIO)
Pin Name
Pin No.
I/O
NETLIGHT
51
DO
Description
Identify
the
40
DO
system
network status.
Module
STATUS
Content
status
identify: High level
power on, low level
power off.
SD interface
Pin Name
Pin No.
I/O
Description
Content
SD_CMD
21
DO
SDIO command
SD_DATA0
22
I/O
SDIO data
Advice add the ESD
SD_DATA1
23
I/O
SDIO data
on
SD_DATA2
24
I/O
SDIO data
Slot. If not use
SD_DATA3
25
I/O
SDIO data
keep it open
SD_CLK
26
DO
SDIO clock
SD_CARD_DET_N
48
DI，PU
you
SD
card
Input pin as SD card
L506A
detecting.
internal pull up,
Copyright © Shanghai Mobiletek Communication Ltd
have
L506 Hardware Design
H: SD card is removed
so SD card slot
L: SD card is inserted
should
choose
insert detect PIN
connect
the
ground. If not use
keep it open
SIM interface
Pin Name
USIM_DETECT
Pin No.
53
I/O
DI，PU
Description
Content
Input pin as USIM card
L506
detect pin.
internal pull up.
H: USIM is removed
If not use keep
L: USIM is inserted
it open.
have
USIM Card data I/O,
which has been
pulled up with a 10KR
resistor to
USIM_DATA
17
I/O
USIM_VDD in module. Do
not pull
up or pull down in
users’ application
circuit.
All signals of
USIM_RESET
18
DO
USIM Reset
USIM
USIM_CLK
19
DO
USIM Clock
interface should
USIM Card Power
be protected with
output, output
ESD/EMC.
Voltage depends on
USIM mode
USIM_VDD
20
PO
automatically， and
one is
3.0V±10%, another is
1.8V±10%.
Current is less than
50mA.
PCM interface
Pin Name
Pin No.
I/O
Description
PCM_CLK
76
DO
PCM data bit clock.
PCM_SYNC
75
DO
PCM_IN
74
DI
PCM data input.
PCM_OUT
73
DO
PCM data output.
I/O
Description
PCM data frame sync
signal.
Content
If not use keep it
open.
FULL UART/DEBUG PORT
Pin Name
Pin No.
Copyright © Shanghai Mobiletek Communication Ltd
Content
L506 Hardware Design
RTS
66
DI
DET Request to send.
CTS
67
DO
Clear to Send.
RX
68
DI
Receive Data.
If not use keep it
open.
If not use keep it
open.
If not use keep it
open.
Multiplexed
as
MDM_DBG_UART_TX.
RI
69#
DO
Ring Indicator.
If not use keep it
open.
Recommend
reserved the test
point for debug
DCD
70
DO
Carrier detects.
TXD
71
DO
Transmit Data.
If not use keep it
open
If not use keep it
open.
Multiplexed
as
MDM_DBG_UART_RX.
DTR
72#
DI
DTE get ready.
If not use keep it
open.
Recommend
reserved the test
point for debug
I2C interface
Pin Name
Pin No.
I/O
Description
Content
I2C_SCL
55
DO
I2C clock output.
L506
I2C_SDA
56
I/O
I2C data input/output.
Pin No.
I/O
Description
internal
have pulled up to
1.8V
GPIO
Pin Name
Content
Default: GPIO
Optional: Input pin as
GPIO_2/WAKEUP_IN
50
I/O
wake/interrupt
signal to module from
host.
Default: GPIO
GPIO_1/WAKEUP_OU
Optional: Output pin
52
DO
as wake/interrupt
signal to host from
module.
GPIO_3
28
I/O
GPIO
GPIO_0
45
DO
Default: GPIO
Copyright © Shanghai Mobiletek Communication Ltd
If not use keep it
open.
L506 Hardware Design
Optional:
output
control pin.
RF port
Pin Name
Pin No.
I/O
Description
Content
MAIN _ANT
82
AIO
Main Antenna
AUX_ANT
59
AI
diversity antenna
GNSS_ANT
79
AI
GPS antenna
Pin No.
I/O
Description
Others
Pin Name
Content
Analog conversion
ADC1
ADC2
47
46
AI
AI
digital input
interface1
If not use keep it
Analog conversion
open.
digital input
interface2
COEX1
83
I/O
RF
synchronizing
If not use keep it
LTE.
COEX3
86
open.
I/O
Default: RF
synchronizing
Optional: Pull up to
1.8V
COEX2
84#
I/O
(L506A
PIN
15 VDD_1V8)
with
10K resistor force
module in USB
download mode
Recommend placing
BOOT_CFG0
85
DI, PD
Pull up to 1.8V (L506A
test points for
PIN 15 VDD_1V8) with
debug.
10K
resistor
module
in
force
fastboot
mode
Pull up to 1.8V (L506A
PIN 15 VDD_1V8) with
BOOT_CFG1
87
DI, PD
10K
resistor
module
mode
Copyright © Shanghai Mobiletek Communication Ltd
in
force
fastboot
L506 Hardware Design
3.2 Operating condition
Table 3-4 module recommended operating condition
Parameter
Description
Min.
Typ.
Max.
Unit
VBAT
Main power supply for
3.4
3.8
4.2
the module
3.3 Digital I/O characteristics
Table 3-5 1.8V Digital I/O characteristics
Parameter
Description
Min.
Typ.
Max.
Unit
VIH
High level input voltage
0.7*VDD_PX
VDD_PX
VDD_PX+0.3
VIL
Low level input voltage
-0.3
0.2* VDD_PX
VOH
High level output voltage
VDD_PX-0.45
VDD_PX
VOL
Low level output voltage
0.45
IOH
High-level output current
mA
-2
mA
uA
-1
uA
(no pull down resistor)
IOL
Low-level output current
(no pull up resistor)
IIH
Input
high
leakage
current (no
pull down resistor)
IIL
Input low leakage current
(no pull up resistor)
*Note: 1. These parameters are for digital interface pins, such as SP, SDIO, GPIOs
(NETLIGHT,
FLIGHTMODE, STATUS, USIM_DET, SD1_DET), I2C, UART, PCM, COEXn, BOOT_CFGn.
2. L506A TF-card signal (SD_DATA0~SD_DATA3, SD_CLK, SD_CMD), USIM card signal
(USIM_CLK, USIM_DATA, USIM_RST) support dual-voltage (1.8V and 3.0V) mode, and the DC
character show in corresponding function block.
3.4 Power Interface
3.4.1 Power supply pin description
Copyright © Shanghai Mobiletek Communication Ltd
L506 Hardware Design
Table 3-6 DC Power Characteristics
Pin No.
38,39,62,63
Net Name
VBAT
DC Characteristic（V）
Description
Power supply for
the module
Min.
Typ.
Max.
3.4
3.8
4.2
2.85
1.8/3.0
1.8
1,2,5,10,14,37,40,
41,43,57,58,60,61,
GND
GND
64,65,77,78,80,81
44
20
15
VCC_EXT
USIM_VDD
VDD_1V8
88-99*
GND
Power supply for
external SD card
Power supply for
VDD SIM
LDO 1.8V output
Thermal
and
welding
fixed
plate
Note: Pin88~Pin99 (total12pin) is design for the thermal welding fixed plate.
3.4.2 Power supply requirements
There are four VBAT PIN power for the module, VBAT directly power supply for the module
baseband and PA, and operating rating is 3.4V~4.2V; In the weak network environment, the antenna
will be maximum power emission. The peak current of the module under the 3G mode may reach
the peak current of 1.8A. power supply to reach 2A, the average current to reach 0.9A above.
maximum peak current can reach 2A, So the max power supply current must more than 2 A. Figure
3-2 sign for instantaneous pulse diagram.
Figure 3-2 instantaneous pulse
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L506 Hardware Design
Table 3-7 VBAT power supply interface characteristics
Symbol
Description
VBAT
Power
supply
voltage
IVBAT(peak)
Power supply p
current
IVBAT(average)
Power
Min
Typ
Max
Unit
3.4
3.8
4.2
2*
1.5
20
uA
mA
supply
average
current
IVBAT(power-off)
Power
supply
current
in power off
mode
IVBAT(power-save)
Power
supply
current
in power save
mode(sleep
mode)
3.4.3 Power Supply Design Guide
Make sure that the input voltage at the VBAT pin will never drop below 3.4V even during a
transmit burst when the current consumption rises up to more than 2A. If the power voltage drops
below 3.4V, the RF performance of module may be affected. Using large tantalum capacitors (above
300uF) will be the best way to reduce the voltage drops. If the power current cannot support up to 2A,
users must introduce larger capacitor (typical 1000uF) to storage electric power. For the consideration
of RF performance and system stability, some multi-layer ceramic chip (MLCC) capacitors (0.1/1uF)
need to be used for EMC because of their low ESR in high frequencies. Note that capacitors should be
put beside VBAT pins as close as possible. Also User should keep VBAT net wider than 2 mm to
minimize PCB trace impedance on circuit board. The following figure is the recommended circuit.
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L506 Hardware Design
Figure 3-3 VBAT input application circuit
Note: The Cd, Ce, Cb, Cc and Cf are recommended being mounted for L506, but the Ca, Cb, Ce,
Cc and Cf for tune.
In addition, in order to get a stable power source, it is suggested to use a Zener diode of which
reverse Zener voltage is 5.1V and dissipation power is more than 500mW.
Table 3-8: Recommended Zener diode models
NO.
Manufacturer
Part Number
Power
Package
On semi
MMSZ5231BT1G
500mW
SOD123
Prisemi
PZ3D4V2H
500mW
SOD123
Vishay
MMSZ4689-V
500mW
SOD123
Crownpo
CDZ55C5V1SM
500mW
0805
3.4.4 Recommended Power supply circuit
If the voltage difference is not big,We recommend DCDC or LDO is used for the power supply of the
module, make sure that the peak current of power components can rise up to more than 2A. The
following figure is the reference design of +5V input linear regulator power supply. The designed
output for the power supply is 3.8V.
Figure 3-4 Reference circuit of the LDO power supply
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L506 Hardware Design
If there is a big difference between the input voltage and the desired output (VBAT) or better
efficiency is more important, a switching converter power supply will be preferable. The following
figure is the reference circuit.
Figure 3-5 Reference circuit of the DCDC power supply
Note: DCDC may deprave RF performance because of ripple current intrinsically.
3.4.5 Power Supply Layout guide
The layout of the power supply section and the related components is of vital importance in the
power module design. If processes this part layout is not good, will lead to various effects, such as bad
EMC, effective the emission spectrum and receiving sensitivity, etc. So the power supply part design
is very important, when you design this part you should notes below contents: 1. DC DC switch power
should place away from the antenna and other sensitivity circuit; 2. Consider the voltage drop and the
module current requirement, the layout line should better above 100mil. If conditions allow should add
a power shape plane.
3.5 USIM interface
3.5.1 Pin definition
The L506 integrated a ISO 7816-2 standard USIM port, and the module can automatic identify the
voltage demo according the USIM to allow the mobile equipment to attach to the network. Both 1.8V
and 3.0V SIM Cards are supported.
Table 3-9 USIM Electronic characteristic in 1.8V mode (USIM_VDD =1.8V)
Symbol
Parameter
Min.
Typ.
Max.
Unit
USIM_VDD
LDO power output
1.75
1.8
1.95
VIH
High-level input voltage
VIL
Low-level input voltage
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0.65·USI
USIM_V
M_VDD
-0.3
DD +0.3
0.35·USI
M_VDD
L506 Hardware Design
VOH
High-level output voltage
VOL
Low-level output voltage
USIM_V
--
DD -0.45
DD
USIM_V
0.45
Table 3-10: USIM Electronic characteristic 3.0V mode (USIM_VDD =3.0V)
Symbol
Parameter
Min.
Typ.
Max.
Unit
USIM_VDD
LDO power output
2.75
3.0
3.05
VIH
High-level input voltage
VIL
Low-level input voltage
VOH
High-level output voltage
VOL
Low-level output voltage
0.65*USI
M_VDD
0.25·USI
M_VDD
USIM_V
USIM_V
DD
AL
DD -0.45
DD +0.3
-0.3
USIM_V
0.45
3.5.2 Design Guide
USIM electronic characteristics as the table 3-8,3-9 show.
LY
In order to meet the 3 GPP TS 51.010 1 protocol and EMC certification requirements. Suggest
USIM slot near the location of the module USIM card interface, to avoid running for too long, lead to
serious deformation of waveform and effect signal integrity, USIM_CLK and USIM_DATA signal
lines suggest ground protect. Between the USIM VCC & GND add a 1uF and a 33 pF capacitor in
parallel, Between the USIM_CLK& GND, USIM_RST& GND, USIM DATA& GND add a 33 pF
capacitor in parallel, for filter the RF signal interference.
3.5.3 USIM interface reference circuit
Copyright © Shanghai Mobiletek Communication Ltd
L506 Hardware Design
Figure 3-6 USIM Reference circuit
Note:USIM_DATA have added the pull-up resistance in the module design.
3.6 PCM interface
3.6.1 PCM interface definition
L506 provides hardware PCM interface for external codec. L506 PCM interface can be used in
short sync master mode only, and only supports 16 bits linear format：
Table 3-11 PCM interface definition
Pin No.
Signal name
I/O Type
PCM
DC Characteristics（V）
Min.
Typ.
Max.
-0.3
1.8
1.9
75
PCM_SYNC
synchronizing
signal
74
PCM_DIN
PCM data input
-0.3
1.8
1.9
73
PCM_DOUT
PCM Data output
-0.3
1.8
1.9
76
PCM_CLK
PCM Data clock
-0.3
1.8
1.9
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L506 Hardware Design
Figure 3-7 PCM_SYNC timing
Figure 3-8 Codec to L506 module timing
Figure 3-9 L506 to codec module timing
Table 3-12 PCM interface Timing
DC characters
Parameter
T(sync)
T(synch)
T(syncl)
T(clk)
T(clkh)
Descriptions
Min.
Typ.
Max.
Unit
PCM_SYNC cycle
125
us
PCM_SYNC high level hold
488
ns
124.5
us
PCM_CLK cycle
488
ns
PCM_CLK high level hold
244
ns
time
PCM_SYNC
low level hold
time
time
Copyright © Shanghai Mobiletek Communication Ltd
L506A Hardware Design
T(clkl)
PCM_CLK low level hold time
244
ns
T(susync)
PCM_SYNC establish time
122
ns
T(hsync)
PCM_SYNC hold time
366
ns
T(sudin)
PCM_IN establish time
60
ns
T(hdin)
PCM_IN hold time
60
ns
From PCM_CLK rising edge to
60
ns
60
ns
T(pdout)
PCM_OUT valid time
From PCM_CLK falling edge
T(zdout)
to
PCM_OUT
high
impendence delay time
3.6.2 PCM interface application
L506A only support the host mode, PCM_SYNC,PCM_CLK is the output pin，PCM_SYN as the
synchronizing output 8kHz sync signal. PCM Data support 8bit or 16bit data.
PCM_DIN
PCM_DOUT
PCM_SYNC
PCM_CLK
GND
L506A
0R
0R
0R
0R
PCM_OUT
PCM_IN
PCM_SYNC
PCM_CLK
GND
CODEC
Figure 3-10 PCM application circuit（L506 in host mode）
Note:1. L506 PCM port DC character is base on 1.8 voltage, please pay attention the voltage
matching.
2. If your design need this function, you should add the crystal for PCM clock. About the
crystal type please contact our market.
3. L506 default design base on NAU8814 as the codec chip, the detail design please refer to
《L506 reference design》 .
3.7 USB2.0 interface
3.7.1 USB interface pin definition
L506 integrated a USB 2.0 port and low speed mode full speed mode and high speed mode
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L506 Hardware Design
transmission speed between the AP and the host. Below table is the module USB pin definition
Table 3-13 USB interface pin definition
Pin No.
Signal name
I/O type
12
USB_DM
13
USB_DP
DC characteristic（V）
Min.
Typ.
Max.
USB2.0 date D-
USB2.0 data D+
3.7.2 USB Interface application
USB bus is mainly used for data transmission, software upgrading, module testing. Work in the
high-speed mode of the USB line, if you need ESD design, ESD protection device must meet the
junction capacitance value <5pf, otherwise the larger junction capacitance will cause waveform
distortion, the impact of bus communication. Differential impedance of differential data line in 90ohm
+ 10%. In your application must add a 47Kohm resistor between USB_VBUS to ground.
VBUS
0R
VBUS
USB_DP
USB_DP
USB_DM
0R
USB_DM
GND
GND
USB_ID
L506A
47K
HOST(P
C)
Figure 3-11 USB application
3.8 UART Interface
3.8.1 Pin description
L506 module provides a flexible 7-wire UART (universal asynchronous serial transmission)
interface. UART as a full asynchronous communication interface, Support the standard modem
handshake signal control, Comply with the RS - 232 interface protocols. And also support four wire
serial bus interface or the 2-wire serial bus interface mode, and the module can be through the UART
Copyright © Shanghai Mobiletek Communication Ltd
L506 Hardware Design
interface for serial communication with the outside (DET) and the AT command input, etc. L506
module is a DCE (Data Communication Equipment) and client PC is a DTE (Data Terminal
Equipment).AT commands are entered and serial communication is performed through UART
interface. The pin signal is defined as shown in below table.
Table 3-14 UART pin definition
Pin No.
Pin
I/O type
Descriptions
71
UART_TX
DO
UART data transmission
68
UART_RX
DI
UART data receive
69
UART_RI
DO
Ring Indicator.
66
UART_RTS
DO
UART DET request to send
72
UART_DTR
DI
DTE get ready.
67
UART_CTS
DI
UART Clear to Send.
70
UART_DCD
DO
UART Carrier detects.
Note：UART_RI, UART_DTR can be used as two line UART interface for system debugging, See
table 3-3 Pin functional description.
3.8.2 UART interface application
UART_RI, UART_DTR default status is the system log port, so we recommend that users
keep reserved the interface and test points in design. The L506 UART is 1.8V interface. A level
shifter should be used if user’s application is equipped with a 3.3V UART interface. The level
shifter TXB0108RGYR provided by Texas Instruments is recommended. The reference design of
the TXB0108RGYR is in the following figures. About the application as below:
Copyright © Shanghai Mobiletek Communication Ltd
L506 Hardware Design
L506 (DCE)
Serial Port
Client(DET)
Serial Port
TXD1
TXD
RXD1
RXD
RTS1
RTS
CTS1
CTS
DTR1
DTR
DCD1
DCD
RING1
RING
GND
GND
Figure 3-12 UART 4 Line connection mode
L506A(DCE)
Serial Port
Client (DTE)
Serial Port
TXD1
TXD
RXD1
RXD
RTS1
RTS
CTS1
CTS
DTR1
DTR
DCD1
DCD
RING1
RING
GND
GND
Figure 3-13 UART 2 Line connection mode
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L506 Hardware Design
L506 (DCE)
Serial Port
Client (DTE)
Serial Port
TXD1
TXD
RXD1
RXD
RTS1
RTS
CTS1
CTS
DTR1
DTR
DCD1
DCD
RING1
RING
GND
GND
Figure 3-14
UART Full mode
Figures 3-16 Voltage transfer Reference Circuit
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L506 Hardware Design
3.9 Power on/off and reset interface
3.9.1 Pin definition
L506 can be powered on by pulling PWRKEY pin down to ground. This pin is already internal
pulled up to 1.8V in module, so external pull-up resistor is not necessary. Placing a100nF capacitor
and an ESD protection diode close to the PWRKEY pin is strongly recommended. Please refer to the
following figure for recommended reference circuit L506 also have a RESET pin to reset module.
This function is used as an emergency reset only when AT command “AT+CPOF” and the PWRKEY
pin has no effect. User can pull RESET pin to ground, then module will reset. This pin is already
pulled up with a 40KΩ resistor to 1.8V in module, so external pull-up resistor is not necessary. Placing
a100nF capacitor and an ESD protection diode close to the RESET pin is strongly recommended.
Please refer to the following figure for recommended reference circuit, you can pull-down this pin to
ground and hold about 200 MS and then release will force the module
enter reset state
Table 3-15 power on/off and reset key define
AL
Pin No.
Net name
I/O Typ.
descriptions
PWRKEY
DI
L506A power on/off pin (internal pull-up to
1.8V)
RESET
DI
L506A RESET pin (internal pull-up to 1.8V)
3.9.2 Power on sequence
Table 3-16 power on timing chart.
Ton
Power on low level pulse
100
500
--
ms
Ton(status)
Power on time (According to the
15
--
25
10
--
20
1.17
1.8
2.1
-0.3
0.3
STATUS pin judgment)
Ton(uart)
Power on time (according the UART
pin judgement)
VIH
Input high level voltage of
PWRKEY pin
VIL
Input low level voltage of PWRKEY
pin
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L506A Hardware Design
Figures 3-17 Power on Timing sequence
Note: the STATUS pin can be used to identify whether has been power on, when the module has
access to electricity and initialization is completed, the STATUS output high level, or has
maintained low level.
3.9.3 Power off sequence
The following methods can be used to power down. These procedures will make module
disconnect from the network and allow the software to enter a safe state, and then save data before
completely powering the module off.
● Method 1: Power off L506A by pulling the PWRKEY pin down
● Method 2: Power off L506A by AT command “AT+CPOF”
● Method 3: over-voltage or under-voltage automatic power down.
● Method 4: over-temperature or under-temperature automatic power down.
Note: 1. About the AT command “AT+CPOF” detail please refer document [1].
2. Over-voltage or under-voltage may cause automatic power down.
3. Over-temperature or under-temperature may cause automatic power down.
Table 3-17 Power off timing chart.
Toff
The time of active low level
2.5
--
--
--
--
--
--
--
--
1.17
1.8
2.1
-0.3
0.3
pulse on PWRKEY pin to power off
module
Toff(status
The time from power-off issue to
STATUS pin output low level
(indicating power off)
Toff(uart)
The time from power-off issue to
UART port off
Toff-on
The buffer time from power-off
issue to power-on issue
VIH
Input high level voltage of
PWRKEY pin
VIL
Input low level voltage of PWRKEY
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L506 Hardware Design
pin
User can power off the L506 by pulling PWRKEY down to ground for a specific time. The
power off scenario is illustrated in the following figure.
Figures 3-18 Power off Timing sequence
Note: the STATUS pin can be used to identify whether has been power on, when the module has
access to electricity and initialization is completed, the STATUS output high level, or has
maintained low level.
3.9.4 Reset sequence
L506 can lower module RESET pin to restart the module.
Table 3-18 Reset pin electrical properties
Symbol
Net name
Min.
Typ.
Max.
Unit
Treset
Reset pin low level hold time
50
100
500
ms
VIH
Reset pin input high level
1.17
1.8
2.1
VIL
Reset pin input low level
-0.3
0.3
Note: it is recommended that only in an emergency, such as module without response, use the
RESET pin. In addition, under the module power off status the RESET pin is invalid.
3.9.5 Power on/off and reset interface application
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L506 Hardware Design
500mS
RESET
Pulse
4.7K
47K
500mS
PWRKEY
Pulse
4.7K
47K
L506A
Figure 3-19: Reference power on/off reset circuit
Another way to control the PWRKEY pin is directly using a push button switch. Need to set a button near
the TVS to ESD protection. The image below for reference circuit:
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L506 Hardware Design
Figure 3-20: power on/off and reset recommended circuit (physical buttons)
3.10 Interactive interface
3.10.1 Pin definition
Table 3-19 list the interface is mainly with the application processor interactive interface,
including query, wake up four types, status indication, flight mode interface.
Table 3-19 Interactive interface
Pin No.
Signal
I/O type
Descriptions
50
GPIO_2/WAKEUP_IN
DI
Default: GPIO
Optional: Input pin as wake up interrupt
signal to module from host.
52
GPIO_1/WAKEUP_OU
Default: GPIO
Optional: Output pin as the module wake up
the AP
49
STATUS
DO
AP inquire the module status
54
FLGHTMODE
DI
Pull up to 1.8V made the system enter in
flight mode, at this mode will tune off all
the wireless function
45
GPIO_0
DO
General GPIO module output (used for
keyboard backlighting, etc.)
28
GPIO_3
I/O
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GPIO
L506 Hardware Design
3.10.2 interactive interface application
L506 provides three shook hands with application processor communication signals.
Application processor can query whether the module boot normal work through STATUS. Through
the WAKEUP_OUT query module is in sleep mode, and sleep in the module, through
WAKEUP_IN wake module. Similarly, when application processor in the sleep state, the L506
modules can through WAKEUP_OUT wake application processor.
STATUS：Module sleep instructions, high level indicator to sleep, low level instructions for the
awakened state;
WAKEUP_IN： The host can lower the signal awakens the module，If, low level has maintained,
module can't sleep.
WAKEUP_OUT: when L506A need to communicate with the AP, module can be set this pin for low
level to awaken application processor.
FLGHTMODE：Through the external output high level module into flight mode;
L506A
Figure 3-21: Flight mode recommended circuit (physical buttons)
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L506 Hardware Design
3.11 Net Light interface
3.11.1 Pin define
Table 3-20 LED pin definitions
Pin No.
Net name
I/O type
description
51
NETLIGHT
DO
Module net state identify control LED port
3.11.2 Net light application
The L506 module has 1 pins for controlling the LED display, which can be used as an indicator
of network connection status. Different network states are represented by the mode of the flashing
light. This pin is an GPIO，with An external NPN Transistor，External connect VBAT can directly
drive LED. Drive current capacity varies according to external NPN model，recommend use
DTC143ZEBTL，Drive current biggest can reach 100 mA, below is the reference circuit.
VLED
LED
R1
L506A
R2
Figure 3-22 Status indicator reference circuit
Note: R1, R2 value according to the voltage VLED and LED working current.
Table 3-21 NETLIGHT status
Net Status
Module working status
Always on
Searching Network/Call Connect
200ms ON, 200ms OFF
Data Transmit
800ms ON, 800ms OFF
Registered network
OFF
Power off / Sleep
Note: NETLIGHT output low level as “ON”, and high level as “OFF”.
Copyright © Shanghai Mobiletek Communication Ltd
L506 Hardware Design
3.12 SD card interface
3.12.1 Pin descriptions
L506 provides a 4-bit SD/MMC interface with clock rate up to 52MHz. The operation voltage
of MMC/SD interface is 2.85V with SD/MMC memory cards up to 128G(FAT4), which is
compatible with SDIO Card Specification (version 3.0), Secure Digital (Physical Layer
Specification, version 3.0) and Multimedia Card Host Specification MMC (version 4.4)
Table 3-22 SD characteristics
Symbol
VDD_EXT**
VIH
VIL
VOH
VOL
Parameter
Typ.
Min.
LDO output
High-level input
0.625*VDD_
voltage
EXT
Low-level input
voltage
-0.3
High-level output
2.75*VDD_E
voltage
XT
Low-level output
voltage
Max.
Unit
2.85
VDD_EXT+0.3
2.85
0.25*VDD_EX
VDD_EXT
0.125*VDD_E
XT
SD card I/O load capacity for linear output displacement, concrete can be calculated according to the
following chart;
Figure 3-23 VOL/VOH IV curve
3.12.2 SD card interface design guideline
L506 VDD_EXT for external SD card interface of power supply, in the card slot position should
add the ESD protection circuit; If you need to support SD hot plug design need to add SD_DET
signals. Due to the default hot plug pin of L506 check for low level to identify the card insert status,
so you need to choose the detect PIN connected to the ground when SD card is inserted into the SD
slot, below is the reference circuit.
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L506 Hardware Design
Figure 3-24 SD card recommended circuit
3.12.3 SD card signal PCB line rules
Due to the SD signal is the high-speed digital interface, so it’s layout rules should be in accordance
with the high speed digital rules.
1.Protect other sensitive signals/circuits from SDC corruption.
2. Protect SDC signals from noisy signals (clocks, SMPS, etc.).
3. 50 Ω nominal, ±10% trace impedance.
4. CLK to DATA/CMD length matching < 1 mm.
5. Total routing length < 50 mm recommended.
6. Spacing to all other signals = 2x line width.6 Bus capacitance < 15 pF.
3.13 System boot configuration and download
3.13.1 Pin definition
L506 can configure BOOT_CONFIG (Boot Configuration) pin to Configuration module power-on
mode and the forced entry USB download mode.
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L506 Hardware Design
Table 3-23 Boot configuration and force USB download
Pin No.
Net name
Function description
85
BOOT_CFG0
Pull up this pin change boot
note
configuration register value
87
BOOT_CFG1
Pull up this pin change boot
configuration register value
84
COEX2(Syste
FOCE_USB_BOOT
Pull up this pin change boot
Multiplex
m on)
(before system
configuration register value
pin
on)
3.13.2 Boot configuration and force USB interface application
1.8V
SW1
COEX2/FORCE_USB_BOOT
10K
SW2
BOOT_CFG0
SW3
BOOT_CFG0
L506A
Figure 3-25 boot configuration and force USB download recommended circuit
Copyright © Shanghai Mobiletek Communication Ltd
3.14 Analog and Digital conversion (ADC) interface
L506 Hardware Design
L506 integrated two analog-to-digital conversion interface, specific parameters are as follows:
Table 3-25 ADC1, ADC2 characters
characters
Min.
Typ.
Max.
Unit
ADC resolution
--
15
--
Bits
Transfer time
--
442
--
ms
Copyright © Shanghai Mobiletek Communication Ltd
50
Input voltage range
0.3
--
VBAT
Input resistance
--
--
MΩ
Note: 1. use "AT + CADC" and "AT + CADC2" can read ADC1 and ADC2 voltage on the pin.
More information please refer to the document [1].
2. The need for special software version to support access to the ADC.
3.15 I2C interface
3.15.1 I2C pin definition
I2C is used to communicate with peripheral equipment and can be operated as either a transmitter or
receiver, depending on the device function. Both SDA and SCL are bidirectional lines connected with
I2C interface. Its operation voltage is 1.8V. High speed mode transmission rate can reach 400 KBPS,
Because L506 have internal pulled up to the I2C interface, so in your design needn’t pull up. Figure
3-15 is the reference design:
Figure 3-28 I2C reference design
Note: 1. L506 I2C only support host mode.
2. Only special software version support inquire the I2C.
3.16 Antenna interface
3.16.1 RF signal PCB layout guide
L506 provides RF antenna interface. Customer’s antenna should be located in the host board and
connected to module’s antenna pad through micro-strip line or other types of RF trace and the trace
impedance must be controlled in 50Ω. we recommends that the total insertion loss between the
antenna pad and antenna should meet the following requirements:
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● WCDMA 1900<0.9dB
● WCDMA 850<0.5 dB
● LTE (F<1GHz) <0.5dB
● LTE (1GHz
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