Motorola Barcode Reader Cpx8000 Users Manual Series CPX8216/8216T CompactPCI System Reference

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CPX8000 Series CPX8216/CPX8216T
CompactPCI® System

Reference Manual
CPX8216A/RM4
August 2002 Edition

© Copyright 2002 Motorola Inc.
All rights reserved.
Printed in the United States of America.
Motorola® and the Motorola symbol are registered trademarks of Motorola, Inc.
PowerPC® and the PowerPC logo are registered trademarks of International Business
Machines Corporation (IBM) and are used by Motorola, Inc. under license from IBM.
CompactPCI® is a registered trademark of the PCI Industrial Computer Manufacturer’s
Group (PICMG).
All other product or service names mentioned in this document are trademarks or registered
trademarks of their respective holders.

Safety Summary
The following general safety precautions must be observed during all phases of operation, service, and repair of
this equipment. Failure to comply with these precautions or with specific warnings elsewhere in this manual
could result in personal injury or damage to the equipment.
The safety precautions listed below represent warnings of certain dangers of which Motorola is aware. You, as
the user of the product, should follow these warnings and all other safety precautions necessary for the safe
operation of the equipment in your operating environment.

Ground the Instrument.
To minimize shock hazard, the equipment chassis and enclosure must be connected to an electrical ground. If the
equipment is supplied with a three-conductor AC power cable, the power cable must be plugged into an approved
three-contact electrical outlet, with the grounding wire (green/yellow) reliably connected to an electrical ground
(safety ground) at the power outlet. The power jack and mating plug of the power cable meet International
Electrotechnical Commission (IEC) safety standards and local electrical regulatory codes.

Do Not Operate in an Explosive Atmosphere.
Do not operate the equipment in any explosive atmosphere such as in the presence of flammable gases or fumes.
Operation of any electrical equipment in such an environment could result in an explosion and cause injury or
damage.

Keep Away From Live Circuits Inside the Equipment.
Operating personnel must not remove equipment covers. Only Factory Authorized Service Personnel or other
qualified service personnel may remove equipment covers for internal subassembly or component replacement
or any internal adjustment. Service personnel should not replace components with power cable connected. Under
certain conditions, dangerous voltages may exist even with the power cable removed. To avoid injuries, such
personnel should always disconnect power and discharge circuits before touching components.

Use Caution When Exposing or Handling a CRT.
Breakage of a Cathode-Ray Tube (CRT) causes a high-velocity scattering of glass fragments (implosion). To
prevent CRT implosion, do not handle the CRT and avoid rough handling or jarring of the equipment. Handling
of a CRT should be done only by qualified service personnel using approved safety mask and gloves.

Do Not Substitute Parts or Modify Equipment.
Do not install substitute parts or perform any unauthorized modification of the equipment. Contact your local
Motorola representative for service and repair to ensure that all safety features are maintained.

Observe Warnings in Manual.
Warnings, such as the example below, precede potentially dangerous procedures throughout this manual.
Instructions contained in the warnings must be followed. You should also employ all other safety precautions
which you deem necessary for the operation of the equipment in your operating environment.

Warn ing

Warning

To prevent serious injury or death from dangerous voltages, use extreme
caution when handling, testing, and adjusting this equipment and its
components.

Flammability
All Motorola PWBs (printed wiring boards) are manufactured with a flammability rating
of 94V-0 by UL-recognized manufacturers.

CE Notice (European Community)
Warnin g

!
Warning

This is a Class A product. In a domestic environment, this product may
cause radio interference, in which case the user may be required to take
adequate measures.

Motorola Computer Group products with the CE marking comply with the EMC Directive
(89/336/EEC). Compliance with this directive implies conformity to the following
European Norms:
EN55022 “Limits and Methods of Measurement of Radio Interference Characteristics
of Information Technology Equipment”; this product tested to Equipment Class A
EN55024 “Information technology equipment—Immunity characteristics—Limits and
methods of measurement”
This product also fulfills EN60950 (product safety) which is essentially the requirement for
the Low Voltage Directive (73/23/EEC).
AC configurations of this system also meet the requirements of the following European
standards:
EN61000-3-2 “Limits of Harmonic Current Emissions (equipment input current ≤ 16
A per phase)”
EN61000-3-3 “Limits of Voltage Fluctuations and Flicker in Low-Voltage Supply
Systems for Equipment with Rated Current ≤ 16 A”
In accordance with European Community directives, a “Declaration of Conformity” has
been made and is available on request. Please contact your sales representative.
This product is not a workstation per the European Ergonomic Standard.
Kein Bildschirmarbeitsplatz nach dem Europäischen Ergonomie Standard.

FCC Class A
This equipment has been tested and found to comply with the limits for a Class A digital
device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide
reasonable protection against harmful interference when the equipment is operated in a
commercial environment. This equipment generates, uses, and can radiate radio frequency
energy and, if not installed and used in accordance with the instruction manual, may cause
harmful interference to radio communications. Operation of this equipment in a residential
area is likely to cause harmful interference in which case the user will be required to correct
the interference at his own expense.
Changes or modifications not expressly approved by Motorola Computer Group could void
the user’s authority to operate the equipment.
Use only shielded cables when connecting peripherals to assure that appropriate radio
frequency emissions compliance is maintained.

EMI Caution
Caution

!
Caution

This equipment generates, uses and can radiate electromagnetic energy. It
may cause or be susceptible to electromagnetic interference (EMI) if not
installed and used with adequate EMI protection.

Notice
While reasonable efforts have been made to assure the accuracy of this document,
Motorola, Inc. assumes no liability resulting from any omissions in this document, or from
the use of the information obtained therein. Motorola reserves the right to revise this
document and to make changes from time to time in the content hereof without obligation
of Motorola to notify any person of such revision or changes.
Electronic versions of this material may be read online, downloaded for personal use, or
referenced in another document as a URL to the Motorola Computer Group Web site. The
text itself may not be published commercially in print or electronic form, edited, translated,
or otherwise altered without the permission of Motorola, Inc.
It is possible that this publication may contain reference to or information about Motorola
products (machines and programs), programming, or services that are not available in your

country. Such references or information must not be construed to mean that Motorola
intends to announce such Motorola products, programming, or services in your country.

Limited and Restricted Rights Legend
If the documentation contained herein is supplied, directly or indirectly, to the U.S.
Government, the following notice shall apply unless otherwise agreed to in writing by
Motorola, Inc.
Use, duplication, or disclosure by the Government is subject to restrictions as set forth in
subparagraph (b)(3) of the Rights in Technical Data clause at DFARS 252.227-7013 (Nov.
1995) and of the Rights in Noncommercial Computer Software and Documentation clause
at DFARS 252.227-7014 (Jun. 1995).
Motorola, Inc.
Computer Group
2900 South Diablo Way
Tempe, Arizona 85282

Contents
About this Manual
Summary of Changes ................................................................................................xix
Systems Supported ....................................................................................................xxi
Overview ..................................................................................................................xxii
Comments and Suggestions .....................................................................................xxii
Conventions Used in This Manual ......................................................................... xxiii
CHAPTER 1

System Architecture

PICMG Compliance ................................................................................................. 1-1
System Domains ....................................................................................................... 1-1
System Layout .......................................................................................................... 1-2
CPX8216 ........................................................................................................... 1-2
CPX8216T (H.110) ........................................................................................... 1-4
Bus Access and Control ........................................................................................... 1-4
The Hot Swap Controller/Bridge (HSC) Module .................................................... 1-5
Hot Swap Controller ................................................................................................ 1-6
System Processor Configurations ............................................................................ 1-7
The Simplex Configuration ............................................................................... 1-7
The Active/Passive Configuration .................................................................... 1-8
The Active/Active or Load-Sharing Configuration .......................................... 1-9
I/O Configurations ................................................................................................. 1-10
Peripherals .............................................................................................................. 1-10
Power/Fan Modules ........................................................................................ 1-10
Drive Modules .................................................................................................1-11
CPU Complex Architecture ................................................................................... 1-12
The CPU Module ............................................................................................ 1-12
Switching Service to the Passive CPU ............................................................ 1-13
Chassis ID for CPX8216T ..................................................................................... 1-13
Alarms and LEDs ................................................................................................... 1-13
H.110 Telephony Bus ............................................................................................. 1-14
Board Insertion and Extraction Features ................................................................ 1-14
Staged Pins ...................................................................................................... 1-15
BD_SEL# ........................................................................................................ 1-15
ENUM# ........................................................................................................... 1-15

vii

Hot Swap Control Status Register (CSR) ........................................................ 1-16
The Hot Swap Process ............................................................................................ 1-16
Physical Connection Process ........................................................................... 1-17
Hardware Connection Process ......................................................................... 1-17
Software Connection Process .......................................................................... 1-18
Software Disconnection Process ..................................................................... 1-18
Typical Insertion and Extraction Processes ..................................................... 1-19
Device Drivers ........................................................................................................ 1-19
CHAPTER 2

CPU Modules

Overview .................................................................................................................. 2-1
CPX750HA ............................................................................................................... 2-1
Connectors and Jumper Settings ....................................................................... 2-4
Backplane Connectors (P5, P4, P3, P2, P1) ............................................... 2-4
Front USB Connectors (J17 and J18) ......................................................... 2-4
10BaseT/100BaseTx Connector (J8) ......................................................... 2-4
COM1 Connector (J15) .............................................................................. 2-5
Debug Connector (J19) .............................................................................. 2-6
DRAM Mezzanine Connector (J10) ........................................................ 2-10
EIDE Compact FLASH Connector (J9) ................................................... 2-14
Flash Bank Selection (J6) ......................................................................... 2-15
CPV5350 ................................................................................................................ 2-16
Connectors ....................................................................................................... 2-18
Transition Module ........................................................................................... 2-19
DRAM Memory Configuration ....................................................................... 2-20
Keyboard/Mouse PS2 Connector .................................................................... 2-20
Ethernet Connectors ........................................................................................ 2-21
Universal Serial Bus (USB) Connector ........................................................... 2-21
Serial Port Connectors ..................................................................................... 2-22
Video Connector .............................................................................................. 2-22
CHAPTER 3

CPX8540 Carrier Card

Overview .................................................................................................................. 3-1
CPX8540 Carrier Card ............................................................................................. 3-1
Connector Pinouts ..................................................................................................... 3-4

viii

CHAPTER 4

PMC Modules

Overview .................................................................................................................. 4-1
SCSI-2 Controller PMC ........................................................................................... 4-1
Switch Settings .................................................................................................. 4-3
Connector Pin Assignments .............................................................................. 4-4
CHAPTER 5

Transition/Bridge Modules

Overview .................................................................................................................. 5-1
CPX750HATM Transition Module .......................................................................... 5-1
Serial Ports 3 and 4 Default Configuration ....................................................... 5-2
Serial Port Interface Jumper (J8 and J9) ........................................................... 5-4
Connectors ........................................................................................................ 5-4
Backplane Connectors (J3/J4/J5) ............................................................... 5-4
Asynchronous Serial Port Connectors (J10 and J11) ................................. 5-6
Asynchronous/Synchronous Serial Port Connectors (J6 and J24) ............. 5-7
Parallel I/O Port Connector (J7) ................................................................ 5-9
Keyboard/Mouse Connector (J16) ........................................................... 5-10
USB Connectors (J19 and J18) ................................................................ 5-10
EIDE Connector (J15) ............................................................................. 5-11
Floppy Port Connector (J17) .................................................................... 5-12
+5Vdc Power Connector (J14) ................................................................ 5-12
Speaker Output Connector (J13) .............................................................. 5-13
PMC I/O Connectors ............................................................................... 5-14
Installing the Serial Interface Modules ........................................................... 5-16
Port Configuration Diagrams .......................................................................... 5-18
COM1 and COM2 Asynchronous Serial Ports ........................................ 5-18
Asynchronous/Synchronous Serial Ports ................................................. 5-20
CPV5350TM80 Transition Module ....................................................................... 5-29
Connectors ...................................................................................................... 5-31
Keyboard/Mouse PS2 Connector ............................................................. 5-32
Ethernet Connectors ................................................................................. 5-33
Serial Port Connectors ............................................................................. 5-33
Video Connector ...................................................................................... 5-34
Parallel Port Connector (J20) ................................................................... 5-35
EIDE Headers (J5) ................................................................................... 5-36
Floppy Header (J9) .................................................................................. 5-38
Keyboard/Mouse/Power LED Header (J6) .............................................. 5-40
USB Headers (J12 and J19) ..................................................................... 5-41
SM Bus and LM78 Header (J1) ............................................................... 5-42
Fan Tachometer Headers (J3 and J4) ....................................................... 5-43

Indicator LED/Miscellaneous Header (J2) ............................................... 5-43
CHAPTER 6

Subassembly Reference

Chapter Overview ..................................................................................................... 6-1
Parts of the System ................................................................................................... 6-2
CompactPCI Card Cage Reference .......................................................................... 6-4
Backplane Reference ................................................................................................ 6-5
Power Supply Connectors (PS1, PS2, PS3) ............................................................. 6-6
H.110 Power Connector (CPX8216T Only) ............................................................. 6-7
Alarm Interface Connector (ALARM) ..................................................................... 6-8
Floppy Drive Connectors (FDA, FDB) .................................................................... 6-8
IDE Drive Connectors (IDEA and IDEB) ................................................................ 6-9
Peripheral Power Connectors (PWR1, PWR2, PWR3, PWR4) ............................. 6-10
Peripheral Signal Connectors (SIG1, SIG2, SIG3, SIG4) ...................................... 6-11
CompactPCI Connectors (P1, P2, P3, P4, P5)—CPX8216 Standard Backplane .. 6-11
Primary (Front) Side I/O Connectors (Slots 1-6 and 11-16) ........................... 6-11
Primary (Front) Side CPU Slot Connectors (7 and 9) ..................................... 6-17
Secondary (Rear) Side I/O Connectors ........................................................... 6-26
CPU Transition Module Connectors
(Transition Slots 7 and 9) ....................................................................................... 6-27
Hot Swap Controller/Bridge Connectors (Transition Slots 8 and 10) .................... 6-29
H.110 Bus Connectors—CPX8216T System Only ................................................ 6-37
Primary (Front) Side I/O Connectors .................................................................... 6-38
Primary (Front) Side (Slots 1-6 and 11-16) .................................................... 6-38
Primary (Front) Side CPU Connectors ............................................................ 6-40
Primary (Front) Side HSC Connectors ............................................................ 6-40
Secondary (Rear) Side I/O Connectors .................................................................. 6-50
Secondary (Rear) Side CPU Transition Module Connectors ................................. 6-50
Alarm Display Panel ............................................................................................... 6-51
Alarm Display Panel Interface Connector (J4) ....................................................... 6-53
Remote Alarm Connector (J1) ................................................................................ 6-53
Power Distribution Panel ........................................................................................ 6-54
AC Power Distribution Panel (CPX8216) ....................................................... 6-54
Dual Input DC Power Distribution Panel (CPX8216) .................................... 6-55
Dual Breaker DC Power Distribution Panel (CPX8216) ................................ 6-55
H.110 DC Power Distribution Panel (CPX8216T) ......................................... 6-56
Power Supplies ....................................................................................................... 6-58

APPENDIX A

Specifications

Environmental Characteristics .................................................................................A-1
Power Supply Electrical Specifications ...................................................................A-2
APPENDIX B

Related Documentation

Motorola Computer Group Documents ...................................................................B-1
Related Specifications ..............................................................................................B-2
URLs ........................................................................................................................B-4

List of Figures
Figure 1-1. CPX8216 Domains ............................................................................... 1-2
Figure 1-2. CPX8216 Standard System Layout ...................................................... 1-3
Figure 1-3. CPX8216T H.110 System Layout ........................................................ 1-4
Figure 1-4. CPX8216 I/O Bus Connectivity ........................................................... 1-5
Figure 1-5. The CPX8216T H.110 Bus ................................................................. 1-14
Figure 2-1. CPV5350 Component Side View ....................................................... 2-19
Figure 2-2. Keyboard/Mouse Connector Diagram ................................................ 2-20
Figure 3-1. PMC Modules to CPX8540 Carrier Card ............................................ 3-2
Figure 3-2. Installing a PMC Module ..................................................................... 3-3
Figure 5-1. CPX750HATM Transition Module ...................................................... 5-3
Figure 5-2. Serial Port Interface Jumper (J9) Settings ............................................ 5-4
Figure 5-3. DTE Port Configuration (COM1 and COM2) ................................... 5-19
Figure 5-4. EIA-232-D DCE Port Configuration (Ports 3 and 4) ......................... 5-21
Figure 5-5. EIA-232-D DTE Port Configuration (Ports 3 and 4) ......................... 5-22
Figure 5-6. EIA-530 DCE Port Configuration (Ports 3 and 4) ............................. 5-23
Figure 5-7. EIA-530 DTE Port Configuration (Ports 3 and 4) ............................. 5-24
Figure 5-8. V.35-DCE Port Configuration (Ports 3 and 4) .................................... 5-25
Figure 5-9. V.35-DTE Port Configuration (Ports 3 and 4) .................................... 5-26
Figure 5-10. X.21-DCE Port Configuration (Ports 3 and 4) ................................. 5-27
Figure 5-11. X.21-DTE Port Configuration (Ports 3 and 4) ................................. 5-28
Figure 5-12. Keyboard/Mouse Connector Diagram .............................................. 5-32
Figure 6-1. CPX8216 Front View ........................................................................... 6-2
Figure 6-2. CPX8216 Rear View ............................................................................ 6-3
Figure 6-3. Card Cage Rail Color Scheme—CPX8216 Standard System .............. 6-4
Figure 6-4. Card Cage Rail Color Scheme—CPX8216T H.110 System ................ 6-4
Figure 6-5. CPX8216 and CPX8216T Backplane—Primary Side ......................... 6-5
Figure 6-6. The CPX8216T H.110 Bus ................................................................. 6-37
Figure 6-7. Alarm Display Panel Block Diagram ................................................. 6-51
Figure 6-8. Alarm Display Panel—Front View .................................................... 6-52
Figure 6-9. AC Power Distribution Panel—Front View ....................................... 6-54
Figure 6-10. Dual Input DC Power Distribution Panel—Front View ................... 6-55
Figure 6-11. Dual Breaker DC Power Distribution Panel—Front View ............... 6-56
Figure 6-12. H.110 DC Power Distribution Panel ................................................ 6-57

xiii

List of Tables
Table 2-1. CompactPCI Boards ............................................................................... 2-1
Table 2-2. USB 0 Connector J18 ............................................................................. 2-4
Table 2-3. USB 1 Connector J17 ............................................................................. 2-4
Table 2-4. 10BaseT/100BaseTx Connector J8 ........................................................ 2-5
Table 2-5. COM1 Connector J15 ............................................................................ 2-5
Table 2-6. Debug Connector (J19) .......................................................................... 2-6
Table 2-7. DRAM Mezzanine Connector (J10) .................................................... 2-10
Table 2-8. EIDE Compact FLASH Connector J9 ................................................. 2-14
Table 2-9. CPV5350 Front Panel Connectors, Board Headers and Components . 2-18
Table 2-10. Keyboard/Mouse P/S2 Connector Pin Assignments (J50) ................ 2-20
Table 2-11. Ethernet Connector Pin Assignments (J13 and J6) ............................ 2-21
Table 2-12. USB Connector Pin Assignments (J14) ............................................. 2-21
Table 2-13. Serial Port Connector Pin Assignments (J24 and J25) ...................... 2-22
Table 2-14. Video Connector Pin Assignments (J23) ........................................... 2-22
Table 3-1. CPCI J3 I/O Connector Pinout ............................................................... 3-4
Table 3-2. CPCI J5 I/O Connector Pinout ............................................................... 3-4
Table 3-3. PCI 32-bit Interface Connector P11/J11, P21/J21 ................................. 3-5
Table 3-4. PCI 32-bit Interface Connector P12/J12, P22/J22 ................................. 3-7
Table 3-5. PCI 64 bit PCI extension on PMC Connector J13, J23 ......................... 3-8
Table 3-6. User-Defined I/O PCI Interface Connector P14/J14, P24/J24 ............... 3-9
Table 4-1. PMC Switch Settings ............................................................................. 4-3
Table 4-2. PMC Pin Assignments ........................................................................... 4-4
Table 5-1. System Components ............................................................................... 5-1
Table 5-2. J3 User I/O Connector ............................................................................ 5-5
Table 5-3. J5 User I/O Connector ............................................................................ 5-6
Table 5-4. COM1 (J11) and COM2 (J10) ............................................................... 5-7
Table 5-5. Serial Port 3 (J6) .................................................................................... 5-7
Table 5-6. Serial Port 4 (J24) .................................................................................. 5-8
Table 5-7. Parallel I/O Connector (J7) .................................................................... 5-9
Table 5-8. Keyboard/Mouse Connector (J16) ....................................................... 5-10
Table 5-9. EIDE Connector (J15) ...........................................................................5-11
Table 5-10. Floppy Connector (J17) ..................................................................... 5-12
Table 5-11. +5Vdc Power Connector (J14) ........................................................... 5-13
Table 5-12. Speaker Output Connector (J13) ........................................................ 5-13

Table 5-13. PMC I/O Connector (J2) .................................................................... 5-14
Table 5-14. PMC I/O Connector (J21) .................................................................. 5-15
Table 5-15. Keyboard/Mouse P/S2 Connector Pin Assignments (J14) ................. 5-32
Table 5-16. Ethernet Connector Pin Assignments (J13 and J18) .......................... 5-33
Table 5-17. Serial Port Connector Pin Assignments
(J21 and J10) ........................................................................................................... 5-33
Table 5-18. Video Connector Pin Assignments (J16) ............................................ 5-34
Table 5-19. Parallel Connector Pin Assignments (J20) ......................................... 5-35
Table 5-20. EIDE Header (J5) Pin Assignments ................................................... 5-36
Table 5-21. Floppy Header (J9) Pin Assignments ................................................. 5-38
Table 5-22. Keyboard/Mouse/Power LED Header (J6) Pin Assignments ............ 5-40
Table 5-23. USB Headers (J12 and J19) Pin Assignments .................................... 5-41
Table 5-24. SM Bus and LM78 Header (J1)Pin Assignments .............................. 5-42
Table 5-25. Fan Tachometer Header (J3 and J4) Pin Assignments ....................... 5-43
Table 5-26. Indicator LED/Miscellaneous Header (J2) Pin Assignments ............. 5-43
Table 6-1. System Components ............................................................................... 6-1
Table 6-2. PS1, PS2, and PS3 Pin Assignments ...................................................... 6-6
Table 6-3. Fan Module Pin Assignments ................................................................ 6-7
Table 6-4. H.110 Power Connector ......................................................................... 6-7
Table 6-5. ALARM Connector Pin Assignments .................................................... 6-8
Table 6-6. FDA and FDB Pin Assignments ............................................................ 6-8
Table 6-7. IDEA and IDEB Pin Assignments ......................................................... 6-9
Table 6-8. PWR1, PWR2, PWR3, PWR4 Pin Assignments ................................. 6-10
Table 6-9. SIG1, SIG2, SIG3, SIG4 Pin Assignments .......................................... 6-11
Table 6-10. P5 Connector, I/O Slots 1-6 and 11-16
(User I/O) ................................................................................................................ 6-12
Table 6-11. P4 Connector, I/O Slots 1-6 and 11-16 (User I/O) ............................. 6-12
Table 6-12. P3 Connector, I/O Slots 1-6 and 11-16 (User I/O) ............................. 6-12
Table 6-13. P2 Connector, I/O Slots 1-6 and 11-16 (CPCI Bus) ........................... 6-13
Table 6-14. P1 Connector, I/O Slots 1-6 and 11-16 (CPCI Bus) ........................... 6-14
Table 6-15. P5 Connector, CPU Slots 7 and 9 ....................................................... 6-17
Table 6-16. P4 Connector, CPU Slots 7 and 9 ....................................................... 6-18
Table 6-17. P3 Connector, CPU Slots 7 and 9 ....................................................... 6-20
Table 6-18. P2 Connector, CPU Slot 7 (Domain A) .............................................. 6-20
Table 6-19. P2 Connector, CPU Slot 9 (Domain B) .............................................. 6-22
Table 6-20. P1 Connector, CPU Slots 7 and 9 ....................................................... 6-23
Table 6-21. P5 Connector, I/O Slots 1-6 and 11-16 (User I/O) ............................. 6-26
Table 6-22. P4 Connector, I/O Slots 1-6 and 11-16 (User I/O) ............................. 6-26
Table 6-23. P3 Connector, I/O Slots 1-6 and 11-16 (User I/O) ............................. 6-26

xvi

Table 6-24. P5 Connector, CPU Transition Module Slots .................................... 6-27
Table 6-25. P3 Connector, CPU Transition Slots 7 and 9 ..................................... 6-28
Table 6-26. P5 Connector, HSC/Bridge (Slots 8 and 10) ...................................... 6-29
Table 6-27. P4 Connector, HSC/Bridge (Slots 8 and 10) ...................................... 6-29
Table 6-28. P3 Connector, HSC Slots 8 and 10 .................................................... 6-31
Table 6-29. P2 Connector, HSC Slot 10 ................................................................ 6-32
Table 6-30. P2 Connector, HSC Slot 8 .................................................................. 6-34
Table 6-31. P1 Connector, HSC Slots 8 and 10 .................................................... 6-35
Table 6-32. P4 Connector, I/O Slots 1-6, 11-16 .................................................... 6-38
Table 6-33. P5 Connector, HSC/Bridge (Slots 8 and 10) ...................................... 6-40
Table 6-34. P4 Connector, HSC Slots 8 and 10 .................................................... 6-42
Table 6-35. P3 Connector, HSC Slots 8 and 10 .................................................... 6-44
Table 6-36. P2 Connector, HSC Slot 10 ................................................................ 6-45
Table 6-37. P2 Connector, HSC Slot 8 .................................................................. 6-47
Table 6-38. P1 Connector, HSC Slots 8 and 10 .................................................... 6-48
Table 6-39. P5 Connector, I/O Slots 1-6 and 11-16 (User I/O) ............................. 6-50
Table 6-40. P3 Connector, I/O Slots 1-6 and 11-16 (User I/O) ............................. 6-50
Table 6-41. Alarm LED Color and Description .................................................... 6-52
Table 6-42. Alarm Display Panel Interface Connector (J4) .................................. 6-53
Table 6-43. Remote Alarm Connector (J1) ........................................................... 6-53
Table 6-44. DC Analog Voltages for H.110 Bus ................................................... 6-57
Table A-1. Total Regulation (per Output) ...............................................................A-3
Table B-1. Related Specifications ...........................................................................B-2

xvii

About this Manual
This manual is directed at the person who needs detailed configuration and
specification information for CompactPCI modules and system
subassemblies of the CPX8000 series computer system. Included is an
overview of the system architecture for the CPX8216 and CPX81216T
systems. It also presents the correct strapping and pin-out information for
the modules and subassemblies covered.
This manual does not provide installation, removal, or use procedures.
People requiring this type of information should refer to the CompactPCI
CPX8216 and CPX8216T System Installation and Use manual as listed in
Appendix B, Related Documentation.

Summary of Changes
This manual has been revised and replaced any previous editions. Below
is a history of the changes affecting this manual.
Date

Change

July 2002

Updated PMC Module chapter, see Chapter 4, PMC
Modules.
Load sharing information added, see The Active/Active or
Load-Sharing Configuration on page 1-9
Domain ownership further defined, see Chapter 1, System
Architecture
Dual breaker DC power distribution panel information
added (with Smart cable), see Dual Breaker DC Power
Distribution Panel (CPX8216) on page 6-55.

April 2002

Section describing system domains and domain
ownership information added, see System Domains on
page 1-1.
Section describing hot swap controllers added, see Hot
Swap Controller on page 1-6.

xix

Date

Change
Power distribution information added, see Power
Distribution Panel on page 6-54.

August 2001

Details about assigning chassis IDs on the CPX8216T
system added. See Chassis ID for CPX8216T on page
1-13.
Updated model numbers, see Systems Supported in this
section.

April 2001

Added cautions regarding hot swap software and hot
swappable drives.

July 2000

Updated pin assignment tables for connector P2
(HSC and CPU slots.)

March 2000

DC Input voltage changed to -36Vdc to -72Vdc. Changed
URLs to reflect new Web sites.

November 1999

Added System Architecture chapter.
Added TNV branch circuit safety standards information.
Added the Index.

August 1999

Added information for the CPV5350 Intel CPU
Added information for the H.110 Backplane and Power
Distribution Panel for the CPX8216T system

May 1999

Replaced Figure 2-1 with corrected board illustration

January 1999

Original Document

Systems Supported
This information in this manual applies to the modules and subassemblies
supported by the following systems:
Model Number

Description

CPX8216SK24

CPX8216 Dual SCSI 466 MHz PowerPC Starter Kit,
256MB

CPX8216TSK24

CPX8216T Dual EIDE 700 MHz Pentium Starter Kit,
512MB

CPX8216SK25

CPX8216 Dual EIDE 700 MHz Pentium Starter Kit,
512MB

CPX8216TSK25

CPX8216T Dual EIDE 466 MHz PowerPC Starter
Kit, 256MB

xxi

Overview
This manual is divided into the following topics:
❏ Chapter 1, System Architecture
❏ Chapter 2, CPU Modules
❏ Chapter 3, CPX8540 Carrier Card
❏ Chapter 4, PMC Modules
❏ Chapter 5, Transition/Bridge Modules
❏ Chapter 6, Subassembly Reference
❏ Appendix A, Specifications
❏ Appendix B, Related Documentation

Comments and Suggestions
Motorola welcomes and appreciates your comments on its documentation.
We want to know what you think about our manuals and how we can make
them better. Mail comments to:
Motorola Computer Group
Reader Comments DW164
2900 S. Diablo Way
Tempe, Arizona 85282
You can also submit comments to the following e-mail address:
reader-comments@mcg.mot.com
In all your correspondence, please list your name, position, and company.
Be sure to include the title and part number of the manual and tell how you
used it. Then tell us your feelings about its strengths and weaknesses and
any recommendations for improvements.

xxii

Conventions Used in This Manual
The following typographical conventions are used in this document:
bold
is used for user input that you type just as it appears; it is also used for
commands, options and arguments to commands, and names of
programs, directories and files.
italic
is used for names of variables to which you assign values. Italic is also
used for comments in screen displays and examples, and to introduce
new terms.
courier
is used for system output (for example, screen displays, reports),
examples, and system prompts.
, or
represents the carriage return or Enter key.
Ctrl
represents the Control key. Execute control characters by pressing the
Ctrl key and the letter simultaneously, for example, Ctrl-d.

xxiii

1System Architecture

PICMG Compliance
The CPX8216 system is designed to be fully compliant with the
CompactPCI Hot Swap Specification developed by the PCI Industrial
Computers Manufacturing Group (PICMG). With the proper software
support and testing, it should be possible to integrate all proprietary and
third-party I/O modules which are compatible with this specification.
Further, the system allows the use of I/O modules which are not hot
swappable, but the system must be powered off when such modules are
inserted and extracted.
The CPX8216 also features the ability to hot swap system and nonsystem
processor boards, a feature which is beyond the scope of the PICMG
specification. As part of its commitment to open standards, Motorola will
propose that the processor hot swap capabilities of the CPX8216 be added
to the Hot Swap Specification. At this point, however, there are no thirdparty CPU modules which are compatible with the CPX8216 system.

System Domains
The high availability and high slot count of the CPX8216 systems is made
possible by implementing two host CPU slots and multiple CompactPCI
bus segments in a single chassis. These bus segments, along with other
system resources are grouped into two logical domains, A and B, which
can be controlled by either host-HSC pair regardless of the bus segment the
host sits on. Domain A includes CompactPCI bus segment A (slots 1 to 8),
the power supply/fan tray modules and alarm controls. In the CPX8216,
domain B consists of the CompactPCI bus segment B (slots 9 to 16). For
further information on domain control or ownership, see the section, Hot
Swap Controller on page 1-6.

1-1

System Architecture

Alarm Controls

Bus A

Bus B

Drive
Bays

Power Supply/Fan Trays

Domain A

Domain B

Domain A/B

Figure 1-1. CPX8216 Domains

System Layout
The CPX8216 is a 16-slot, high-availability CompactPCI system with two
separate 6-slot CompactPCI I/O domains and the capability to contain
redundant CPU modules and redundant Hot-Swap Controller (HSC)
modules. It is also possible to configure the system as a simplex, high I/O
system containing a single CPU-HSC pair. Even as a simplex system, the
CPX8216 still provides improved availability through redundant power
supplies and the control/monitoring capabilities of the HSC, as described
in The Hot Swap Controller/Bridge (HSC) Module on page 1-5.

CPX8216
The CPX8216 standard system consists of two 8-slot subsystems, or
domains, each with two slots for the host processor and six slots for
nonhost CompactPCI boards. The HSC board mounts in the rear of the
chassis, behind the secondary CPU slot. Figure 1-2 on page 1-3 provides a
diagram of this configuration.

1-2

Computer Group Literature Center Web Site

CPX8216

Rear Card Locations
Segment A
CPU Transition Module

Segment B
HSC

Segment B
Transition Slots

Segment B
CPU Transition Module

Segment A
HSC

Segment B
Transition Slots

Segment A
I/O Slots

Segment B
I/O Slots

Compact PCI
Segment A

Compact PCI Bus
Segment B

Front Card Locations
2450 9812

Figure 1-2. CPX8216 Standard System Layout
Each of the two independent I/O domains has its own system processor
slot. Each system processor has direct access to its local bus through an
onboard PCI-to-PCI (P2P) bridge. Each domain is also capable of
supporting a Hot Swap Controller (HSC) module that contains its own P2P
bridge. Thus, in a fully redundant configuration, there are two bridges that
have access to each of the I/O buses—one associated with the CPU and one
with the HSC. Only one of the bridges may be active at a time, however.

http://www.motorola.com/computer/literature

1-3

System Architecture

CPX8216T (H.110)
The CPX8216T H.110 system consists of two 8-slot subsystems, or
domains, each with one slot for the host processor, one slot for the frontloaded HSC, and six slots for nonhost CompactPCI boards. Figure 1-3 on
page 1-4 provides a diagram of this configuration.
Rear Card Locations
Segment A
CPU Transition Module

Segment B
CPU Transition Module

Segment B
Transition Slots

Segment A
I/O Slots
Compact PCI
Segment A

Segment B
Transition Slots

CPU
A
Segment B
HSC

CPU
B
Segment A
HSC

Segment B
I/O Slots
Compact PCI Bus
Segment B

Front Card Locations

Figure 1-3. CPX8216T H.110 System Layout

Bus Access and Control
In the fully redundant configuration, the CPU in the left system slot, CPU
A, is associated with the HSC in the right HSC slot, HSC A (note that HSC
A actually sits on the Domain B bus). There is a local connection between
each CPU-HSC pair that allows the CPU in one domain to control the other
domain through its HSC. This architecture is illustrated in the following
figure.

1-4

Computer Group Literature Center Web Site

The Hot Swap Controller/Bridge (HSC) Module

Special Backplane
PCI Interconnects
C H
P S
U C

C H
P S
U C

A B

B A

I/O Domain A

I/O Domain B

I/O

S
L
O
T

Primary CompactPCI
Buses

Figure 1-4. CPX8216 I/O Bus Connectivity
In addition to providing bridges to the remote I/O buses, the HSC provides
the services necessary to hot swap CPU boards and nonhost processor
boards and also controls the system alarm panel, fans, and power supplies.

The Hot Swap Controller/Bridge (HSC) Module
The HSC module connects to the CPU module through a local PCI bus, as
illustrated in Figure 1-2 and Figure 1-3. The HSC module contains a PCIto-PCI bridge and also contains a Hot Swap Controller.
The functionality provided by the HSC is at the heart of the High
Availability CPX8216 System. Its primary functions include:
❏ Providing a bridge between the two eight-slot CompactPCI buses
so that they can be managed by a single CPU module
❏ Maintaining a Control Status Register which contains information
on the status of each system module

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1-5

System Architecture

❏ Controlling power and resets to each system module through
radial connections
❏ Monitoring and controlling CPU boards, nonhost boards, and
peripherals, including power and fan sleds, board and system
LEDs, and alarms

Hot Swap Controller
Each of the nonhost slots in the system can be controlled from either HSC.
When an HSC has control over a domain it has control over the nonhost
boards in that domain. Each host processor/bridge pair is controlled as a
single item by the other processor/bridge pair. The bridge and the host
processor are linked together so that both must be present for power to be
applied. A host processor cannot be operated without its HSC.
With the CPX8216 architecture it is important that the system initializes to
a state that allows the host processors and HSCs to be in control of the
system. The default conditions are:
❏ System processors and bridges are powered up (if present)
❏ System processors and bridges are disconnected from their busses
❏ HSCs are not in control of either domain
❏ Nonhost boards are powered off
❏ Peripheral bays are powered up (if present)
❏ Fans and power supplies are powered on
Note

System components such as fans and power supplies may be
controlled by either HSC but not both. Default control belongs to
Domain A and whichever HSC has control of Domain A has
control of the system functions.
If Domain A is not controlled, nonhost boards are powered-off
and all LED updates to the display panel and power supplies are
suspended. Also, monitoring of alarm inputs from the display
panel and power supplies are inhibited.

1-6

Computer Group Literature Center Web Site

System Processor Configurations

Subsequent to the default, the system software must determine the
configuration of the system and then proceed to change it.

System Processor Configurations
The CPX8216 is a flexible system that allows for multiple configurations
of processor control, I/O redundancy, and peripheral configurations. The
following sections briefly touch on possible configurations.
As noted above, there are three possible processor/control configurations:
❏ A simplex system containing a single CPU-HSC pair controlling
both I/O domains
❏ An active/passive configuration similar to the simplex
configuration, but providing a warm backup for both the CPU and
the HSC
❏ An active/active or load-sharing configuration in which each CPU
runs a single domain while also serving as a backup to the other
CPU.
Note

H.110 traffic and HA Linux do not support a loadsharing configuration.

The following sections give a general description of these configurations.

The Simplex Configuration
Because of the flexible nature of the CPX8216, it is possible to configure
it with different levels of redundancy and availability. For applications
which do not require the benefits of full high availability, it is possible to
configure the CPX8216 as a simplex, 16-slot system. This configuration
provides the benefits of redundant power supplies and the system
monitoring capabilities of the fully redundant configuration.

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1-7

System Architecture

The simplex configuration is illustrated in the following figure.
C
P
U

H
S
C

I/O Domain A

I/O Domain B

I/O

S
L
O
T

The Active/Passive Configuration
In the active/passive configuration, one CPU manages all twelve I/O slots,
much like in the simplex configuration. In addition, the second CPU serves
as a warm standby, ready to run the system in the event of a failure on the
active system.
The active/passive configuration is illustrated in the following figure.
Active CPU

Active HSC

I/O Domain A

1-8

C H
P S
U C

A B

B A

I/O Domain B

Passive
CPU/HSC

I/O

S
L
O
T

Computer Group Literature Center Web Site

The Active/Active or Load-Sharing Configuration

The Active/Active or Load-Sharing Configuration
In the load sharing configuration, each CPU manages six of the twelve I/O
slots, much like a dual 8-slot system with the added benefit of one CPU
being able to control all twelve I/O slots if the other CPU fails. It is
important in a load-sharing configuration to note that the total critical
activity does not exceed the capabilities of a single CPU, because either
one of the CPUs must be ready to take over the load carried by the other.
The active/active configuration is illustrated in the following figure.

C H
P S
U C

A B

B A

I/O Domain A

Note

I/O Domain B

I/O

S
L
O
T

H.110 traffic and HA Linux do not support a load-sharing
configuration.

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1-9

System Architecture

I/O Configurations
The CPX8216 contains two independent 8-slot CompactPCI buses. One
slot in each bus is dedicated to a system processor, and another is needed
for the HSC. This leaves six slots on each bus to support I/O devices or
nonsystem processors.
One possible configuration is to use the CPX8216 as a high I/O
CompactPCI system with redundant CPUs. With this configuration, it is
possible to run twelve independent I/O modules within a CPX8216
system. Applications requiring dense processing power could use all
twelve I/O slots to support nonsystem processors.
Such a system would be protected against a CPU or HSC fault, but it would
be vulnerable to data losses if any of the I/O modules or nonsystem
processor modules were to fail. In systems handling critical data, it is
possible to implement a 2N or an N+1 I/O redundancy strategy that allows
the level of service to be continued in the event that a module fails.
In the case of a 2N-redundant system, each I/O module or nonsystem
processor module is matched with an identical module on the other bus.
The paired modules can be configured in an active/passive arrangement or
a load-sharing arrangement in which each carries half of the load of a
single module. In an N+1 arrangement, multiple modules are backed up by
a single spare. For example, a single passive nonsystem processor module
can be used to back up five others.

Peripherals
Power/Fan Modules
The CPX8216 system requires a minimum of two power/fan sled modules
and a fan-only sled module to provide adequate power and cooling for a
fully loaded, nonredundant system. The system can contain a third power
supply/fan sled as part of an N+1 strategy, meaning that the system can
continue providing service if one of the modules fails. These modules are
hot swappable and available for DC and AC environments.

1-10

Computer Group Literature Center Web Site

Drive Modules

The fans run at either high speed (default) or temperature controlled, which
can be changed using the operating system software via the API.

Drive Modules
The CPX8216 contains four hot-swappable peripheral bays, all of which
support both SCSI and EIDE protocols.
Caution

!
Caution

The hot swapping of hard drives is supported when your system is
configured with the appropriate software support for hot swap and when
the drives are in a hot-swap drive carrier.

SCSI devices can be configured to be fully hot-swappable, and data can be
hot switched between two independent SCSI controllers. EIDE devices are
assigned to a single EIDE controller. They can be warm swapped, meaning
that a failed device can be replaced once the controller has been powered
off.
The rear of the CPX8216 chassis may be configured with either single or
double, fixed, floppy drives. Floppy drives are not hot-swappable.
For more information on installing both hot-swappable and non-hotswappable drives, refer to the Drive Removal and Installation chapter of
the CPX8216 and CPX8216T CompactPCI System Installation and Use
manual.

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1-11

System Architecture

CPU Complex Architecture
The CPU complex in the CPX8216 contains two CPU modules and their
corresponding Hot Swap Controller (HSC) modules. The figure below
illustrates the architecture, including elements on the boards as well as
local connections between the CPU modules and the PCI-to-PCI (P2P)
connections to the local CompactPCI buses.
Local Connections between CPU Modules

RAM

Proc

RAM
HSC

Proc

HSC

Enet

Serial
Link

ISA

Enet
P2P

P2P

IDE

P2P

ISA

Serial
Link

IDE

CompactPCI Bus

The CPU Module
In addition to the processor, RAM, etc., each CPU module contains one:
❏ Up to two Ethernet controllers
❏ Up to two serial communications links
❏ P2P bridge to the local CompactPCI bus
❏ Local PCI Bus connection to the HSC

1-12

Computer Group Literature Center Web Site

Switching Service to the Passive CPU

Switching Service to the Passive CPU
The switchover from one CPU to another is initiated by the passive CPU
when there is an indication that there is something wrong with the active
CPU--such as a failed heartbeat protocol. The passive side notifies the
active side that it is about to begin a switchover process. If the active side
agrees to the switchover, then the two sides coordinate the hand-off and no
bus signals, clocks, or devices should be corrupted. If the active system
fails to cooperate with the takeover attempt, then we must assume that bus
signals, clocks, and devices attached to the bus may be corrupted.
In a more extreme takeover, it is possible for the passive CPU to power-on
reset the active CPU and to take control that way.

Chassis ID for CPX8216T
A unique 5-bit chassis ID can be assigned for each CPX8216T system.
Hex values are on the rotary switches located on the HSC boards. A jumper
can be added to J14 to double the number of unique identifiers. This
feature should be used if more than 15 chassis are deployed in one location.
The HSC boards are shipped with no jumper as the default. For guidelines
on setting the chassis ID on your CPX8216T system, refer to the CPX8000
Series CPX8216 and CPX8216T CompactPCI System Installation and Use
manual.

Alarms and LEDs
In order to provide a uniform appearance, without depending on individual
board manufacturers, the CPX8216 contains a separate alarm display
panel, which runs across the top of the chassis. In addition to In
Service/Out of Service LED indicators for all sixteen slots, the alarm
display panel contains LEDs for system status (System in
Service/Component out of Service/System out of Service) and for the three
standard Telco levels (Critical/Major/Minor). The three Telco alarms are
also signalled through a dry contact relay.

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1-13

System Architecture

H.110 Telephony Bus
The CPX8216T supports an H.110 Computer Telephony Bus. The H.110
bus uses P4/J4 as defined in the PICMG specification for CompactPCI.

H. 110 Bus

P2
CompactPCI Bus

System Slot
HSC Slot
2557 9906

Figure 1-5. The CPX8216T H.110 Bus

Board Insertion and Extraction Features
The PICMG specification details software and hardware features, in order
to support hot swapping of I/O boards. Hardware features include:
❏ Staged pins that control voltages when inserting or extracting
boards
❏ BD_SEL#, HEALTHY#, and ENUM# signals
❏ Hot swap control status register

1-14

Computer Group Literature Center Web Site

Staged Pins

Staged Pins
The PICMG CompactPCI hot swap specification provides for three
separate pin lengths in order to control the insertion and extraction
voltages and to notify the system when boards are inserted or extracted.
The longest pins, which include VCC pins and GND pins, are the first to
mate during the insertion process and the last to break contact during
extraction. These pins are used to supply power to pre-charge the PCI
interface signals to a neutral state before they contact the bus. This precharging serves to minimize the capacitive effects of the board as it makes
or breaks contact with the bus.
The medium-length pins carry PCI and other signal traffic.
The shortest pins are used to assert signals, including BD_SEL#. During
insertion, the BD_SEL# signal enables the board to attach to the local PCI
bus. On extraction, it causes the board to logically and electrically
disconnect from the PCI bus before the bus pins physically break contact
with the bus.

BD_SEL#
BD_SEL# is asserted by one of the pins that mate last on insertion and
break first on extraction. On insertion, the signal tells the board to connect
to the PCI bus. On extraction this pin breaks first, causing the board to
logically and electrically disconnect from the PCI bus before the PCI bus
pins physically break contact with the bus.

ENUM#
An ENUM interrupt is generated when a board is hot inserted into the
CPX8216 chassis, or when an operator trips the board microswitch by
raising its ejector handles. The signal informs the active CPU that the
status of a board has changed. The CPU then identifies the board by polling
the INSert and EXTract bits in all of the boards’ Control Status Registers.

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1-15

System Architecture

Hot Swap Control Status Register (CSR)
The CPX8216 supports hot swap CompactPCI cards with the standard
control status register defined by the PICMG Hot Swap Specification. The
register is visible in PCI configuration space and provides hot swap control
and status bits: INS and EXT. The INS signal is set when ENUM# is
asserted by a board being inserted into the system. The EXT signal is
asserted when ENUM# is asserted by an operator triggering the
microswitch in the board handles. The host also uses these bits to
acknowledge and de-assert ENUM#.

The Hot Swap Process
PICMG divided the complete hot swap process into physical, hardware
and software connection processes. These processes are formally broken
down further into a group of transitional states, which are illustrated in the
following figure.

PH Y SIC AL
H AR D W A R E
C O N N EC T IO N C O N N E C T IO N ST AT E S
S T AT ES

P1
H0

H 1F

SO F T W A R E
C O N N E C T IO N
S T AT ES

S2 Q

S3 Q

When inserting a board, it goes through all states from P0 to S3.
Conversely, a board transitions from S3 to P0 before being extracted.
During normal operation, no states are skipped. Extracting a board in a
software connection state other than S0 is likely to disrupt software enough
to crash the system, but the CompactPCI bus, from a purely electrical point
of view, will not be disrupted enough to cause logic levels to be violated.
Certain states are overlapping. For example, when the board is fully seated
(completed P1), but has not yet started the hardware connection process

1-16

Computer Group Literature Center Web Site

Physical Connection Process

(H0), it said to be in the P1/H0 state. Similarly, one can speak of a board
being in the H2/S0 state.

Physical Connection Process
The physical connection process is the basic process of putting a board into
a live system, or physically removing the board. The process includes two
states:
❏ P0 - The board is physically separate from the system
❏ P1 - The board is fully seated, but not powered, and not active on
the PCI bus. All pins are connected.

Hardware Connection Process
The hardware connection process involves the electrical connection or
disconnection of the board. This process includes three states:
❏ H0 - The board is not active on the PCI bus. This state is equivalent
to P1 above.
❏ H1 - The board has powered up and is sufficiently initialized to
connect to the PCI bus.
❏ H2 - The board is powered, and enabled for access by a PCI bus
transaction (normally by the host) in PCI configuration space only.
The board configuration space is not yet initialized.
When a newly inserted board has completed H2, the board is operable
from a hardware perspective. It has run its power up diagnostics, initialized
itself, loaded EEPROM data, etc. The blue LED is off in the H2 state,
indicating that the board should not be pulled out.

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1-17

System Architecture

Software Connection Process
The software connection process includes the tasks needed to configure
and load software. This process contains four states:
❏ S0 - The Software Connection Process has not been initiated. The
board’s configuration space registers are accessible but not yet
initialized.
❏ S1 - The board is configured by the system. The system has
initialized the board’s PCI configuration space registers with I/O
space, memory space, interrupts and PCI bus numbers. The board
is ready to be accessed by a device driver, but no drivers are loaded
at this time.
❏ S2 - The necessary supporting software (drivers, etc.) have been
loaded. The board is ready for use by the OS and/or the
application, but no operations involving the board are active or
pending.
❏ S3 - The board is active. Software operations are either active or
pending.

Software Disconnection Process
The software disconnection process defines two additional states which
are used when quiescing activity on a board in preparation for extraction:
❏ S3Q - The software is completing current operations, but is not
allowed to start new ones. When current operations are completed,
the board transitions to S2.
❏ S2Q - The board is quiesced. This is the same state as S2, except
that no new operations are allowed to be initiated.
The Software Disconnection Process proceeds as S3, S3Q, S2Q, S1, and
finally S0.

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Computer Group Literature Center Web Site

Typical Insertion and Extraction Processes

Typical Insertion and Extraction Processes
Many of the steps in the insertion and extraction processes are automated
by software. After the operator installs a board, it automatically advances
to P1. The hardware connection process proceeds automatically and
asserts the ENUM# signal to initiate the software connection process. The
host responds to the bussed ENUM# signal by reading the Hot Swap
Control Status Register of each board to find out which one is signaling an
insertion or extraction (INS or EXT bit asserted). Upon detecting an
insertion, the Host responds by adding software drivers to support the
newly inserted board.
Extraction is initiated when the operator opens the board ejector handle,
which activates a mechanical switch to assert ENUM#. The hot plug
system driver senses ENUM# and notifies software that board activity
must be quiesced and that software device drivers should be unloaded. The
application that is using the board is informed that the resource is no longer
available. When the board is ready for extraction, software informs the
operator by illuminating the blue LED. After extraction, all system
resources previously assigned to that board are made available for other
uses.

Device Drivers
In order to take full advantage of the high availability functions of the
CPX8216, and to support hot swap, board device drivers need to be
enhanced. Drivers need to cease all activity when the device is about to be
hot swapped, and they need to support initialization of the device without
support from the device firmware or BIOS.
Further, high availability device drivers need to be able to enter a standby
mode while bus control is being passed from one CPU to another. They
also provide diagnostic interfaces for run time fault detection and for preinitialization testing of newly inserted boards.

http://www.motorola.com/computer/literature

1-19

2CPU Modules

Overview
This chapter provides reference information for the CompactPCI system
controller/host CPU modules supported in the CPX8216 system.
The correct jumper setting and pin-out information is provided for each
module.
Note

The CPX750HA is sometimes identified as an MCP750HA in
some chassis and firmware documentation, for packaging and
ordering purposes, but both numbers apply to the same board.
Your system may not contain all boards listed in this chapter, or
it may contain third-party boards that are not listed in this
chapter. For information about third-party boards, refer to the
board manufacturer’s documentation.

This chapter contains information for the following CompactPCI boards:

Table 2-1. CompactPCI Boards
Part No.

Description

Slots
Occupied

Page

CPX750HA

PowerPC Hot Swappable CPU

2-1

CPV5350

Intel Hot Swappable CPU

2-16

CPX750HA
The CPX750HA is a single-slot, single-board computer equipped with a
PowerPC™ 750 Series microprocessor. The processor implements a
backside cache controller and the board comes with 1MB of cache
memory.

2-1

CPU Modules

The CPX750HA offers many standard features desirable in a CompactPCI
computer system, such as:

❏ PCI Bridge and Interrupt Controller
❏ ECC Memory Controller chipset
❏ 5MB to 9MB of linear FLASH memory
❏ IDE CompactFlash memory
❏ 16MB to 256MB of ECC-protected DRAM
❏ Interface to a CompactPCI bus
❏ Several I/O peripherals
The I/O peripheral interfaces present on the onboard PCI bus include:
❏ One 10/100-BASE-T Ethernet interface
❏ One USB host controller
❏ One SA master/slave interface
❏ One Fast EIDE interface
❏ One PMC Slot
Functions provided from the ISA bus are two asynchronous and two
synchronous/asynchronous serial ports, keyboard, mouse, a floppy disk
controller, printer port, a real time clock, and NVRAM.
The CPX750HA interfaces to a CompactPCI bus using a DEC 21154 PCIto-PCI bridge device. This device provides a 64-bit primary and a 64-bit
secondary interface allowing full 64-bit data access between CompactPCI
bus devices and the host/PCI bridge. This bus is capable of driving seven
CompactPCI slots.
Another key feature of the CPX750HA is the PCI (Peripheral Component
Interconnect) bus. In addition to the onboard local bus peripherals, the PCI
bus supports an industry-standard mezzanine interface, IEEE P1386.1
PMC (PCI Mezzanine Card). PMC modules offer a variety of possibilities
for I/O expansion.

2-2

Computer Group Literature Center Web Site

CPX750HA

The base board supports PMC I/O for the front panel or through backplane
connector J3 to a CPX750HATM transition module.

J6
3

1
2

J11

J12

49
50

1
2

J13

J14

49
50

1
2

PCI MEZZANINE CARD

10/1 00 BASE T

J8
2

F1
J3

XU1

J15

COM 1

J10
F3

XU2

RST
J2

ABT
190

DS3

DS4

189

DS1

DS2

BFL CPU

CPCI CPI
1

J17
4

USB 1

J18
4

USB 0

2
1

J19

190
189

2213 9804

http://www.motorola.com/computer/literature

2-3

CPU Modules

Connectors and Jumper Settings
The next sections provide pinout information and jumper settings for the
CPX750HA board. Additional pinout assignments can be found in
Chapters 3 through 6.
Backplane Connectors (P5, P4, P3, P2, P1)
Refer to the backplane reference section for the backplane connector pin
assignments.
Front USB Connectors (J17 and J18)
Two USB Series A receptacles are located at the front panel of the
CPX750HA board. The pin assignments for these connectors are as
follows:

Table 2-2. USB 0 Connector J18
1

UVCC0

UDATA0N

UDATA0P

GND

Table 2-3. USB 1 Connector J17
1

UVCC1

UDATA1N

UDATA1P

GND

10BaseT/100BaseTx Connector (J8)
The 10BaseT/100BaseTx Connector is an RJ45 connector located on the
front panel of the CPX750HA board. The pin assignments for this
connector are as follows:

2-4

Computer Group Literature Center Web Site

Connectors and Jumper Settings

Table 2-4. 10BaseT/100BaseTx Connector J8
1

TD+

TD-

RD+

AC Terminated

RD-

AC Terminated

COM1 Connector (J15)
A standard DB9 receptacle is located on the front panel of the CPX750HA
to provide the interface to the COM1 serial port. These COM1 signals are
also routed to J11 on the transition module. A terminal may be connected
to J15 or J11 on the transition module but not both at the same time. The
pin assignments for this connector is as follows:

Table 2-5. COM1 Connector J15

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DCD

RXD

TXD

DTR

GND

DSR

RTS

CTS

2-5

CPU Modules

Debug Connector (J19)
A 190-pin connector (J19 on the CPX750HA base board) provides access
to the processor bus (MPU bus) and some bridge/memory controller
signals. It can be used for debugging purposes. The pin assignments are
listed in the following table.

Table 2-6. Debug Connector (J19)

2-6

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

PA8

PA9

PA10

PA11

PA12

PA13

PA14

PA15

PA16

PA17

PA18

PA19

PA20

PA21

PA22

PA23

PA24

PA25

PA26

PA27

PA28

PA29

PA30

PA31

PA_PAR0

PA_PAR1

PA_PAR2

PA_PAR3

APE*

RSRV*

PD0

PD1

PD2

PD3

GND

Computer Group Literature Center Web Site

Connectors and Jumper Settings

Table 2-6. Debug Connector (J19) (continued)
43

PD4

PD5

PD6

PD7

PD8

PD9

PD10

PD11

PD12

PD13

PD14

PD15

PD16

PD17

PD18

PD19

PA20

PD21

PD22

PD23

PD24

PD25

PD26

PD27

PD28

PD29

PD30

PD31

PD32

PD33

PD34

PD35

PD36

PD37

PD38

PD39

PD40

PD41

PD42

PD43

PD44

PD45

PD46

PD47

PD48

PD49

PA50

PD51

PD52

PD53

PD54

PD55

http://www.motorola.com/computer/literature

+5V

2-7

CPU Modules

Table 2-6. Debug Connector (J19) (continued)

2-8

PD56

GND

PD57

PD58

PD59

PD60

PD61

100

101

PD62

PD63

102

103

PDPAR0

PDPAR1

104

105

PDPAR2

PDPAR3

106

107

PDPAR4

PDPAR5

108

109

PDPAR6

PDPAR7

110

111

No Connection

112

113

DPE*

DBDIS*

114

115

TT0

TSIZ0

116

117

TT1

TSIZ1

118

119

TT2

TSIZ2

120

121

TT3

No Connection

122

123

TT4

No Connection

124

125

CI*

No Connection

126

127

WT*

No Connection

128

129

GLOBAL*

No Connection

130

131

SHARED*

DBWO*

132

133

AACK*

TS*

134

135

ARTY*

XATS*

136

137

DRTY*

TBST*

138

139

TA*

No Connection

140

141

TEA*

No Connection

142

143

No Connection

DBG*

144

145

No Connection

DBB*

146

+3.3V

Computer Group Literature Center Web Site

Connectors and Jumper Settings

Table 2-6. Debug Connector (J19) (continued)
147

No Connection

ABB*

148

149

TCLK_OUT

MPUBG-0*

150

151

No Connection

MPUBR0*

152

153

MPUBR1*

IRQ0*

154

155

MPUBG1*

MCHK*

156

157

WDT1TO*

SMI*

158

159

WDT2TO*

CKSTPI*

160

161

L2BR*

CKSTPO*

162

163

L2BG*

HALTED (N/C)

164

165

CLAIM*

TLBISYNC*

166

167

No Connection

TBEN

168

169

No Connection*

No Connection

170

171

No Connection*

No Connection

172

173

No Connection*

No Connection

174

175

No Connection

NAPRUN

176

177

SRST1*

QREQ*

178

179

SRESET*

QACK*

180

181

HRESET*

CPUTDO

182

183

GND

CPUTDI

184

185

CPUCLK1

CPUTCK

186

187

No Connection

CPUTMS

188

189

No Connection

CPUTRST*

190

http://www.motorola.com/computer/literature

GND

2-9

CPU Modules

DRAM Mezzanine Connector (J10)
A 190-pin connector (J10 on the CPX750HA base board) supplies the
interface between the memory bus and the RAM300 DRAM mezzanine.
The pin assignments are listed in the following table.

Table 2-7. DRAM Mezzanine Connector (J10)

2-10

A_RAS∗

A_CAS∗

B_RAS∗

B_CAS∗

C_RAS∗

C_CAS∗

D_RAS∗

D_CAS∗

OEL∗

OEU∗

WEL∗

WEU∗

ROMACS∗

ROMBCS∗

RAMAEN

RAMBEN

RAMCEN

EN5VPWR

RAL0

RAL1

RAL2

RAL3

RAL4

RAL5

RAL6

RAL7

RAL8

RAL9

RAL10

RAL11

RAL12

RAU0

RAU1

RAU2

RAU3

RAU4

RAU5

RAU6

RAU7

RAU8

RAU9

RAU10

RAU11

RAU12

GND

Computer Group Literature Center Web Site

Connectors and Jumper Settings

Table 2-7. DRAM Mezzanine Connector (J10) (continued)
45

RDL0

RDL1

RDL2

RDL3

RDL4

RDL5

RDL6

RDL7

RDL8

RDL9

RDL10

RDL11

RDL12

RDL13

RDL14

RDL15

RDL16

RDL17

RDL18

RDL19

RDL20

RDL21

RDL22

RDL23

RDL24

RDL25

RDL26

RDL27

RDL28

RDL29

RDL30

RDL31

RDL32

RDL33

RDL34

RDL35

RDL36

RDL37

RDL38

RDL39

RDL40

RDL41

RDL42

RDL43

RDL44

RDL45

RDL46

RDL47

RDL48

RDL49

RDL50

RDL51

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+5V

GND

2-11

CPU Modules

Table 2-7. DRAM Mezzanine Connector (J10) (continued)

2-12

RDL52

RDL53

RDL54

RDL55

100

101

RDL56

RDL57

102

103

RDL58

RDL59

104

105

RDL60

RDL61

106

107

RDL62

RDL63

108

109

CDL0

CDL1

110

111

CDL2

CDL3

112

113

CDL4

CDL5

114

115

CDL6

CDL7

116

117

No Connection

118

119

RDU0

RDU1

120

121

RDU2

RDU3

122

123

RDU4

RDU5

124

125

RDU6

RDU7

126

127

RDU8

RDU9

128

129

RDU10

RDU11

130

131

RDU12

RDU13

132

133

RDU14

RDU15

134

135

RDU16

RDU17

136

137

RDU18

RDU19

138

139

RDU20

RDU21

140

141

RDU22

RDU23

142

143

RDU24

RDU25

144

145

RDU26

RDU27

146

147

RDU28

RDU29

148

+3.3V

Computer Group Literature Center Web Site

Connectors and Jumper Settings

Table 2-7. DRAM Mezzanine Connector (J10) (continued)
149

RDU30

RDU31

150

151

RDU32

RDU33

152

153

RDU34

RDU35

154

155

RDU36

RDU37

156

157

RDU38

RDU39

158

159

RDU40

RDU41

160

161

RDU42

RDU43

162

163

RDU44

RDU45

164

165

RDU46

RDU47

166

167

RDU48

RDU49

168

169

RDU50

RDU51

170

171

RDU52

RDU53

172

173

RDU54

RDU55

174

175

RDU56

RDU57

176

177

RDU58

RDU59

178

179

RDU60

RDU61

180

181

RDU62

RDU63

182

183

CDU0

CDU1

184

185

CDU2

CDU3

186

187

CDU4

CDU5

188

189

CDU6

CDU7

190

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GND

2-13

CPU Modules

EIDE Compact FLASH Connector (J9)
A 50-pin Compact FLASH card header connector provides the EIDE
interface to the Compact FLASH Memory Card. The pin assignments for
this connector are as follows:

Table 2-8. EIDE Compact FLASH Connector J9

2-14

GND

DATA3

DATA4

DATA5

DATA6

DATA7

DCS1A_L

GND

+5V

GND

DA2

DA1

DA0

DATA0

DATA1

DATA2

NO CONNECT

CD2_L

CD1_L

DATA11

DATA12

DATA13

DATA14

DATA15

DCS3A_L

NO CONNECT

DIORA_L

DIOWA_L

NO CONNECT

INTRQA

+5V

MASTER/SLAVE

NO CONNECT

RST_L

DIORDYA

NO CONNECT

Computer Group Literature Center Web Site

Connectors and Jumper Settings

Table 2-8. EIDE Compact FLASH Connector J9
45

NO CONNECT

DATA8

DATA9

DATA10

GND

Flash Bank Selection (J6)
The CPX750HA base board has provision for 1MB of 16-bit flash
memory. The RAM300 memory mezzanine accommodates 4MB or 8MB
of additional 64-bit flash memory.
The flash memory is organized in either one or two banks, each bank either
16- or 64-bits wide. Bank B contains the onboard debugger, PPCBug.
To enable flash bank A (4MB or 8MB of firmware resident on soldered-in
devices on the RAM300 mezzanine), place a jumper across header J6 pins
1 and 2. To enable flash bank B (1MB of firmware located in sockets on
the base board), place a jumper across header J6 pins 2 and 3.
J6

Flash Bank A Enabled (4MB/8MB, Soldered)

http://www.motorola.com/computer/literature

Flash Bank B Enabled (1MB, Sockets)
(Factory Configuration)

2-15

CPU Modules

CPV5350
The CPV5350 Single Board Computer (SBC) is a hot swap, CompactPCI
(Compact Peripheral Communication Interface) compliant computer with
high availability platform support. It is powered by a PICMG (PCI
Industrial Computer Manufacturers Group) compatible Pentium® II
Deschutes Mobile Module. The CPV5350’s 6U CompactPCI standard
form factor (160mm x 233mm x 61mm), 4HP (.8 inch) is designed for
installation into PICMG CompactPCI-compliant backplanes.
The CPV5350 provides:
❏ Standard PC I/O
❏ USB
❏ PCI EIDE
❏ 3D AGP graphics
❏ Dual fast Ethernet controllers
❏ Optional onboard CompactFlash™ connector
The CPV5350’s front panel has connectors for:
❏ Keyboard/mouse
❏ Video
❏ Two serial ports (COM1 and COM2)
❏ Two Ethernet ports
❏ Two USB ports
❏ LED Indicator lights for watchdog alarm, speaker status, hard disk
drive activity, and power.
Refer to the following illustration for front panel connectors and LEDs on
the CPV5350.

2-16

Computer Group Literature Center Web Site

CPV5350

2
Video
V
I
D
E
O

COM 1

COM 2

Ethernet 1

Ethernet 2

USB

1
E
T
H
E
R
N
E
T

Keyboard/Mouse
RESET

Indicator
Lights

RESET

ALRM SPKR

HDD

PWR

CPV5350

http://www.motorola.com/computer/literature

2-17

CPU Modules

Connectors
The next table lists the connectors available to support devices on the
CPV5350. Figure 2-1 on page 2-19 shows the location of the connectors
described in the table.

Table 2-9. CPV5350 Front Panel Connectors, Board
Headers and Components

2-18

Connector

Description

Backplane connector

Ethernet 2

EIDE

J10

Reserved (in-circuit programming)

J12

Reserved (in-circuit emulator)

J13

Ethernet 1

J14

USB port 1

J16

Reset (connected to push-button on the front panel)

J21

Flash ROM

J23

Video connector

J24

COM1 (Serial Port 1)

J25

COM2 (Serial Port 2)

J50

Keyboard/Mouse

Computer Group Literature Center Web Site

Transition Module

2
J5

U50

U34

U35

U30

U31

U38
8

2
1

J17

J20

U25
1

BT1

2475 9901

J12

U26

U55

J21
U11
T1

U62

J23

J24

J25

J13

J14

J51 CR2 CR4
1

J50
CRI

CR3

Figure 2-1. CPV5350 Component Side View

Transition Module
The CPV5350TM80 transition module provides backplane I/O through the
J3 and J5 connectors on the CPV5350 controller module.
When the identical function is available through the CPV5350’s front
panel and the rear transition module, you can use either the front or the
rear, not both.

http://www.motorola.com/computer/literature

2-19

CPU Modules

DRAM Memory Configuration
The CPV5350 has one 168-pin DIMM site for memory expansion. The
DIMM sites accept industry standard PC100-compliant DIMM modules
(8, 16, 32, 64, 128, or 256MB) with or without ECC. You can use either
registered or unbuffered memory modules.

Keyboard/Mouse PS2 Connector
The keyboard/mouse connector (J50) uses a 6-pin, female PS/2 connector.

Table 2-10. Keyboard/Mouse P/S2 Connector Pin
Assignments (J50)
Pin
Number

Signal
Mnemonic

Signal Description

KBDDAT

Keyboard Data

AUXDAT

Auxiliary Data

GND

Ground

KBDVCC

Keyboard Power (current limited to .75 Amp)

KBDCLK

Keyboard Clock

AUXCLK

Auxiliary Clock

CGND

Common Ground

1
7
2489 9902

Figure 2-2. Keyboard/Mouse Connector Diagram

2-20

Computer Group Literature Center Web Site

Ethernet Connectors

Ethernet 1 (J13) and Ethernet 2 (J6) use standard RJ-45 connectors.

Table 2-11. Ethernet Connector Pin Assignments (J13 and
J6)
Pin
Number

Signal Mnemonic

Signal Description

TX+

Differential transmit lines

TX-

Differential transmit lines

RX+

Differential receive lines

RX-

Differential receive lines

Universal Serial Bus (USB) Connector
USB Port 1 and Port 2 (J14) use a 2 x 4 pin USB connector.

Table 2-12. USB Connector Pin Assignments (J14)
Pin
Number

Signal Mnemonic

Signal Description

+5V

Current limited USB power

DATA+

USB serial communication differential

DATA-

USB serial communication differential

GND

USB port common

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2-21

CPU Modules

Serial Port Connectors
COM 1 (Serial Port 1) (J24) and COM 2 (Serial Port 2) (J25) use 2 x 9-pin
D-sub connectors.

Table 2-13. Serial Port Connector Pin Assignments (J24
and J25)
Pin
Number

Signal
Mnemonic

Signal Description

DCD-

data set has detected the data carrier

Receives serial data input from communication
link

Sends serial output to communication link

DTR-

data set is ready to establish a communication link

GND

Ground

DSR-

data set is ready to establish a communication link

RTS-

indicates to data set that UART is ready to
exchange data

CTS-

data set is ready to exchange data

RI-

modem has received a telephone ringing signal

Video Connector
The video connector (J23) uses a 15-pin high density D-sub connector.

Table 2-14. Video Connector Pin Assignments (J23)

2-22

Pin
Number

Signal Mnemonic

Signal Description

RED

Red signal

GREEN

Green signal

BLUE

Blue signal

Computer Group Literature Center Web Site

Video Connector

Table 2-14. Video Connector Pin Assignments (J23)
Pin
Number

Signal Mnemonic

Signal Description

Not connected

DACVSS

Video return

DACVSS

Video return

DACVSS

Video return

DACVSS

Video return

Not connected

DACVSS

Video return

Not connected

DDCDAT

Display data channel data signal for
DDC2 support

HSYNC

Horizontal synchronization

VSYNC

Vertical synchronization

DDCCLK

Display data channel clock signal for
DDC2 support

http://www.motorola.com/computer/literature

2-23

3CPX8540 Carrier Card

Overview
This chapter provides reference information for the CPX8540 carrier card.
The CPV8540 is a 64-bit, 6U, single-width (4HP) CompactPCI® card that
provides front access to PMC modules with both front and rear I/O
connectivity. Rear I/O connections via J3 and J5 allow its use in both
standard CompactPCI backplanes and CompactPCI backplanes with the
H.110 CT bus. The correct jumper settings and pin-out information is
provided for each connector on the carrier card.
This chapter does not include the system controller/host modules. For
information about the system controller/host, refer to Chapter 2, CPU
Modules.

CPX8540 Carrier Card
The CPX8540 carrier card provides connectivity to a wide variety of
video, ATM, analog, serial, and many other functions. The board supports
one double-width or two single-width PMC mezzanine modules.
Once connected, the PMC modules are accessed via front panel
connections of the carrier card. In addition, I/O lines are brought out to the
carrier card’s rear 2mm pin and socket connectors, allowing rear panel
connections in systems such as the CPX8216T chassis.
Key features of the CPX8540 are:
❏ Supports standard (IEEEP1386.1) PMC mezzanine modules
❏ Holds one double-width or two single-width modules
❏ All PMC I/O brought out to the front panel and to rear connectors
❏ Single CompactPCI load via DEC 21154 bridge
❏ Supports 5.0 or 3.3 Volt PMC modules
❏ Supports Plug and Play

3-1

CPX8540 Carrier Card

The CPX8540 reports itself to the system as a bridge chip with the PMC
functions behind it.
The following two figures provide overviews of the card.

PMC2

PMC1

Bridge

Figure 3-1. PMC Modules to CPX8540 Carrier Card

3-2

Computer Group Literature Center Web Site

CPX8540 Carrier Card

J22
J21

J24
J23

J12
J11
J14
J13

Single Width
PMC Module

Figure 3-2. Installing a PMC Module

http://www.motorola.com/computer/literature

3-3

CPX8540 Carrier Card

Connector Pinouts
The tables in this section provide the connector pinout information for the
rear connectors on the carrier card.

Table 3-1. CPCI J3 I/O Connector Pinout
ROW A

ROW B

ROW C

ROW D

ROW E

+3.3V

+5V

PMC1IO5

PMC1IO4

PMC1IO3

PMC1IO2

PMC1IO1

PMC1IO10

PMC1IO9

PMC1IO8

PMC1IO7

PMC1IO6

PMC1IO15

PMC1IO14

PMC1IO13

PMC1IO12

PMC1IO11

PMC1IO20

PMC1IO19

PMC1IO18

PMC1IO17

PMC1IO16

PMC1IO25

PMC1IO24

PMC1IO23

PMC1IO22

PMC1IO21

PMC1IO30

PMC1IO29

PMC1IO28

PMC1IO27

PMC1IO26

PMC1IO35

PMC1IO34

PMC1IO33

PMC1IO32

PMC1IO31

PMC1IO40

PMC1IO39

PMC1IO38

PMC1IO37

PMC1IO36

PMC1IO45

PMC1IO44

PMC1IO43

PMC1IO42

PMC1IO41

PMC1IO50

PMC1IO49

PMC1IO48

PMC1IO47

PMC1IO46

PMC1IO55

PMC1IO54

PMC1IO53

PMC1IO52

PMC1IO51

PMC1IO60

PMC1IO59

PMC1IO58

PMC1IO57

PMC1IO56

V(I/O)

PMC1IO64

PMC1IO63

PMC1IO62

PMC1IO61

NOTE: PMC1IO* signals are those connected to the lower PMC slot, or slot 1.

Table 3-2. CPCI J5 I/O Connector Pinout
ROW A

ROW B

ROW C

ROW D

ROW E

PMC2IO5

PMC2IO4

PMC2IO3

PMC2IO2

PMC2IO1

PMC2IO10

PMC2IO9

PMC2IO8

PMC2IO7

PMC2IO6

PMC2IO15

PMC2IO14

PMC2IO13

PMC2IO12

PMC2IO11

3-4

Computer Group Literature Center Web Site

Connector Pinouts

Table 3-2. CPCI J5 I/O Connector Pinout (continued)
10

PMC2IO20

PMC2IO19

PMC2IO18

PMC2IO17

PMC2IO16

PMC2IO25

PMC2IO24

PMC2IO23

PMC2IO22

PMC2IO21

PMC2IO30

PMC2IO29

PMC2IO28

PMC2IO27

PMC2IO26

PMC2IO35

PMC2IO34

PMC2IO33

PMC2IO32

PMC2IO31

PMC2IO40

PMC2IO39

PMC2IO38

PMC2IO37

PMC2IO36

PMC2IO45

PMC2IO44

PMC2IO43

PMC2IO42

PMC2IO41

PMC2IO50

PMC2IO49

PMC2IO48

PMC2IO47

PMC2IO46

PMC2IO55

PMC2IO54

PMC2IO53

PMC2IO52

PMC2IO51

PMC2IO60

PMC2IO59

PMC2IO58

PMC2IO57

PMC2IO56

V(I/O)

PMC2IO64

PMC2IO63

PMC2IO62

PMC2IO61

NOTE: PMC2IO* signals are those connected to the upper PMC slot, or slot 2.

Table 3-3. PCI 32-bit Interface Connector P11/J11, P21/J21
Pin#

Signal Name

Pin #

TCK

-12V

GND

INTA#

INTB#

INTC#

BUSMODE1#

+5V

INTD#

PCI-RSVD*

GND

PCI-RSVD*

CLK

GND

GNT#

REQ#

+5V

V (I/O)

AD[31]

AD[28]

AD[27]

AD[25]

GND

http://www.motorola.com/computer/literature

3-5

CPX8540 Carrier Card

Table 3-3. PCI 32-bit Interface Connector P11/J11, P21/J21 (continued)

Pin#

Signal Name

Pin #

GND

C/BE[3]#

AD[22]

AD[21]

AD[19]

+5V

V (I/O)

AD[17]

FRAME#

GND

IRDY#

DEVSEL#

+5V

GND

LOCK#

SDONE#

SBO#

PAR

GND

V (I/O)

AD[15]

AD[12]

AD[11]

AD[09]

+5V

GND

C/BE[0]#

AD[06]

AD[05]

AD[04]

GND

V (I/O)

AD[03]

AD[02]

AD[01]

AD[00]

+5V

GND

REQ64#

3-6

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Connector Pinouts

Table 3-4. PCI 32-bit Interface Connector P12/J12, P22/J22
Pin#

Signal Name

Pin #

+12V

TRST#

TMS

TDO

TDI

GND

PCI-RSVD*

BUSMODE2#

+3.3V

RST#

BUSMODE3#

+3.3V

BUSMODE4#

PCI-RSVD*

GND

AD[30]

AD[29]

GND

AD[26]

AD[24]

+3.3V

IDSEL

AD[23]

+3.3V

AD[20]

AD[18]

GND

AD[16]

C/BE[2]#

GND

PMC-RSVD

TRDY#

+3.3V

GND

STOP#

PERR#

GND

+3.3V

SERR#

C/BE[1]#

GND

AD[14]

AD[13]

GND

AD[10]

AD[08]

+3.3V

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3-7

CPX8540 Carrier Card

Table 3-4. PCI 32-bit Interface Connector P12/J12, P22/J22 (continued)

Pin#

Signal Name

Pin #

AD[07]

PMC-RSVD

+3.3V

PMC-RSVD

GND

PMC-RSVD

GND

PMC-RSVD

ACK64#

+3.3V

GND

PMC-RSVD

Table 3-5. PCI 64 bit PCI extension on PMC Connector J13, J23
Pin#

Signal Name

Pin #

GND

C/BE7#

C/BE6#

C/BE5#

C/BE4#

GND

V(I/O)

PAR64

AD63

AD62

AD61

GND

AD60

AD59

AD58

AD57

GND

V(I/O)

AD56

AD55

AD54

AD53

GND

AD52

AD51

AD50

3-8

Computer Group Literature Center Web Site

Connector Pinouts

Table 3-5. PCI 64 bit PCI extension on PMC Connector J13, J23
Pin#

Signal Name

Pin #

AD49

GND

AD48

AD47

AD46

AD45

GND

V(I/O)

AD44

AD43

AD42

AD41

GND

AD40

AD39

AD38

AD37

GND

AD36

AD35

AD34

AD33

GND

V(I/O)

AD32

GND

Table 3-6. User-Defined I/O PCI Interface Connector P14/J14, P24/J24
Pin#

Signal Name

1-64

I/O

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3-9

4PMC Modules

Overview
This chapter provides reference information for the PMC module
supported in the CPX8216 system.

SCSI-2 Controller PMC
The SCSI-2 controller provides fast and wide, single-ended, SCSI-2
(Small Computer System Interface-2) high throughput connectivity for
host carrier boards equipped with PMC (PCI Mezzanine Card)
connections.
The PMC adapter is a plug-and-play device with systems that are
compliant with the PCI Local Bus Specification (revision 2.0).
This controller has the following capabilities:
❏ Single-wide PMC module
❏ 32-bit wide PCI bus support
❏ 128Kb onboard flash memory
❏ 20 Mbps Fast and Wide SCSI-2
❏ Single-ended SCSI-2 interfaces
❏ Front and rear User I/O
❏ 68-pin front panel connector
❏ 64-pin JN4/PN4 rear connector
❏ +3.3V and +5V signaling
❏ Compliance to PCI local bus specification (Revision 2.0)

4-1

PMC Modules

The following figure shows the PMC150 component layout and front
panel.

PN2

PN4

4
PN1

U31
U1

JP40

U15

U14

U13

4118 0702

4-2

Computer Group Literature Center Web Site

Switch Settings

Switch Settings
Use this table as a guideline for configuring the 6-position dip switch on
your PMC.

Table 4-1. PMC Switch Settings

4
Switch

On Function

Off Function

Default

Use INTA

No Use INTA

Use INTB

No Use INTB

Off

Use INTC

No Use INTC

Off

Use INTD

No Use INTD

Off

TERM Enable

TERM Disable

Little Endian

Big Endian

Configure the Big/Little endian mode to your appropriate application for proper
software operation.
Make sure only one INTx line switch is in the ON position.
Enable TERM ENAB is On only if this SCSI controller is physically at the end
of the SCSI bus. If the SCSI controller is in any other position on the bus, TERM
ENAB must be in the OFF mode.

Terminators - The SCSI bus (cable) must be properly terminated at each
end of the bus. The first and last device on the bus should be the only
devices that are set to terminate the bus.
Terminator Power - The SCSI terminators require adequate voltage to
properly terminate the SCSI bus. All SCSI host adapters on the bus should
be set to supply terminator power; and where possible, be located at the
end of the bus and serve as bus terminators.The terminator resistors must
be present on the first and last device on the bus only.
For further information on this PMC, visit the Technobox, Inc. web site at
http://www.technobox.com.

http://www.motorola.com/computer/literature

4-3

PMC Modules

Connector Pin Assignments
The table below provides the connector pin assignments for the SCSI
connector on the PMC adapter. The connector uses a 68-pin Euro-style
SCSI cable, either shielded for external or internal cabinet applications or
non-shielded for internal cabinet applications only. For rear I/O, a 64-pin
conductor cable is used. The pin assignments are also provided in the
following table.

Table 4-2. PMC Pin Assignments

4-4

Signal
name

68-Pin
Connector
Number

64-Pin
Conductor
Cable
Number

Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground

1
2
3
4
5
6
7
8
9
10
11

1
3
5
7
9
11
13
15
17
19
21

Ground
Ground
Ground
Ground
Ground
TERMPWR
TERMPWR
Reserved
Ground
Ground
Ground
Ground

12
13
14
15
16
17
18
19
20
21
22
23

23
25
27
29
31
33
N/C
N/C
35
37
39
41

68-Pin
Connector
Number

Signal
name

2
4
6
8
10
12
14
16
18
20
22

35
36
37
38
39
40
41
42
43
44
45

-DB(12)
-DB(13)
-DB(14)
-DB(15)
-DB(P1)
-DB(0)
-DB(1)
-DB(2)
-DB(3)
-DB(4)
-DB(5)

24
26
28
30
32
34
N/C
N/C
36
38
40
42

46
47
48
49
50
51
52
53
54
55
56
57

-DB(6)
-DB(7)
-DB(P)
Ground
Ground
TERMPWR
TERMPWR
Reserved
Ground
-ATN
Ground
-BSY

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Connector Pin Assignments

Table 4-2. PMC Pin Assignments (continued)

Signal
name

68-Pin
Connector
Number

64-Pin
Conductor
Cable
Number

Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground

24
25
26
27
28
29
30
31
32
33
34

43
45
47
49
51
53
55
57
59
61
63

http://www.motorola.com/computer/literature

44
46
48
50
52
54
56
58
60
62
64

68-Pin
Connector
Number

Signal
name

58
59
60
61
62
63
64
65
66
67
68

-ACK
-RST
-MSG
-SEL
-C/D
-REQ
-I/O
-DB(8)
-DB(9)
-DB(10)
-DB(11)

4-5

5Transition/Bridge Modules

Overview
This chapter provides reference information for the various transition and
bridge modules supported in the CPX8216 system.
The correct jumper setting and pin-out information is provided for each
module.
Note

The CPX750HATM is also used with the MCP750HA in some
chassis configurations.
Your system may not contain all boards listed in this chapter, or
it may contain third-party boards that are not listed in this
chapter. For information about third-party boards, refer to the
board manufacturer’s documentation.

The following table lists the modules covered in this chapter:

Table 5-1. System Components
Topic:

Page:

CPX750HATM Transition Module

5-1

CPV5350TM80 Transition Module

5-29

CPX750HATM Transition Module
The CPX750HATM transition module provides the interface between the
standard Parallel Port, EIDE port, floppy port, keyboard/mouse port, Serial
Port connectors, and the CPX750HA CompactPCI Single Board Computer
module.

5-1

Transition/Bridge Modules

The CPX750HATM transition module includes:
❏ Industry-standard connectors for these interfaces:
–

Two asynchronous RJ-45 serial ports (DTE)

–

Two asynchronous/synchronous HD-26 serial ports, labeled
Serial 3 and Serial 4 on the face plate, which can be configured
for EIA-232-D, EIA-530, V.35, or X.21 interfaces (DCE or
DTE) through the installation of Motorola’s Serial Interface
Modules (SIMs)

–

One parallel port (IEEE Standard 1284-I compliant)

–

One combination keyboard/mouse port

❏ Two 60-pin Serial Interface Module (SIM) connectors for
configuring the asynchronous/synchronous serial ports
❏ One 40-pin header for EIDE port
❏ One 34-pin header for floppy port
❏ Two 64-pin headers for PMCIO (1 ground pin provided with each
PMCIO signal)
Figure 5-1 on page 5-3 shows the CPX750HATM transition module
component layout and the front panel. See Connectors on page 5-4 for a
list of the front panel port connectors.

Serial Ports 3 and 4 Default Configuration
The CPX750HATM serial ports 3 and 4 are factory configured as follows:
❏ Serial Port 3: DTE (with SIMM 01-W3877B01A installed)
❏ Serial Port 4: DCE (with SIMM 01-W3876B01A installed)

5-2

Computer Group Literature Center Web Site

13
26

J24

SERIAL 4

1
2

1
14

59
60

13
26

1
2

SERIAL 3

1
14

J23

17
34

64
63

59
60

PARALLEL

2
1

1
18

J10

J8
3

COM 2

J21

J11

J14

J13

COM 1

2
1

J16

KB/MS

64
63

J19

J17

J18

J15

USB 1

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USB 0

2
1

34
33

40
39

2214 9804

Serial Ports 3 and 4 Default Configuration

Figure 5-1. CPX750HATM Transition Module

5-3

Transition/Bridge Modules

Serial Port Interface Jumper (J8 and J9)
J8 (for serial port 3) and J9 (for serial port 4) set the serial ports to either
DTE or DCE communication. For more information about configuring the
serial port, see Installing the Serial Interface Modules on page 5-16.

DTE

DCE
11650 9610

Figure 5-2. Serial Port Interface Jumper (J9) Settings

Connectors
Refer to Figure 5-1 on page 5-3 for the location of the following connectors
Backplane Connectors (J3/J4/J5)
I/O signals and power are provided to the CPX750HATM from the
CPX750 through CompactPCI connectors J3 and J5. The J4 connector is
for physical alignment purposes only and has no functional pin
connections or assignments.
Connector J3 is a 95-pin AMP Z-pack 2mm hard metric type B connector.
This connector routes the I/O signals for the PMC I/O and serial channels.
The pin assignments for J3 are as follows (outer row F is assigned and used
as ground pins but is not shown in the table):
Connector J4 is a 110-pin 2mm hard metric type A connector. This
connector is placed on the board for alignment purposes only. The keying
tabs on the type A connector assist with alignment of pins in the backplane
connector during insertion of the boards. No signals are connected to J4
except the row F ground pins.
Connector J5 is a 110-pin AMP Z-pack 2mm hard metric type B connector.
This connector routes the I/O signals for the IDE (secondary port), the
keyboard, the mouse, the two USB ports, and the printer ports. The pin

5-4

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Connectors

assignments for J5 are as follows (the outer row F is assigned and used as
ground pins but is not shown in the table):
Table 5-2 and Table 5-3 provide the pin assignments and signal mnemonics
for connectors J3 and J5 (J4 is not shown)

Table 5-2. J3 User I/O Connector
ROW A

ROW B

ROW C

ROW D

ROW E

Reserved

+12V

-12V

RXD3

RXD4

Reserved

GND

RXC3

GND

RXC4

Reserved

MXCLK

MXDI

MXSYNC_L

MXDO

Reserved

GND

TXC3

GND

TXC4

Reserved

TXD3

TXD4

+3.3V

+5V

PMCIO5

PMCIO4

PMCIO3

PMCIO2

PMCIO1

PMCIO10

PMCIO9

PMCIO8

PMCIO7

PMCIO6

PMCIO15

PMCIO14

PMCIO13

PMCIO12

PMCIO11

PMCIO20

PMCIO19

PMCIO18

PMCIO17

PMCIO16

PMCIO25

PMCIO24

PMCIO23

PMCIO22

PMCIO21

PMCIO30

PMCIO29

PMCIO28

PMCIO27

PMCIO26

PMCIO35

PMCIO34

PMCIO33

PMCIO32

PMCIO31

PMCIO40

PMCIO39

PMCIO38

PMCIO37

PMCIO36

PMCIO45

PMCIO44

PMCIO43

PMCIO42

PMCIO41

PMCIO50

PMCIO49

PMCIO48

PMCIO47

PMCIO46

PMCIO55

PMCIO54

PMCIO53

PMCIO52

PMCIO51

PMCIO60

PMCIO59

PMCIO58

PMCIO57

PMCIO56

VIO

PMCIO64

PMCIO63

PMCIO62

PMCIO61

Row F is assigned and used as ground pins but is not shown in the table

http://www.motorola.com/computer/literature

5-5

Transition/Bridge Modules

Table 5-3. J5 User I/O Connector

ROW A

ROW B

ROW C

ROW D

ROW E

Reserved

GND

Reserved

+5V

SPKROC_L

KBDDAT

KBDCLK

KBAUXVCC

AUXDAT

AUXCLK

Reserved

GND

Reserved

STB_L

GND

UVCC0

Reserved

AFD_L

Reserved

GND

UVCC1

PD2

INIT_L

PD1

ERR_L

PD0

PD6

PD5

PD4

PD3

SLIN_L

SLCT

BUSY

ACK_L

PD7

RTSa

CTSa

RIa

GND

DTRa

DCDa

+5V

RXDa

DSRa

TXDa

RTSb

CTSb

RIb

+5V

DTRb

DCDb

GND

RXDb

DSRb

TXDb

TR0_L

WPROT_L

RDATA_L

HDSEL_L

DSKCHG_L

MTR1_L

DIR_L

STEP_L

WDATA_L

WGATE_L

Reserved

INDEX_L

MTR0_L

DS1_L

DS0_L

CS1FX_L

CS3FX_L

DA1

Reserved

GND

Reserved

DA0

DA2

DMARQ

IORDY

DIOW_L

DMACK_L

DIOR_L

DD14

DD0

GND

DD15

INTRQ

DD3

DD12

DD2

DD13

DD1

DD9

DD5

DD10

DD4

DD11

RESET_L

DRESET_L

DD7

DD8

DD6

Row F is assigned and used as ground pins but is not shown in the table

Asynchronous Serial Port Connectors (J10 and J11)
The interface for the asynchronous serial ports, COM1 and COM2, is
provided with two RJ-45 connectors, J11 and J10. The connector shields

5-6

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Connectors

for these ports are tied to chassis ground. The pin assignments and signal
mnemonics for these connectors are listed in the next table.

Table 5-4. COM1 (J11) and COM2 (J10)
Pin

Signal

DCD

RTS

GND

TXD

RXD

GND

CTS

DTR

Asynchronous/Synchronous Serial Port Connectors (J6 and J24)
The interface for the asynchronous/synchronous serial ports 3 and 4 is
provided by two HD-26 connectors, J6 and J24. The connector shields for
these ports are tied to chassis ground.
The pin assignments and signal mnemonics for Serial Port 3 are listed in
Table 5-5, and the pin assignments and signal mnemonics for Serial Port 4
are listed in Table 5-6.

Table 5-5. Serial Port 3 (J6)
Pin

Signal

No Connect

SP3_P14

TXD3

TXCI3

RXD3

SP3_P16

RTS3

RXCI3

CTS3

LLB3

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5-7

Transition/Bridge Modules

Table 5-5. Serial Port 3 (J6) (continued)

Signal

DSR3

SP3_P19

GND

DTR3

DCD3

RLB3

SP3_P9

RI3

SP3_P10

SP3_P23

SP3_P11

TXCO3

SP3_P12

TM3

SP3_P13

SP3_P26

Table 5-6. Serial Port 4 (J24)

5-8

Signal

No Connect

SP4_P14

TXD4

TXCI4

RXD4

SP4_P16

RTS4

RXCI4

CTS4

LLB4

DSR4

SP4_P19

GND

DTR4

DCD4

RLB4

SP4_P9

RI4

SP4_P10

SP4_P23

SP4_P11

TXCO4

SP4_P12

TM4

SP4_P13

SP4_P26

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Connectors

Parallel I/O Port Connector (J7)
The interface for the parallel port is a standard IEEE P1284-C, 36-pin
connector, J7. The functionality of each signal depends on the mode of
operation of this bidirectional Parallel Peripheral Interface. Refer to the
IEEE P1284 D2.00 Standard for a complete description of each signal
function. The connector shield is tied to chassis ground.
The pin assignments and signal mnemonics for this connector are listed in
the next table.

Table 5-7. Parallel I/O Connector (J7)
Pin

Signal

PRBSY

GND

PRSEL

GND

PRACK_

GND

PRFAULT_

GND

PRPE

GND

PRD0

GND

PRD1

GND

PRD2

GND

PRD3

GND

PRD4

GND

PRD5

GND

PRD6

GND

PRD7

GND

PRINIT_

GND

PRSTB_

GND

SELIN_

GND

AUTOFD_

GND

Pull-up

No Connect

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5-9

Transition/Bridge Modules

Keyboard/Mouse Connector (J16)
The Keyboard/Mouse interface is provided by a 6-pin circular DIN
connector. To use the keyboard function only, a keyboard may be
connected directly to this connector. To use both the keyboard and the
mouse functions, use the Y-adapter cable provided with the
CPX750HATM. Refer to the following table for pin assignments.

Table 5-8. Keyboard/Mouse Connector (J16)

5
Pin

Signal

KBD DAT

MSDAT

GND

+5Vdc Fused

KBDCLK

MSCLK

USB Connectors (J19 and J18)
The standard version of the CPX750 routes the USB port signals only to
the CPX750 front panel USB connectors J18 and J17. Therefore the USB
port connectors (J19 and J18) on the CPX750HATM are not active. The
USB ports can be routed to the CPX750HATM using an alternate build
option of the CPX750. Contact your local Motorola Sales office for details.

5-10

Computer Group Literature Center Web Site

Connectors

EIDE Connector (J15)
The CPX750HATM provides a 40-pin header (J15) to interface to the
CPX750 secondary EIDE port. The pin assignments and signal mnemonics
for this connector are listed in the next table.

Table 5-9. EIDE Connector (J15)
Pin

Signal

DRESET_L

GND

DD7

DD8

DD6

DD9

DD5

DD10

DD4

DD11

DD3

DD12

DD2

DD13

DD1

DD14

DD0

DD15

GND

No Connect

DMARQ

GND

DIOW_L

GND

DIOR_L

GND

IORDY

No Connect

DMACK_L

GND

INTRQ

No Connect

DA1

No Connect

DA0

DA2

CS1FX_L

CS3FX_L

No Connect

GND

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5-11

Transition/Bridge Modules

Floppy Port Connector (J17)
The CPX750HATM provides a 34-pin header (J17) to interface to a floppy
disk drive. The pin assignments and signal mnemonics for this connector
are listed in the next table.

Table 5-10. Floppy Connector (J17)

Signal

GND

No Connect

GND

No Connect

GND

No Connect

INDEX_L

GND

MTR0_L

GND

DS1_L

No Connect

DS0_L

GND

MTR1_L

No Connect

DIR_L

GND

STEP_L

GND

WDATA_L

GND

WGATE_L

GND

TR0_L

GND

WPROT_L

GND

RDATA_L

GND

HDSEL_L

GND

DSKCHG_L

+5Vdc Power Connector (J14)
The CPX750HATM has a 4-pin header that can be used to provide +5Vdc
power to offboard devices. This power is derived from the fused +5Vdc
power on the CPX750. Any external device powered from this connector

5-12

Computer Group Literature Center Web Site

Connectors

must not draw more than 200mA. The pin assignments are listed in the
following table.

Table 5-11. +5Vdc Power Connector (J14)
Pin

Signal

+5Vdc

GND

No Connect

Speaker Output Connector (J13)
The 2-pin header (J13) provides connection to an external speaker from the
CPX750 PCB Counter 2 output. The speaker driver, located on the
CPX750 PCB, consists of a 500 mA (max) current sink transistor in series
with a 33 ohm resistor. The pin assignments are listed in the following
table.

Table 5-12. Speaker Output Connector (J13)
Pin

Signal

GND

SPKROC_L

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5-13

Transition/Bridge Modules

PMC I/O Connectors
The PMC I/O connectors consist of two 64-pin header connectors J2 and
J21. The pin assignments and signal mnemonics for these connectors are
listed below.

Table 5-13. PMC I/O Connector (J2)

5-14

Signal

GND

PMCIO1

GND

PMCIO2

GND

PMCIO3

GND

PMCIO4

GND

PMCIO5

GND

PMCIO6

GND

PMCIO7

GND

PMCIO8

GND

PMCIO9

GND

PMCIO10

GND

PMCIO11

GND

PMCIO12

GND

PMCIO13

GND

PMCIO14

GND

PMCIO15

GND

PMCIO16

GND

PMCIO17

GND

PMCIO18

GND

PMCIO19

GND

PMCIO20

GND

PMCIO21

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Connectors

Table 5-13. PMC I/O Connector (J2) (continued)
Pin

Signal

GND

PMCIO22

GND

PMCIO23

GND

PMCIO24

GND

PMCIO25

GND

PMCIO26

GND

PMCIO27

GND

PMCIO28

GND

PMCIO29

GND

PMCIO30

GND

PMCIO31

GND

PMCIO32

Table 5-14. PMC I/O Connector (J21)
Pin

Signal

GND

PMCIO33

GND

PMCIO34

GND

PMCIO35

GND

PMCIO36

GND

PMCIO37

GND

PMCIO38

GND

PMCIO39

GND

PMCIO40

GND

PMCIO41

GND

PMCIO42

GND

PMCIO43

http://www.motorola.com/computer/literature

5-15

Transition/Bridge Modules

Table 5-14. PMC I/O Connector (J21) (continued)

Signal

GND

PMCIO44

GND

PMCIO45

GND

PMCIO46

GND

PMCIO47

GND

PMCIO48

GND

PMCIO49

GND

PMCIO50

GND

PMCIO51

GND

PMCIO52

GND

PMCIO53

GND

PMCIO54

GND

PMCIO55

GND

PMCIO56

GND

PMCIO57

GND

PMCIO58

GND

PMCIO59

GND

PMCIO60

GND

PMCIO61

GND

PMCIO62

GND

PMCIO63

GND

PMCIO64

Installing the Serial Interface Modules
Configure the serial ports 3 and 4 for the required interface by installing
the appropriate SIM.

5-16

Computer Group Literature Center Web Site

Installing the Serial Interface Modules

Prior to installing the SIMs, set the jumpers on header J8 (for Serial Port
3) and header J9 (for Serial Port 4) for either DCE or DTE. Set the jumper
to position 1-2 if the SIM is for a DTE interface. Set the jumper to position
2-3 if the SIM is for a DCE interface.

DCE

DTE

5
You must set the jumpers and install the SIMs prior to installing the
CPX750HATM transition module in the system chassis.
The SIMs plug into connector J23 (for Serial Port 3) or J1 (for Serial Port
4) on the CPX750HATM transition module.
Install the SIMs on the CPX750HATM transition module per the following
procedure:
1. Align the SIM so that P1 on the SIM lines up with the appropriate SIM
connector (J23 for Serial Port 3 or J1 for Serial Port 4) on the transition
module. Note the position of the alignment key on P1. See the next
figure.
2. Place the SIM onto the transition module SIM connector, making sure
that the mounting holes also line up with the standoffs on the transition
module.
Mounting Hole

P1
Alignment
Key

Mounting Hole

http://www.motorola.com/computer/literature

11637 9610

5-17

Transition/Bridge Modules

3. Gently press the top of the SIM to seat it on the transition module SIM
connector. If the SIM does not seat with gentle pressure, re-check the
alignment of the connectors.
Note

Do not force the SIM onto the transition module.

4. Secure the SIM to the transition module standoffs with the two
Phillips-head screws provided. Do not over tighten the screws.

Port Configuration Diagrams
The following sections describe the configurations for COM1 and COM2
asynchronous serial ports.
COM1 and COM2 Asynchronous Serial Ports
The asynchronous serial port (COM1 and COM2) configuration is shown
in Figure 5-3 on page 5-19.

5-18

Computer Group Literature Center Web Site

Port Configuration Diagrams

9
1
6
COM1

(Front J15
Panel)

2
4
7
3
5

5
TXD

SOUT1

RTS

RTS1#

DTR

DTR1#

RXD

SIN1

CTS

CTS1#

5
7

COM1
(J11)

DSR1#
DCD

DCD1#
RI1#

1
3

GND
PC87307

J5
TXD

SOUT2

RTS

RTS2#

DTR

DTR2#

RXD

SIN2

CTS

CTS2#

8
5
7

COM2
(J10)

DSR2#
DCD

DCD2
RI2#

1
3

GND
6

CPX750

CPX750HATM
Transition Module
2105 9710

Figure 5-3. DTE Port Configuration (COM1 and COM2)

http://www.motorola.com/computer/literature

5-19

Transition/Bridge Modules

Asynchronous/Synchronous Serial Ports
The asynchronous/synchronous serial port (Port 3 and Port 4) interface
configuration diagrams are on the following pages.

5-20

Computer Group Literature Center Web Site

Port Configuration Diagrams

Z85230 SCC

DB25
RXD

TXD

CTS#

RTS#

TXD

RXD

RTS#

CTS#

DTR#

DCD#

TRXC

RTXC

J3/MX

TXC

2
1

RXC#

J8, J9

ETXC

3
5
2
4

20
15
17
24

Z8536 CIO
DCD#

DTR#

TM#

LLB#

RI#

RLB#

RI#

GND
CPX750

CPX750HATM
Transition Module

6
21

TM#

25
22

DSR#

EIA-232-D DCE SIM
2106 971

Figure 5-4. EIA-232-D DCE Port Configuration (Ports 3 and 4)

http://www.motorola.com/computer/literature

5-21

Transition/Bridge Modules

Z85230 SCC

DB25
TXD

TXD

RTS#

RXD

CTS#

DCD#

TRXC

RTXC

J3/MX

2
4
3
5
8

ETXC 24

2
1

TXC#

J8, J9

RXC

15
17

Z8536 CIO
DTR

DTR#

LLB#

RLB#

DSR#

RI#

GND#
CPX750

CPX750HATM
Transition Module

6
22

TM#

25
7

EIA-232-D DTE SIM
2107 971

Figure 5-5. EIA-232-D DTE Port Configuration (Ports 3 and 4)

5-22

Computer Group Literature Center Web Site

Port Configuration Diagrams

Z85230 SCC

DB25

TXD

RXDB
RXDA

RTS_

CTSB
CTSA
TXDB

RXD

+
-

CTS_

+
+
-

14
2

RTSB
RTSA

TXCB
TXCA

2
1

TRXC

RXCB
RXCA

J8, J9
RTXC

ETXCB
ETXCA

+
-

J3/MX

DCDB
DCDA

Z8536 CIO
DTR_

LL_

+
-

RI_

+
-

TM_

-V
-V

RL
LL
GND

CPX750

CPX750HATM
Transition Module

12
15
9
17
11
24

10
8

DSRB
DSRA

DSR_

23
20

RL_

DTRA

13
5

TXDA

DTRB
DCD_

16
3

22
6
21
18
7

EIA-530-D DCE SIM
2108 9710

Figure 5-6. EIA-530 DCE Port Configuration (Ports 3 and 4)

http://www.motorola.com/computer/literature

5-23

Transition/Bridge Modules

Z85230 SCC

DB25

TXD

TXDB
TXDA

RTS_

RTSB
RTSA

19
4

RXDB

RXD

+
-

CTS_

+
-

DCD_

+
-

RXDA
CTSB
CTSA
DTRB
DTRA
ETXCB
ETXCA

3
2
1

TRXC

+
-

J8, J9
RTXC

TXCB
TXCA
RXCB
RTXCA

+
-

J3/MX

DTRB
DTRA

Z8536 CIO
DTR_

LL_

+
-

RI_

+
-

TM_

-V
-V

(R)
TM
GND

CPX750

CPX750HATM
Transition Module

13
5
10
20
8
11
15
24
12
17
15
9
17

23
20

DSRB
DSRA

DSR_

16
3

RL_

14
2

22
6
26
25
7

EIA-530-D DTE SIM
2109 9710

Figure 5-7. EIA-530 DTE Port Configuration (Ports 3 and 4)

5-24

Computer Group Literature Center Web Site

Port Configuration Diagrams

Z85230 SCC

DB25
Term

TXD

RXDB
RXDA
CTS

RTS_
Term

+
-

RXD

TXDB
TXDA
RTS

DCD_

DTR

CTS_
Term

3
2
1

TRXC

J3/MX

Term

J8, J9

Term

+
-

RTXC

TXCB
TXCA
RXCB
RXCA
ETXCB
ETXCA

16
3
5
14
2
4

5
20
12
15
9
17
11
24

Z8536 CIO
DCD

DTR_
LL_
RL_

DSR
DSR_
RI_
TM_

GND

V.35-DCE SIM
CPX750

CPX750HATM
Transition Module
Term = V.35 Termination Network

2110 971

Figure 5-8. V.35-DCE Port Configuration (Ports 3 and 4)

http://www.motorola.com/computer/literature

5-25

Transition/Bridge Modules

Z85230 SCC

DB25
Term

TXD

RTS

RTS_
Term

+
-

RXD

DCD

DCD_
Term

3
2
1

TRXC

Term

+
-

J8, J9

Term

+
-

RTXC

Z8536 CIO

RXDB
RXDA
CTS

CTS_

TXDB
TXDA

J3/MX

RXCB
RXCA

9
17

RI_

TM_

GND

CPX750

CPX750HATM
Transition Module

12
15
17

DSR

DSR_

TXCB
TXCA

RL_

16
3

11
24
15

LL_

ETXCB
ETXCA

DTR

DTR_

14
2

20
18
21
6
22
25
7

V.35-DCE SIM

Term = V.35 Termination Network

2111 971

Figure 5-9. V.35-DTE Port Configuration (Ports 3 and 4)

5-26

Computer Group Literature Center Web Site

Port Configuration Diagrams

Z85230 SCC

DB25
RXDB
RXDA

TXD

16
3

RTS_
RXD

+
-

CTS_

+
-

TXDB
TXDA
CTRLB
CTRLA

14
2
11
24

DCD_

3
2
1

TRXC

J3/MX

SETB
SETA

12
15
17

J8, J9

RTXC

Z8536 CIO

INDB
INDA

DTR_
LL_

RL_

9
17

DSR_
RI_

TM_

+V
GND
7

X.21 DCE SIM
CPX750

CPX750HATM
Transition Module
2112 971

Figure 5-10. X.21-DCE Port Configuration (Ports 3 and 4)

http://www.motorola.com/computer/literature

5-27

Transition/Bridge Modules

Z85230 SCC

DB25
TXDB
TXDA

TXD

CTRLB
CTRLA

RTS_

RXDB

+
-

RXD

14
2
11
24

RXDA

16
3

INDB
INDLA

9
17

SETB
SETA

12
15

CTS_

+
-

DCD_

3
2
1

TRXC

J3/MX

NC
+
-

J8, J9

RTXC

Z8536 CIO
DTR_
LL_

RL_

DSR_
RI_

TM_

+V
GND

X.21 DTE SIM
CPX750

CPX750HATM
Transition Module

Figure 5-11. X.21-DTE Port Configuration (Ports 3 and 4)

5-28

Computer Group Literature Center Web Site

CPV5350TM80 Transition Module

CPV5350TM80 Transition Module
The CPV5350TM80 transition module provides rear I/O connectivity for
the CPV5350 CPU controller module.
The CPV5350TM80 provides rear panel connections for:
❏ Two Ethernet ports
❏ Two serial ports

❏ Two Universal Serial Bus ports
❏ One parallel port
❏ One video port
❏ One keyboard/mouse port
❏ On-board headers for keyboard/mouse/power LED
❏ On-board headers for a speaker and reset
❏ On-board EIDE header (supports up to four devices), floppy
drives,
When the identical function is available through the CPV5350 controller’s
front panel and the CPV5350TM80 transition module’s panel, you can use
either the front or the rear connector, but not both.

http://www.motorola.com/computer/literature

5-29

Transition/Bridge Modules

The next figure shows the CPV5350TM80 front panel and on-board
connectors and jumpers.

PWR
GND
GND

GND

J14
J6
KBDCLK
KBDDAT
MDAT
GND
KVCC
MCLK

J13

J19

1
E
T
H
E
R
N
E
T

5
J12
J18

2
T2
1

J21

J9
T1

J10

J16

J1
GND
VCC
SMCLK
SMDATA
SMALT
GND

BTI
BYPASS
VCC
GND
GND
INTRUDER

PBRRESET
SCSI
PIDE
SIDE
ALARM
SPKR

GND
VCC
VCC
VCC
VCC
VCC

J2
J3
J4

J20

V
I
D
E
O

P
A
R
A
L
L
E
L

CPV5350TM

2493 9902

5-30

Computer Group Literature Center Web Site

Connectors

Connectors
The following table lists the connectors available to support devices on the
CPV5350. The figure on the preceding page shows the location of the
connectors described in the table.
Connector

Description

SM Bus and LM78 connector

EIDE indicator lights, push-button reset, alarm indicator,
and speaker connector

Fan tachometer connector

EIDE connector

Keyboard/Mouse, power LED connector

Miscellaneous Power

Floppy Connector

J10

COM 2

J12

USB port

J13

Ethernet 1

J14

Keyboard/Mouse

J16

Video Connector

J18

Ethernet 2

J19

USB Port

J20

Parallel port connector

J21

COM1

http://www.motorola.com/computer/literature

5-31

Transition/Bridge Modules

Keyboard/Mouse PS2 Connector
The keyboard/mouse connector (J14) uses a 6-pin, female PS/2 connector.

Table 5-15. Keyboard/Mouse P/S2 Connector Pin
Assignments (J14)

Signal Mnemonic

Signal Description

KBDDAT

Keyboard Data

AUXDAT

Auxiliary Data

GND

Ground

KBDVCC

Keyboard Power (current limited to .75 Amp)

KBDCLK

Keyboard Clock

AUXCLK

Auxiliary Clock

CGND

Common Ground

1
7
2489 9902

Figure 5-12. Keyboard/Mouse Connector Diagram

5-32

Computer Group Literature Center Web Site

Connectors

Ethernet Connectors
Ethernet 1 (J13) and Ethernet 2 (J18) use standard RJ-45 connectors.

Table 5-16. Ethernet Connector Pin Assignments (J13 and
J18)
Pin

Signal Mnemonic

Signal Description

TX+

Differential transmit lines

TX-

Differential transmit lines

RX+

Differential receive lines

RX-

Differential receive lines

Serial Port Connectors
COM 1 (Serial Port 1, J21) and COM 2 (Serial Port 2, J10) use 2 x 9-pin
D-sub connectors.

Table 5-17. Serial Port Connector Pin Assignments
(J21 and J10)
Pin

Signal
Mnemonic

Signal Description

DCD-

Data set has detected the data carrier

Receives serial data input from communication link

Sends serial output to communication link

DTR-

Data set is ready to establish a communication link

GND

Ground

http://www.motorola.com/computer/literature

5-33

Transition/Bridge Modules

Table 5-17. Serial Port Connector Pin Assignments
(J21 and J10) (continued)

Signal
Mnemonic

Signal Description

DSR-

Data set is ready to establish a communication link

RTS-

Indicates to data set that UART is ready to exchange data

CTS-

Data set is ready to exchange data

RI-

Modem has received a telephone ringing signal

Video Connector
The video connector (J16) uses a 15-pin high density D-sub connector.

Table 5-18. Video Connector Pin Assignments (J16)

5-34

Signal
Mnemonic

Signal Description

RED

Red signal

GREEN

Green signal

BLUE

Blue signal

Not connected

DACVSS

Video return

DACVSS

Video return

DACVSS

Video return

DACVSS

Video return

Not connected

DACVSS

Video return

Not connected

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Connectors

Table 5-18. Video Connector Pin Assignments (J16)
Pin

Signal
Mnemonic

Signal Description

DDCDAT

Display data channel data signal for DDC2 support

HSYNC

Horizontal synchronization

VSYNC

Vertical synchronization

DDCCLK

Display data channel clock signal for DDC2 support

Parallel Port Connector (J20)
The parallel port (J20) uses a 25-pin, D-sub connector.

Table 5-19. Parallel Connector Pin Assignments (J20)
Pin

Signal Mnemonic

Signal Description

STROBE-

Data at parallel port is valid

Parallel data lines

Parallel data line

ACK-

Acknowledge data retrieval

BUSY

Printer cannot accept more data

Printer out of paper

SELECT

Set high when selected

AFD-

Causes printer to add a line feed

http://www.motorola.com/computer/literature

5-35

Transition/Bridge Modules

Table 5-19. Parallel Connector Pin Assignments (J20)

Signal Mnemonic

Signal Description

ERR-

Set low when an error is detected

INIT-

Initializes the printer

SLIN-

Selects the printer

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

EIDE Headers (J5)

Table 5-20. EIDE Header (J5) Pin Assignments

5-36

Signal
Mnemonic

Signal
Description

Signal
Mnemonic

Signal
Description

Reset

Reset signal
to drive

GND

Ground

DD7

Drive data
line

DD8

Drive data
line

DD6

Drive data
line

DD9

Drive data
line

DD5

Drive data
line

DD10

Drive data
line

Computer Group Literature Center Web Site

Connectors

Table 5-20. EIDE Header (J5) Pin Assignments
Pin

Signal
Mnemonic

Signal
Description

Signal
Mnemonic

Signal
Description

DD4

Drive data
line

DD11

Drive data
line

DD3

Drive data
line

DD12

Drive data
line

DD2

Drive data
line

DD13

Drive data
line

DD1

Drive data
line

DD14

Drive data
line

DD0

Drive data
line

DD15

Drive data
line

GND

Ground

DMARQ

Drive DMA
request

GND

Ground

IOW

Drive I/O
write

GND

Ground

IOR

Drive I/O
read

GND

Ground

IORDY

Drive is ready
for I/O cycles

CSEL

Cable select

DMACK

Drive DMA
acknowledge

GND

Ground

INTRQ

Drive
interrupt
request

IOCS16

16 bit
register is
decoded

http://www.motorola.com/computer/literature

5-37

Transition/Bridge Modules

Table 5-20. EIDE Header (J5) Pin Assignments

Signal
Mnemonic

Signal
Description

Signal
Mnemonic

Signal
Description

DA1

Drive register
and data port
address lines

PDIAG

Output from
drive 1 and
monitored
by drive 0

DA0

Drive register
and data port
address lines

DA2

Drive
register and
data port
address lines

CS1

Chip select
drive 0, also
command
register block
select

CS3

Chip select
drive 1, also
command
register
block select

DASP

Drive active
slave present

GND

Ground

Floppy Header (J9)

Table 5-21. Floppy Header (J9) Pin Assignments

5-38

Signal
Mnemonic

Signal
Description

Signal
Mnemonic

Signal
Description

GND

Drive
common

DRVDENS0

Disk density
select
communication

GND

Drive
common

DRVDENS1

Disk density
select
communication

GND

Drive
common

INDEX

Beginning of a
track

Computer Group Literature Center Web Site

Connectors

Table 5-21. Floppy Header (J9) Pin Assignments
Pin

Signal
Mnemonic

Signal
Description

Signal
Mnemonic

Signal
Description

GND

Drive
common

MTR0

Motor enable
output

GND

Drive
common

DS1

Drive select 1

GND

Drive
common

DS0

Drive select 0

GND

Drive
common

MTR1

Motor enable
output

GND

Drive
common

DIR

Controls
direction of the
floppy disk drive
head during seek
operation

GND

Drive
common

STEP

Supplies step
pulses to move
head during seek
operations

GND

Drive
common

WDATA

Writes serial data
to disk drive

GND

Drive
common

WGATE

Enables head of
disk drive to
write to disk

GND

Drive
common

TR0

Head of floppy
disk drive is at
track 0

http://www.motorola.com/computer/literature

5-39

Transition/Bridge Modules

Table 5-21. Floppy Header (J9) Pin Assignments

Signal
Mnemonic

Signal
Description

Signal
Mnemonic

Signal
Description

GND

Drive
common

WPROT

Disk is write
protected

GND

Drive
common

RDATA

Raw read data
from disk drive

GND

Drive
common

HDSEL

Determines the
side of the floppy
disk being
accessed

GND

Drive
common

DSKCHG

Notifies disk
drive controller
that the drive
door is open

Keyboard/Mouse/Power LED Header (J6)
The table below shows the pin assignments for the keyboard, mouse, and
power LED header.

Table 5-22. Keyboard/Mouse/Power LED Header (J6) Pin
Assignments

5-40

Signal
Mnemonic

Signal
Description

Signal
Mnemonic

Signal
Description

PWRLED

Power LED
Indicator

KBDCLK

Clock for
keyboard

GND

Ground

KBDDAT

Data line for
keyboard

Computer Group Literature Center Web Site

Connectors

Table 5-22. Keyboard/Mouse/Power LED Header (J6) Pin
Assignments (continued)
Pin

Signal
Mnemonic

Signal
Description

Signal
Mnemonic

Signal
Description

GND

Ground

AUXDAT

Data line for
mouse

GND

Ground

GND

Ground

KBDVCC

Keyboard
power (.75A)

AUXCLK

Clock for
mouse

USB Headers (J12 and J19)

Table 5-23. USB Headers (J12 and J19) Pin Assignments
Pin

Signal Mnemonic

Signal Description

+5V

Current limited USB power

DATA-

USB serial communications differential pair

DATA+

USB serial communications differential pair

GND

USB Port common

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5-41

Transition/Bridge Modules

SM Bus and LM78 Header (J1)

Table 5-24. SM Bus and LM78 Header (J1)Pin
Assignments

5-42

Signal
Mnemonic

Signal
Description

Signal
Mnemonic

Signal
Description

OPEN-

Chassis
intrusion
signal

GND

Ground

GND

Ground

SMBALERT-

SM bus
interrupt
signal

GND

Ground

SMBDATA

SM bus data
strobe signal

VCC

SM bus
power

SMBCLK

SM bus
clock signal

BYPASS

Power
switch
bypass signal

VCC

SM bus
power

BT1-

Board
temperature
interrupt
signal

GND

Ground

Computer Group Literature Center Web Site

Connectors

Fan Tachometer Headers (J3 and J4)
Refer to the next table for pin assignments and signal descriptions for the
Fan Tachometer headers (J3 and J4) on the CPV5350 Transition Module.

Table 5-25. Fan Tachometer Header (J3 and J4) Pin
Assignments
Pin

Signal Mnemonic

Signal Description

VCC

SM bus power

TACH

Tachometer input for fan

GND

Ground

+12V

12 volt power

Indicator LED/Miscellaneous Header (J2)

Table 5-26. Indicator LED/Miscellaneous Header (J2) Pin
Assignments
Pin

Signal
Mnemonic

Signal Description

Signal
Mnemonic

Signal
Description

VCC

+5V power (limited
to .75A total)

SPEAKER

Speaker
output

VCC

+5V power (limited
to .75A total)

ALARM

Alarm
indicator
LED

http://www.motorola.com/computer/literature

5-43

Transition/Bridge Modules

Table 5-26. Indicator LED/Miscellaneous Header (J2) Pin
Assignments (continued)

5-44

Signal
Mnemonic

Signal Description

Signal
Mnemonic

Signal
Description

VCC

+5V power (limited
to .75A total)

EIDE_LED

Secondary
channel
EIDE
activity LED

VCC

+5V power (limited
to .75A total)

VCC

+5V power (limited
to .75A total)

GND

Ground

PBRESET-

Push button
reset

Computer Group Literature Center Web Site

6Subassembly Reference

Chapter Overview
This chapter provides reference information for the various subassemblies
of the CPX8216 and CPX8216T system. It covers only those items
associated with the system enclosure. For information about CompactPCI
board components, refer to the appropriate chapter in this manual.
The following table lists the system components covered in this chapter:

Table 6-1. System Components
Topic:

Page:

Parts of the System

6-2

CompactPCI Card Cage Reference

6-4

Backplane Reference

6-5

Alarm Display Panel

6-51

Power Distribution Panel

6-54

Power Supplies

6-58

6-1

Subassembly Reference

Parts of the System
Front Peripheral Bay

Alarm Board

SYSTEM
STATUS

SYSTEM
IN SERVICE

COMPONENT
OUT OF SERVICE

TELCO
STATUS

TBD

MINOR

MAJOR

ALARM
CONNECTION

CRITICAL

CompactPCI
Cardcage

16
ESD BONDING
POINT

Cable
Pass-Thru

OUT OF
SERVICE

IN
SERVICE

OUT OF
SERVICE

IN
SERVICE

OUT OF
SERVICE

IN
SERVICE

Power Supplies

Figure 6-1. CPX8216 Front View

6-2

Computer Group Literature Center Web Site

Parts of the System

Floppy Housing

Transition Module Cage

ESD
BONDING
POINT

l
0

Power Distribution Panel

Figure 6-2. CPX8216 Rear View

http://www.motorola.com/computer/literature

6-3

6-4
I/O Slot (Black)

2
3
None
I/O Trns (Black)
I/O Trns (Black)
I/O Trns (Black)

I/O Trns (Black)
I/O Trns (Black)

H.110 Bridge (Tan)
I/O Slot (Black)
I/O Slot (Black)
I/O Slot (Black)
I/O Slot (Black)
I/O Slot (Black)
I/O Slot (Black)

I/O Trns (Black)
I/O Trns (Black)

CPU (Red)
None
I/O Slot (Black)
I/O Slot (Black)

9
10
11
12 13
14
15 16

I/O Slot (Black)

Bridge (Tan)

None

I/O Slot (Black)

CPU Trns (Red)

CPU (Red)

7
I/O Slot (Black)

Bridge (Tan)

I/O Slot (Black)

I/O Trns (Black)

I/O Trns (Black)
CPU Trns (Red)

I/O Slot (Black)

I/O Trns (Black)

8
9
10
11
12 13
14
15 16

I/O Trns (Black)

None

7
CPU Trns (Red)

6
H.110 Bridge (Tan)

CPU Trns (Red)

CPU (Red)

5
CPU (Red)

I/O Trns (Black)

I/O Slot (Black)

4
I/O Trns (Black)

I/O Slot (Black)

I/O Trns (Black)

I/O Slot (Black)

3
I/O Slot (Black)

I/O Slot (Black)

I/O Trns (Black)

I/O Trns (Black)
I/O Trns (Black)

I/O Slot (Black)

I/O Trns (Black)

I/O Slot (Black)

1
I/O Trns (Black)

I/O Trns (Black)

I/O Slot (Black)

Subassembly Reference

CompactPCI Card Cage Reference
Industry standard CompactPCI cardguides are used for the front controller
boards and rear transition boards. The CPU slot is identified with red guide
rails, the I/O slots with black rails, and the Hot Swap Controller/Bridge
slots with tan rails (see Figure 6-3 and Figure 6-4 on page 6-4).
Rear Slots

Backplane

Front Slots

Figure 6-3. Card Cage Rail Color Scheme—CPX8216 Standard System
Rear Slots

Backplane

Figure 6-4. Card Cage Rail Color Scheme—CPX8216T H.110 System
Front Slots

Each slot, both controller and transition, has one ESD cardguide clip and
one ESD alignment pin clip. All clips are located on the bottom cardguide
only.

Computer Group Literature Center Web Site

Backplane Reference

Backplane Reference
The backplane provides the interconnect for all 16-slot, 6U CompactPCI
bus, N+1 power distribution, alarm signal distribution, and IDE device
signal/status distribution.
All sixteen CompactPCI slots accept any standard 6U CompactPCI board
or transition module which meet IEEE 1101.1, IEEE 1101.10, and
IEEE1101.11 specifications. The slots are 64-bit, 33 MHz PCI compliant.
Secondary Side
Alarm, Floppy, IDE
PWR, and SIG Connectors
ALARM

FDA FDB

IDEA IDEB
PWR1

SIG1

PWR2

PWR3

SIG2

SIG3

PWR4

SIG4

PRIMARY SIDE
PS1

PS2

PS3

H.110 BAT
and Ring
Voltages on
Secondary
Side
(CPX8216T
Only)

Figure 6-5. CPX8216 and CPX8216T Backplane—Primary Side

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6-5

Subassembly Reference

Power Supply Connectors (PS1, PS2, PS3)
The three power supply connectors, PS1, PS2, and PS3, are located on the
primary side of the backplane.
Note

The shaded pins are high current pins. Present[n]# is grounded
on the backplane.

Table 6-2. PS1, PS2, and PS3 Pin Assignments

6-6

Signal

GND

Present[n]#

GND

-12Vdc

+3.3Vdc

A_DOUT#

+3.3Vdc

PS[n]_DIN#

+S5Vdc

-12Vdc

-S5Vdc

N/C

+5_Share

N/C

+S3.3Vdc

N/C

-S3.3Vdc

N/C

+3.3_Share

N/C

+12Vdc

+5Vdc

+12Vdc

+5Vdc

+12Vdc

GND

A_CLK

GND

PS[n]_FRAME#

Computer Group Literature Center Web Site

H.110 Power Connector (CPX8216T Only)

Table 6-3. Fan Module Pin Assignments
Pin

Signal

Color

Signal

N/C

+12V_System In

Color

N/C

Grey

+12V_System Out

Brown

+12V_Fan

Red

+12V_Fan_Rtn

Black

Tach

Blue

Speed Ctl

Yellow

N/C

H.110 Power Connector (CPX8216T Only)
H.110 BAT and Ring voltages are supplied to the backplane directly from
the Power Distribution Panel. This section applies to CPX8216T systems
only.

Table 6-4. H.110 Power Connector
Pin

Signal

-Vbat

Vbat RTN

-SELVbat

SELVbat RTN

VRG

VRG RTN

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6-7

Subassembly Reference

Alarm Interface Connector (ALARM)
The alarm interface connector is located on the secondary side of the
backplane. Alarm signals are routed through the backplane to the ALARM
connector. The alarm board attaches to this connector by ribbon cable.

Table 6-5. ALARM Connector Pin Assignments

Signal

ALM_A_CLK

GND

ALM_B_CLK

GND

ALM_A_DOUT#

ALM_A_5V

ALM_B_DOUT#

ALM_B_5V

ALM_A_FRAME#

ALM_B_FRAME#

ALM_A_DIN#

Floppy Drive Connectors (FDA, FDB)
The backplane supports two standard IDE floppy drives. The floppy drive
connectors, FDA and FDB, are located on the secondary side of the
backplane. FDA is controlled by domain A, and FDB is controlled by
domain B.

Table 6-6. FDA and FDB Pin Assignments

6-8

Signal

GND

Not Connected

GND

Not Connected

Key (pin missing)

Not Connected

GND

F_[n]_INDEX#

GND

F_[n]_MTRO#

GND

F_[n]_DS1#

Computer Group Literature Center Web Site

IDE Drive Connectors (IDEA and IDEB)

Table 6-6. FDA and FDB Pin Assignments (continued)
Pin

Signal

GND

F_[n]_DS0#

GND

F_[n]_MTR1#

GND

F_[n]_DIR#

GND

F_[n]_STEP#

GND

F_[n]_WDATA#

GND

F_[n]_WGATE#

GND

F_[n]_TR0#

GND

F_[n]_WPROT#

GND

F_[n]_RDATA#

GND

F_[n]_HDSEL#

GND

F_[n]_DSKCHG#

IDE Drive Connectors (IDEA and IDEB)
The two IDE drive connectors are located on the secondary side of the
backplane. IDEA is controlled by Domain A; IDEB by Domain B.

Table 6-7. IDEA and IDEB Pin Assignments
Pin

Signal

IDE_[n]_RST#

GND

IDE_[n]_D7

IDE_[n]_D8

IDE_[n]_D6

IDE_[n]_D9

IDE_[n]_D5

IDE_[n]_D10

IDE_[n]_D4

IDE_[n]_D11

IDE_[n]_D3

IDE_[n]_D12

IDE_[n]_D2

IDE_[n]_D13

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6-9

Subassembly Reference

Table 6-7. IDEA and IDEB Pin Assignments (continued)

Signal

IDE_[n]_D1

IDE_[n]_D13

IDE_[n]_D0

IDE_[n]_D15

GND

Key (pin missing)

IDE_[n]_DMARQ

GND

IDE_[n]_DIOW#

GND

IDE_[n]_DIOR#

GND

IDE_[n]_IORDY

No Connect

IDE_[n]_DMACK#

GND

IDE_[n]_INTRQ

IDE_[n]_IOCS16#

IDE_[n]_DA1

IDE_[n]_PDIAG#

IDE_[n]_DA0

IDE_[n]_DA2

IDE_[n]_CS1FX#

IDE_[n]_CS3FX#

IDE_[n]_DASP

GND

Peripheral Power Connectors (PWR1, PWR2,
PWR3, PWR4)
The four peripheral power connectors are located on the secondary side of
the CPX8216 backplane. All four connectors have the same pin-out and
can be used interchangeably.

Table 6-8. PWR1, PWR2, PWR3, PWR4 Pin Assignments

6-10

Signal

+5 Volts

Ground

Computer Group Literature Center Web Site

Peripheral Signal Connectors (SIG1, SIG2, SIG3, SIG4)

Table 6-8. PWR1, PWR2, PWR3, PWR4 Pin Assignments
Pin

Signal

Ground

+12 Volts

Peripheral Signal Connectors (SIG1, SIG2,
SIG3, SIG4)
The four peripheral signal connectors are located on the secondary side of
the CPX8216 backplane. All four connectors have the same pin-out. The
connectors map to different locations in the Hot Swap Controller
peripheral registers, and cannot be used interchangeably.

Table 6-9. SIG1, SIG2, SIG3, SIG4 Pin Assignments
Pin

Signal

Per[n]_Pwr_ON#

Per[n]_LED1#

Per[n]_LED2#

Per[n]_PSNT_A#

Per[n]_PSNT_B#

CompactPCI Connectors (P1, P2, P3, P4, P5)—
CPX8216 Standard Backplane
Primary (Front) Side I/O Connectors (Slots 1-6 and 11-16)
In the front I/O slots (system slots 1-6 and 11-16), connectors P3, P4, and
P5 are reserved for user I/O.

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6-11

Subassembly Reference

Connectors P1 and P2 carry the CompactPCI bus (bus A for slots 1-6, bus
B for slots 11-16).

Table 6-10. P5 Connector, I/O Slots 1-6 and 11-16
(User I/O)
POS

Row Z

Row A

Row B

Row C

Row D

Row E

Row F

22-1

GND

I/O

GND

All I/O pins pass through the backplane to the transition module, they do not make any connection
to the backplane.

Table 6-11. P4 Connector, I/O Slots 1-6 and 11-16 (User I/O)
POS

Row Z

Row A

Row B

Row C

Row D

Row E

Row F

25-15

GND

I/O

GND

I/O

GND

14
13

KEY AREA

12
11-1

GND

I/O

All I/O pins pass through the backplane to the transition module, they do not make any connection
to the backplane.

Table 6-12. P3 Connector, I/O Slots 1-6 and 11-16 (User I/O)
POS

Row Z

Row A

Row B

Row C

Row D

Row E

Row F

19-1

GND

I/O

GND

All I/O pins pass through the backplane to the transition module, they do not make any connection
to the backplane.

6-12

Computer Group Literature Center Web Site

Primary (Front) Side I/O Connectors (Slots 1-6 and 11-16)

Table 6-13. P2 Connector, I/O Slots 1-6 and 11-16 (CPCI Bus)
POS

Row
Z

Row A

Row B

Row C

Row D

Row E

Row
F

GND

GA4

GA3

GA2

GA1

GA0

GND

RSV

GND

RSV

GND

RSV

GND

RSV

GND

_BRSVP2
A18

_BRSVP2B
18

_BRSVP2
C18

GND

_BRSVP2E18

GND

_BRSVP2
A17

GND

_BRSVP2
A16

_BRSVP2B
16

GND

_BRSVP2
A15

GND

_AD[35]

_AD[34]

_AD[33]

GND

_AD[32]

GND

_AD[38]

GND

VIO

_AD[37]

_AD[36]

GND

_AD[42]

_AD[41]

_AD[40]

GND

_AD[39]

GND

_AD[45]

GND

VIO

_AD[44]

_AD[43]

GND

_AD[49]

_AD[48]

_AD[47]

GND

_AD[46]

GND

_AD[52]

GND

VIO

_AD[51]

_AD[50]

GND

_AD[56]

_AD[55]

_AD[54]

GND

_AD[53]

GND

_AD[59]

GND

VIO

_AD[58]

_AD[57]

GND

GND
_BRSVP2E16

GND
GND

Signals beginning with an underscore (_) are prefixed with the bus name:
*For boards located in slots 1-6 (Domain A), the signal name is prefixed with PCI_A (for
example, PCI_A_AD[49]).
*For boards located in slots 11-16 (Domain B), the signal name is prefixed with PCI_B (for
example, PCI_B_AD[49]).
Signals RSV are not connected.
Signals beginning with _BRSV are bussed, but not used.

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6-13

Subassembly Reference

Table 6-13. P2 Connector, I/O Slots 1-6 and 11-16 (CPCI Bus)

POS

Row
Z

Row A

Row B

Row C

Row D

Row E

Row
F

GND

_AD[63]

_AD[62]

_AD[61]

GND

_AD[60]

GND

_C/BE[5]#

GND

VIO

C/BE[4]#

_PAR64

GND

VIO

_BRSVP2B
4

_C/BE[7]#

GND

_C/BE[6]

GND

GND
GND

GND

Table 6-14. P1 Connector, I/O Slots 1-6 and 11-16 (CPCI Bus)
POS

Row
Z

Row A

Row B

Row C

Row D

Row E

Row
F

GND

_REQ64#

A_ENUM#

3.3V

GND

_AD[1]

VIO

_AD[0]

_ACK64#

GND

6-14

Computer Group Literature Center Web Site

Primary (Front) Side I/O Connectors (Slots 1-6 and 11-16)

Table 6-14. P1 Connector, I/O Slots 1-6 and 11-16 (CPCI Bus)
POS

Row
Z

Row A

Row B

Row C

Row D

Row E

Row
F

GND

3.3V

_AD[4]

_AD[3]

_AD[2]

GND

_AD[7]

GND

3.3V

_AD[6]

_AD[5]

GND

3.3V

_AD[9]

_AD[8]

_M66EN

_C/BE[0]#

GND

_AD[12]

GND

VIO

_AD[11]

_AD[10]

GND

3.3V

_AD[15]

_AD[14]

GND

_AD[13]

GND

_SERR#

GND

3.3V

_PAR

_C/BE[1]

GND

3.3V

_SDONE

_SBO#

GND

_PERR#

GND

_DEVSEL#

GND

VIO

_STOP#

_LOCK#

GND

3.3V

_FRAME#

_IRDY#

BD_SEL[n]#

_TRDY#

GND

1412

KEY AREA

GND

_AD[18}

_AD[17]

_AD[16]

GND

_C/BE[2]#

GND

_AD[21]

GND

3.3V

_AD[20]

_AD[19]

GND

_C/BE[3]

_IDSEL

_AD[23]

GND

_AD[22]

GND

_AD[26]

GND

VIO

_AD[25]

_AD[24]

GND

_AD[30]

_AD[29]

_AD[28]

GND

_AD[27]

GND

REQ[N]#

GND

3.3V

CLK[N]

_AD[31]

GND

_BRSVP1A
5

_BRSVP1B
5

RST[N]#

GND

GNT[N]#

GND

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6-15

Subassembly Reference

Table 6-14. P1 Connector, I/O Slots 1-6 and 11-16 (CPCI Bus)
POS

Row
Z

Row A

Row B

Row C

Row D

Row E

Row
F

GND

_BRSVP1A
4

HLTY[N]#

VIO

_INTP

_INTS

GND

_INTA#

_INTB#

_INTC#

_INTD#

GND

TCK

TMS

TDO

TDI

GND

-12V

TRST#

+12V

GND

Signals beginning with an underscore (_) are prefixed with the bus name:

*For boards located in slots 1-6 (Domain A), the signal name is prefixed with PCI_A (for
example, PCI_A_AD[49]).
*For boards located in slots 11-16 (Domain B), the signal name is prefixed with PCI_B (for
example, PCI_B_AD[49]).
Signals RSV are not connected.
Signals beginning with _BRSV are bussed, but not used.
Signal A_ENUM# in Domain A (slots 1-6), B_ENUM# in Domain B (Slots 11-16).

6-16

Computer Group Literature Center Web Site

Primary (Front) Side CPU Slot Connectors (7 and 9)

Table 6-15. P5 Connector, CPU Slots 7 and 9
POS

Row
Z

Row A

Row B

Row C

Row D

Row E

Row
F

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

_TR0#

_WPROT#

_RDATA#

_HDSEL#

_DSKCHG
#

GND

_MTR1#

_DIR#

_STEP#

_WDATA#

_WGATE#

GND

_RSV1#

_INDEX#

_MTR0#

_DS1#

A_DS0#

GND

_CS1FX#

_CS3FX#

_DA1

_DASP#

_RSV0#

GND

Signals in bold text are prefixed with IDE_A if the board resides in slot 7 or IDE_B if the board
resides in slot 9.
Signals in shaded cells are prefixed with F_A if the board resides in slot 7 or F_B if the board
resides in slot 9.
All I/O pins pass through the backplane to the transition module; they do not make any connection
to the backplane.

http://www.motorola.com/computer/literature

6-17

Subassembly Reference

Table 6-15. P5 Connector, CPU Slots 7 and 9 (continued)

POS

Row
Z

Row A

Row B

Row C

Row D

Row E

Row
F

GND

_IOCS16#

I/O

_PDIAG#

_DA0

_DA2

GND

_DMARQ

_IORDY

_DIOW#

_DMACK#

_DIOR#

GND

_D14

_D0

I/O

_D15

_INTRQ

GND

_D3

_D12

_D2

_D13

_D1

GND

_D9

_D5

_D10

_D4

_D11

GND

I/O

_RST#

_D7

_D8

_D6

GND

Table 6-16. P4 Connector, CPU Slots 7 and 9
POS

Row Z

Row A

Row B

Row C

Row D

Row E

Row F

GND

_AD36

_AD35

_AD34

_AD33

_AD32

GND

_AD40

_AD39

_AD38

GND

_AD37

GND

_AD45

_AD44

_AD43

_AD42

_AD41

GND

_AD49

_+3.3

_AD48

_AD47

_AD46

GND

_AD53

_AD52

_AD51

GND

_AD50

GND

The _+5 and _+3 in the shaded cells are provided by the CPU board; they are not connected to the
system power plane. These signals are prefixed with CPUA if the board resides in slot 7 or CPU
B if the board resides in slot 8 (for example, CPUA_+5).
Signals beginning with an underscore (_) are prefixed with the local PCI bus name:
*For boards located in slot 7 (Domain A), the signal name is prefixed with L_PCI_A (for example,
L_PCI_A_AD17).
*For boards located in slot 9 (Domain B), the signal name is prefixed with L_PCI_B (for example,
L_PCI_B_AD17).

6-18

Computer Group Literature Center Web Site

Primary (Front) Side CPU Slot Connectors (7 and 9)

Table 6-16. P4 Connector, CPU Slots 7 and 9 (continued)
POS

Row Z

Row A

Row B

Row C

Row D

Row E

Row F

GND

_AD57

_+3.3

_AD56

_AD55

_AD54

GND

_AD61

_AD60

_AD59

GND

_AD58

GND

_CBE4#

_+3.3

_PAR64

_AD63

_AD62

GND

_REQ64#

_CBE7#

_CBE6#

GND

_CBE5#

GND

_AD2

_+3.3

_AD1

_AD0

_ACK64#

GND

_AD6

_AD5

_AD4

GND

_AD3

GND

1412

KEY AREA

GND

_AD9

_AD8

_CBE0#

GND

_AD7

GND

_AD13

_+5

_AD12

_AD11

_AD10

GND

_PAR

_CBE1#

_AD15

GND

_AD14

GND

_STOP#

_+5

_LOCK#

_PERR#

_SERR#

GND

_FRAME#

_IRDY#

_TRDY#

GND

_DEVSEL
#

GND

_AD18

_+5

_AD17

_AD16

CBE2#

GND

_AD21

_CLK

_AD20

GND

_AD19

GND

_CBE3#

_+5

_IDSEL

_AD23

_AD22

GND

_AD28

_AD27

_AD26

_AD25

_AD24

GND

_GNT#

_REQ#

_AD31

_AD30

_AD29

GND

_INTA#

_INTB#

_INTC#

_INTD#

_RST#

GND

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6-19

Subassembly Reference

Table 6-17. P3 Connector, CPU Slots 7 and 9

POS

Row Z

Row A

Row B

Row C

Row D

Row E

Row F

GND

I/O

GND

HS_REQ_

I/O

GND

HS_GNT_

I/O

GND

HS_FLT_

I/O

GND

HS_EJ_

I/O

GND

14-1

GND

I/O

GND

All I/O pins pass through the backplane to the transition module; they do not make any
connection to the backplane.
If the CPU is mounted in slot 7, the HS signals will end with A (for example, HS_REQ_A).
If the CPU is mounted in slot 9, the HS signals will end with B (for example, HS_REQ_B).

Table 6-18. P2 Connector, CPU Slot 7 (Domain A)
POS

Row Z

Row A

Row B

Row C

Row D

Row E

Row F

GND

GA4

GA3

GA2

GA1

GA0

GND

CLK6

GND

RSV

GND

CLK5

GND

RSV

GND

RSV

GND

RSV

GND

_BRSVP2
A18

_BRSVP2
B18

_BRSVP2
C18

GND

_BRSVP2
E18

GND

_BRSVP2
A17

GND

_PRST#

_REQ6#

GNT6#

GND

_BRSVP2
A16

_BRSVP2
B16

_DEG#

GND

_BRSVP2
E16

GND

Signals beginning with an underscore (_) are prefixed with the bus name PCI_A (for example,
PCI_A_AD[49]).
Signals RSV are not connected.
Signals beginning with _BRSV are bussed, but not used.

6-20

Computer Group Literature Center Web Site

Primary (Front) Side CPU Slot Connectors (7 and 9)

Table 6-18. P2 Connector, CPU Slot 7 (Domain A) (continued)
POS

Row Z

Row A

Row B

Row C

Row D

Row E

Row F

GND

_BRSVP2
A15

GND

_FAL#

REQ5#

GNT5#

GND

_AD[35]

_AD[34]

_AD[33]

GND

_AD[32]

GND

_AD[38]

GND

VIO

_AD[37]

_AD[36]

GND

_AD[42]

_AD[41]

_AD[40]

GND

_AD[39]

GND

_AD[45]

GND

VIO

_AD[44]

_AD[43]

GND

_AD[49]

_AD[48]

_AD[47]

GND

_AD[46]

GND

_AD[52]

GND

VIO

_AD[51]

_AD[50]

GND

_AD[56]

_AD[55]

_AD[54]

GND

_AD[53]

GND

_AD[59]

GND

VIO

_AD[58]

_AD[57]

GND

_AD[63]

_AD[62]

_AD[61]

GND

_AD[60]

GND

_C/BE[5]#

GND

VIO

C/BE[4]#

_PAR64

GND

VIO

_BRSVP2
B4

_C/BE[7]#

GND

_C/BE[6]

GND

CLK4

GND

GNT3#

REQ4#

GNT4#

GND

CLK2

CLK3

_SYSEN#

GNT2#

REQ3#

GND

CLK1

GND

REQ1#

GNT1#

REQ2#

GND

Signals beginning with an underscore (_) are prefixed with the bus name PCI_A (for example,
PCI_A_AD[49]).
Signals RSV are not connected.
Signals beginning with _BRSV are bussed, but not used.

http://www.motorola.com/computer/literature

6-21

Subassembly Reference

Table 6-19. P2 Connector, CPU Slot 9 (Domain B)

POS

Row Z

Row A

Row B

Row C

Row D

Row E

Row F

GND

GA4

GA3

GA2

GA1

GA0

GND

CLK16

GND

RSV

GND

CLK15

GND

RSV

GND

RSV

GND

RSV

GND

_BRSVP2
A18

_BRSVP2
B18

_BRSVP2
C18

GND

_BRSVP2
E18

GND

_BRSVP2
A17

GND

_PRST#

_REQ16#

GNT16#

GND

_BRSVP2
A16

_BRSVP2
B16

_DEG#

GND

_BRSVP2
E16

GND

_BRSVP2
A15

GND

_FAL#

REQ15#

GNT15#

GND

_AD[35]

_AD[34]

_AD[33]

GND

_AD[32]

GND

_AD[38]

GND

VIO

_AD[37]

_AD[36]

GND

_AD[42]

_AD[41]

_AD[40]

GND

_AD[39]

GND

_AD[45]

GND

VIO

_AD[44]

_AD[43]

GND

_AD[49]

_AD[48]

_AD[47]

GND

_AD[46]

GND

_AD[52]

GND

VIO

_AD[51]

_AD[50]

GND

_AD[56]

_AD[55]

_AD[54]

GND

_AD[53]

GND

_AD[59]

GND

VIO

_AD[58]

_AD[57]

GND

_AD[63]

_AD[62]

_AD[61]

GND

_AD[60]

GND

_C/BE[5]#

GND

VIO

C/BE[4]#

_PAR64

GND

VIO

_BRSVP2
B4

_C/BE[7]#

GND

_C/BE[6]

GND

Signals beginning with an underscore (_) are prefixed with the bus name PCI_B (for example,
PCI_B_AD[49]).
Signals RSV are not connected.
Signals beginning with _BRSV are bussed, but not used.

6-22

Computer Group Literature Center Web Site

Primary (Front) Side CPU Slot Connectors (7 and 9)

Table 6-19. P2 Connector, CPU Slot 9 (Domain B) (continued)
POS

Row Z

Row A

Row B

Row C

Row D

Row E

Row F

GND

CLK14

GND

GNT13#

REQ14#

GNT14#

GND

CLK12

CLK13

_SYSEN#

GNT12#

REQ13#

GND

CLK11

GND

REQ11#

GNT11#

REQ12#

GND

Signals beginning with an underscore (_) are prefixed with the bus name PCI_B (for example,
PCI_B_AD[49]).
Signals RSV are not connected.
Signals beginning with _BRSV are bussed, but not used.

6
Table 6-20. P1 Connector, CPU Slots 7 and 9
POS

Row Z

Row A

Row B

Row C

Row D

Row E

Row F

GND

_REQ64
#

A_ENU
M#

3.3V

GND

_AD[1]

VIO

_AD[0]

_ACK64
#

GND

3.3V

_AD[4]

_AD[3]

_AD[2]

GND

_AD[7]

GND

3.3V

_AD[6]

_AD[5]

GND

3.3V

_AD[9]

_AD[8]

_M66EN

_C/BE[0]
#

GND

_AD[12]

GND

VIO

_AD[11]

_AD[10]

GND

3.3V

_AD[15]

_AD[14]

GND

_AD[13]

GND

Signals beginning with an underscore (_) are prefixed with the bus name:
*For boards located in slot 7 (Domain A), the signal name is prefixed with PCI_A (for example,
PCI_A_AD[49]).
*For boards located in slot 9 (Domain B), the signal name is prefixed with PCI_B (for example,
PCI_B_AD[49]).
Shaded cell A_ENUM# applies to Domain A; Domain B signal B_ENUM#.
Signals RSV are not connected.
Signals beginning with _BRSV are bussed, but not used.
Signals enclosed in parentheses () are not used

http://www.motorola.com/computer/literature

6-23

Subassembly Reference

Table 6-20. P1 Connector, CPU Slots 7 and 9 (continued)

POS

Row Z

Row A

Row B

Row C

Row D

Row E

Row F

GND

_SERR#

GND

3.3V

_PAR

_C/BE[1]

GND

3.3V

_SDONE

_SBO#

GND

_PERR#

GND

_DEVSE
L#

GND

VIO

_STOP#

_LOCK#

GND

3.3V

_FRAME
#

_IRDY#

BD_SEL
[n]#

_TRDY#

GND

14-12

KEY AREA

GND

_AD[18}

_AD[17]

_AD[16]

GND

_C/BE[2]
#

GND

_AD[21]

GND

3.3V

_AD[20]

_AD[19]

GND

_C/BE[3]

_IDSEL

_AD[23]

GND

_AD[22]

GND

_AD[26]

GND

VIO

_AD[25]

_AD[24]

GND

_AD[30]

_AD[29]

_AD[28]

GND

_AD[27]

GND

(REQ#)

GND

3.3V

(CLK)

_AD[31]

GND

_BRSVP
1A5

_BRSVP
1B5

RST[N]#

GND

(GNT#)

GND

_BRSVP
1A4

HLTY[N]
#

VIO

_INTP

_INTS

GND

_INTA#

_INTB#

_INTC#

_INTD#

GND

6-24

Computer Group Literature Center Web Site

Primary (Front) Side CPU Slot Connectors (7 and 9)

Table 6-20. P1 Connector, CPU Slots 7 and 9 (continued)
POS

Row Z

Row A

Row B

Row C

Row D

Row E

Row F

GND

TCK

TMS

TDO

TDI

GND

-12V

TRST#

+12V

GND

Signals RSV are not connected.
Signals beginning with _BRSV are bussed, but not used.
Signals enclosed in parentheses () are not used

http://www.motorola.com/computer/literature

6-25

Subassembly Reference

Secondary (Rear) Side I/O Connectors
Note

I/O slot connectors P2 and P1 do not connect through to the
transition module.

Table 6-21. P5 Connector, I/O Slots 1-6 and 11-16 (User
I/O)
POS

Row Z

Row A

Row B

Row C

Row D

Row E

Row F

22-1

GND

I/O

GND

All I/O pins pass through the backplane to the transition module, they do not
make any connection to the backplane.

Table 6-22. P4 Connector, I/O Slots 1-6 and 11-16 (User
I/O)
POS

Row Z

Row A

Row B

Row C

Row D

Row E

Row F

25-15

GND

I/O

GND

I/O

GND

14
13

KEY AREA

12
11-1

GND

I/O

All I/O pins pass through the backplane to the transition module, they do not
make any connection to the backplane.

Table 6-23. P3 Connector, I/O Slots 1-6 and 11-16 (User
I/O)
POS

Row Z

Row A

Row B

Row C

Row D

Row E

Row F

19-1

GND

I/O

GND

All I/O pins pass through the backplane to the transition module, they do not
make any connection to the backplane.

6-26

Computer Group Literature Center Web Site

CPU Transition Module Connectors (Transition Slots 7 and 9)

CPU Transition Module Connectors
(Transition Slots 7 and 9)
Note

CPU transition module connectors P4, P2, and P1 are not
connected.

Table 6-24. P5 Connector, CPU Transition Module Slots
POS

Row
Z

Row A

Row B

Row C

Row D

Row E

Row
F

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

RSVD

GND

RSVD

GND

RSVD

GND

RSVD

GND

All I/O pins pass through the backplane; they do not make any connection to the
backplane.
All RSVD pins are internally connected and pass through. They are reserved for
the IDE and Floppy drive signals; the transition module should avoid
connections to these pins.

http://www.motorola.com/computer/literature

6-27

Subassembly Reference

Table 6-24. P5 Connector, CPU Transition Module Slots

POS

Row
Z

Row A

Row B

Row C

Row D

Row E

Row
F

GND

RSVD

I/O

RSVD

GND

RSVD

GND

RSVD

I/O

RSVD

GND

RSVD

GND

RSVD

GND

I/O

RSVD

GND

Table 6-25. P3 Connector, CPU Transition Slots 7 and 9
POS

Row
Z

Row A

Row
B

Row
C

Row
D

Row
E

Row
F

GND

I/O

GND

RSVD

I/O

GND

RSVD

I/O

GND

RSVD

I/O

GND

RSVD

I/O

GND

14-1

GND

I/O

GND

All I/O pins pass through the backplane, they do not make any connection to the
backplane.
All RSVD pins are internally connected and pass through. They are reserved for
the IDE and Floppy drive signals; the transition module should avoid
connections to these pins.

6-28

Computer Group Literature Center Web Site

Hot Swap Controller/Bridge Connectors (Transition Slots 8 and 10)

Hot Swap Controller/Bridge Connectors
(Transition Slots 8 and 10)
The Hot Swap Controller/Bridge for Domain A resides in transition
module slot 10. The Hot Swap Controller/Bridge for Domain B resides in
transition module slot 8.

Table 6-26. P5 Connector, HSC/Bridge (Slots 8 and 10)
POS

Row Z

Row A

Row B

Row C

Row D

Row E

Row F

22-1

GND

RSVD

GND

Connector P5 is reserved for future use.

Table 6-27. P4 Connector, HSC/Bridge (Slots 8 and 10)
POS

Row
Z

Row A

Row B

Row C

Row D

Row E

Row
F

GND

_AD36

_AD35

_AD34

_AD33

_AD32

GND

_AD40

_AD39

_AD38

_GND

_AD37

GND

_AD45

_AD44

_AD43

_AD42

_AD41

GND

_AD49

_+3.3

_AD48

_AD47

_AD46

GND

_AD53

_AD52

_AD51

_GND

_AD50

GND

_AD57

_+3.3

_AD56

_AD55

_AD54

GND

_AD61

_AD60

_AD59

_GND

_AD58

GND

_CBE4#

_+3.3

_PAR64

_AD63

_AD62

GND

The _GND, _+5 and _+3 in the shaded cells are provided by the CPU board; they are not
connected to the system power plane. These signals are prefixed with CPUA if the board resides
in slot 10 or CPUB if the board resides in slot 8 (for example, CPUA_+5).
Unshaded signals beginning with an underscore (_) are prefixed with the local PCI bus name:
*For boards located in slot 10 (Domain A), the signal name is prefixed with L_PCI_A (for
example, L_PCI_A_AD17).
*For boards located in slot 8 (Domain B), the signal name is prefixed with L_PCI_B (for
example, L_PCI_B_AD17).

http://www.motorola.com/computer/literature

6-29

Subassembly Reference

Table 6-27. P4 Connector, HSC/Bridge (Slots 8 and 10) (continued)

POS

Row
Z

Row A

Row B

Row C

Row D

Row E

Row
F

GND

_REQ64#

_CBE7#

_CBE6#

_GND

_CBE5#

GND

_AD2

_+3.3

_AD1

_AD0

_ACK64#

GND

_AD6

_AD5

_AD4

_GND

_AD3

GND

14-12

KEY AREA

GND

_AD9

_AD8

_CBE0#

_GND

_AD7

GND

_AD13

_+5

_AD12

_AD11

_AD10

GND

_PAR

_CBE1#

_AD15

_GND

_AD14

GND

_STOP#

_+5

_LOCK#

_PERR#

_SERR#

GND

_FRAME#

_IRDY#

_TRDY#

_GND

_DEVSEL
#

GND

_AD18

_+5

_AD17

_AD16

CBE2#

GND

_AD21

_CLK

_AD20

_GND

_AD19

GND

_CBE3#

_+5

_IDSEL

_AD23

_AD22

GND

_AD28

_AD27

_AD26

_AD25

_AD24

GND

_GNT#

_REQ#

_AD31

_AD30

_AD29

GND

_INTA#

_INTB#

_INTC#

_INTD#

_RST#

GND

6-30

Computer Group Literature Center Web Site

Hot Swap Controller/Bridge Connectors (Transition Slots 8 and 10)

Table 6-28. P3 Connector, HSC Slots 8 and 10
POS

Row Z

Row A

Row B

Row C

Row D

Row E

Row F

GND

A/B#

ALM_B_5
V

INT_HSC_
2

Per3_Pwr_
ON#

Per1_Pwr_
ON#

GND

HS_REQ_
B

HS_REQ_
A

INT_HSC_
1

Per3_LED1
#

Per1_LED1
#

GND

HS_GNT_
B

HS_GNT_
A

INT_HSC_
4

Per3_LED2
#

Per1_LED2
#

GND

HS_FLT_B

HS_FLT_A

INT_HSC_
3

Per3_PSN
T_B#

Per1_PSN
T_B#

GND

HS_EJ_B

HS_EJ_A

INT_HSC_
6

Per4_Pwr_
ON#

Per2_Pwr_
ON#

GND

INT_HSC_
8

INT_HSC_
7

INT_HSC_
5

Per4_LED1
#

Per2_LED1
#

GND

A_CLK

A_DOUT#

PS_1_DIN
#

Per4_LED2
#

Per2_LED2
#

GND

B_CLK

B_DOUT#

PS_2_DIN
#

Per4_PSN
T_B#

Per2_PSN
T_B#

GND

ALM_A_F
RAME#

PS_1_FRA
ME#

PS_3_DIN
#

ALM_A_D
IN#

GND

ALM_B_F
RAME#

PS_2_FRA
ME#

PS_3_FRA
ME#

GND

RST3#

RST6#

HLTY10#

GND

RST2#

RST5#

GND

RST1#

GND

BD_SEL6#

GND
B_ENUM#

GND

RST16#

RST13#

GND

HLTY9#

RST15#

RST12#

GND

RST4#

HLTY8#

RST14#

RST11#

GND

HLTY6#

HLTY7#

HLTY16#

BD_SEL16
#

GND

A/B# GND Domain B (slot 8).
ALM_B_5V in Domain B (slot 8); ALM_A_5V in Domain A (slot 10).
B_ENUM# in Domain B (slot 8); A_ENUM in Domain A (slot 10).
BD_SEL7# in Domain B, BD_SEL9# in Domain A.

http://www.motorola.com/computer/literature

6-31

Subassembly Reference

Table 6-28. P3 Connector, HSC Slots 8 and 10 (continued)
POS

Row Z

Row A

Row B

Row C

Row D

Row E

Row F

GND

BD_SEL5#

HLTY5#

BD_SEL7#

HLTY15#

BD_SEL15
#

GND

BD_SEL4#

HLTY4#

RST10#

HLTY14#

BD_SEL14
#

GND

BD_SEL3#

HLTY3#

RST9#

HLTY13#

BD_SEL13
#

GND

BD_SEL2#

HLTY2#

RST8#

HLTY12#

BD_SEL12
#

GND

BD_SEL1#

HLTY1#

RST7#

HLTY11#

BD_SEL11
#

GND

6
A/B# GND Domain B (slot 8).
ALM_B_5V in Domain B (slot 8); ALM_A_5V in Domain A (slot 10).
B_ENUM# in Domain B (slot 8); A_ENUM in Domain A (slot 10).
BD_SEL7# in Domain B, BD_SEL9# in Domain A.

Table 6-29. P2 Connector, HSC Slot 10
POS

Row Z

Row A

Row B

Row C

Row D

Row E

Row F

GND

GA4

GA3

GA2

GA1

GA0

GND

CLK6

GND

RSV

GND

CLK5

GND

RSV

GND

RSV

GND

RSV

GND

_BRSVP2
A18

_BRSVP2
B18

_BRSVP2
C18

GND

_BRSVP2
E18

GND

_BRSVP2
A17

GND

(_PRST#)

_REQ6#

GNT6#

GND

Signals beginning with an underscore (_) are prefixed with the bus name PCI_B (for example,
PCI_B_AD[49]).
Signals in parentheses are not used.

6-32

Computer Group Literature Center Web Site

Hot Swap Controller/Bridge Connectors (Transition Slots 8 and 10)

Table 6-29. P2 Connector, HSC Slot 10 (continued)
POS

Row Z

Row A

Row B

Row C

Row D

Row E

Row F

GND

_BRSVP2
A16

_BRSVP2
B16

(_DEG#)

GND

_BRSVP2
E16

GND

_BRSVP2
A15

GND

(_FAL#)

REQ5#

GNT5#

GND

_AD[35]

_AD[34]

_AD[33]

GND

_AD[32]

GND

_AD[38]

GND

VIO

_AD[37]

_AD[36]

GND

_AD[42]

_AD[41]

_AD[40]

GND

_AD[39]

GND

_AD[45]

GND

VIO

_AD[44]

_AD[43]

GND

_AD[49]

_AD[48]

_AD[47]

GND

_AD[46]

GND

_AD[52]

GND

VIO

_AD[51]

_AD[50]

GND

_AD[56]

_AD[55]

_AD[54]

GND

_AD[53]

GND

_AD[59]

GND

VIO

_AD[58]

_AD[57]

GND

_AD[63]

_AD[62]

_AD[61]

GND

_AD[60]

GND

_C/BE[5]#

GND

VIO

C/BE[4]#

_PAR64

GND

VIO

_BRSVP2
B4

_C/BE[7]#

GND

_C/BE[6]

GND

CLK4

GND

GNT3#

REQ4#

GNT4#

GND

CLK2

CLK3

_SYSEN#

GNT2#

REQ3#

GND

CLK1

GND

REQ1#

GNT1#

REQ2#

GND

Signals beginning with an underscore (_) are prefixed with the bus name PCI_B (for example,
PCI_B_AD[49]).
Signals in parentheses are not used.

http://www.motorola.com/computer/literature

6-33

Subassembly Reference

Table 6-30. P2 Connector, HSC Slot 8

POS

Row Z

Row A

Row B

Row C

Row D

Row E

Row F

GND

GA4

GA3

GA2

GA1

GA0

GND

CLK16

GND

RSV

GND

CLK15

GND

RSV

GND

RSV

GND

RSV

GND

_BRSVP2
A18

_BRSVP2
B18

_BRSVP2
C18

GND

_BRSVP2
E18

GND

_BRSVP2
A17

GND

(_PRST#)

_REQ16#

GNT16#

GND

_BRSVP2
A16

_BRSVP2
B16

(_DEG#)

GND

_BRSVP2
E16

GND

_BRSVP2
A15

GND

(_FAL#)

REQ15#

GNT15#

GND

_AD[35]

_AD[34]

_AD[33]

GND

_AD[32]

GND

_AD[38]

GND

VIO

_AD[37]

_AD[36]

GND

_AD[42]

_AD[41]

_AD[40]

GND

_AD[39]

GND

_AD[45]

GND

VIO

_AD[44]

_AD[43]

GND

_AD[49]

_AD[48]

_AD[47]

GND

_AD[46]

GND

_AD[52]

GND

VIO

_AD[51]

_AD[50]

GND

_AD[56]

_AD[55]

_AD[54]

GND

_AD[53]

GND

_AD[59]

GND

VIO

_AD[58]

_AD[57]

GND

_AD[63]

_AD[62]

_AD[61]

GND

_AD[60]

GND

_C/BE[5]#

GND

VIO

C/BE[4]#

_PAR64

GND

VIO

_BRSVP2
B4

_C/BE[7]#

GND

_C/BE[6]

GND

CLK14

GND

GNT13#

REQ14#

GNT14#

GND

Signals beginning with an underscore (_) are prefixed with the bus name PCI_A (for example,
PCI_A_AD[49]).
Signals in parentheses are not used.

6-34

Computer Group Literature Center Web Site

Hot Swap Controller/Bridge Connectors (Transition Slots 8 and 10)

Table 6-30. P2 Connector, HSC Slot 8 (continued)
POS

Row Z

Row A

Row B

Row C

Row D

Row E

Row F

GND

CLK12

CLK13

_SYSEN#

GNT12#

REQ13#

GND

CLK11

GND

REQ11#

GNT11#

REQ12#

GND

Signals beginning with an underscore (_) are prefixed with the bus name PCI_A (for example,
PCI_A_AD[49]).
Signals in parentheses are not used.

Table 6-31. P1 Connector, HSC Slots 8 and 10
POS

Row Z

Row A

Row B

Row C

Row D

Row E

Row F

GND

_REQ64#

A_ENUM#

3.3V

GND

_AD[1]

VIO

_AD[0]

_ACK64#

GND

3.3V

_AD[4]

_AD[3]

_AD[2]

GND

_AD[7]

GND

3.3V

_AD[6]

_AD[5]

GND

3.3V

_AD[9]

_AD[8]

_M66EN

_C/BE[0]#

GND

_AD[12]

GND

VIO

_AD[11]

_AD[10]

GND

3.3V

_AD[15]

_AD[14]

GND

_AD[13]

GND

_SERR#

GND

3.3V

_PAR

_C/BE[1]

GND

3.3V

_SDONE

_SBO#

GND

_PERR#

GND

_DEVSEL
#

GND

VIO

_STOP#

_LOCK#

GND

3.3V

_FRAME#

_IRDY#

BD_SEL[n
]#

_TRDY#

GND

1412

KEY AREA

GND

_AD[18}

_AD[17]

_AD[16]

GND

_C/BE[2]#

GND

_AD[21]

GND

3.3V

_AD[20]

_AD[19]

GND

_C/BE[3]

_IDSEL

_AD[23]

GND

_AD[22]

GND

A_ENUM# in Domain A (slot 10); B_ENUM# in Domain B (slot 8).

http://www.motorola.com/computer/literature

6-35

Subassembly Reference

Table 6-31. P1 Connector, HSC Slots 8 and 10 (continued)

POS

Row Z

Row A

Row B

Row C

Row D

Row E

Row F

GND

_AD[26]

GND

VIO

_AD[25]

_AD[24]

GND

_AD[30]

_AD[29]

_AD[28]

GND

_AD[27]

GND

REQ[N]#

GND

3.3V

CLK[N]

_AD[31]

GND

_BRSVP1
A5

_BRSVP1
B5

RST[N]#

GND

GNT[N]#

GND

_BRSVP1
A4

HLTY[N]#

VIO

_INTP

_INTS

GND

_INTA#

_INTB#

_INTC#

_INTD#

GND

TCK

TMS

TDO

TDI

GND

-12V

TRST#

+12V

GND

A_ENUM# in Domain A (slot 10); B_ENUM# in Domain B (slot 8).

6-36

Computer Group Literature Center Web Site

H.110 Bus Connectors—CPX8216T System Only

H.110 Bus Connectors—CPX8216T System
Only
On each domain, the H.110 bus passes through connector P4 across the I/O
and HSC slots. It does not connect to the CPU slot (see Figure 6-6).

H. 110 Bus

P2
CompactPCI Bus

System Slot
HSC Slot
2557 9906

Figure 6-6. The CPX8216T H.110 Bus

http://www.motorola.com/computer/literature

6-37

Subassembly Reference

Primary (Front) Side I/O Connectors
The tables in the next few sections provide pin assignments for all I/O,
HSC and CPU slots. For further connector pinouts, refer to the table below.
Pinout Information for See:
Connector:

Table 6-10 on page 6-12

Table 6-32 on page 6-38

Table 6-12 on page 6-12

Table 6-13 on page 6-13

Table 6-14 on page 6-14

Primary (Front) Side (Slots 1-6 and 11-16)
The I/O connectors for slots 1-6 and 11-16, except for the P4 connector,
which carries the H.110 bus, use the same pinouts as the standard
CPX8216 backplane.

Table 6-32. P4 Connector, I/O Slots 1-6, 11-16
POS

Row
Z

Row A

Row B

Row C

Row D

Row E

Row
F

SGA4

SGA3

SGA2

SGA1

SGA0

GA4

GA3

GA2

GA1

GA0

+12V

CT_RST[n]#

CT_EN[n]#

-12V

CT_MC

PSF0#

RSVD

NP=Not Populated. P4 implements the full H.110 Bus connections, which requires P4 to use
depopulated connectors.
CT_RST1# through CT_RST6# are routed radially to the bridge slots.
CT_EN1# is connected to BD_SEL1# on the backplane, and so forth.
[n]=n is the slot number.
Refer to the H.110 specifications for line terminations.

6-38

Computer Group Literature Center Web Site

Primary (Front) Side (Slots 1-6 and 11-16)

Table 6-32. P4 Connector, I/O Slots 1-6, 11-16 (continued)
POS

Row
Z

Row A

Row B

Row C

Row D

Row E

Row
F

-SELVbat

PSF1#

RSVD

SELVbat RTN

VRG

VRG RTN

-Vbat

Vbat RTN

14-12

KEY AREA

CT_D29

CT_D30

CT_D31

V(I/O)

CT_FRAME_A#

GND

CT_D27

+3.3V

CT_D28

+5V

CT_FRAME_B#

GND

CT_D24

CT_D25

CT_D26

GND

FR_COMP#

GND

CT_D21

CT_D22

CT_D23

+5V

CT_C8_A

GND

CT_D19

+5V

CT_D23

GND

CT_C8_A

GND

CT_D16

CT_D17

CT_D18

GND

CT_NETREF_1

GND

CT_D13

CT_D14

CT_D15

+3.3V

CT_NETREF_2

GND

CT_D11

+5V

CT_D12

+3.3V

SCLK

GND

CT_D8

CT_D9

CT_D10

GND

SCLK-D

GND

CT_D4

CT_D5

CT_D6

CT_D7

GND

CT_D0

+3.3V

CT_D1

CT_D2

CT_D3

GND

http://www.motorola.com/computer/literature

6-39

Subassembly Reference

Primary (Front) Side CPU Connectors
The CPU connectors on the CPX8216T H.110 backplane use the same
pinouts as the CPX8216 standard backplane.

For Pinout Information
for Connector:

See:

Table 6-15 on page 6-17

Table 6-16 on page 6-18

Table 6-17 on page 6-20

P2-Domain A

Table 6-18 on page 6-20

P2-Domain B

Table 6-19 on page 6-22

Table 6-20 on page 6-23

Primary (Front) Side HSC Connectors
The HSC/Bridge slot is unique. All five connectors (P5 through P1) use
standard tails, and none of the connectors pass through to the rear.

Table 6-33. P5 Connector, HSC/Bridge (Slots 8 and 10)
POS

Row Z

Row A

Row B

Row C

Row D

Row E

Row F

GND

_AD36

_AD35

_AD34

_AD33

_AD32

GND

_AD40

_AD39

_AD38

_GND

_AD37

GND

_AD45

_AD44

_AD43

_AD42

_AD41

GND

_AD49

_+3.3

_AD48

_AD47

_AD46

GND

6-40

Computer Group Literature Center Web Site

Primary (Front) Side HSC Connectors

Table 6-33. P5 Connector, HSC/Bridge (Slots 8 and 10) (continued)
POS

Row Z

Row A

Row B

Row C

Row D

Row E

Row F

GND

_AD53

_AD52

_AD51

_GND

_AD50

GND

_AD57

_+3.3

_AD56

_AD55

_AD54

GND

_AD61

_AD60

_AD59

_GND

_AD58

GND

_CBE4#

_+3.3

_PAR64

_AD63

_AD62

GND

_REQ64#

_CBE7#

_CBE6#

_GND

_CBE5#

GND

_AD2

_+3.3

_AD1

_AD0

_ACK64#

GND

_AD6

_AD5

_AD4

_GND

_AD3

GND

1412

KEY AREA

GND

_AD9

_AD8

_CBE0#

_GND

_AD7

GND

_AD13

_+5

_AD12

_AD11

_AD10

GND

_PAR

_CBE1#

_AD15

_GND

_AD14

GND

_STOP#

_+5

_LOCK#

_PERR#

_SERR#

GND

_FRAME#

_IRDY#

_TRDY#

_GND

_DEVSEL
#

GND

_AD18

_+5

_AD17

_AD16

CBE2#

GND

_AD21

_CLK

_AD20

_GND

_AD19

GND

_CBE3#

_+5

_IDSEL

_AD23

_AD22

GND

_AD28

_AD27

_AD26

_AD25

_AD24

GND

http://www.motorola.com/computer/literature

6-41

Subassembly Reference

Table 6-33. P5 Connector, HSC/Bridge (Slots 8 and 10) (continued)
POS

Row Z

Row A

Row B

Row C

Row D

Row E

Row F

GND

_GNT#

_REQ#

_AD31

_AD30

_AD29

GND

_INTA#

_INTB#

_INTC#

_INTD#

_RST#

GND

*For boards located in slot 10 (Domain A), the signal name is prefixed with L_PCI_A (for
example, L_PCI_A_AD17).
*For boards located in slot 8 (Domain B), the signal name is prefixed with L_PCI_B (for example,
L_PCI_B_AD17).

Table 6-34. P4 Connector, HSC Slots 8 and 10
POS

Row
Z

Row A

Row B

Row C

Row D

Row E

Row
F

SGA4

SGA3

SGA2

SGA1

SGA0

GA4

GA3

GA2

GA1

GA0

+12V

CT_RST[n]#

CT_EN[n]#

-12V

CT_MC

PSF0#

RSVD

-SELVbat

PSF1#

RSVD

SELVbat RTN

VRG

VRG RTN

6-42

Computer Group Literature Center Web Site

Primary (Front) Side HSC Connectors

Table 6-34. P4 Connector, HSC Slots 8 and 10 (continued)
POS

Row
Z

Row A

Row B

Row C

Row D

Row E

Row
F

-Vbat

Vbat RTN

1412

KEY AREA

CT_D29

CT_D30

CT_D31

V(I/O)

CT_FRAME_A#

GND

CT_D27

+3.3V

CT_D28

+5V

CT_FRAME_B#

GND

CT_D24

CT_D25

CT_D26

GND

FR_COMP#

GND

CT_D21

CT_D22

CT_D23

+5V

CT_C8_A

GND

CT_D19

+5V

CT_D23

GND

CT_C8_A

GND

CT_D16

CT_D17

CT_D18

GND

CT_NETREF_1

GND

CT_D13

CT_D14

CT_D15

+3.3V

CT_NETREF_2

GND

CT_D11

+5V

CT_D12

+3.3V

SCLK

GND

CT_D8

CT_D9

CT_D10

GND

SCLK-D

GND

CT_D4

CT_D5

CT_D6

CT_D7

GND

CT_D0

+3.3V

CT_D1

CT_D2

CT_D3

GND

http://www.motorola.com/computer/literature

6-43

Subassembly Reference

Table 6-35. P3 Connector, HSC Slots 8 and 10

POS

Row
Z

Row A

Row B

Row C

Row D

Row E

Row
F

GND

A/B#

ALM_B_5
V

INT_HSC_
2

Per3_Pwr_
ON#

Per1_Pwr_
ON#

GND

HS_REQ_B

HS_REQ_A

INT_HSC_
1

Per3_LED1
#

Per1_LED1
#

GND

HS_GNT_B

HS_GNT_
A

INT_HSC_
4

Per3_LED2
#

Per1_LED2
#

GND

HS_FLT_B

HS_FLT_A

INT_HSC_
3

Per3_PSNT
_B#

Per1_PSNT
_B#

GND

HS_EJ_B

HS_EJ_A

INT_HSC_
6

Per4_Pwr_
ON#

Per2_Pwr_
ON#

GND

INT_HSC_
8

INT_HSC_
7

INT_HSC_
5

Per4_LED1
#

Per2_LED1
#

GND

A_CLK

A_DOUT#

PS_1_DIN#

Per4_LED2
#

Per2_LED2
#

GND

B_CLK

B_DOUT#

PS_2_DIN#

Per4_PSNT
_B#

Per2_PSNT
_B#

GND

ALM_A_F
RAME#

PS_1_FRA
ME#

PS_3_DIN#

ALM_A_DI
N#

GND

ALM_B_F
RAME#

PS_2_FRA
ME#

PS_3_FRA
ME#

GND

RST3#

RST6#

HLTY10#

GND

RST2#

RST5#

GND

RST1#

GND

BD_SEL6#

GND
B_ENUM#

GND

RST16#

RST13#

GND

HLTY9#

RST15#

RST12#

GND

RST4#

HLTY8#

RST14#

RST11#

GND

HLTY6#

HLTY7#

HLTY16#

BD_SEL16
#

GND

A/B# GND Domain B (slot 8).
ALM_B_5V in Domain B (slot 8); ALM_A_5V in Domain A (slot 10).
B_ENUM# in Domain B (slot 8); A_ENUM in Domain A (slot 10).
BD_SEL7# in Domain B, BD_SEL9# in Domain A.

6-44

Computer Group Literature Center Web Site

Primary (Front) Side HSC Connectors

Table 6-35. P3 Connector, HSC Slots 8 and 10 (continued)
POS

Row
Z

Row A

Row B

Row C

Row D

Row E

Row
F

GND

BD_SEL5#

HLTY5#

BD_SEL7#

HLTY15#

BD_SEL15
#

GND

BD_SEL4#

HLTY4#

RST10#

HLTY14#

BD_SEL14
#

GND

BD_SEL3#

HLTY3#

RST9#

HLTY13#

BD_SEL13
#

GND

BD_SEL2#

HLTY2#

RST8#

HLTY12#

BD_SEL12
#

GND

BD_SEL1#

HLTY1#

RST7#

HLTY11#

BD_SEL11
#

GND

A/B# GND Domain B (slot 8).
ALM_B_5V in Domain B (slot 8); ALM_A_5V in Domain A (slot 10).
B_ENUM# in Domain B (slot 8); A_ENUM in Domain A (slot 10).
BD_SEL7# in Domain B, BD_SEL9# in Domain A.

Table 6-36. P2 Connector, HSC Slot 10
POS

Row Z

Row A

Row B

Row C

Row D

Row E

Row F

GND

GA4

GA3

GA2

GA1

GA0

GND

CLK6

GND

RSV

GND

CLK5

GND

RSV

GND

RSV

GND

RSV

GND

_BRSVP2
A18

_BRSVP2
B18

_BRSVP2
C18

GND

_BRSVP2
E18

GND

_BRSVP2
A17

GND

(_PRST#)

_REQ6#

GNT6#

GND

Signals beginning with an underscore (_) are prefixed with the bus name PCI_B (for example,
PCI_B_AD[49]).
Signals in parentheses are not used.

http://www.motorola.com/computer/literature

6-45

Subassembly Reference

Table 6-36. P2 Connector, HSC Slot 10 (continued)

POS

Row Z

Row A

Row B

Row C

Row D

Row E

Row F

GND

_BRSVP2
A16

_BRSVP2
B16

(_DEG#)

GND

_BRSVP2
E16

GND

_BRSVP2
A15

GND

(_FAL#)

REQ5#

GNT5#

GND

_AD[35]

_AD[34]

_AD[33]

GND

_AD[32]

GND

_AD[38]

GND

VIO

_AD[37]

_AD[36]

GND

_AD[42]

_AD[41]

_AD[40]

GND

_AD[39]

GND

_AD[45]

GND

VIO

_AD[44]

_AD[43]

GND

_AD[49]

_AD[48]

_AD[47]

GND

_AD[46]

GND

_AD[52]

GND

VIO

_AD[51]

_AD[50]

GND

_AD[56]

_AD[55]

_AD[54]

GND

_AD[53]

GND

_AD[59]

GND

VIO

_AD[58]

_AD[57]

GND

_AD[63]

_AD[62]

_AD[61]

GND

_AD[60]

GND

_C/BE[5]#

GND

VIO

C/BE[4]#

_PAR64

GND

VIO

_BRSVP2
B4

_C/BE[7]#

GND

_C/BE[6]

GND

CLK4

GND

GNT3#

REQ4#

GNT4#

GND

CLK2

CLK3

_SYSEN#

GNT2#

REQ3#

GND

CLK1

GND

REQ1#

GNT1#

REQ2#

GND

Signals beginning with an underscore (_) are prefixed with the bus name PCI_B (for example,
PCI_B_AD[49]).
Signals in parentheses are not used.

6-46

Computer Group Literature Center Web Site

Primary (Front) Side HSC Connectors

Table 6-37. P2 Connector, HSC Slot 8
POS

Row Z

Row A

Row B

Row C

Row D

Row E

Row F

GND

GA4

GA3

GA2

GA1

GA0

GND

CLK16

GND

RSV

GND

CLK15

GND

RSV

GND

RSV

GND

RSV

GND

_BRSVP2
A18

_BRSVP2
B18

_BRSVP2
C18

GND

_BRSVP2
E18

GND

_BRSVP2
A17

GND

(_PRST#)

_REQ16#

GNT16#

GND

_BRSVP2
A16

_BRSVP2
B16

(_DEG#)

GND

_BRSVP2
E16

GND

_BRSVP2
A15

GND

(_FAL#)

REQ15#

GNT15#

GND

_AD[35]

_AD[34]

_AD[33]

GND

_AD[32]

GND

_AD[38]

GND

VIO

_AD[37]

_AD[36]

GND

_AD[42]

_AD[41]

_AD[40]

GND

_AD[39]

GND

_AD[45]

GND

VIO

_AD[44]

_AD[43]

GND

_AD[49]

_AD[48]

_AD[47]

GND

_AD[46]

GND

_AD[52]

GND

VIO

_AD[51]

_AD[50]

GND

_AD[56]

_AD[55]

_AD[54]

GND

_AD[53]

GND

_AD[59]

GND

VIO

_AD[58]

_AD[57]

GND

_AD[63]

_AD[62]

_AD[61]

GND

_AD[60]

GND

_C/BE[5]#

GND

VIO

C/BE[4]#

_PAR64

GND

VIO

_BRSVP2
B4

_C/BE[7]#

GND

_C/BE[6]

GND

CLK14

GND

GNT13#

REQ14#

GNT14#

GND

Signals beginning with an underscore (_) are prefixed with the bus name PCI_A (for example,
PCI_A_AD[49]).
Signals in parentheses are not used.

http://www.motorola.com/computer/literature

6-47

Subassembly Reference

Table 6-37. P2 Connector, HSC Slot 8 (continued)
POS

Row Z

Row A

Row B

Row C

Row D

Row E

Row F

GND

CLK12

CLK13

_SYSEN#

GNT12#

REQ13#

GND

CLK11

GND

REQ11#

GNT11#

REQ12#

GND

Signals beginning with an underscore (_) are prefixed with the bus name PCI_A (for example,
PCI_A_AD[49]).
Signals in parentheses are not used.

Table 6-38. P1 Connector, HSC Slots 8 and 10

6
POS

Row
Z

Row A

Row B

Row C

Row D

Row E

Row
F

GND

_REQ64#

A_ENUM
#

3.3V

GND

_AD[1]

VIO

_AD[0]

_ACK64#

GND

3.3V

_AD[4]

_AD[3]

_AD[2]

GND

_AD[7]

GND

3.3V

_AD[6]

_AD[5]

GND

3.3V

_AD[9]

_AD[8]

_M66EN

_C/BE[0]
#

GND

_AD[12]

GND

VIO

_AD[11]

_AD[10]

GND

3.3V

_AD[15]

_AD[14]

GND

_AD[13]

GND

_SERR#

GND

3.3V

_PAR

_C/BE[1]

GND

3.3V

_SDONE

_SBO#

GND

_PERR#

GND

_DEVSEL#

GND

VIO

_STOP#

_LOCK#

GND

3.3V

_FRAME#

_IRDY#

BD_SEL[n]#

_TRDY#

GND

1412

KEY AREA

GND

_AD[17]

_AD[16]

GND

_C/BE[2]
#

GND

_AD[18}

A_ENUM# in Domain A (slot 10); B_ENUM# in Domain B (slot 8).

6-48

Computer Group Literature Center Web Site

Primary (Front) Side HSC Connectors

Table 6-38. P1 Connector, HSC Slots 8 and 10 (continued)
POS

Row
Z

Row A

Row B

Row C

Row D

Row E

Row
F

GND

_AD[21]

GND

3.3V

_AD[20]

_AD[19]

GND

_C/BE[3]

_IDSEL

_AD[23]

GND

_AD[22]

GND

_AD[26]

GND

VIO

_AD[25]

_AD[24]

GND

_AD[30]

_AD[29]

_AD[28]

GND

_AD[27]

GND

REQ[N]#

GND

3.3V

CLK[N]

_AD[31]

GND

_BRSVP1A5

_BRSVP1B5

RST[N]#

GND

GNT[N]#

GND

_BRSVP1A4

HLTY[N]#

VIO

_INTP

_INTS

GND

_INTA#

_INTB#

_INTC#

_INTD#

GND

TCK

TMS

TDO

TDI

GND

-12V

TRST#

+12V

GND

A_ENUM# in Domain A (slot 10); B_ENUM# in Domain B (slot 8).

http://www.motorola.com/computer/literature

6-49

Subassembly Reference

Secondary (Rear) Side I/O Connectors
Note

I/O slot connectors P4, P2, and P1 do not connect through to the
transition module.

Table 6-39. P5 Connector, I/O Slots 1-6 and 11-16 (User
I/O)
POS

Row Z

Row A

Row B

Row C

Row D

Row E

Row F

22-1

GND

I/O

GND

All I/O pins pass through the backplane to the transition module, they do not
make any connection to the backplane.

Table 6-40. P3 Connector, I/O Slots 1-6 and 11-16 (User
I/O)
POS

Row Z

Row A

Row B

Row C

Row D

Row E

Row F

19-1

GND

I/O

GND

All I/O pins pass through the backplane to the transition module, they do not
make any connection to the backplane.

Secondary (Rear) Side CPU Transition Module
Connectors
The CPU transition module connectors use the same pinouts as the
connectors in the CPX8216 standard backplane.
Note

CPU connectors P4, P2, and P1 do not pass through the
backplane.

For Pinout Information
for Connector:
See:

6-50

Table 6-24 on page 6-27

Table 6-25 on page 6-28

Computer Group Literature Center Web Site

Alarm Display Panel

Telco
Relay
LEDs
Uncommitted
Digital Inputs

Alarm PLD

POR

REG
GND

POWER

System LEDs

PWR A
PWR B

HSC IFC Conn

System Alarm Conn

The alarm display panel provides the system LEDs and remote alarm
functions for the CPX8216 and the CPX8216T. It is powered and
controlled from each of the two Hot Swap Controllers within the system
(see Figure 6-7).

Slot 2 LEDs

Clock A
Frame A
DOUT A
DIN A

Clock B
Frame B
Data B

Slot 1 LEDs

Domain A
Logic

o
o
o
Slot 6 LEDs
Slot 11 LEDs
Domain B
Logic

o
o
o
Slot 15 LEDs

Figure 6-7. Alarm Display Panel Block Diagram
The alarm display panel features three system status LEDs, three Telco
alarm status LEDs, three slot status LEDs for each slot, and an RJ-45
connector for Telco alarm status output to an external interface (see Figure
6-8). Normally, only two of the three slot status LEDs are visible—the
third is covered by the panel’s overlay.

http://www.motorola.com/computer/literature

6-51

Subassembly Reference

SYSTEM

SYSTEM
IN SERVICE

STATUS

COMPONENT

TELCO

COMPONENT
OUT OF SERVICE

MINOR

MAJOR

ALARM

CRITICAL

STATUS

CONNECTION

Figure 6-8. Alarm Display Panel—Front View
The alarm display panel LEDs are controlled by bits in the Hot Swap
Controller’s register, which are set by the system software. This allows full
user customization of alarm event reporting. The next table provides the
color and standard nomenclature for the LEDs on the alarm panel.

Table 6-41. Alarm LED Color and Description
Alarm
Controller Board Slot
Status

System Status

Telco Status

6-52

LED Color

Description

Green

In Service

Yellow

N/A (or Out of Service)

Red

Out of Service

Green

System In Service

Yellow

Component Out of Service

Red

System Out of Service

Yellow

Minor

Red

Major

Red

Critical

Computer Group Literature Center Web Site

Alarm Display Panel Interface Connector (J4)

Alarm Display Panel Interface Connector (J4)
Connector J4 receives system alarm signals from the backplane connector
ALARM.

Table 6-42. Alarm Display Panel Interface Connector (J4)
Pin

Signal

ALM_A_CLK

GND

ALM_B_CLK

GND

ALM_A_DOUT#

ALM_A_5V

ALM_B_DOUT#

ALM_B_5V

ALM_A_FRAME#

ALM_B_FRAME#

ALM_A_DIN#

Remote Alarm Connector (J1)
The RJ-45 remote alarm connector (J1) provides standard telco alarm
signals to remote alarm equipment. The connector also has a jacket shield
to protective earth ground through two separate pins (E1 and E2).

Table 6-43. Remote Alarm Connector (J1)
Pin

Signal

Critical Alarm

Minor Alarm

Critical Alarm Return

Minor Alarm Return

Major Alarm

Rack Alarm

Major Alarm Return

Rack Alarm Return

http://www.motorola.com/computer/literature

6-53

Subassembly Reference

Power Distribution Panel
The power distribution panel, located in the rear of the chassis below the
transition module cardcage, distributes the AC or DC input power to the
system’s power supplies.
There are three versions of the power distribution panel:
❏ AC (CPX8216)
❏ Dual Input DC (CPX8216)
❏ Dual Breaker DC (CPX8216)

❏ H.110 DC (CPX8216T)
The CPX8216T can be configured with AC or DC power, however only
the DC version has the dual input option and the H.110 bus analog voltage
inputs.The H.110 bus on P4/J4 operates without the analog voltages
present, but if analog cards are being used (for example, line or trunk
cards) the analog voltages are required.
If the system requires the analog H.110 bus, voltages need to use the dual
DC power distribution panel. If the system requires an AC configuration,
a special AC power distribution panel must be used. Contact your
Motorola sales representative for information.

AC Power Distribution Panel (CPX8216)
The AC version of the panel is shown in the figure below.

l
0

90-260 VAC

Figure 6-9. AC Power Distribution Panel—Front View

6-54

Computer Group Literature Center Web Site

Dual Input DC Power Distribution Panel (CPX8216)

Dual Input DC Power Distribution Panel (CPX8216)
The dual input DC version allows redundant input power supplies for full
high-availability applications. It is recommended that each input source be
independent of the other.

-48 VDC

-48 VDC RTN

-48 VDC
-48 VDC RTN

2572 9907

Figure 6-10. Dual Input DC Power Distribution Panel—Front View
Use 12 AWG or larger wire with a #10 ring terminal to connect the DC
power source to the system.
Ring Terminal
WIDTH

STUD SIZE: #10
WIDTH: .490 inch (12.446 mm) or smaller
WIRE GAGE: 12AWG or bigger

Dual Breaker DC Power Distribution Panel (CPX8216)
The dual breaker 48VDC version also allows redundant input power
supplies for full high-availability applications. It is recommended that each
input source be independent of the other. This power distribution panel has
two 30A push/pull circuit breakers and is designed for use with a Smart
cable that includes breakers and additional circuitry that detect the failure
of a single input DC power supply.

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6-55

Subassembly Reference

Figure 6-11. Dual Breaker DC Power Distribution Panel—Front View
The dual breaker DC power distribution panel is available without the two
30A circuit breakers, provided that circuit breaker protection is provided
elsewhere and there is allowance for a rating of 30A for each feed.

Use either a standard Smart cable or the optional right-angle Smart cable
(for limited space requirements) to connect the DC power source to the
system. Cable length is 10 feet.
Part Number

Cable Description

30-W2750E01A

Standard Smart cable

30-W2750E03A

Right-angle Smart cable

H.110 DC Power Distribution Panel (CPX8216T)
The H.110 DC power distribution panel provides dual DC input for system
power as well six additional power input connectors for the H.110 BAT
and Ring Voltages. The H.110 DC power distribution panel is only
compatible with the CPX8216T system.
Caution

!
Caution

6-56

The six H.110 power inputs must only be attached to approved Telephone
Network Voltage (TNV) branch circuits. TNV branch circuits must
comply with all requirements called for in these safety standards: IEC
950/EN60 950, UL #1950, and CSA #950. Attaching those inputs to nonTNV-approved power sources will cause the system to fail compliance
with safety regulations and may cause damage to the system backplane and
system components.

Computer Group Literature Center Web Site

H.110 DC Power Distribution Panel (CPX8216T)

-SEL VBAT

System Power
Terminal Blocks

SEL VBAT RTN

VRG

VRG RTN

VBAT RTN

-VBAT

H.110 BAT and
Ring Voltage
Terminal Block

-48 VDC

-48 VDC
RTN

-48 VDC
-48 VDC
RTN

2573 9907

Figure 6-12. H.110 DC Power Distribution Panel
The analog voltages on the H.110 bus are:

Table 6-44. DC Analog Voltages for H.110 Bus
Description

Voltage Inputs

Battery

-48V DC

Return

Nominal 48V, range of 40V to 72V

Ringing

90 VAC nominal

SELV

24V DC nominal, range of <60V

Use 12 AWG or larger wire with a #10 ring terminal to connect the DC
system power source to the system. Use 12 AWG or larger wire with a #6
ring terminal to connect the DC TNV voltages to the H.110 power
connectors.
Ring Terminal - H.110 Power

Ring Terminal - System Power
WIDTH

STUD SIZE: #6

STUD SIZE: #10
WIDTH: .490 inch (12.446 mm) or smaller

WIRE GAGE: 12AWG or bigger

http://www.motorola.com/computer/literature

WIRE GAGE: 12AWG or bigger

6-57

Power Supplies

Power Supplies
The AC and DC power supplies are mounted on a sled along with the
replaceable cooling fans and are discussed in the CPX8000 Series
CPX8216 and CPX8216T System Installation and Use manual.
For the power coupling to the backplane, refer to the information in Power
Supply Connectors (PS1, PS2, PS3) on page 6-6. For the electrical
specification for the power supply, refer to Power Supply Electrical
Specifications on page A-2.

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6-58

ASpecifications

Environmental Characteristics
ENVIRONMENTAL CHARACTERISTICS
Temperature
Operating:

0º to 50º C (32º to 122º F) continuous duty with linear current derating
between +50º C to +60º C (122º to 140º F) to 50% maximum rated power

Storage and Transit:

-25º TO +85º C (-13º to 185º F)

Maximum Altitude
Operating:

Linear current derating to 85% between 8,000 feet and 12,000 feet

Storage and Transit:

30,000 feet

Shock

No degradation at 25g shock of 11ms duration at 1/2 sine wave in three
planes.

Vibration

No degradation at sine 10 to 100 to 10Hz to 2g 10min/decade three planes.
Meets NEBS Bellcore TR-NWT-000063, Zone 4 Earthquake Vibration

Acoustic Noise

Maximum sound level 70dbA (measured at 1 meter from the power supply
at all points around it using a sound-level meter meeting ANSI Standard
S1.4-1983, General Purpose Sound-Level Meter)

Cooling

The power supply meets all specifications when cooled by the fan in its
subenclosure within the restriction of the system enclosure.

A-1

Specifications

Power Supply Electrical Specifications
AC Input

AC Voltage: 90 Vac to 132 Vac or 190 Vac to 260 Vac (autoranging)
AC Frequency: 47 Hz to 63 Hz
Power Factor: Minimum 0.98 at full load and nominal line
Turn-on Surge Current: 20 Amps at +/- 2A for one line cycle
Efficiency: -72% typical at full load and nominal line, including output Oring diodes
Input Current: Measured 6.0A maximum at 115 Vac, 3A maximum at 230 Vac at
475 watts

DC Input

DC Voltage: -36 Vdc to -72 Vdc (autoranging)
Turn-on Threshold: -38.5 Vdc to -41Vdc
Turn-on Surge Current: 20 Amps at -36 Vdc maximum in less than 4 msec.
Efficiency: 70% minimum at full load and nominal line, including output Oring
diodes
Input Current: Measured 13A @ -48 Vdc at 475W

Output

All measurements are made at the output connector of the power supply. The power
supply is used in an N+1 power system. Each voltage output supports power sharing.
Minimum Load Operation: None
Total Regulation: Total regulation is any combination of line, load and cross
regulation, actual set point (as a deviation from the nominal set point), warm up, and
temperature that results in an output voltage that deviates from the nominal set point.
Table A-1 provides the total regulation for each output:

A-2

Computer Group Literature Center Web Site

Power Supply Electrical Specifications

Table A-1. Total Regulation (per Output)
Output
Number

Voltage

Set Point at Load

Maximum
Current

Loads

Total
Regulation

+5.0V

+5.06Vdc@20A
+/- 5 mV

40A

0 to 40A

±3%

+3.3V

+3.36Vdc@20A
+/- 5 mV

40A

0 to 40A

±3%

+12.0V

+12.1Vdc@4A
+/- 24 mV

10.4A cont.
(11.5A peak
for max. 5
sec.)

0 to 10.4A

±5%

-12.0V

-12.1Vdc@2A
+/- 12 mV

0 to 4A

±5%

Output Power

400 Watts total continuous maximum from all outputs. Any mix of
outputs totaling 400W is acceptable.

DC Output Voltage
Adjustment

No output adjustments.

Output Noise

Total periodic and random deviation (PARD) noise found on outputs of
the power module shall be, as measured at the backplane:
-From 0 to 30 MHz bandwidth for ripple <50 mV
-From 0 to 100 MHz bandwidth for spikes <75 mV

Overload Protection

All DC outputs have a method to protect the power supply from overloads
and shorts. When one output is overloaded, then all outputs are turned off.
Cycling the AC or DC input off then on will cause the power supply to
attempt recovery.

Output to Output Short The power supply provides protection when any output is shorted to any
Protection
other output. A short is considered to be any interconnection that results
in any output deviating from its regulation range by more than 0.7 Volts.
Cycling the AC or DC input off then on will cause the power supply to
attempt recovery.

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A-3

Specifications

Overshoot

Overshoot does not exceed 2.0% of any output voltage under the
following conditions: power failure, enabled, disabled, and AC input
cycled on/off. Overshoot is the phenomena where the magnitude of
voltage of an output temporarily exceeds its final or stabilized value.

Load Change Transient Any DC voltage returns to 1% within 2mS in response to a 25% change
Response
in the load. The +5V output does not vary more than 3% in response to a
25% change in load. The 12V output does not go out of regulation during
a 0.5A change in the +12V load.
Proper Operation
The power supply operates properly when subjected to a 10% delta
During Dynamic Loads dynamic load with a 50% duty cycle at all frequencies from zero to 2
MHz, or 2 times the switching frequency of the power supply, whichever
is greater.
Undershoot and Reverse With respect to its normal zero reference voltage, no output voltage,
Voltage
under any normal condition, become of a polarity opposite to its normal
operation polarity (excluding applying an external reverse voltage).
Output Risetime

The +5V output will have a monotonic rise from 2V to 4.75V. The +5V
output will transition from +2V to +4.75V in less than 50mS when loaded
to 37.5A or less.
The +5V output will always be above +3.3V output.
The +3.3V output will transition from +2V to 13.3V in less than 50mS.
The skew in risetime between +5V and +3.3V outputs will be less than 50
mS.
The +12V output will transition from +2V to +10.8V in less than 50 mS.
The above conditions will be over the complete input range and load
range, from minimum to maximum load with a capacitive load.

Holdover Storage

A-4

Output voltage stays within regulation limits for at least 20 msec. from
the last peak of the line voltage cycle after input power is removed. The
power supply does not latch off during an AC line loss condition that is
less than the hold up time.

Computer Group Literature Center Web Site

Power Supply Electrical Specifications

Over Voltage Protection A Single Fault condition is the failure of any one device within the power
supply. The condition includes both the shorting of any output and the
failure of any one device within the power supply.
Under any single fault condition:
The +5V outputs limit voltage at 6.4Vdc maximum.
The +3.3V output limits voltage at 4.2Vdc maximum
The ±12V outputs do not exceed ±15.0Vdc, respectively.
Control Signals

ENABLE POWER# (Input to Power Supply):
Turns on and off the power supply outputs. When the Enable Power#
signal is low, the power supply will be ON. When the Enable Power#
signal is high or open, the power supply will be OFF.
POWER GOOD# (Output from Power Supply):
This signal is low when the power supply output voltages are good. The
signal is high when the power supply voltages are bad. The voltage is
good when it is within ±5% of the set voltage.

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A-5

BRelated Documentation

Motorola Computer Group Documents
The Motorola publications listed below are referenced in this manual. You
can obtain paper or electronic copies of Motorola Computer Group
publications by:
❏ Contacting your local Motorola sales office
❏ Visiting MCG’s World Wide Web literature site,
http://www.motorola.com/computer/literature
❏ To locate and view the most up-to-date product information in
PDF or HTML format, visit
http://www.motorola.com/computer/literature.

Document Title

Motorola
Publication Number

Compact PCI CPX8216 and CPX8216T System Installation and
Use

CPX8216A/IH

MCP750HA Hot Swap CompactPCI Single Board Computer
Installation and Use

MCP750HA/IH

MCP750 CompactPCI Single Board Computer Installation and
Use

MCP750A/IH

MCP750 Single Board Computer Programmer’s Reference Guide

MCP750A/PG

PPCBug Firmware Package User’s Guide

PPCBUGA1/UM, and
PPCBUGA2/UM

B-1

Motorola Barcode Reader Cpx8000 Users Manual Series CPX8216/8216T CompactPCI System Reference

CPX8216T to the manual c84dcecc-2b50-4038-8423-b3caad68e6a7

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