Qisda M27 GSM/GPRS MODULE User Manual USERS MANUAL

Qisda Corporation GSM/GPRS MODULE USERS MANUAL

USERS MANUAL

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M27
GSM GPRS Wireless Module
User Manual
Rev. 0.1
30, July 2007
COPYRIGHT BENQ Corporation
This document contains proprietary technical information which is the property of BenQ Corporation and
is issued in strict confidential and shall not be disclosed to others parties in whole or in parts without
written permission of BenQ Corporation
The documents contain information on a product, which is under development and is issued for
customer evaluation purposes only.
BENQ may make changes to product specifications at any time, without notice.
BenQ Corporation
Networking & Communications BG
18 JiHu Road, Nei-Hu, Taipei 114, Taiwan, R.O.C.
Tel: +886-2-2799-8800
Fax: +886-2-2656-6399
http://www.benq.com
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1.
OVERVIEW ...........................................................................................................................................................................................................4
2.
M27 KEY FEATURES AT A GLANCE .............................................................................................................................................................5
3.
DESIGN GUIDE ORGANIZATION..................................................................................................................................................................7
4.
PIN ASSIGNMENT OF M27 MODULE ...........................................................................................................................................................8
4.1.
M27 MODULE PLACEMENT ...............................................................................................................................................................9
4.2.
GROUND PIN .......................................................................................................................................................................................9
4.3.
VBATRF PIN (PIN 2, PIN 4, PIN 6, PIN 8) / VBATBB PIN (PIN 1) ...................................................................................................9
4.4.
PWON PIN.......................................................................................................................................................................................10
4.5.
VBACKUP PIN ...............................................................................................................................................................................10
4.5.1 VBACKUP MAIN FEATURE ..................................................................................................................................................................10
4.5.2 FUNCTIONAL DESCRIPTION ...................................................................................................................................................................10
4.5.3ELECTRICAL SPECIFICATION...................................................................................................................................................................11
Power ON / Power OFF and Backup Conditions ...................................................................................................... 11
Backup Battery Charger Interface ............................................................................................................................. 11
Current consumption in BACKUP mode ................................................................................................................... 11
4.5.4GENERAL CHARGING C IRCUIT ...............................................................................................................................................................11
4.5.5 VBACKUP C HARGING ..........................................................................................................................................................................12
4.6.
ONNOFF PIN ...................................................................................................................................................................................12
4.7.
ADCIN PIN ......................................................................................................................................................................................13
4.8.
3.3 EXT PIN .....................................................................................................................................................................................13
4.9.
VRIO PIN .........................................................................................................................................................................................14
PERIPHERALS ...................................................................................................................................................................................................15
5.1.
SIM ...................................................................................................................................................................................................15
5.2.
AUDIO ...............................................................................................................................................................................................15
5.3.
KEYBOARD....................................................................................................................................................................................17
5.4.
LCM..................................................................................................................................................................................................19
5.5.
PAGING INDICATOR ...........................................................................................................................................................................21
5.6.
CAMERA INTERFACE .........................................................................................................................................................................26
5.7.
NAND FLASH INTERFACE ................................................................................................................................................................28
5.8.
MICRO SD INTERFACE......................................................................................................................................................................30
UART INTERFACE............................................................................................................................................................................................31
6.1
DUAL EXTERNAL UART SOLUTION .................................................................................................................................................35
6.2
SINGLE EXTERNAL UART SOLUTION ..............................................................................................................................................38
6.2.1
SINGLE EXTERNAL UART SOLUTION: NXP SC16C850LIET........................................................................................................38
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6.2.2
SINGLE EXTERNAL UART SOLUTION: EXAR XR16L570IL24 .....................................................................................................40
USB INTERFACE ...............................................................................................................................................................................................41
7.1
USB CHARGER SOLUTION ................................................................................................................................................................42
GPIO MAPPING .................................................................................................................................................................................................43
LEVEL SHIFTER DESIGN ..............................................................................................................................................................................44
10. LAYOUT NOTICE..............................................................................................................................................................................................45
11. ANTENNA INTERFACE ..................................................................................................................................................................................46
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1.
Overview
This design guide is based mainly on the M27 evaluation board (EVB). The M27 EVB enables you
to evaluate the M27 module and peripheral design. In addition, it provides sample firmware that you can
use as a starting point to develop code. To give the users the system concept of the interconnections
between the host and M27 module, a system block diagram is provided as the following:
The reference schematics for M27 peripherals will be given in details in this design guide. Since the
interconnections between the host and M27 vary by application, we tend to give only reference designs
of general functions, such as AT command by RS232, re-download mechanisms, and flow control of
USB, etc.
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2.
M27 Key Features at a glance
M27 provides basic features (see in the following table) for our customers, and provide compile tool
to our customers, it will gives you maximum flexibility for easy integration with the Man-Machine
Interface (MMI).
Feature
Implementation
Power supply
Single supply voltage 3.3V- 4.5V
Power saving
Minimizes power consumption in SLEEP mode to 3mA
Charging
Supports charging monitoring
Frequency bands
 Quad-band GSM850/EGSM900/DCS1800/PCS1900
 Compliant to GSM/GPRS Phase 2/2+ , GPRS class 10
GSM class
Small MS
Transmit power
 Class 4 (2W) at GSM850
 Class 4 (2W) at EGSM900
 Class 1 (1W) at DCS1800
 Class 1 (1W) at PCS1900
Audio interfaces
Two analog audio interfaces.
Audio features
Speech codec modes:
Serial interfaces: UART
♦
Half Rate (ETS 06.20)
♦
Full Rate (ETS 06.10)
♦
Enhanced Full Rate (ETS 06.50 / 06.60 / 06.80)
♦
Adaptive Multi Rate (AMR)
 1.8V Bi-directional bus for AT commands and data UART.
 6-wire serial interface. Supports RTS/CTS Hardware handshake
and software XON/XOFF flow control.
 Auto baud rate detects 1200 to 115200 bps
 UART can be used for CSD service and send AT command of
controlling module.
 UART can be multiplexing function, you can use USB at the same
time
LCM interface
 Support 1.8V SPI interface(CS, SDO,D/Cn, CLK, RST)
Phonebook management
Supported phonebook types: SM, FD,LD, ME
SIM Application Toolkit
Supports SAT class 3, GSM 11.14 Release 98
Ringing tones
Offers a choice of
different ringing tones / melodies, easily selectable
with AT commands
Temperature range
 Operational temperature : -20  ~ +80 
 Functional temperature : -30  ~ +85 
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 Storage temperature : -40 ~ +85 
SMS
 MT, MO, CB, Text and PDU mode
SIM interface
 Supported SIM card: 1.8V/3V
 External SIM card holder has to be connected via interface
connector (note that card holder is not part of M27)
External antenna
Connected via 50 Ohm antenna connector or antenna pad
Real time clock
Implemented
Physical characteristics
Size: 45.7 x 43 x 6.8 mm
Weight: 11.0g
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3.
Design Guide Organization
The rest of the manual is organized as follows:
Section 4
Pin out definition of M27 module is given along with the RF antenna placement and
trace guidelines. In addition, the recommended power on; and handshaking
sequences are shown.
Section 5
Reference schematics for M27 peripheral, i.e., SIM, Audio, Keyboard, LCM, Paging
indicator, Camera, NAND flash, and Micro SD.
Section 6
The UART interface.
Section 7
The USB interface and USB charger solution..
Section 8
GPIO mapping.
Section 9
Level shifter design.
Section 10
Layout notice
Section 11
Antenna Interface
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4.
Pin Assignment of M27 module
The following is the pin out definition of the M27 module
NAND flash interface (14 pin assignment)
Note: For pin 97, 98, 99,100- MCSI and GPIO muxed pins, they have different functions depending on
the MODE field of the pin configuration register. Mode 0GPIO function, Mode 1MCSI function
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4.1.
M27 Module Placement
In M27 module, we have one 50ohm antenna port (interfaced by Antenna pad and grounding) for
signal transfer. In addition, the RF signal will be impacted by high frequency noise interference. We
strongly suggest the audio trace and SIM signal trace to be as short as possible and as far away as
possible from the RF trace and power line to prevent cross coupling.
The M27 offer one approach to connecting the antenna shown in the Figure:
4.2.
Antenna pad and grounding plane placed on the bottom side.
Ground Pin
There are 12 ground pins in M27 module, they should be connected to the PCB ground plane (The
ground plane in PCB should be as large as possible).
4.3.
VBATRF Pin (Pin 2, Pin 4, Pin 6, Pin 8) / VBATBB Pin (Pin 1)
The “Power amplifier” is supplied by the VBATRF pins. During transmitting mode, high output
power will draw a large amount of current. The width of this power trace that is connected to the VBATRF
pins could not be less than 80mils. In addition, it is better to shunt a 100uF (low ESR) bypass capacitor
on VBATRF pins to prevent voltage drop and to reduce ripple. Furthermore, another chip in the module
is supplied by the VBATBB pin. The width of this trace that connected to this pin should also be wider.
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4.4.
PWON PIN
The pin POWON is dedicated to powering on the M27 module. The pin is initially HIGH when
power is applied to the M27 module. Once the pin is pulled low for more than 120 ms. M27 will power on.
Pin Name
PWON
Pin Out
14
Pull
PU
Reset
Config
Description
Input
Power On
120ms
4.5.
VBACKUP PIN
4.5.1 VBACKUP Main Feature
When main battery power (VBAT) is low or removed, real time information would be lost. For some
purposes, customers would like to keep some data (e.g. RTC) in above conditions that the data can be
accessed when main battery power is fed again.
For example, customers need RTC continuously
running while main battery is removed. To achieve this function, M27 provides VBACKUP Pin for
backup battery connection. Backup battery would supply backup power to keep M27 RTC running.
4.5.2 Functional Description
To keep real time data for system application during low power or no power condition, M27 allows
external battery to provide power to module built-in RTC circuit via “VBACKUP” Pin. The battery can be
charged by M27 “VBACKUP” Pin as proposed in section 4.5.4. Customers could choose rechargeable
battery which meets the M27 electrical specification show in next section.
If customers would like to keep real time information alive longer than an hour, Li-ion battery would
be a better choice.
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4.5.3Electrical Specification
 Power ON / Power OFF and Backup Conditions
PARAMETER
TEST CONDITIONS
Battery voltage to enter
Measured on the VBAT
ACTIV mode from OFF mode
terminal
Battery voltage to enter
VBACKUP 3.2, measured on
BACKUP mode from ACTIV
the VBAT terminal, monitored
mode
on the ONnOFF terminal
MIN
TYP
Max
3.3
UNIT
2.6
2.75
2.9
MIN
TYP
Max
UNIT
350
500
900
ÂľA
2.9
3.1
3.3
MIN
TYP
Max
UNIT
43
65
ÂľA
8.6
12
 Backup Battery Charger Interface
PARAMETER
Backup battery charging
TEST CONDITIONS
VBACKUP = 2.8 V
current
End backup battery charging
IVBACKUP = −10 µA,
voltage:
 Current consumption in BACKUP mode
PARAMETER
VBACKUP OFF mode
TEST CONDITIONS
VBAT=3.6V,
Ck=32KHz Clock ON
VBACKUP=3.2V,
VBAT=0V,
BACKUP on backup battery
Ck=32KHz Clock ON
mode
VBACKUP=0V,
VBAT=2.4V,
ÂľA
16
22
Ck=32KHz Clock ON
4.5.4General Charging Circuit
“VBACKUP” Pin is the in M27 to connect external Li-ion battery. This reference circuit is our
recommendation.
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4.5.5 VBACKUP Charging
The backup battery can be charged by an external circuit or by M27 module itself via the pad
“VBACKUP”. An external circuit with a programmable voltage regulator allows recharging the backup
battery. The backup battery charge starts when the following conditions are met:
Backup battery charge is enabled by a control bit
Charging power supply (main battery) voltage > Backup Battery voltage
Charging power supply (main battery) voltage > 2.8V
4.6.
ONnOFF PIN
This provide Digital Baseband Rest
Pin Name
Pin Out
Pull
ON n OFF
13
PD
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Reset
Output
Config
Description
Output Hardware Reset
12
C o n f id e n t ia l P r o p e r t y
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4.7.
ADCIN PIN
Battery monitoring is performed by the multiplexed 10–channel 10–bit ADC MADC used to
measure the battery voltage, battery temperature, battery type, battery charge current, battery charger
input voltage and the backup battery voltage. The signals are converted into digital 10– bit words, stored
in auxiliary ADC output registers and transmitted to an external C. This reference circuit is our
recommendation.
Pin Name
ADCIN
ADCIN2
4.8.
Pin Out
22
3.3 EXT PIN
Pin Name
3.3V_EXT
Š2007 B e n Q
Pin Out
Pull
Reset
Input
Input
Pull
Reset
Config
Description
Main Battery Voltage detection
A/D converter
Config
Description
3.3V Power Supply for LCM & Back light
LED
and UART in M27 EVB
61
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4.9.
VRIO PIN
Power supply for external level shifters
Pin Name
Pin Out
VRIO
Pull
Reset
Config
Description
1.8V output voltage for external level
shifters(Note)
Note: Level shifter: PMGD280UN for UART, ADG3308BRUZ-REEL for NAND flash, Add/data bus,
SN74LVCH162244AGR, PCA9306DCTR and SN74AVC1T45YZPR for Camera
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5
Peripherals
5.1.
SIM
The SIM Card digital interface in the M27 ensures the translation of logic levels between M27 and the
SIM Card, for the transmission of 3 different signals: SIM_CLK; a reset signal from M27 to the SIM
Card (SIM_RST); and serial data from M27 to the SIM Card (SIM_IO). The SIM card interface can be
programmed to drive a 1.8V SIM Card.
6 Pin SIM Socket
5.2.
Audio
There are 2 embedded audio drivers built in the BenQ M27 module. The 2 drivers can drive different
kinds of audio load (such as Handheld, or hands free).
Handheld
Microphone 2
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Ear output
Hand free
Microphone 1
Speaker output
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Audio Path Selection AT Commands
The M27 module provides the switching of audio paths using AT commands (In connection status):
Default value: case (1)
(1) AT$HANDHELD (EARN, EARP, MICIN2, MICIP2)
(2) AT$HANDFREE (SPKPA, SPKNA, MICIN1, MICIP1)
5.3.
KEYBOARD
5.3.1 Keyboard Controller Overview
The keyboard controller can handle up to 5*5 keyboards, operates on a 32-kHz clock, and can
generate wake-up events when the device is in sleep mode, and this reference circuit is our
recommendation.
Pin Name
Pin Out
KBR0
46
KBR1
48
KBR2
50
KBR3
52
KBR4
54
KBC0
36
KBC1
38
KBC2
40
KBC3
44
KBC4
46
Pull
PU
PU
PU
PU
PU
Reset
Input high
Input high
Input high
Input high
Input high
Output
Output
Output
Output
Output
Config
Description
Keypad matrix 4 Row access
Keypad matrix 4 Row access
Keypad matrix 4 Row access
Keypad matrix 4 Row access
Keypad matrix 4 Row access
Keypad matrix 4 column access
Keypad matrix 4 column access
Keypad matrix 4 column access
Keypad matrix 4 column access
Keypad matrix 4 column access
5.3.2 Reference circuit
J8
ROW4
ROW2
ROW0
KBC1
KBC3
ROW4
ROW2
ROW0
KBC1
KBC3
10
ROW3
ROW1
KBC0
KBC2
10
KBC4
ROW3
ROW1
KBC0
KBC2
KBC4
KB connector
R31
100 J
KBR0
R32
100 J
KBR1
R33
100 J
KBR2
R34
100 J
KBR3
R35
KBR4
100 J
ROW0
ROW1
ROW2
ROW3
ROW4
C37
22P J
KBC0
C38
C39
C40
C41
22P J
T2 15V 150PF
. .
KBC1
T3 15V 150PF
. .
KBC2
T4 15V 150PF
. .
KBC3
T5 15V 150PF
. .
KBC4
T6 15V 150PF
. .
22P J
22P J
22P J
Close to the Key Pad
connector
5.3.3 Main Features
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The keyboard controller includes the following main features:
- Support of multi-configuration keyboards up to 5 rows x 5 columns
- Integrated programmable timer
- Programmable interrupt (IT) generation on key events
- Event detection on both key press and key release
- Multi-key press detection and decoding
- Long key detection on prolonged key press
- Programmable time-out on permanent key press or after keyboard release
5.3.4 Signals and I/O Description
Figure shows a typical 5*5 keyboard connection to the M27 keyboard controller.
Matrix Keyboard
KBR0
KBR1
KBR2
KBR3
KBR4
M27
KBC0
Module
KBC1
KBC2
KBC3
KBC4
5.3.5 Key Mapping
Š2007 B e n Q
C0
C1
C2
C3
C4
R0
Select
Up
Down
Dial
Return
R1
Vol+
SMS
R2
Vol-
ESC
R3
Re-Dial
Del
R4
Handfree
Set
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5.4.
LCM (SPI interface)
M27 Provides SPI LCM interface for customer application, it gives you the flexibility to develop
customized application, and this reference circuit is our recommendation.
Pin Name
Pin Out
Pull
Reset
Config Description
3.3_EXT
61
Power Supply for LCM & Back light LED
LCM_CS
49
Chip Select \ Chip Select A
LCM_SDO
51
Serial input data \ Serial Input Data
LCM_D/Cn
53
Register select Input pin
(Data/Instruction) \ Read signal
LCM_CLK
55
Serial Input clock \ Write signal
LCM_RST
57
Reset Input Pin \ Chip Select B
LEDB
11
Back light LED Sink
5.4.1 Reference schematics
5.4.2 Dot Matrix LCM spec
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Dot Matrix LCM spec
SHENZHEN WELLST WGM12864COG-21
9 2 .0
General specifications
3 .0
8 6 .0
7 1 .1
6 5 . 5V . A
43 . 0
M A X
8 .0
1 .6
1 1 .5
8 .0
2 6 .0
3 8 .0V . A
3 5 .0
3 0. 0
0 . 47 5
2 . 54X 7 = 2 0. 3 2
M A X
6 4. 0
1 2 .0
1 3 0
1 4.0
5 2 . 0Âą 0. 2
0. 45
1 9. 0
0. 49
5 7 .0
48 . 3
2 0. 0
0. 5 1 5
1 0.5
DOT S: 1 2 8 *6 4
Display format: 128 * 64 dot matrix graphic
Microprocessor interface: Serial
Power level: 3.3V
Module size: 92 x 57X8 mm
Definition of Terminals
Pin No.
Symbol
Level

8 .0
6 .0
Function
CS1B
Chip select
RES1B
D/C
H/L
Reset input pin
Register select input pin (Data/Instruction )
SCK
H/L
Serial input clock
SDA
H/L
Serial input data
VCC
3.0V
GND
0V
Ground
LED-
0V
Power supply for LED
LED+
3V
Power supply for LED
Power supply for lcm
5.4.2 7 Segment LCM spec
7 segment LCM spec
 
 
General specifications
Display format: 29 Digit(7 segment)+24 Prompt
Microprocessor interface: Serial
Power level: 3.3V
Module size: 115.5 x 48X12 mm
Definition of Terminals
Pin No.
Symbol
VDD
3.3V
Main Power
GND
0V
Ground
DATA
CMOS (In) (Pull up)
Serial input data
/WR
CMOS (In) (Pull up)
Write signal (Rising edge trigger)
/RD
CMOS (In) (Pull up)
Read signal (Rising edge trigger)
/CSA
CMOS (In) (Pull up)
Chip Select A
/CSB
CMOS (In) (Pull up)
Chip Select B
LED+
3.3V
Power supply for LED
LED-
0V
sink pin for LED
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Function
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5.5.
LCM (parallel bus interface)
M27 provides parallel bus (8 bit) LCM interfaces for customer application.
It gives you the
flexibility to develop customized application, and a reference circuit is provided here.
LCM parallel bus signal pins of M27 module
Pin Name
Pin Out
Pull
Reset
Config Description
DATA/ADD0
64
Bit 0 for Data bus
DATA/ADD1
66
Bit 1 for Data bus
DATA/ADD2
68
Bit 2 for Data bus
DATA/ADD3
70
Bit 3 for Data bus
DATA/ADD4
72
Bit 4 for Data bus
DATA/ADD5
74
Bit 5 for Data bus
DATA/ADD6
76
Bit 6 for Data bus
DATA/ADD7
78
Bit 7 for Data bus
RnW
80
Write signal
nMOE
62
Read signal
GPIO37
32
A0==>Command/Data
GPIO14
34
Reset
3.3V_EXT
61
3.3V power supply
5.5.1 Reference schematics (LCM connector pins on M27 EVB)
P18V
Reset
J404
P18V
3.3V_EXT
DATA_ADD6_PAD
DATA_ADD4_PAD
DATA_ADD2_PAD
DATA_ADD0_PAD
RnW_PAD
GPIO14
X1
X2
11
13
15
17
19
21
23
11
13
15
17
19
21
23
10
12
14
16
18
20
22
24
GND
DATA_ADD7_PAD
DATA_ADD5_PAD
DATA_ADD3_PAD
DATA_ADD1_PAD
nMOE_PAD
GPIO37
A0==>Command/Data
nCS1_PAD
VBAT
10
12
14
16
18
20
22
24
Y1
Y2
LCD 8bit connector
GND
Š2007 B e n Q
C o r p o r a t io n
M 27 U s e r M a n u a l
VBAT
C150
0.1U K
GND
21
C o n f id e n t ia l P r o p e r t y
V e r s i o n : 0. 1
- 2007/ J u l / 3 0
Level shifters between M27 pins and LCM connector
P1V8_M27
DATA_ADD7
DATA_ADD6
DATA_ADD5
DATA_ADD4
DATA_ADD3
DATA_ADD2
DATA_ADD1
DATA_ADD0
U4
ADG3308BRUZ-REEL
20
2 VCCAVCCY 19
A1
18
Y 2 17
4 A2
Y 3 16
5 A3
Y 4 15
6 A4
Y 5 14
7 A5
Y 6 13
8 A6
Y 7 12
9 A7
Y 8 11
3.3V_EXT 10 A8
EN
GND
3.3V_EXT
DATA_ADD7_PAD
DATA_ADD6_PAD
DATA_ADD5_PAD
DATA_ADD4_PAD
DATA_ADD3_PAD
DATA_ADD2_PAD
DATA_ADD1_PAD
DATA_ADD0_PAD
GND
P1V8_M27
RnW
ADD16
ADD17
ADD18
ADD19
nCS1
nCS2
nMOE
U3
ADG3308BRUZ-REEL
20
2 VCCAVCCY 19
A1
Y1
18
Y2 17
4 A2
Y3 16
5 A3
Y4 15
6 A4
Y5 14
7 A5
Y6 13
8 A6
Y7 12
9 A7
Y8 11
3.3V_EXT 10 A8
EN
GND
3.3V_EXT
RnW_PAD
ADD16_PAD
ADD17_PAD
ADD18_PAD
ADD19_PAD
nCS1_PAD
nCS2_PAD
nMOE_PAD
GND
Š2007 B e n Q
C o r p o r a t io n
M 27 U s e r M a n u a l
22
C o n f id e n t ia l P r o p e r t y
V e r s i o n : 0. 1
- 2007/ J u l / 3 0
5.5.2 Dimension and Pin assignment for parallel bus type LCM (YMC240160-04AAAYDGL)
Š2007 B e n Q
C o r p o r a t io n
M 27 U s e r M a n u a l
23
C o n f id e n t ia l P r o p e r t y
V e r s i o n : 0. 1
- 2007/ J u l / 3 0
Pin assignment of parallel bus type LCM (YMC240160-04AAAYDGL)
5.6.
Touch screen controller
For USB charger application, there are two choices for the touch screen controller with SPI
interface or I2C interface.
5.6.1 SPI type touch screen controller(MTK MT6301)
+Vcc
DCLK
X+
nCS
Y+
Din
XBusy
YDout
GND PenIRQ
VBAT IOVdd
AUX
Vref
GND
X1 6
Y1 7
0.1U K X2 8
Y2 9
GND10
11
12
C146
17
3.3V_EXT
U25
MT6301
16
15
14 3.3V_EXT
13
C147
R167
R168
R169
R171
0 0402
0 0402
0 0402
0 0402
LCM_CLK
LCM_CS
LCM_SDO
LCM_SDI
PenIRQ
R173
47K J
0.1U K
GND
GND
Š2007 B e n Q
C o r p o r a t io n
M 27 U s e r M a n u a l
24
C o n f id e n t ia l P r o p e r t y
V e r s i o n : 0. 1
- 2007/ J u l / 3 0
1
3 LCM_CLK_CON
U15
PMGD280UN
P1V8_M27
10K J
10K J
R76
S1
D1
G1
G2
D2
S2
LCM_CLK
LCM_CLK
LCM_CS
LCM_SDO
10K J R77
10K J
R78
3.3V_EXT
R79
LCM_SDI
3 LCM_SDI_CON
3 LCM_CS_CON
P1V8_M27
10K J
10K J
U13
PMGD280UN
S1
R68
R70
G1
G2
D2
S2
LCM_CS
D1
10K J R69
3.3V_EXT
10K J
R71
3 LCM_SDO_CON
LCM_SDO
5.6.2 I2C type touch screen controller(TI TSC2003)
U28
3.3V_EXT
C149
X1 2
Y1 3
0.1U K X2 4
Y2 5
GND 6
TSC2003
+Vdd
IN1
X+
IN2
Y+
A0
XA1
YSCL
GND
SDA
Vbat1PENIRQ
Vbat2
Vref
16
15
14
13
12
11
10
GND
GND
I2C_SCL_PAD
I2C_SDA_PAD
PenIRQ
R172
47K J
C148
0.1U K
3.3V_EXT
GND
3.3V_EXT
R164
150K
R166
10K J
R165
10K J
I2C_SCL_PAD
I2C_SDA_PAD
C o r p o r a t io n
M 27 U s e r M a n u a l
EN
GND
Vref 2 Vref 1
SCL2 SCL1
SDA2 SDA1
GND
C144
C145
0.1U K
0.1U K
GND
Š2007 B e n Q
P1V8_M27
U22
PCA9306DCTR
25
I2C_SCL
I2C_SDA
GND
C o n f id e n t ia l P r o p e r t y
V e r s i o n : 0. 1
- 2007/ J u l / 3 0
5.7.
Paging Indicator
LEDA is dedicated for paging indication. The application circuit is shows as below. The diagram
below illustrates the application schematic for LED driver inputs LEDA. In each case the current
limiter resistor R has to be selected in order to be compliant with maximum current drive capability of
each input.
Name
Pin
LEDA
Max drive
current
20mA
Highest level
voltage
VBATBB
Lowest level supply
Description
voltage
2.4
VBATBB paging indicator
560
LEDA is controlled through software program using a dedicated GPIO, which is built in the M27
module, it can write program to control the LED pin state.
5.8.
Camera interface
The camera interface supports data in ITU-R BT.656 format. The ITU-R BT.656 Standard specifies
a method for transferring YUV422 data over an 8-bit interface. The Parallel Camera module can provide
a Camera Reference clock (CAM_XCLK) to the camera sensor based on on-chip APLL (48MHz) clock
sources
CAM_PWDN
10K J
R160
P1V8_M27
10K J
R162
U20
PMGD280UN
S1
D1
G1
G2
D2
S2
CAM_PWDN_PAD
10K J
R161
3.3V_EXT
10K J
R163
3.3V_EXT
3,5,7,8
nCAM_RST
nCAM_RST_PAD
Š2007 B e n Q
C o r p o r a t io n
M 27 U s e r M a n u a l
26
C o n f id e n t ia l P r o p e r t y
V e r s i o n : 0. 1
- 2007/ J u l / 3 0
3.3V_EXT
R164
150K
R166
10K J
R165
10K J
I2C_SCL_PAD
I2C_SDA_PAD
P1V8_M27
U22
PCA9306DCTR
EN
GND
Vref 2 Vref 1
SCL2 SCL1
SDA2 SDA1
GND
C144
C145
0.1U K
0.1U K
I2C_SCL
I2C_SDA
GND
GND
CAM_DB5_PAD
CAM_DB4_PAD
CAM_DB3_PAD
CAM_DB2_PAD
41
40
38
37
48
CAM_DB1_PAD
CAM_DB0_PAD
36
35
33
32
25
30
29
27
26
24
2A0
2A1
2A2
2A3
2OE
4A0
4A1
4A2
4A3
4OE
C142
C143
0.1U K
0.1U K 0.1U K 0.1U K
GND
1Y0
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
2Y3
3Y0
3Y1
3Y2
3Y3
3A0
3A1
3A2
3A3
3OE
C141
4Y0
4Y1
4Y2
4Y3
CAM_HS
CAM_LCLK
CAM_DB7
CAM_DB6
11
12
CAM_DB5
CAM_DB4
CAM_DB3_CAM_VS 3
CAM_DB2
13
14
16
17
CAM_DB1
CAM_DB0
19
20
22
23
SN74LVCH162244AGR
10
15
21
28
34
39
45
GND
1A0
1A1
1A2
1A3
1OE
C140
Gnd1
Gnd2
Gnd3
Gnd4
Gnd5
Gnd6
Gnd7
Gnd8
CAM_HS_PAD
CAM_LCLK_PAD
CAM_DB7_PAD
CAM_DB6_PAD
CAM_PWDN_PAD
47
46
44
43
Vcc1
Vcc2
Vcc3
Vcc4
U21
18
31
42
P1V8_M27
GND
Š2007 B e n Q
C o r p o r a t io n
M 27 U s e r M a n u a l
27
C o n f id e n t ia l P r o p e r t y
V e r s i o n : 0. 1
- 2007/ J u l / 3 0
P1V8_M27C70
3.3V_EXT
C71
0.1U K
0.1U K
GND
U27
VCCA
3 CAM_XCLK
VCCB
GND
DIR
CAM_XCLK_PAD
P1V8_M27
SN74AVC1T45Y ZPR
GND
J403
GND
CAM_HS_PAD
CAM_VSYNC
CAM_PWDN_PAD
CAM_LCLK_PAD
P2V5
P1V8_M27
I2C_SDA_PAD
CAM_XCLK_PAD
I2C_SCL_PAD
C159
0.1U K
10
10
20
19
18
17
16
15
14
13
12
11
20
19
18
17
16
15
14
13
12
11
nCAM_RST_PAD
CAM_DB7_PAD
CAM_DB6_PAD
CAM_DB5_PAD
CAM_DB4_PAD
GND
CAM_DB3_PAD
CAM_DB2_PAD
CAM_DB1_PAD
CAM_DB0_PAD
DSC connector
GND
5.9.
NAND flash interface
The aim of this NAND flash controller is to have a fully automatic transfer process from/to
the NAND flash port. The interface implements an 8-bit parallel data bus (commands, addresses, and
data are multiplexed) in addition to the control signals for selecting chip, writing/reading, command and
address latching, and ready/busy status. The NAND flash chip used in M27 EVB is Samsung
K9F5608U0D-JIB0 FBGA (32M x 8 Bit Memory).It is necessary to add 2 pcs of bi-directional level
shifter to interface the M27 and the NAND flash chip.
P1V8_M27
NDF_0_M25
NDF_1_M25
NDF_2_M25
NDF_3_M25
NDF_4_M25
NDF_5_M25
NDF_6_M25
NDF_7_M25
U31
ADG3308BRUZ-REEL
20
2 VCCAVCCY 19
A1
Y1
18
Y2 17
4 A2
Y3 16
5 A3
Y4 15
6 A4
Y5 14
7 A5
Y6 13
8 A6
Y7 12
9 A7
Y8 11
3.3V_EXT 10 A8
EN
GND
3.3V_EXT
NDF_0
NDF_1
NDF_2
NDF_3
NDF_4
NDF_5
NDF_6
NDF_7
GND
Š2007 B e n Q
C o r p o r a t io n
M 27 U s e r M a n u a l
28
C o n f id e n t ia l P r o p e r t y
V e r s i o n : 0. 1
- 2007/ J u l / 3 0
P1V8_M27
U32
ADG3308BRUZ-REEL
20
2 VCCAVCCY 19
ND_RE_M25
A1
Y1
18
ND_CLE_M25
Y2 17
4 A2
ND_ALE_M25
A3
Y3 16
ND_RDY_M25
Y4 15
6 A4
ND_CE1_M25
A5
Y5 14
ND_WE_M25
Y6 13
8 A6
Y7 12
9 A7
Y8 11
3.3V_EXT 10 A8
EN
GND
3.3V_EXT
ND_RE
ND_CLE
ND_ALE
ND_RDY
ND_CE1
ND_WE
GND
3.3V_EXT
ND_WE
ND_ALE
ND_CLE
ND_CE1
ND_RE
ND_RDY
ND_WE
ND_ALE
ND_CLE
ND_CE1
ND_RE
ND_RDY
F6
G4
U2
A1
A5
A2
B3
A4
B2
A6
H1
H6
A3
/WP
/WE
ALE
CLE
/CE
/RE
R/B
VCC
VCCQ
3.3V_EXT
VSS
VSS
VSS
IO7
IO6
IO5
IO4
IO3
IO2
IO1
IO0
LOCKPRE
K9F5608U0D-JIB0
32MX8bit, 1.8V interface
Š2007 B e n Q
C o r p o r a t io n
M 27 U s e r M a n u a l
29
G6
H5
G5
H4
H3
H2
G2
F2
NDF_7
NDF_6
NDF_5
NDF_4
NDF_3
NDF_2
NDF_1
NDF_0
E6
NAND_PRE
NDF_7
NDF_6
NDF_5
NDF_4
NDF_3
NDF_2
NDF_1
NDF_0
R704
0 0402
C o n f id e n t ia l P r o p e r t y
V e r s i o n : 0. 1
- 2007/ J u l / 3 0
5.10. Micro SD interface
The micro-SD card SPI interface is compatible with SPI hosts available on the market. As any other
SPI device the micro-SD card SPI channel consists of the following 4 signals: CS, CLK, DI, DO
1.8V
C8
0.1uF
U7
CLK
CLK
VCCB
DIR
VRIO
SN74AVC1T45YZPR
C10
C11
0.1U K
0.1U K
3.3V
1.8V
GND
0.1uF
BGND
VCCA
BGND
3.3V
C9
CMD
CS
CMD
CS
VCCA
J1
A1
A2
GND
VCCB
B1
B2
12
DIR
P1V8
SN74LVC2T45DCUR
1.8V
3.3V
DATA
CARD DETECT
DATA
CARD DETECT
3.3V
C12
C13
0.1U K
0.1U K
U9
VCCA
A1
A2
GND
VCCB
B1
B2
DIR
Trans Flash card connector
CLK
DO/DATA
DI/CMD
CS
CARD DETECT
VDD
VSS
GND
GND
GND
GND
U8
10
R22
DNI_10K
SN74LVC2T45DCUR
Š2007 B e n Q
C o r p o r a t io n
M 27 U s e r M a n u a l
30
C o n f id e n t ia l P r o p e r t y
V e r s i o n : 0. 1
- 2007/ J u l / 3 0
6
UART Interface
UART/RS232
The UART includes the following additional features
- Hardware flow control (such as RTS/CTS) consists of two control signal lines between the Host
(DTE) and Client (DCE) that are used to control the flow of data between the devices.
- Auto-baud rate with the possibility of baud-rates ranging from 1200 to 115.2K bits.
Pin Name
TX
RX
RTS
CTS
Pin Out
24
26
28
30
Pull
PU
PD
Reset
Output / 1
Input
Input
Config
Description
UART-Transmit Data(M27 side)
UART-Receive Data(M27 side)
UART-Request To Send(M27 side)
UART-Clear To Send(M27 side)
Note: The difference between Reset and Config in the pin definition table
M27 only provide 1.8V UART interface. If the host (DTE) is 3.3V system, it needs additional Level
shifter circuit on EVB.
 HOST Device
VDD2=3.3V
VDD1=1.8V
(DTE)
 Client Device
M27 (DCE)
10K
10K
 TX
RX
RX
TX
RTS
CTS
CTS
DCD
Level shift
RTS
DCD
RI
RI
GND
GND
DSR
DTR
UART Interfaces
Š2007 B e n Q
C o r p o r a t io n
M 27 U s e r M a n u a l
31
C o n f id e n t ia l P r o p e r t y
V e r s i o n : 0. 1
- 2007/ J u l / 3 0
UART interface on M27
1.8V-3.3V level shifter for UART interface
Š2007 B e n Q
C o r p o r a t io n
M 27 U s e r M a n u a l
32
C o n f id e n t ia l P r o p e r t y
V e r s i o n : 0. 1
- 2007/ J u l / 3 0
UART transceiver ICL3237A
HW flow control
When the hardware flow control type is recommended for communication between the Host(DTE)
and client(DCE). Regarding the hardware flow control mechanism between the system (host side) and
module (client side).
The GSM engine is designed for use as a DCE. Based on the conventions for DCE-DTE Connections it
communicates with the customer application (DTE) using the following signals:
♦ Port/TX @ Host Device sends data to the module’s /RX signal line
♦ Port/RX @ Host Device receives data from the module’s /TX signal line
♦ Port/RTS @ Host Device sends data to the module’s /CTS signal line
♦ Port/CTS @ Host Device receives data from the module’s /RTS signal line
Š2007 B e n Q
C o r p o r a t io n
M 27 U s e r M a n u a l
33
C o n f id e n t ia l P r o p e r t y
V e r s i o n : 0. 1
- 2007/ J u l / 3 0

HOST
Device
Client
Device
TX
TX
RX
RX
RTS
RTS
CTS
CTS
DCD
DCD
RI
RI
GND
GND
DSR
DTR
Auto baud Rate Mechanism
The M27 module UART is set at Auto-baud rate. This means when the M27 is powered on, it
automatically detects the baud rate after the first AT command sent by the host Device. The baud rate is
locked at the initially detected rate unless the following conditions:
Š2007 B e n Q
C o r p o r a t io n
M 27 U s e r M a n u a l
34
C o n f id e n t ia l P r o p e r t y
V e r s i o n : 0. 1
- 2007/ J u l / 3 0
6.1 Dual external UART solution
M27 support 1 UART interface. M27 module support 4 bit address and 8 bit data bus with some
associated control lines. The memory bus is Intel interface with 2 independent Read/Write control lines.
For dual external UART port, there are 2 chips which are pin-to-pin compatible, except the ground plane.
The one is the NXP SC16C852L, the other is EXAR XR16M2550. The function blocks and reference
schematics are shown below. For single external UART solution, please refer to section 6.2.
Dual UART interface NXP SC16C852L
1.8 V dual UART, 5 Mbit/s (max.) with 128-byte FIFOs, parallel bus interface
Package HVQFN32(5x5mm), LQFP48(9x9mm)
Š2007 B e n Q
C o r p o r a t io n
M 27 U s e r M a n u a l
35
C o n f id e n t ia l P r o p e r t y
V e r s i o n : 0. 1
- 2007/ J u l / 3 0
Dual UART interface EXAR XR16M2550
HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO
Package 32 PIN QFN(5x5mm), 48 PIN TQFP (9x9mm)
Level shifter
EXAR XR16M2550 / NXP SC16C852L
A[0..2]
A[0..2]
IOR#
IOW#
UART_CSA#
UART_CSB#
UART_INTA
UART_INTB
UART_RESET
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
IOR#
IOW#
UART_CSA#
UART_CSB#
UART_INTA
UART_INTB
UART_RESET
XTAL1
XTAL2
NC
NC
33
R8
U1
GND
R11 576K J
27
28
29
30
31
32
20
19
18
14
12
22
21
24
10
11
0 ohm 9
17
X1 24MHz
VCC
TXA
RXA
RTSA#
CTSA#
TXB
RXB
RTSB#
CTSB#
26
1.8V
1.8V
10K J
R2
R4
U2
PMGD280UN
S1
D1
G1
G2
D2
S2
UART_TXA
10K J R1
3.3V
10K J
R5
23
UART_RXA
25
1.8V
10K J
10K J
15
R7
R9
U4
PMGD280UN
S1
D1
G1
G2
D2
S2
UART_RSTA
10K J R6
3.3V
10K J
R10
16
UART_CTSA
1.8V
C6
22P J
10K J
GND
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
13
D[0..7]
D[0..7]
C7
22P J
10K J
10K J
R13
R14
U5
PMGD280UN
S1
D1
G1
G2
D2
S2
UART_TXB
10K J R12
3.3V
10K J
R15
UART_RXB
1.8V
10K J
10K J
R19
R20
U6
PMGD280UN
S1
D1
G1
G2
D2
S2
UART_RSTB
10K J R17
3.3V
10K J
R21
UART_CTSB
Š2007 B e n Q
C o r p o r a t io n
M 27 U s e r M a n u a l
36
C o n f id e n t ia l P r o p e r t y
V e r s i o n : 0. 1
- 2007/ J u l / 3 0
3.3V
C1
3.3V_EXT
10U 6.3V
3,5,7,9
R3
0 J 0603
U3
26
UART
14
15
13
UART_TXA
UART_RSTA
UART_TXB
24
23
22
19
17
UART_RXA
UART_CTSA
UART_RXB
21
20
18
M27 SIDE(DCE)
UART
16
VCC
C1+
C1-
GND
SHDN
MBAUD
C2+
C2V+
V-
EN
T1IN
T2IN
T3IN
T4IN
T5IN
T1OUT
T2OUT
T3OUT
T4OUT
T5OUT
R1OUT
R2OUT
R3OUT
R1IN
R2IN
R3IN
R1OUTB
ICL3237CA
28
25
C2
0.47U M
C3
0.47U M
27
C4
0.47U M
C5
0.47U M
10
12
RXD
CTS
RS232_RX2
RI
DCD
11
TXD
RTS
RS232_TX2
PC SIDE(DTE)
PC SIDE(DTE)
3.3V_EXT
R16
N/A
R18
0 J 0603
DCD
DSR
RXD
RTS
TXD
CTS
DTR
RI
GND
UART
PORT1
D-SUB9 FEMALE
RS232_RX2 2
RS232_TX2 3
UART
PORT2
D-SUB9 FEMALE
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6.2 Single external UART solution
For single external UART solution, there are two options: the one is NXP SC16C850LIET, the other
is EXAR XR16L570IL24. The function block and reference schematics are shown below:
6.2.1
Single external UART solution: NXP SC16C850LIET
Single UART interface NXP SC16C850LIET
1.8 V single UART, 5 Mbit/s (max.) with 128-byte FIFOs parallel bus interface
Package TFBGA36(3.5x3.5mm), HVQFN32( 5x5mm)
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1.8V
IOR#
A3
IOW#
B4
F1
UART_RESET
D0
D1
D2
D3
D4
D5
D6
D7
VDD
F4
E4
F5
E5
F6
E6
D6
D5
VDD
D[0..7]
D0
D1
D2
D3
D4
D5
D6
D7
TX
SC16C850LIET
RX
RTS
CTS
IOR
IOW
DTR
RI
RESET
CD
A[0..2]
D1
INT
N.C.
N.C.
1.8V
C6
10K J
10K J
R52
R53
S1
D1
G1
G2
D2
S2
UART_TXB
10K J R51
3.3V
10K J
R54
D2
UART_RXB
D3
E1
Note : UART_TXA, UART_RXA, UART_RSTA,
UART_CTSA are from M27
F3
E3
F2
A2
A4
B2
B3
E2
VSS
UART_INTA
N.C.
LOWPWR
VSS
B5
N.C.
C5
U18
PMGD280UN
C4
UART_LOWPWR
N.C.
CS
C2
B6
A0
A1
A2
A5
UART_CSA#
DSR
XTAL1
C1
C3
B1
XTAL2
A0
A1
A2
A6
A[0..2]
A1
U16
D[0..7]
D4
C22
0.1U K
R57 0 ohm
R58 576K J
X3 24MHz
C27
22P J
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C28
22P J
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6.2.2
Single external UART solution: EXAR XR16L570IL24
Single UART interface EXAR XR16L570IL24
SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
Package 24 PIN QFN(4x4mm), 32 PIN QFN(5x5mm)
A[0..2]
A[0..2]
IOR#
IOW#
UART_CSA#
UART_INTA
3.3V
UART_RESET
Y1
VDD
OUT
GND
Cont
C20
U13
20
21
22
23
24
14
13
12
11
15
17
0.047U K
XR16L570IL24
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
IOR#
IOW#
UART_CS#
PwrSave
UART_INT
UART_RESET
CLK
VCC
TXA
RXA
RTS#
CTS#
19
1.8V
1.8V
10K J
10K J
R45
R46
U14
PMGD280UN
S1
D1
G1
G2
D2
S2
UART_TXB
10K J R44
3.3V
10K J
R47
16
UART_RXB
18
GND
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
10
D[0..7]
D[0..7]
24MHZ
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7
USB Interface
USB signals are transmitted on a twisted pair of data cables, labeled D+ and D−. These collectively
use half-duplex differential signaling to combat the effects of electromagnetic noise on longer lines. D+
and D− usually operate together; They are not separate simplex connections. Transmitted signal levels
are 0.0–0.3 volts for low and 2.8–3.6 volts for high.
The USB supports three data rates
- Low Speed rate of 1.5 M bit/s (183 KiB/s).
- Full Speed rate of 12 M bit/s (1.5 MiB/s).
USB connector pin out
Pin
Mini Function
M27
VBUS (4.4–5.25 V)
VBUS (2.7–5.25 V)
D−
USB_DM
D+
USB_DP
ID
Ground
Pin Name
VBUS
USB_DP
USB_DM
Pin Out
16
18
20
Pull
PD
Ground
Reset
Config
Description
Power Supply VBUS line
USB data bus (positive terminal)
USB data bus (negative terminal)
Note: The difference between Reset and Config in the pin definition table
Host Device
Š2007 B e n Q
EVB
M27
VBUS
VBUS
VBUS
USB_DM
USB_DM
USB_DM
USB_DP
USB_DP
USB_DP
ID
ID
GND
GND
C o r p o r a t io n
M 27 U s e r M a n u a l
GND
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7.1 USB charger solution
For USB charger application, our suggestion is to use the Linear Technology LTC4067 as the
Li-ion battery charger.
This chip manages the power supplies that would be typical for a USB powered device or from an
adaptor to an intermediate voltage bus. The battery charger is a CC/CV timer terminated type capable of
charge currents up to 1.25A. The adaptor input has over-voltage protection to 13V. An external MOSFET
will disconnect the adaptor if the voltage exceeds 6V; protecting the input against damage in case an
unregulated adaptor is accidentally plugged in.
C192TBKT-B
U8
SI2343DS
C125
0.47U K
0.01U K
C14
10U 6.3V
R26
10K J
ILIM0
ILIM1
TR_10K
(0402)
GATE
IN
BAT
NTC
ILIM0
PROG
ILIM1
TR1
OUT
OVI
OVP
CLPROG
R28
2K J
100 J
LTC4067EDE
CHRG
12
VBUS
R25
GND
C108
Q2
11
GSM/GPRS module
C13
10U 6.3V
10
1 Cell Li-ion battery
R27
2K J
Actual charge current
Ibat=Vprog/2k
13
Wall input
4.35V~6V
D1
Note : ILIM0,ILIM1 are 1.8V interface
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8
GPIO MAPPING
The module provides 4 independent GPIO pins configurable in read or write mode. The function for
these I/O pins is List below.
Pin Name Pin No
I/O
PU
Reset
Config
Description
GPIO 1
87
I/O
PU
Input Low
General purpose I/O 1
GPIO 10
60
I/O
PU
Input Low
General purpose I/O 10
GPIO 14
34
I/O
PD
Input Low
General purpose I/O 14
GPIO 37
32
I/O
Input Float
General purpose I/O 37
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9
Level Shifter Design
9.1 Introduction
The bi-directional level shifter circuit described in this application note consists of one discrete
MOS-FET for each bus line. In spite of its surprising simplicity, it not only fulfils the requirement of
bi-directional level shifting without a direction control signal, but it also has the next additional features:
- Isolating of a powered-down bus section from the rest of the bus system,
- Protection of the “Lower voltage” side against high voltage spikes at the ‘Higher voltage” side.
The bi-directional level shifter can be used in standard mode (0 to 100 kbit/s) or in fast mode (0 to 400
kbit/s) I2C-bus systems, without any change. The following descriptions apply for both modes.
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10. Layout notice
10.1 THT hole and pad size for 2x7 connector
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11. Antenna Interface
11.1 Antenna Installation & Consideration
M27 is capable of sustaining a total mismatch at the antenna pad without any damage, even when
transmitting at maximum RF power. The RF interface has an impedance of 50Ω. M27 must be applied
to 50 ohm load/ antenna, or else the output power will degrade seriously. Antenna supplier needs to
ensure that the impedance of the operating frequency range is closed to 50Ω.
The external antenna must be matched properly to achieve best performance regarding radiated
power, DC-power consumption, modulation accuracy and harmonic suppression. Antenna matching
networks are not included on the M27 PCB and should be placed in the host application.
Due to the Antenna selection is more important for the wireless performance, this application will
provide the Antenna requirements for mobile quad-band modules (GSM850. EGSM, DCS and PCS)
(Table11.1~Table11.4).
Table11.1. Frequency Bands
Item
Description
Requirement
Transmit Bands (TX)
GSM850: 869 ~ 894 MHz
EGSM: 880 ~ 915 MHz
DCS: 1710 ~ 1785 MHz
PCS: 1850 ~ 1910 MHz
Receive Bands (RX)
GSM850: 824 ~ 849 MHz
EGSM: 925 ~ 960 MHz
DCS: 1805 ~ 1880 MHz
PCS: 1930 ~ 1990 MHz
Table11.2. VSWR
Item
Description
VSWR
Š2007 B e n Q
Measurement
C o r p o r a t io n
M 27 U s e r M a n u a l
Requirement
 2 : 1
Network analyzer is used to measure
VSWR, and the result must be measured
with the matching circuit provided by
Antenna vendor.
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Table11.3. Gain
Item
Description
Average gain
Requirement
 0 dBi
 0.5 dBi
Peak gain
Measurement
The gain deviation (Peak gain – minimum
gain) of all angles in H-plane should be less
than 4dB in low, middle and high channels.
The higher gain in DCS/PCS band would
be preferred.
The same as the Table11.2 item2. measure
the radiation pattern at the lowest, middle
and highest frequency for each band. And it
must be measured in Chamber, including
XY, XZ and YZ planes.
Table11.4. Power Rating
Item
Description
.Maximum Value:
2W(CW)
A 50 coaxial cable is connected to the 50
 feeding point on the PCB. The power is
Measuring Method
applied for 10 minutes at the middle
frequency of each Tx band. After the test
then measure the VSWR.
Š2007 B e n Q
Criteria
C o r p o r a t io n
M 27 U s e r M a n u a l
Requirement
The antenna shall satisfy the VSWR as
described in Table11.2. No visual deterioration shall occur during or after the test.
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11.2 Antenna Pad & Cable Soldering
The antenna can be soldered to the antenna pad. For proper grounding connect the
antenna to the ground plane on the bottom of M27 which must be connected to the ground
plane of the application.(Fig.11.1)
Notes on soldering:
To prevent damage to the module and to obtain long-term solder joint properties you are
advised to maintain the standards of good engineering practice for soldering.
Be sure to solder the antenna core to the pad and the shielding of the coax cable to the
ground plane of the module next to the antenna pad. The direction of the cable is not
relevant from the electrical point of view.
M27 material properties:
M27 PCB: FR4
Antenna pad: Gold plated pad
Antenna Pad
Antenna Cable
Fig.11.1 Antenna Pad & Cable Soldering
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Š2007 B e n Q
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