Realtek Semiconductor RTL8187SE 802.11b/g RTL8187SE miniCard User Manual xRTL8187SE DataSheet 1 0 11 DRAFT

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RTL8187SE
SINGLE-CHIP WIRELESS LAN NETWORK
INTERFACE CONTROLLER w/PCI EXPRESS
INTERFACE
DATASHEET
Rev. 1.0
16 January 2008
Track ID: JATR-1076-21
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com.tw
RTL8187SE
Datasheet
COPYRIGHT
©2008 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any langµAge in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied,
including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in
this document or in the product described in this document at any time. This document could include
technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are
trademarks/registered trademarks of their respective owners.
CONFIDENTIALITY
This document is confidential and should not be provided to a third-party without the permission of Realtek
Semiconductor Corporation.
USING THIS DOCUMENT
This document is intended for the software engineer’s reference and provides detailed programming
information.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide. In that event, please contact your
Realtek representative for additional information that may help in the development process.
REVISION HISTORY
Revision
1.0
Release Date
2008/01/16
Summary
First release.
Single-Chip Wireless LAN Network Interface Controller
w/PCI Express Interface
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RTL8187SE
Datasheet
Table of Contents
1.
GENERAL DESCRIPTION ...............................................................................................................................................1
2.
FEATURES ..........................................................................................................................................................................3
3.
SYSTEM APPLICATIONS ................................................................................................................................................4
4.
BLOCK DIAGRAMS ..........................................................................................................................................................5
5.
PIN ASSIGNMENTS...........................................................................................................................................................7
5.1.
6.
PACKAGE IDENTIFICATION ..............................................................................................................................................7
PIN DESCRIPTIONS ..........................................................................................................................................................8
6.1.
6.2.
6.3.
6.4.
6.5.
6.6.
6.7.
6.8.
POWER MANAGEMENT/ISOLATION INTERFACE ...............................................................................................................8
PCI EXPRESS INTERFACE ................................................................................................................................................8
EEPROM INTERFACE .....................................................................................................................................................9
POWER PINS ....................................................................................................................................................................9
LED INTERFACE............................................................................................................................................................10
BASEBAND AND RF PINS ...............................................................................................................................................10
BLUETOOTH CO-EXISTENCE PINS .................................................................................................................................11
CLOCK AND OTHER PINS ...............................................................................................................................................11
7.
EEPROM (93C46 OR 93C56) CONTENTS ....................................................................................................................11
8.
PCI EXPRESSTM ................................................................................................................................................................12
8.1. PCI EXPRESS BUS INTERFACE ....................................................................................................................................12
8.1.1.
PCI Express Transmitter ......................................................................................................................................12
8.1.2.
PCI Express Receiver ...........................................................................................................................................12
8.2. PCI CONFIGURATION SPACE TABLE ..............................................................................................................................13
8.3. PCI CONFIGURATION SPACE FUNCTIONS ......................................................................................................................16
8.4. PCI CONFIGURATION SPACE STATUS ............................................................................................................................17
8.4.1.
Status ....................................................................................................................................................................17
8.4.2.
RIDR (Revision ID Register) ................................................................................................................................18
8.4.3.
PIFR (Programming Interface Register)..............................................................................................................18
8.4.4.
SCR (Sub-Class Register).....................................................................................................................................18
8.4.5.
BCR (Base-Class Register)...................................................................................................................................18
8.4.6.
CLS (Cache Line Size)..........................................................................................................................................18
8.4.7.
LTR (Latency Timer Register) ..............................................................................................................................18
8.4.8.
HTR (Header Type Register)................................................................................................................................18
8.4.9.
BIST (Built-In Self-Test) .......................................................................................................................................18
8.4.10. IOAR (Input Output Address Register).................................................................................................................19
8.4.11. MEMAR (Memory Address Register) ...................................................................................................................19
8.4.12. CISPtr (CardBus Card Information Structure Pointer) .......................................................................................19
8.4.13. SVID (Subsystem Vendor ID) ...............................................................................................................................20
8.4.14. SMID (Subsystem ID)...........................................................................................................................................20
8.4.15. ILR (Interrupt Line Register)................................................................................................................................20
8.4.16. IPR (Interrupt Pin Register).................................................................................................................................20
8.4.17. MNGNT (Minimum Grant Timer: Read only)......................................................................................................20
8.4.18. MXLAT (Maximum Latency Timer: Read only) ...................................................................................................20
8.5. DEFAULT VALUE AFTER POWER-ON (RSTB ASSERTED)..............................................................................................20
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8.6. PCI POWER MANAGEMENT FUNCTIONS ........................................................................................................................22
8.7. MESSAGE SIGNALED INTERRUPT (MSI) ........................................................................................................................25
8.7.1.
MSI Capability Structure in PCI Configuration Space ........................................................................................25
8.7.2.
Message Control...................................................................................................................................................26
8.7.3.
Message Address ..................................................................................................................................................26
8.7.4.
Message Upper Address.......................................................................................................................................27
8.7.5.
Message Data .......................................................................................................................................................27
9.
FUNCTIONAL DESCRIPTION ......................................................................................................................................28
9.1. TRANSMIT & RECEIVE OPERATIONS .............................................................................................................................28
9.1.1.
Transmit ...............................................................................................................................................................28
9.1.2.
Receive .................................................................................................................................................................35
9.2. LOOPBACK OPERATION .................................................................................................................................................39
9.3. QOS FUNCTIONS ...........................................................................................................................................................39
9.4. LED FUNCTIONS ...........................................................................................................................................................39
10.
APPLICATION DIAGRAM .........................................................................................................................................40
11.
ELECTRICAL CHARACTERISTICS........................................................................................................................41
11.1.
TEMPERATURE LIMIT RATINGS .................................................................................................................................41
11.2.
DC CHARACTERISTICS ..............................................................................................................................................41
11.3.
AC CHARACTERISTICS ..............................................................................................................................................42
11.3.1. Serial EEPROM Interface Timing (93C46(64*16)/93C56(128*16))...................................................................42
11.4.
PCI EXPRESS BUS PARAMETERS ...............................................................................................................................43
11.4.1. Differential Transmitter Parameters ....................................................................................................................43
11.4.2. Differential Receiver Parameters.........................................................................................................................44
11.4.3. REFCLK Parameters ...........................................................................................................................................44
11.4.4. Auxiliary Signal Timing Parameters ....................................................................................................................48
12.
MECHANICAL DIMENSIONS ...................................................................................................................................49
13.
ORDERING INFORMATION .....................................................................................................................................50
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List of Tables
TABLE 1. POWER MANAGEMENT/ISOLATION INTERFACE ..............................................................................................................8
TABLE 2. PCI EXPRESS INTERFACE ...............................................................................................................................................8
TABLE 3. EEPROM INTERFACE ....................................................................................................................................................9
TABLE 4. POWER PINS ...................................................................................................................................................................9
TABLE 5. LED INTERFACE...........................................................................................................................................................10
TABLE 6. BASEBAND AND RF PINS ..............................................................................................................................................10
TABLE 7. BLUETOOTH CO-EXISTENCE PINS ................................................................................................................................11
TABLE 8. CLOCK AND OTHER PINS ..............................................................................................................................................11
TABLE 9. PCI CONFIGURATION SPACE TABLE .............................................................................................................................13
TABLE 10. COMMAND REGISTER IN PCI CONFIGURATION SPACE .................................................................................................16
TABLE 11. PCI CONFIGURATION SPACE STATUS...........................................................................................................................17
TABLE 12. INPUT OUTPUT ADDRESS REGISTER .............................................................................................................................19
TABLE 13. MEMORY ADDRESS REGISTER .....................................................................................................................................19
TABLE 14. PCI CONFIGURATION SPACE TABLE ............................................................................................................................20
TABLE 15. MESSAGE CONTROL.....................................................................................................................................................26
TABLE 16. MESSAGE ADDRESS .....................................................................................................................................................26
TABLE 17. MESSAGE UPPER ADDRESS ..........................................................................................................................................27
TABLE 18. MESSAGE DATA ...........................................................................................................................................................27
TABLE 19. TX DESCRIPTOR FORMAT (BEFORE TRANSMITTING, OWN=1, TX COMMAND MODE 1)................................................28
TABLE 20. TX STATUS DESCRIPTOR ..............................................................................................................................................30
TABLE 21. TX STATUS DESCRIPTOR (AFTER TRANSMITTING, OWN=0, TX STATUS MODE)...........................................................33
TABLE 22. TX STATUS DESCRIPTOR (AFTER TRANSMITTING, OWN=0, TX STATUS MODE)...........................................................34
TABLE 23. RX COMMAND DESCRIPTOR (OWN=1) .......................................................................................................................35
TABLE 24. RX COMMAND DESCRIPTOR (OWN=1) .......................................................................................................................35
TABLE 25. RX STATUS DESCRIPTOR (OWN=0) ............................................................................................................................36
TABLE 26. RX STATUS DESCRIPTOR..............................................................................................................................................37
TABLE 27. TEMPERATURE LIMIT RATINGS ....................................................................................................................................41
TABLE 28. DC CHARACTERISTICS .................................................................................................................................................41
TABLE 29. EEPROM ACCESS TIMING PARAMETERS ....................................................................................................................42
TABLE 30. DIFFERENTIAL TRANSMITTER PARAMETERS ................................................................................................................43
TABLE 31. DIFFERENTIAL RECEIVER PARAMETERS.......................................................................................................................44
TABLE 32. REFCLK PARAMETERS ...............................................................................................................................................44
TABLE 33. AUXILIARY SIGNAL TIMING PARAMETERS...................................................................................................................48
TABLE 34. ORDERING INFORMATION ............................................................................................................................................50
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Track ID: JATR-1076-21 Rev. 1.0
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Datasheet
List of Figures
FIGURE 1. BLOCK DIAGRAM ..........................................................................................................................................................5
FIGURE 2. RF BLOCK DIAGRAM ....................................................................................................................................................6
FIGURE 3. PIN ASSIGNMENTS.........................................................................................................................................................7
FIGURE 4. MESSAGE CAPABILITY STRUCTURE ............................................................................................................................25
FIGURE 5. APPLICATION DIAGRAM ..............................................................................................................................................40
FIGURE 6. SERIAL EEPROM INTERFACE TIMING ........................................................................................................................42
FIGURE 7. SINGLE-ENDED MEASUREMENT POINTS FOR ABSOLUTE CROSS POINT AND SWING ...................................................46
FIGURE 8. SINGLE-ENDED MEASUREMENT POINTS FOR DELTA CROSS POINT .............................................................................46
FIGURE 9. SINGLE-ENDED MEASUREMENT POINTS FOR RISE AND FALL TIME MATCHING ..........................................................46
FIGURE 10. DIFFERENTIAL MEASUREMENT POINTS FOR DUTY CYCLE AND PERIOD .....................................................................47
FIGURE 11. DIFFERENTIAL MEASUREMENT POINTS FOR RISE AND FALL TIME .............................................................................47
FIGURE 12. DIFFERENTIAL MEASUREMENT POINTS FOR RINGBACK..............................................................................................47
FIGURE 13. REFERENCE CLOCK SYSTEM MEASUREMENT POINT AND LOADING ...........................................................................48
FIGURE 14. AUXILIARY SIGNAL TIMING .......................................................................................................................................48
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Datasheet
1.
General Description
The Realtek RTL8187SE is a low-profile highly integrated cost-effective Single-Chip Wireless LAN
network interface controller that integrates a Wireless LAN MAC, a baseband processor, and 2.4GHz RF
onto one chip. It provides a PCI Express bus controller, and full compliance with IEEE 802.11 and IEEE
802.11b/g specifications. It also complies with WMM, 802.11e, and CCX specifications.
To reduce protocol overhead, the RTL8187SE supports Short InterFrame Space (SIFS) burst mode to send
packets back-to-back. A protection mechanism prevents collisions among 802.11b nodes.
Direct Sequence Spread Spectrum (DSSS), Complementary Code Keying (CCK), and Orthogonal
Frequency Division Multiplexing (OFDM) baseband processing are implemented to support all IEEE
802.11b, and 802.11g data rates. Differential phase shift keying modulation schemes, DBPSK and DQPSK
with data scrambling capability, are available, along with complementary code keying to provide data rates
of 1, 2, 5.5, and 11Mbps, with long or short preamble. A high-speed Fast Fourier Transform (FFT)/Inverse
Fast Fourier Transform (IFFT), combined with BPSK, QPSK, 16QAM and 64QAM modulation of the
individual sub-carriers, provides data rates of 6, 9, 12, 18, 24, 36, 48 and 54Mbps, with rate-compatible
punctured convolutional coding with a coding rate of 1/2, 2/3, and 3/4.
An enhanced signal detector, an adaptive frequency domain equalizer, and a soft-decision Viterbi decoder
are built-in to alleviate severe multipath effects. Efficient IQ-imbalance calibration, DC offset, phase noise,
frequency offset, and timing offset compensation reduce radio frequency front-end impairments. Selectable
digital transmit and receive FIR filters are provided to meet the requirements of transmit spectrum masks,
and to reject adjacent channel interference, respectively. Both in the transmitter and receiver,
programmable scaling in the digital domain trades the qµAntization noise against the increased probability
of clipping. Robust signal detection, symbol boundary detection, and channel estimation perform well at
the minimum sensitivity.
The RTL8187SE supports fast receiver Automatic Gain Control (AGC) and antenna diversity functions,
and an adaptive transmit power control function to obtain better performance in the analog portions of the
transceiver. It also has on-chip digital-to-analog converters and analog-to-digital converters for analog I
and Q inputs and outputs, transmit TSSI and receiver RSSI inputs, and transmit and receiver AGC outputs.
Single-Chip Wireless LAN Network Interface Controller
w/PCI Express Interface
Track ID: JATR-1076-21 Rev. 1.0
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Datasheet
It supports Advanced Configuration Power management Interface (ACPI), Legacy PCI power management,
and PCI Express power management for modern operating systems that are capable of Operating System
directed Power Management (OSPM). PCI MSI (Message Signaled Interrupt) function and PCI Express
Device Serial Number Capability are also supported.
In addition to the ACPI feature, the RTL8187SE also supports remote wake-up (including AMD Magic
Packet and Microsoft® wake-up frame) in both ACPI and APM environments. To support Wake on
Wireless LAN from a deep power down state (e.g., D3cold, i.e. main power is off and only auxiliary power
exists), the auxiliary power source must be able to provide the needed power. When auxiliary power is
applied and the main power remains off, the RTL8187SE is ready and waiting for a Magic Packet or
wake-up frame to wake the system up.
The RTL8187SE supports an enhanced link list descriptor-based buffer management architecture, which is
an essential part of a design for a modern network interface card. It contributes to lowering CPU utilization.
Also, the RTL8187SE features inter-connect PCI Express technology. PCI Express is a high-bandwidth,
low pin count, serial, interconnect technology that offers significant improvements in performance over
conventional PCI and also maintains software compatibility with existing PCI infrastructure. Support is
also provided for Multiple BSSID, Adjustable fallback steps and fallback rates during auto rate fallback,
TX Power Tracking, Enhanced three-wire mechanism, Parallel Control Interface between Baseband and
RF, and Bluetooth coexistence.
The RTL8187SE keeps network maintenance costs low and eliminates usage barriers. The RTL8187SE is
highly integrated and requires no ‘glue’ logic or external memory.
Single-Chip Wireless LAN Network Interface Controller
w/PCI Express Interface
Track ID: JATR-1076-21 Rev. 1.0
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Datasheet
2.
Features
Provides PCI Express bus data transfers
and PCI Express memory space or IO
space mapped data transfers of the
RTL8187SE’s operational registers
64-Pin QFN with ‘Green’ package
State machine implementation without
external memory (RAM, flash) requirement
Supports ACPI (Rev 1.0, 1.0b, 2.0)
Complies with IEEE 802.11b/g standards
Supports Wake-On-WLAN (WoWLAN)
function and remote wake-up (Magic Packet
and Microsoft® wake-up frame)
Supports descriptor-based buffer management
Integrated Wireless LAN MAC and Direct
Sequence Spread Spectrum/OFDM Baseband
Processor in one chip
Supports auxiliary power auto-detect, and sets
the related capability of power management
registers in PCI Express configuration space
Enhanced signal detector, adaptive frequency
domain equalizer, and soft-decision Viterbi
decoder to alleviate severe multipath effects
IEEE 802.11g protection mechanisms for both
RTS/CTS and CTS-to-self
Processing Gain compliant with FCC
Burst-mode support for dramatically enhanced
throughput
On-Chip A/D and D/A converters for I/Q Data,
AGC, and Adaptive Power Control
DSSS with DBPSK and DQPSK, CCK
modulations and demodulations supported
with long and short preamble
Supports both transmit and receive Antenna
Diversity
OFDM with BPSK, QPSK, 16QAM and
64QAM modulations and demodulations
supported with rate compatible punctured
convolutional coding with coding rate of 1/2,
2/3, and 3/4
Data rates of 1, 2, 5.5, 6, 9, 11, 12, 18, 24, 36,
48, and 54Mbps
Supports 40MHz OSC as the internal clock
source. The frequency deviation of the OSC
must be within 25ppm on IEEE 802.11g
Efficient IQ-imbalance calibration, DC offset,
phase noise, frequency offset and timing offset
compensation reduce analog front-end
impairments
PCI Express bus controller
Complies with PCI Express 1.1 and PCI
Express Mini Card Electromechanical
Specification Revision 1.1
Selectable digital transmit and receiver FIR
filters provided to meet transmit spectrum
mask requirements and to reject adjacent
channel interference
PCI power management Revision 1.2
Supports PCI Express Active State Power
Management (ASPM)
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Datasheet
Contains two large independent transmit and
receive FIFO buffers
Programmable scaling both in transmitter and
receiver to trade qµAntization noise against
the increased probability of clipping
Advanced power saving mode when the LAN
and wakeup function are not used
Fast receiver Automatic Gain Control (AGC)
& antenna diversity functions
Uses 93C46 (64*16-bit EEPROM) or 93C56
(128*16-bit EEPROM) to store resource
configuration and ID parameter data
Adaptive transmit power control function
Complies with WMM, 802.11e, and CCX
specifications
LED pins for various network activity
indications
Complies with 802.11i and 802.11j
specifications
Nine GPIO pins supported
Supports digital loopback capability on both
ports
Hardware-based IEEE 802.11i
encryption/decryption engine, including
64-bit/128-bit WEP, TKIP, and AES
Flexible RF transceiver interface for different
RF transceiver applications
Supports Wi-Fi alliance WPA and WPA2
security
Built-in 3.3V to 1.8V regulator
Supports a 32-bit general-purpose timer
3.3V power supply required
0.18m CMOS process
3.
System Applications
Wireless PCI Express adapter
Wireless notebook Mini Card adapter
Wireless system (wireless gateway router, wireless ADSL router, wireless set-top box etc.) with PCI
Express or Mini Card slot
Single-Chip Wireless LAN Network Interface Controller
w/PCI Express Interface
Track ID: JATR-1076-21 Rev. 1.0
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Datasheet
4.
Block Diagrams
MAC
EEPROM
Interface
Radio and
Synthesizer
Control
Serial
Control
LED Driver
Register
WEP/
TKIP/
AES
RTS, CTS,
ACK Frame
Generator
Checksum
Logic
CCA/
NAV
Engine
FIFO
Control
Logic
FIFO
Frame Type
Discriminator
PCI
Express
Interface
Interrupt
Control
Logic
Frame Length
Register
Power and TX/RX Timing Control Logic
Transmit/
Receive
Logic
Interface
From BBP
MAC/BBP
Interface
BBP, TX Section
MAC/BBP
Interface
From
MAC
Scrambler
Digital
Filter
Coding
TX AGC
Control
TX State
Machine
Register
DAC
TXI
DAC
TXQ
DAC
TXAGC
ADC
TXDET
ADC
RXI
ADC
RXQ
BBP, RX Section
MAC/BBP
Interface
To MAC
From
MAC
Descrambler
Decoding
Clear Channel
Assessment/
Signal Quality
Register
RX AGC
Control
RX State
Machine
DAC
ADC
Antenna
Diversity
Control
RXAGC
RSSI
ANTSEL
ANTSELB
Figure 1. Block Diagram
Single-Chip Wireless LAN Network Interface Controller
w/PCI Express Interface
Track ID: JATR-1076-21 Rev. 1.0
RTL8187SE
Datasheet
Figure 2. RF Block Diagram
Single-Chip Wireless LAN Network Interface Controller
w/PCI Express Interface
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WAKEB
CLKREQB
LED1
PERSTB
VDD
GND
REFCLK-
REFCLK+
AGND
HSON
HSOP
VDD
AGND
HSIN
HSIP
Pin Assignments
VAA33
5.
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
49
32
VDD33
TSSI
50
31
GND
TRQP
51
30
LED0
TRQN
52
29
WLACT
TRIN
53
28
BTSTAT
TRIP
54
27
EECS
VAA33
55
26
EESK/9356SEL
R15K
56
25
EEDI/AUX
AGND
57
24
EEDO
VAA33
58
23
VDD
VAA33
59
22
GND
XI
60
21
VDD33
XO
61
20
GND
VAA33
62
19
BTPRI
VD_CBC
63
18
ISOLATEB
VD_DIV
64
RTL8187SE
LLLLLLL
TXXXV
WLRXIND
ANTENSWN
ANTENSWP
17
10 11 12 13 14 15 16
EXTRSTB
GND
RFIN
VDD
RFON
VAA33
RFOP
VCTRL_LDO
TRSWP
TRSWN
PAPE
RFIP
VAA33
65 GND (Exposed Pad)
VAA33
DA8_DEBUG
Figure 3. Pin Assignments
5.1.
Package Identification
Green package is indicated by a ‘G’ in the location marked ‘T’ in Figure 3.
Single-Chip Wireless LAN Network Interface Controller
w/PCI Express Interface
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Datasheet
6.
Pin Descriptions
The following signal type codes are used in the tables:
I: Input
AO: Analog Output
DI: Digital Input
AIO: Analog Input/Output
AI: Analog Input
T/S: Tri-State Bi-Directional Input/Output
O: Output
S/T/S: Sustained Tri-State
DO: Digital Output
6.1.
Symbol
WAKEB
ISOLATEB
6.2.
O/D: Open Drain
Power Management/Isolation Interface
Type
O/D
DI
Table 1. Power Management/Isolation Interface
Pin No Description
33
Power Management Event: Open drain, active low.
Used to reactivate the PCI Express slot’s main power rails and reference clocks.
18
Isolate Pin: Active low.
Used to isolate the RTL8187SE-GR from the PCI Express bus. The
RTL8187SE-GR will not drive its PCI Express outputs (excluding WAKEB) and
will not sample its PCI Express input as long as the Isolate pin is asserted.
PCI Express Interface
Symbol
REFCLK+
REFCLKHSOP
HSON
HSIP
HSIN
PERSTB
Type
Pin No
40
39
43
42
47
46
36
CLKREQB
O/D
34
Table 2. PCI Express Interface
Description
PCI Express Differential Reference Clock Source: 100MHz ±300ppm.
PCI Express Transmit Differential Pair.
PCI Express Receive Differential Pair.
PCI Express Reset Signal: Active low.
When the PERSTB is asserted at power-on state, the RTL8187SE-GR returns
to a pre-defined reset state and is ready for initialization and configuration
after the de-assertion of the PERSTB.
Reference Clock Request Signal. This signal is used by the RTL8187SE-GR to
request starting of the PCI Express reference clock.
Single-Chip Wireless LAN Network Interface Controller
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Track ID: JATR-1076-21 Rev. 1.0
RTL8187SE
Datasheet
6.3.
EEPROM Interface
Symbol
EESK/9356SEL
Type
DO/DI
EEDI/AUX
DO/DI
EEDO
DI
EECS
DO
6.4.
Power Pins
Symbol
VDD33
VAA33
Type
VDD
GND
AGND
VCTRL_LDO
AO
VD_CBC
VD_DIV
Table 3. EEPROM Interface
Pin No
Description
26
EESK in 93C46 (93C56) programming or auto-load mode.
Input Pin as 9356 Select Pin at Initial Power-up.
When this pin is pulled high with a 10K resistor, the 93C56 EEPROM
is used to store the resource data for the RTL8187SE.
The RTL8187SE latches the status of this pin at power-up to
determine which EEPROM (93C46 or 93C56) is used.
After power on and GPIO_EN[5]=1, this pin is GPIO[5].
25
EEDI: Output to serial data input pin of EEPROM.
AUX: Input pin to detect if Aux. Power exists or not on initial
power-on. This pin should be connected to EEPROM. To support
wakeup from ACPI D3cold or APM power-down, this pin must be
pulled high to Aux. Power via a resistor. If this pin is not pulled high to
Aux. Power, the RTL8187SE assumes that no Aux. Power exists.
After power on and GPIO_EN[4]=1, this pin is GPIO[4].
24
This pin is GPIO[3] after power on and GPIO_EN[3]=1, otherwise, it
is EEDO in 93C46 (93C56) programming or auto-load mode.
27
EEPROM Chip Select.
93C46 (93C56) chip select.
Table 4. Power Pins
Pin No
Description
21, 32
+3.3V (Digital).
1, 2, 11, 48, 55, 58, 59, +3.3V (Analog).
62
12, 23, 37, 44
+1.8V.
13, 20, 22, 31, 38, 65 Ground (Digital).
41, 45, 57
Ground (Analog).
10
Reserve this pin for external BJT option to generate 1.8V for digital
core circuit.
63
Reserved for external power transistor.
64
Reserved for external power transistor.
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Datasheet
6.5.
LED Interface
Symbol
LED0
LED1
6.6.
Type
Pin No
30
35
Table 5. LED Interface
Description
LED Pin.
a. PWRON: I2C_CK
b. After PWRON & LED_CONTROL=3’h7: GPIO[0]
c. Other: LED0
LED Pin.
a. PWRON: I2C_IO
b. After PWRON & LED_CONTROL=3’h7: GPIO[1]
c. Other: LED1
Baseband and RF Pins
Symbol
RFOP
RFON
RFIN
RFIP
PAPE
TRSWN
TRSWP
ANTENSWP
ANTENSWN
TSSI
TRQP
Type
AO
AO
AI
AI
DO
DO
DO
DO
DO
AI
AIO
TRQN
AIO
TRIN
AIO
TRIP
AIO
Table 6. Baseband and RF Pins
Pin No Description
2.4GHz Differential RF Power Amplifier Output.
2.4GHz Differential RF Input.
Enable Control for Optional External Power Amplifier
Control Signals for Optional External RF T/R Switch
15
Control Signals for Antenna Switch
16
50
Transmit Signal Strength Indication From External Power Amplifier
51
Via register setting, can be programmed to one of the following four types of pins:
RF TXQP: Input pin for RF TX test
RF RXQP: Output pin for RF RX test
AFE TXQP: Output pin for DAC test
AFE RXQP: Input pin for ADC test
52
Via register setting, can be programmed to one of the following four types of pins:
RF TXQN: Input pin for RF TX test
RF RXQN: Output pin for RF RX test
AFE TXQN: Output pin for DAC test
AFE RXQN: Input pin for ADC test
53
Via register setting, can be programmed to one of the following four types of pins:
RF TXIN: Input pin for RF TX test
RF RXIN: Output pin for RF RX test
AFE TXIN: Output pin for DAC test
AFE RXIN: Input pin for ADC test
54
Via register setting, can be programmed to one of the following four types of pins:
RF TXIP: Input pin for RF TX test
RF RXIP: Output pin for RF RX test
AFE TXIP: Output pin for DAC test
AFE RXIP: Input pin for ADC test
Single-Chip Wireless LAN Network Interface Controller
w/PCI Express Interface
10
Track ID: JATR-1076-21 Rev. 1.0
RTL8187SE
Datasheet
6.7.
Bluetooth Co-Existence Pins
Symbol
WLRXIND
BTPRI
Type
IO
BTSTAT
IO
WLACT
6.8.
Clock and Other Pins
Symbol
R15K
XI
XO
EXTRSTB
DA8_DEBUG
7.
Table 7. Bluetooth Co-Existence Pins
Pin No Description
17
Wireless LAN RX Activity Indicator
19
Bluetooth Priority Pin
This pin is GPIO[2] after power on and GPIO_EN[2]=1, otherwise, this pin is
BTPRI. The BTPRI signal indicates when an important Bluetooth packet is being
transmitted or received.
28
Bluetooth Status
This pin is GPIO[6] after power on and GPIO_EN[6]=1, otherwise, this pin is
BTSTAT. The BTSTAT signal indicates when normal Bluetooth packets are being
transmitted or received.
29
WLAN Activity
The WLAN_Active signal indicates when WLAN is either transmitting or
receiving in the 2.4GHz ISM band.
Type
IO
Pin No
56
60
61
14
49
Table 8. Clock and Other Pins
Description
This pin must be pulled low by a 15K
Input of 40MHz Clock Reference.
Output of 40MHz Clock Reference.
External Reset Pin: Active Low.
Debug Pin.
resistor.
EEPROM (93C46 or 93C56) Contents
The RTL8187SE supports the attachment of an external EEPROM. The 93C46 is a 1Kbit EEPROM
(the 93C56 is a 2Kbit EEPROM). The EEPROM interface provides the ability for the RTL8187SE to read
from, and write data to, an external serial EEPROM device. Values in the external EEPROM allow default
fields in PCI configuration space and IO space to be overridden following an internal power on reset, or
software EEPROM auto-load command. The RTL8187SE will auto-load values from the EEPROM to
these fields in configuration space and IO space. If the EEPROM is not present, the RTL8187SE
initialization uses default values for the appropriate Configuration and Operational Registers. Software can
read and write to the EEPROM using ‘bit-bang’ accesses via the 9346CR Register.
Note: It is suggested to obtain Realtek approval before changing the default settings of the EEPROM.
Single-Chip Wireless LAN Network Interface Controller
w/PCI Express Interface
11
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RTL8187SE
Datasheet
8.
8.1.
PCI EXPRESSTM
PCI EXPRESS Bus Interface
The RTL8187SE is compliant with PCI ExpressTM Base Specification Revision 1.1, and runs at 2.5GHz
signaling rate with X1 link width, i.e., one transmit and one receive differential pairs. The RTL8187SE
supports 4 types of PCI Express messages; interrupt messages, error messages, power management
messages, and hot-plug messages. PCI Express lane polarity reversal and link reversal are also supported to
ease PCB layout constraints.
8.1.1.
PCI Express Transmitter
The RTL8187SE’s PCI ExpressTM block receives digital data recovered from the WLAN MAC interface
and performs data scrambling with Linear Feedback Shift Register (LFSR) and 8B/10B coding technology
into 10-bit code groups. Data scrambling is used to reduce the possibility of electrical resonance on the link,
and 8B/10B coding technology is used to benefit embedded clocking, error detection, and DC balance by
sacrificing the 25 percent overhead to the system through the addition of 2 extra bits. Then, the data code
groups are passed through its serializer for packet framing to generate 2.5 Gbps serial data and transmitted
onto PCB trace to its upstream device via differential driver.
8.1.2.
PCI Express Receiver
The RTL8187SE’s PCI ExpressTM block receives 2.5Gbps serial data from its upstream device to generate
parallel data. The receiver’s PLL circuits are resynchronized to maintain bit and symbol lock. Through
8B/10B decoding technology and data descrambling, the original digital data is able to be recovered and
then the data is passed to the RTL8187SE’s internal WLAN MAC to be transmitted on the air.
Single-Chip Wireless LAN Network Interface Controller
w/PCI Express Interface
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RTL8187SE
Datasheet
8.2.
PCI Configuration Space Table
Note: The following table assumes Power Management is enabled.
Table 9. PCI Configuration Space Table
No.
00h
01h
02h
03h
04h
Name
VID
DID
Command
05h
06h
07h
Status
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
Revision ID
PIFR
SCR
BCR
CLS
LTR
HTR
BIST
IOAR
11h
12h
13h
14h17h
18h1Fh
20h27h
28h2Bh
2Ch
2Dh
2Eh
2Fh
30h
Bit7
VID7
VID15
DID7
DID15
DPERR
DPERR
CLS7
IOAR15
IOAR23
IOAR31
Bit6
VID6
VID14
DID6
DID14
PERRSP
PERRSP
SSERR
SSERR
CLS6
IOAR14
IOAR22
IOAR30
Bit5
Bit4
VID5
VID4
VID13
VID12
DID5
DID4
DID13
DID12
RMABT
RTABT
RMABT
RTABT
CLS5
CLS4
IOAR13
IOAR12
IOAR21
IOAR20
IOAR29
IOAR28
Reserved
Bit3
VID3
VID11
DID3
DID11
IntSt
STABT
STABT
CLS3
IOAR11
IOAR19
IOAR27
Bit2
VID2
VID10
DID2
DID10
BMEN
BMEN
IntDisable
IntDisable
CLS2
IOAR10
IOAR18
IOAR26
Bit1
VID1
VID9
DID1
DID9
MEMEN
MEMEN
CLS1
IOAR9
IOAR17
IOAR25
Bit0
VID0
VID8
DID0
DID8
IOEN
IOEN
SERREN
SERREN
DPD
DPD
CLS0
IOIN
IOAR8
IOAR16
IOAR24
SVID3
SVID11
SMID3
SMID11
BMAR11
BMAR11
BMAR19
BMAR27
SVID2
SVID10
SMID2
SMID10
BMAR18
BMAR26
SVID1
SVID9
SMID1
SMID9
BMAR17
BMAR25
SVID0
SVID8
SMID0
SMID8
BROMEN
BROMEN
BMAR16
BMAR24
ILR3
ILR2
ILR1
ILR0
Reserved
Reserved
Reserved
SVID
Cap_Ptr
RW
RW
SVID7
SVID15
SMID7
SMID15
BMAR15
BMAR15
BMAR23
BMAR31
SVID6
SVID14
SMID6
SMID14
BMAR14
BMAR14
BMAR22
BMAR30
ILR
IPR
MNGNT
RW
IRL7
ILR6
SMID
BMAR
31h
32h
33h
34h
35h3Bh
3Ch
3Dh
3Eh
Type
RW
RW
RW
RW
SVID5
SVID4
SVID13
SVID12
SMID5
SMID4
SMID13
SMID12
BMAR13
BMAR12
BMAR13
BMAR12
BMAR21
BMAR20
BMAR29
BMAR28
Reserved
ILR5
Single-Chip Wireless LAN Network Interface Controller
w/PCI Express Interface
ILR4
13
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RTL8187SE
Datasheet
No.
3Fh
40h
41h
42h
43h
44h
Name
MXLAT
PMID
NextPtr
PMC
PMCSR
45h
464Fh
50h
51h
52h
MSIID
NextPtr
Message
Control
Type
Bit7
Aux_I_b1
PME_D3cold
PME_Status
PME_Status
Bit6
Aux_I_b0
PME_D3hot
64-bit
Address
Capable
53h
54hMessage
57h Address Low
58hMessage
5Bh Address High
5Ch- Message Data
5Dh
Bit5
Bit4
DSI
Reserved
PME_D2
PME_D1
Reserved
Multiple Message Enable
MSI Enable
MSI Enable
D2
RW
RW
64-bit Interrupt Message Address High
RW
16-bit Message Data
Bit1
Bit0
Version
D1
Aux_I_b2
Power State
Power State
PME_En
PME_En
RESERVED
70h
71h
72h73h
PCIEID
NextPtr
PCIE Cap.
74h77h
Device
Capability
Register
Device
Control
Register
7Ah Device Status
Register
7Bh
7Ch
7Dh
Bit2
Multiple Message Enable
Reserved. Always return 0
64-bit Interrupt Message Address Low
5E6Fh
78h79h
Bit3
PMECLK
PME_D0
RW
L0s_acpt_
latency[1]
Role Base
Error rpt
Entend_
tag_support
Legacy
Max_payload_size
Relaxed_
ordering_en
L1_acpt_
latency[2]
Unsupport_
rqst_rpt_en
L1_acpt_
latency[1]
Fatal_err_
rpt_en
L1_acpt_
latency[0]
Non_fatal_
err_rpt_en
No_snoop_en
Auxpwr_
PM_en
RW
7Eh
L1_exit_
lat[0]
7Fh
Link
Capability
Register
L0s_acpt_
latency[0]
Max_read_request_size
AuxPwr_det
Transact_
ion_pending
L0s_exit_
lat[2]
L0s_exit_
lat[1]
L0s_exit_
lat[0]
Single-Chip Wireless LAN Network Interface Controller
w/PCI Express Interface
14
Max_payload_size_support
L0s_acpt_la
tency[2]
Correctable_err_
rpt_en
Entend_
tag_en
Upsupport_ Fatal_err_det Non_fatal_
Correctrqst_det
err_det
able_err_det
Upsupport_ Fatal_err_det Non_fatal_err Correctarqst_det
_det
ble_err_det
ASPM_support
Clock_PM
L1_exit_
lat[2]
L1_exit_
lat[1]0
Track ID: JATR-1076-21 Rev. 1.0
RTL8187SE
Datasheet
No.
80h
Name
Link Control
Register
Type
Bit6
Common_
clock
Common_
clock
Bit5
Bit4
Bit3
RCB
Bit2
Bit1
Bit0
ASPM_control
RCB
ASPM_control
Bit7
Extended_
sync
Extended_
sync
81h
82h
83h
Link Status
Register
84h
Slot
Capability
Register
Slot power
Limit[0]
Hot-Plug
Capable
Hot-Plug
Surprise
85h
86h
87h
88h
Slot Control
Register
89h
8Ah
8Bh
RW
RW
Slot Status
Register
Slot power
Slot power
Slot power
Limit scale[0]
Limit[7]
Limit[6]
Physical slot
Physical
Physical slot
Number[4] slot Number[3] Number[2]
Physical slot
Number[12]
Physical slot
Number[11]
Attn Indicator Attn Indicator
Control[1]
Control[0]
Physical slot
Number[1]
Hot-Plug
Interrupt
Enable
Electromecha Presence Detect MRL Sensor
nical Interlock
State
State
Status
8ChFFh
Single-Chip Wireless LAN Network Interface Controller
w/PCI Express Interface
Slot_clock_
cfg
Power
Attn indicator MRL sensor Power control
indicator
present
present
present
present
Slot power
Slot power
Slot power
Slot power
Limit[5]
Limit[4]
Limit[3]
Limit[2]
Physical slot Physical slot No common Electromecha
Number[1]
Number[0]
Complete nical interlock
support
present
Physical slot Physical slot Physical slot Physical slot
Number[9]
Number[8]
Number[7]
Number[6]
Command
Presence
MRL Sensor
Completed
Detect
Changed
interrupt
Changed
Enable
Enable
Enable
Data Link Electromecha
Power
Layer State nical Interlock Controller
Changed
Control
Control
Enable
Command
Presence
MRL Sensor
Completed
Detect
Changed
Changed
Reversed
Enable
clock_PM
Enable
clock_PM
Attn button
present
Slot power
Limit[1]
Slot power
Limit
scale[1]
Physical slot
Number[5]
Power Fault Attn Bottom
Detected
Pressed
Enable
Enable
Power
Indicator
Control[1]
Power
Indicator
Control[0]
Power Fault Attn Botton
Detected
pressed
Data Link
Layer State
Changed
Reversed
15
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RTL8187SE
Datasheet
8.3.
PCI Configuration Space Functions
The PCI configuration space is intended for configuration, initialization, and catastrophic error handling
functions. The functions of the configuration space of the RTL8187SE are described below.
VID: Vendor ID. This field will be set to a value corresponding to a PCI Vendor ID in the external
EEPROM. If there is no EEPROM, this field will default to a value of 10ECh, which is Realtek
Semiconductor’s PCI Vendor ID.
DID: Device ID. This field will be set to a value corresponding to a PCI Device ID in the external
EEPROM. If there is no EEPROM, this field will default to a value of 8185h.
Command: The command register is a 16-bit register used to provide coarse control over a device's ability
to generate and respond to PCI cycles.
Bit
15:11
10
Symbol
INTDIS
FBTBEN
SERREN
ADSTEP
PERRSP
VGASNOOP
MWIEN
SCYCEN
BMEN
MEMEN
IOEN
Table 10. Command Register in PCI Configuration Space
Description
Reserved.
Interrupt Disable.
This Bit enables/disables the RTL8187SE to assert Int# signal.
1: Force disable assertion of the Int# signal.
0: Enable enable assertion of the Int# signal (default value after PCI reset)
Fast Back-To-Back Enable. Does not apply to PCI Express. Must be hardwired to 0.
System Error Enable.
When set to 1, enables reporting of Non-fatal and Fatal errors detected by the device to the Root
Complex. Note that errors are reported if enabled either through this bit or through the
PCI-Express specific bits in the Device Control register.
Address/Data Stepping. Does not apply to PCI Express. Must be hardwired to 0.
Parity Error Response.
In the Status register, the Master Data Parity Error bit is set by a Requester if its Parity Error
Response bit is set and either of the following two conditions occurs:
- If the Requester receives a poisoned Completion.
- If the Requester poisons a write request.
If the Parity Error Response bit is cleared, the Master Data Parity Error status bit is never set.
VGA Palette SNOOP. Does not apply to PCI Express. Must be hardwired to 0.
Memory Write and Invalidate Cycle Enable.
Does not apply to PCI Express. Must be hardwired to 0.
Special Cycle Enable. Does not apply to PCI Express. Must be hardwired to 0.
Bus Master Enable.
When set to 1, the RTL8187SE is capable of acting as a PCI bus master. When set to 0, it is
prohibited from acting as a bus master.
For normal operations, this bit must be set by the system BIOS.
Memory Space Access. When set to 1, the RTL8187SE responds to memory space accesses.
When set to 0, the RTL8187SE ignores memory space accesses.
IO Space Access. When set to 1, the RTL8187SE responds to IO space accesses. When set to 0,
the RTL8187SE ignores IO space accesses.
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RTL8187SE
Datasheet
8.4.
8.4.1.
PCI Configuration Space Status
Status
The status register is a 16-bit register used to record status information for PCI bus related events. Reads to
this register behave normally. Writes are slightly different in that bits can be reset, but not set.
Bit
15
Symbol
DPERR
14
SSERR
13
RMABT
12
RTABT
11
STABT
10:9
DST1~0
DPD
FBBC
66MHz
NewCap
INTSTS
2:0
Table 11. PCI Configuration Space Status
Description
Detected Parity Error.
This bit is set by the RTL8187SE whenever it receives a Poisoned Transaction Layer Packet
(TLP), regardless of the state the Parity Error Enable bit. Default value of this field is 0.
Signaled System Error.
This bit is set when the RTL8187SE sends an ERR_FATAL or ERR_NONFATAL Message, and
the SERR Enable bit in the Command register is 1. Default value of this field is 0.
Received Master Abort.
This bit is set when the RTL8187SE receives a Completion with Unsupported Request
Completion Status. Default value of this field is 0.
Received Target Abort.
This bit is set when the RTL8187SE receives a Completion with Completer Abort Completion
Status. Default value of this field is 0.
Signaled Target Abort.
This bit is set when the RTL8187SE completes a Request using Completer Abort Completion
Status. Default value of this field is 0.
Device Select Timing. Does not apply to PCI Express. Must be hardwired to 0.
Data Parity Error Detected.
This bit is set by the RTL8187SE if its Parity Error Enable bit is set and either of the following
two conditions occurs:
- Requestor receives a Completion marked poisoned
- Requestor poisons a write Request
If the Parity Error Enable bit is cleared, this bit is never set. Default value of this field is 0.
Fast Back-To-Back Capable. Does not apply to PCI Express. Must be hardwired to 0.
Reserved.
66MHz Capable. Does not apply to PCI Express. Must be hardwired to 0.
Capability List.
Indicates the presence of an extended capability list item. Since all PCI Express devices are
required to implement the PCI Express capability structure, this bit must be set to 1.
Interrupt Status.
This bit reflects the interrupt status of the RTL8187SE.
Unlike ISR bits, this bit is a read-only bit and cannot be reset by writing a 1 to this bit. The only
way to reset this bit is to reset the ISR register.
The setting of the ‘Interrupt Disable’ bit in the Command Register has no effect on the state of
the ‘Interrupt Status’ bit.
Only when the ‘Interrupt Disable’ bit is a 0 and the ‘Interrupt Status’ bit is a 1, will the
RTL8187SE’s Int# signal be asserted.
Reserved.
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RTL8187SE
Datasheet
8.4.2.
RIDR (Revision ID Register)
The Revision ID register is an 8-bit register that specifies the RTL8187SE controller revision number.
8.4.3.
PIFR (Programming Interface Register)
The programming interface register is an 8-bit register that identifies the programming interface of the
RTL8187SE controller. The PCI 2.1 specification does not define a specific value for network devices. In
the RTL8187SE controller this is PIFR = 00h.
8.4.4.
SCR (Sub-Class Register)
The Sub-Class Register is an 8-bit register that identifies the function of the RTL8187SE. SCR=0x80
indicates that the RTL8187SE is identified as ‘other network controller’.
8.4.5.
BCR (Base-Class Register)
The Base-Class Register is an 8-bit register that broadly classifies the function of the RTL8187SE.
BCR=02h indicates that the RTL8187SE is a network controller.
8.4.6.
CLS (Cache Line Size)
This field is implemented by PCI Express devices as a read-write field for legacy compatibility purposes
but has no impact on any PCI Express device functionality.
8.4.7.
LTR (Latency Timer Register)
This register is also referred to as primary latency timer for Type 1 Configuration Space header devices.
The primary/master latency timer does not apply to PCI Express. This register must be hardwired to 0.
8.4.8.
HTR (Header Type Register)
Reads will return a 0, writes are ignored.
8.4.9.
BIST (Built-In Self-Test)
Reads will return a 0, writes are ignored.
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RTL8187SE
Datasheet
8.4.10.
IOAR (Input Output Address Register)
This register specifies the BASE IO address, which is required to build an address map during
configuration. It also specifies the number of bytes required as well as an indication that it can be mapped
into IO space.
Bit
31:8
Symbol
IOAR31~8
7:2
IOSIZE
IOIN
8.4.11.
Table 12. Input Output Address Register
Description
Base Input Output Address.
This is set by software to the Base IO address for the operational register map.
Input Output Size Indication.
Read back as 0. This allows the PCI bridge to determine that the RTL8187SE requires 256 bytes
of IO space.
Reserved.
IO Space Indicator.
Read only. Set to 1 by the RTL8187SE to indicate that it is capable of being mapped into IO
space.
MEMAR (Memory Address Register)
This register specifies the base memory address for memory accesses to the RTL8187SE operational
registers. This register must be initialized prior to accessing any RTL8187SE register with memory access.
Table 13. Memory Address Register
Bit
31:8
Symbol
MEM31~8
7:4
MEMSIZE
MEMPF
2:1
MEMLOC
MEMIN
8.4.12.
Description
Base Memory Address.
This is set by software to the base address for the operational register map.
Memory Size.
These bits return 0, which indicates that the RTL8187SE requires 256 bytes of Memory Space.
Memory Pre-Fetchable.
Read only. Set to 0 by the RTL8187SE.
Memory Location Select.
Read only. Set to 0 by the RTL8187SE. This indicates that the base register is 32 bits wide and
can be placed anywhere in the 32-bit memory space.
Memory Space Indicator.
Read only. Set to 0 by the RTL8187SE to indicate that it is capable of being mapped into memory
space.
CISPtr (CardBus Card Information Structure Pointer)
CardBus CIS Pointer. This register does not apply to PCI Express. It must be read-only and must be
hardwired to 0.
Single-Chip Wireless LAN Network Interface Controller
w/PCI Express Interface
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RTL8187SE
Datasheet
8.4.13.
SVID (Subsystem Vendor ID)
This field will be set to a value corresponding to the PCI Subsystem Vendor ID in the external EEPROM. If
there is no EEPROM, this field will default to a value of 10ECh (Realtek Semiconductor’s PCI Subsystem
Vendor ID).
8.4.14.
SMID (Subsystem ID)
This field will be set to a value corresponding to the PCI Subsystem ID in the external EEPROM. If there is
no EEPROM, this field will default to a value of 8198h.
8.4.15.
ILR (Interrupt Line Register)
The Interrupt Line Register is an 8-bit register used to indicate the routing of the interrupt. It is written by
the POST software to set an interrupt line for the RTL8187SE.
8.4.16.
IPR (Interrupt Pin Register)
The Interrupt Pin register is an 8-bit register indicating the interrupt pin used by the RTL8187SE. The
RTL8187SE uses INTA interrupt pin. Read only. IPR = 01h.
8.4.17.
MNGNT (Minimum Grant Timer: Read only)
This register does not apply to PCI Express. It must be read-only and must be hardwired to 0.
8.4.18.
MXLAT (Maximum Latency Timer: Read only)
This register does not apply to PCI Express. It must be read-only and must be hardwired to 0.
8.5.
No.
00h
01h
02h
03h
04h
Default Value After Power-On (RSTB Asserted)
Name
VID
DID
Command
05h
06h
07h
08h
09h
0Ah
Status
Revision
ID
PIFR
SCR
Type
Table 14. PCI Configuration Space Table
Bit7
Bit6
Bit5
Bit4
Bit3
PERRSP
MWIEN
NewCap
DPERR
SSERR RMABT RTABT
STABT
Bit2
Bit1
Bit0
BMEN MEMEN
IOEN
SERREN
DPD
Single-Chip Wireless LAN Network Interface Controller
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RTL8187SE
Datasheet
No.
0Bh
0Ch
0Dh
Name
BCR
CLS
LTR
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h~
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
HTR
BIST
IOAR
MEMAR
Bit7
LTR7
Bit6
LTR6
Bit5
LTR5
CISPtr
SVID
SMID
BMAR
Cap-Ptr
ILR
IPR
MNGNT
MXLAT
Bit4
LTR4
Bit3
LTR3
Bit2
LTP2
Bit1
LTR1
Bit0
LTR0
Ptr2
Ptr1
BROMEN
Ptr0
RESERVED (ALL 0)
31h
32h
33h
34h
35h~
3Bh
3Ch
3Dh
3Eh
3Fh
40h~
FFh
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
BMAR15 BMAR14 BMAR13 BMAR12 BMAR11
Ptr7
Ptr6
Ptr5
Ptr4
Ptr3
RESERVED (ALL 0)
RW
Single-Chip Wireless LAN Network Interface Controller
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RESERVED (ALL 0)
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RTL8187SE
Datasheet
8.6.
PCI Power Management Functions
The RTL8187SE is compliant with ACPI (Rev 2.0), PCI Power Management (Rev. 1.2), and Network
Device Class Power Management Reference Specification (V1.0a), such as to support an Operating
System-Directed Power Management (OSPM) environment.
The RTL8187SE can monitor the network for a Wakeup Frame, a Magic Packet, or a Re-LinkOk, and
notify the system via PME# when such a packet or event occurs. Then the system can be restored to a
normal state to process incoming jobs.
When the RTL8187SE is in power down mode (D1 ~ D3):
The Rx state machine is stopped, and the RTL8187SE monitors the network for wakeup events such as
a Magic Packet, Wakeup Frame, and/or Re-LinkOk, in order to wake up the system. When in power
down mode, the RTL8187SE will not reflect the status of any incoming packets in the ISR register and
will not receive any packets into the Rx FIFO buffer.
The FIFO status and packets that have already been received into the Rx FIFO before entering power
down mode are held by the RTL8187SE.
Transmission is stopped. PCI bus master mode is stopped. The Tx FIFO buffer is held.
After restoration to a D0 state, the RTL8187SE transfers data that was not moved into the Tx FIFO
buffer during power down mode. Packets that were not transmitted completely last time are
re-transmitted.
The D3cold_support_PME bit (bit15, PMC register) and the Aux_I_b2:0 bits (bit8:6, PMC register) in PCI
configuration space depend on the existence of Aux power (bit15, PMC) = 1.
If EEPROM D3cold_support_PME bit (bit15, PMC) = 0, the above 4 bits are all 0’s.
Example:
If EEPROM D3c_support_PME = 1:
If aux. power exists, then PMC in PCI config space is the same as EEPROM PMC
(if EEPROM PMC = C3 F7, then PCI PMC = C3 F7)
If aux. power is absent, then PMC in PCI config space is the same as EEPROM PMC except the above
4 bits are all 0’s (if EEPROM PMC = C3 F7, then PCI PMC = 03 76)
In the above case, if wakeup support is desired when main power is off, it is suggested that the EEPROM
PMC be set to C3 F7 (Realtek EEPROM default value).
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Datasheet
If EEPROM D3c_support_PME = 0:
If aux. power exists, then PMC in PCI config space is the same as EEPROM PMC
(if EEPROM PMC = C3 77, then PCI PMC = C3 77)
If aux. power is absent, then PMC in PCI config space is the same as EEPROM PMC except the above
4 bits are all 0’s (if EEPROM PMC = C3 77, then PCI PMC = 03 76)
In the above case, if wakeup support is not desired when main power is off, it is suggested that the
EEPROM PMC be set to 03 76.
Magic Packet Wakeup occurs only when the following conditions are met:
The destination address of the received Magic Packet is acceptable to the RTL8187SE, e.g. a broadcast,
multicast, or unicast packet addressed to the current RTL8187SE adapter.
The received Magic Packet does not contain a CRC error.
The Magic bit (CONFIG3#5) is set to 1, the PMEn bit (CONFIG1#0) is set to 1, and the PME# can be
asserted in the current power state.
The Magic Packet pattern matches, i.e. 6 * FFh + MISC (can be none) + 16 * DID (Destination ID) in
any part of a valid WLAN packet.
A Wakeup Frame event occurs only when the following conditions are met:
The destination address of the received Wakeup Frame is acceptable to the RTL8187SE, e.g. a
broadcast, multicast, or unicast address to the current RTL8187SE adapter.
The received Wakeup Frame does not contain a CRC error.
The PMEn bit (CONFIG1#0) is set to 1.
The 16-bit CRC* of the received Wakeup Frame matches the 16-bit CRC* of the sample Wakeup Frame
pattern given by the local machine’s OS. Or, the RTL8187SE is configured to allow direct packet
wakeup, e.g. a broadcast, multicast, or unicast network packet.
*16-bit CRC: The RTL8187SE supports two normal wakeup frames (covering 64 mask bytes from offset 0 to
63 of any incoming network packet) and three long wakeup frames (covering 128 mask bytes from offset 0
to 127 of any incoming network packet).
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Datasheet
The PME# signal is asserted only when the following conditions are met:
The PMEn bit (bit0, CONFIG1) is set to 1.
The PME_En bit (bit8, PMCSR) in PCI Configuration Space is set to 1.
The RTL8187SE may assert PME# in the current power state or in isolation state, depending on the
PME_Support (bit15-11) setting of the PMC register in PCI Configuration Space.
A Magic Packet, LinkUp, or Wakeup Frame has been received.
Note: Writing a 1 to the PME_Status (bit15) of the PMCSR register in the PCI Configuration Space clears
this bit and causes the RTL8187SE to stop asserting a PME# (if enabled).
When the device is in power down mode, e.g. D1~D3, the IO, and MEM spaces are all disabled. After a
RST# assertion, the device’s power state is restored to D0 automatically if the original power state was
D3cold. There is no hardware delay at the device’s power state transition. When in ACPI mode, the device
does not support PME (Power Management Enable) from D0 (this is the Realtek default setting of the PMC
register auto-loaded from EEPROM). The setting may be changed from the EEPROM, if required. The
RTL8187SE also supports the legacy LAN WAKE-UP function. The LWAKE pin is used to notify legacy
motherboards to execute the wake-up process whenever the device receives a wakeup event, such as Magic
Packet.
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RTL8187SE
Datasheet
8.7.
8.7.1.
Message Signaled Interrupt (MSI)
MSI Capability Structure in PCI Configuration Space
Figure 4. Message Capability Structure
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RTL8187SE
Datasheet
8.7.2.
Message Control
Bits
15:8
RW
RO
RO
6:4
RW
3:1
RO
RW
8.7.3.
Table 15. Message Control
Field
Description
Reserved
Reserved. Always return 0
64-Bit Address Capable
1: The RTL8187SE is capable of generating a 64-bit
message address.
0: The RTL8187SE is NOT capable of generating a 64-bit
message address.
This bit is read only and the RTL8187SE is set to 1.
Multiple Message Enable
System software (e.g., BIOS, OS) indicates to the RTL8187SE the
number of allocated messages/vectors (equal to or less than the
number of requested messages/vectors).
This field after PCI reset is ‘000’.
Encoding
Number of Messages/Vectors
000
001
010
011
100
16
101
32
110
Reserved
111
Reserved
Multiple Message Capable
Indication to system software (e.g., BIOS, OS) of the number of
RTL8187SE requested vectors.
The RTL8187SE supports only one vector messages/vectors.
Encoding
Number of Messages/Vectors
000
Others
Reserved
MSI Enable
1: Enable MSI (Also the INTx pin is disabled automatically, MSI
and INTx are mutually exclusive), this bit is set by system software.
0: Disable MSI (Default value after power-on or PCI reset)
Message Address
Bits
31:02
RW
RW
01:00
RO
Table 16. Message Address
Field
Description
Message Address
System-Specified Message/Vector Address.
Low DWORD aligned address for MSI memory write transaction.
Reserved
Always Return ‘00’.
This bit is read only.
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Datasheet
8.7.4.
Bits
31:00
8.7.5.
Bits
15:00
Message Upper Address
RW
RW
Table 17. Message Upper Address
Field
Description
Message Upper Address
System-Specified Message/Vector Upper Address.
Upper 32 bits of a 64-bit message/vector address.
This register is effective only when the DAC function is enabled,
i.e., 64-bit addressing is enabled; bit7 in Message Control register
is set.
If the contents of this register are 0, the RTL8187SE only performs
32-bit addressing for the memory write of the messages/vectors.
This bit is read/write.
Message Data
RW
RW
Table 18. Message Data
Field
Description
Message Data
If the Message Enable bit is set, the message/vector data is driven
onto the lower word of the memory write transaction’s data phase.
This bit is read/write.
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Datasheet
9.
9.1.
Functional Description
Transmit & Receive Operations
The RTL8187SE supports a descriptor-based buffer management that will significantly lower host CPU
utilization. The RTL8187SE supports an infinite number of consecutive transmit descriptors, and 64
consecutive receive descriptors, in memory.
There may be a maximum of five descriptor rings. Transmit descriptor rings consist of one beacon transmit
descriptor ring, one high priority descriptor ring, one normal priority descriptor ring, and one low priority
descriptor ring. Each transmit descriptor ring may consist of an infinite number of 8-double-word
consecutive descriptors, and the receive descriptor array may consist of up to sixty-four 4-double-word
consecutive descriptors. The start address of each descriptor group should be in 256byte alignment.
Software must pre-allocate enough buffers and configure all descriptor rings before transmitting and/or
receiving packets.
9.1.1.
Transmit
The following describes what the Tx descriptor may look like, depending on different states in each Tx
descriptor.
Tx Descriptor Format (before transmitting, OWN=1, Tx command mode 1)
Table 19. Tx Descriptor Format (before transmitting, OWN=1, Tx command mode 1)
31 30 29 28
27 26 25 24 23
TXRATE
(4 bits)
D F L
M S S
22 21 20 19 18 17 16 15 14 13 12 11 10
R RTSRAT C M S N BSSID
T O P O _NO
S (4 bits) S R L _
E E C
N F P
Length (15 bits)
9 8 7 6 5 4 3 2 1 0
TPKTSIZE (12 bits)
RTSDUR (16 bits)
TX_BUFFER_ADDRESS
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Offset 0
Offset 4
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Datasheet
31 30 29 28
27 26 25 24 23
22 21 20 19 18 17 16 15 14 13 12 11 10
9 8 7 6 5 4 3 2 1 0
DURATION (16 bits)
M RSVD
Frame_Length (12 bits)
I (3 bits)
NEXT_TX_DESCRIPTOR_ADDRESS
RATE_FALL RTS_RATE RSVD P N R RETRY_LIMIT (8 bits)
RTSAGC (8 bits)
BACK_LIMIT
_FALL
(4bits) I O T
(5 bits)
BACK_LI
F _ _
MIT (4
bits)
R SPC A
AGC (8 bits)
FRAG_QSIZE (16 bits)
RSVD
(4bits)
DELAY_BOUND (16 bits)
Single-Chip Wireless LAN Network Interface Controller
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E BCKEY (6 bits)
29
TPC
_PO
LA
RIT
Offset 12
Offset 16
Offset 20
Offset 24
HW Offset 28
Len
gth
Sele
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RTL8187SE
Datasheet
Offset#
Bit#
31
Symbol
OWN
30
DMA OK
29
FS
28
LS
27:24
TXRATE
23
RTSEN
Table 20. Tx Status Descriptor
Description
Ownership.
When set, this bit indicates that the descriptor is owned by the NIC, and the
data relative to this descriptor is ready to be transmitted. When cleared, it
indicates that the descriptor is owned by the host system. The NIC clears this
bit when the relative buffer data is transmitted. In this case, OWN=1.
DMA OK.
Set by the driver, reset by the RTL8187SE when TX DMA OK. If IMR’s
corresponding bit is set and the driver sets this bit, the RTL8187SE resets this
bit and issues an interrupt right after DMA OK of the last segment (LS). If not,
the RTL8187SE just resets this bit without asserting an interrupt.
First Segment Descriptor.
When set, this bit indicates that this is the first descriptor of a Tx packet, and
that this descriptor is pointing to the first segment of the packet.
Last Segment Descriptor.
When set, indicates that this is the last descriptor of a Tx packet, and this
descriptor is pointing to the last segment of the packet.
Tx Rate.
These five bits indicate the current frame’s transmission rate.
Bit 27
Bit 26
Bit 25
Bit 24
1Mbps
2Mbps
5.5Mbps
11Mbps
6Mbps
9Mbps
12Mbps
18Mbps
24Mbps
36Mbps
48Mbps
54Mbps
Reserved
All other combinations
RTS Enable.
Set to 1, indicates that an RTS/CTS handshake shall be performed at the
beginning of any frame exchange sequence where:
The frame is of type Data or Management,
the frame has a unicast address in the Address1 field,
and the length of the frame is greater than RTSThreshold.
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Datasheet
Offset#
Bit#
22:19
Symbol
RTSRATE
18
CTSEN
17
MOREFRAG
16
SPLCP
15
NO_ENCRYPT
14:12
11:0
BSSID_NO
TPKTSIZE
31
LENGEXT
30:16
Length
15:0
RTSDUR
12
12
31:0
31:16
15
TxBuff
DURATION
MIC_CAL
Description
RTS Rate.
These four bits indicate the RTS frame’s transmission rate before transmitting
the current frame, and will be ignored if the RTSEN bit is set to 0.
Bit 22
Bit 21
Bit 20
Bit 19
1Mbps
2Mbps
5.5Mbps
11Mbps
6Mbps
9Mbps
12Mbps
18Mbps
24Mbps
36Mbps
48Mbps
54Mbps
Reserved
All other combinations
CTS Enable.
Both RTSEN and CTSEN set to 1 indicates that the CTS-to-self protection
mechanism will be used.
More Fragments.
This bit is set to 1 in all data type frames that have another fragment of the
current packet to follow.
Short Physical Layer Convergence Protocol format.
When set, this bit indicates that a short PLCP preamble will be added to the
header before transmitting the frame.
No Encryption.
This packet will be transmitted without encryption even if Tx encryption is
enabled.
BSSID Number.
Transmit Packet Size.
This field indicates the number of bytes required to transmit the frame.
Length Extension.
This bit is used to supplement the Length field (bits 30:16, offset 4). This bit
will be ignored if the TXRATE is set to 1Mbps, 2Mbps, or 5.5Mbps.
Physical Layer Conversion Protocol (PLCP) Length.
The PLCP length field indicates the number of microseconds required to
transmit the frame.
Request To Send (RTS) Duration.
These bits indicate the RTS frame’s duration field before transmitting the
current frame and will be ignored if the RTSEN bit is set to 0.
32-Bit Transmit Buffer Address.
Time duration to send this packet plus SIFS and ACK
Enable MIC Calculation.
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Datasheet
Offset#
12
12
Bit#
14:12
11:0
16
20
31:0
31:27
20
26:23
20
20
22:19
18
20
17
20
16
20
20
24
24
15:8
7:0
31
30:29
24
24
24
24
28
28
27:20
19:16
15:0
31:16
28
28
28
28
28
28
15
14
13:8
5:4
Symbol
RSVD
Frame_Length
Description
Reserved.
Transmit Frame Length.
This field indicates the length in the Tx buffer, in bytes, to be transmitted.
32-Bit Address of the Next Transmit Descriptor.
Data Rate Auto Fallback Limit.
NTDA
RATE_FALL
BACK_LIMIT
RTS_RATE_FALL RTS/CTS Rate Auto Fallback Limit.
BACK_LIMIT
RSVD
Reserved.
PIFS
Point Inter-Frame Space (PIFS).
Setting this bit will cause this frame to be sent after PIFS
NO_ACM
No Admission Control Procedure.
This packet will be sent out without being restricted by admission control
procedures. For example, the management type frames shall be sent using the
access category AC_VO without being restricted by admission control
procedures.
RT_DB
Lifetime limited by RETRY_LIMIT (RT_DB=0) or DELAY_BOUND
(RT_DB=1).
RETRY_LIMIT
Retry Count Limit.
RTSAGC
Tx RTS AGC.
RSVD
Reserved.
SPC
Short Preamble Count.
00: 10 bits
01: 12 bits
10: 14 bits
11: 16 bits
ANTENNA
Tx Antenna.
AGC
Tx AGC.
RSVD
Reserved.
DELAY_BOUND Delay Bound
FRAG_QSIZE
Fragmentation Queue Size.
Upon sending the first frame of a fragmentation sequence, the driver writes the
queue size of the entire fragmentation exchange (including the first frame)
here. MAC uses this value when counting down TXOP. This field is valid
when TCR (0x40) duration processing fields are set to mode 1 or 2.
ENPMPD
Enable Power Meter Pre-Distortion Packet.
EN_BCKEY
Enable Broadcast/Multicast Key Search When Using Multiple BSSID
BCKEY
Specify key to use in CAM for broadcast/multicast.
PT_EN
Enable Power Tracking.
TPC_EN
Enable Transmit Power Control.
TPC_POLARITY TPC Polarity Select.
00: Neither increment nor decrement.
01: Increment
10: Decrement
11: Reserved
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Offset#
28
Bit#
Symbol
TPC_DESEN
28
1:0
HWLengthSelect
Description
TPC Descriptor AGC Enable.
0: Use the value of register TPC_TXAGC_OFDM as 54MHz TXAGC Base
1: Use the value of AGC in the same descriptor as 54MHz TXAGC Base
HW Length Select.
00: No Encryption
01: RC4 Encryption
10: AES Encryption
11: Reserved
Tx Status Descriptor (after transmitting, OWN=0, Tx status mode)
After having transmitted, the Tx descriptor becomes a Tx status descriptor.
Table 21. Tx Status Descriptor (after transmitting, OWN=0, Tx status mode)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7
D F L
U T
M S S
D O
RSVD (11 bits)
RTS RC
Packet RC
R K
(7 bits)
(8 bits)
MPDUExchangeTime (16 bits)
RSVD
TX_BUFFER_ADDRESS
RSVD (20 bits)
Frame_Length (12 bits)
NEXT_TX_DESCRIPTOR_ADDRESS
RSVD
RSVD
RSVD
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1 0
Offset 0
Offset 4
Offset 8
Offset 12
Offset 16
Offset 20
Offset 24
Offset 28
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Datasheet
Offset#
12
12
16
20
24
28
Table 22. Tx Status Descriptor (after transmitting, OWN=0, Tx status mode)
Bit#
Symbol
Description
31
OWN
Ownership.
When set, this bit indicates that the descriptor is owned by the NIC. When
clear, it indicates that the descriptor is owned by the host system. The NIC
clears this bit when the related buffer data has been transmitted. In this
case, OWN=0.
30
DMA_OK
DMA Okay.
29
FS
First Segment Descriptor.
When set, this bit indicates that this is the first descriptor of a Tx packet,
and that this descriptor is pointing to the first segment of the packet.
28
LS
Last Segment Descriptor.
When set, this bit indicates that this is the last descriptor of a Tx packet,
and that this descriptor is pointing to the last segment of the packet.
27:17
RSVD
Reserved.
16
UDR
FIFO under-run during transmission of this packet.
15
TOK
Transmit (Tx) OK.
Indicates that a packet exchange sequence has completed successfully.
14:8
RTS RC
RTS Retry Count. The RTS RC’s initial value is 0. It indicates the number
of retries of RTS.
7:0
Packet RC
Packet Retry Count.
The RC’s initial value is 0. It indicates the number of retries before a
packet was transmitted properly.
31:16
MPDUExchangeTime MPDUExchangeTime corresponds to the just completed MPDU
exchange. The MPDUExchangeTime equals the time required to transmit
the MPDU sequence, i.e., the time required to transmit the MPDU plus
the time required to transmit the expected response frame plus one SIFS.
15:0
RSVD
Reserved.
31:0
TxBuff
32-bit Transmit Buffer Address.
31:12
RSVD
Reserved.
11:0
Frame_Length
Transmit Frame Length.
This field indicates the length in the Tx buffer, in bytes, to be transmitted.
31:0
NTDA
32-bit Address of Next Transmit Descriptor.
31:0
RSVD
Reserved.
31:0
RSVD
Reserved.
31:0
RSVD
Reserved.
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Datasheet
9.1.2.
Receive
This section describes what an Rx descriptor could look like, depending on different states in each Rx
descriptor. An Rx buffer pointed to by one of the Rx descriptors should be at least 4 bytes.
Rx Command Descriptor (OWN=1)
The driver should pre-allocate Rx buffers and configure Rx descriptors before packet reception. The
following describes what a Rx descriptor may look like before packet reception.
Table 23. Rx Command Descriptor (OWN=1)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12
O E
WO
N R
11 10 9 8 7
6 5 4 3 2 1 0
Offset 0
RSVD (18 bits)
Buffer_Size (12 bits)
RSVD
RX_BUFFER_ADDRESS
RSVD
RSVD
Offset#
Bit#
31
30
29:12
11:0
12
31:0
31:0
31:0
Offset 4
Offset 8
Offset 12
Offset 16
Table 24. Rx Command Descriptor (OWN=1)
Symbol
Description
OWN
Ownership.
When set, this bit indicates that the descriptor is owned by the NIC, and is ready
to receive a packet. The OWN bit is set by the driver after having pre-allocated a
buffer at initialization, or the host has released the buffer to the driver. In this
case, OWN=1.
EOR
End of Rx Descriptor Ring.
This bit set to 1 indicates that this descriptor is the last descriptor of the Rx
descriptor ring. Once the NIC’s internal receive descriptor pointer reaches here, it
will return to the first descriptor of the Rx descriptor ring after this descriptor is
used by packet reception.
RSVD
Reserved.
Buffer_Size
Buffer Size.
This field indicates the receive buffer size in bytes.
RSVD
Reserved.
RxBuff
32-bit Receive Buffer Address.
RSVD
Reserved.
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Datasheet
Rx Status Descriptor (OWN=0)
When packet is received, the Rx command descriptor becomes a Rx status descriptor.
Table 25. Rx Status Descriptor (OWN=0)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7
O E F L D F S
WO S S MO P
N R
A V L
F F C
RSVD
(4 bits)
FOT (8 bits)
T RXRATE Q M P B R P
R (4 bits) O A A A E W
S R MR S R
TSFTL
TSFTH
AGC (8 bits)
PWDB_GI2 (8 bits)
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C I
R C
C V
Offset 0
Frame_Length (12 bits)
Offset 4
Offset 8
Offset 12
RSSI
(7 bits)
CFO_BIAS
(6 bits)
36
6 5 4 3 2 1 0
SQ
(8 bits)
SNR_LONG2
END (6 bits)
NUM_MC Offset 16
SI (4 bits)
Track ID: JATR-1076-21 Rev. 1.0
RTL8187SE
Datasheet
Offset#
Bit#
Symbol
31
OWN
30
EOR
29
FS
28
LS
27
DMAF
26
FOVF
25
SPLCP
24
23:20
TRSW
RXRATE
19
QoS
Table 26. Rx Status Descriptor
Description
Ownership.
When set, this bit indicates that the descriptor is owned by the NIC. When
cleared, it indicates that the descriptor is owned by the host system. The NIC
clears this bit when the NIC has filled this Rx buffer with a packet or part of a
packet. In this case, OWN=0.
End Of Rx Descriptor Ring.
This bit set to 1 indicates that this descriptor is the last descriptor of the Rx
descriptor ring. Once the NIC’s internal receive descriptor pointer reaches
here, it will return to the first descriptor of the Rx descriptor ring after this
descriptor is used by packet reception.
First Segment Descriptor.
When set, this bit indicates that this is the first descriptor of a received packet,
and that this descriptor is pointing to the first segment of the packet.
Last Segment Descriptor.
When set, this bit indicates that this is the last descriptor of a received packet,
and this descriptor is pointing to the last segment of the packet.
RX DMA Fail.
When set, this packet will be dropped by software.
FIFO Overflow.
When set, this bit indicates that the receive FIFO was exhausted before this
packet was fully received.
Short Physical Layer Convergence Protocol format.
When set, this bit indicates that a short PLCP preamble was added to the
current received frame.
T/R Switch.
Rx Rate.
These four bits indicate the current frame’s receiving rate.
Bit 23
Bit 22
Bit 21
Bit 20
1Mbps
2Mbps
5.5Mbps
11Mbps
6Mbps
9Mbps
12Mbps
18Mbps
24Mbps
36Mbps
48Mbps
54Mbps
Reserved
All Other Combinations
QoS Packet Received.
When set, this bit indicates that a QoS packet was received.
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Datasheet
Offset#
Bit#
Symbol
18
MAR
17
16
15
14
13
12
11:0
12
12
12
12
12
12
12
31:0
31:0
31:27
26
25
24
23:16
15
14:8
12
7:0
16
31:24
16
23:16
16
15:10
16
9:4
16
3:0
Description
Multicast Address Packet Received.
When set, this bit indicates that a multicast packet was received.
PAM
Physical Address Matched.
When set, this bit indicates that the destination address of this Rx packet
matches the value in the RTL8187SE’s ID registers.
BAR
Broadcast Address Received.
When set, this bit indicates that a broadcast packet was received. BAR and
MAR will not be set simultaneously.
RES
Receive Error.
Valid if DMAF=0
PWRMGT
Receive Power Management Packet.
When set, this bit indicates that the Power Management bit is set on the
received packet.
CRC32
CRC32 Error.
When set, this bit indicates that a CRC32 error has occurred on the received
packet. A CRC32 packet can be received only when RCR_ACRC32 is set.
ICV
Integrity Check Value Error.
When set, this bit indicates that an ICV error has occurred on the received
packet. An ICV packet can be received only when RCR_AICV is set.
Frame_Length
When OWN=0 and LS =1, this bit indicates the received packet length,
including CRC32, in bytes.
TSFTL
A snapshot of the TSFTR’s least significant 32 bits. Valid only when LS is set.
TSFTH
A snapshot of the TSFTR’s most significant 32 bits. Valid only when LS is set.
RSVD
Reserved.
SHIFT
0: 4-byte alignment not needed.
1: 4-byte alignment needed.
WAKEUP
The received packet is a unicast wakeup packet.
DECRYPTED
The received packet has been decrypted.
AGC
The AGC of the received packet.
ANTENNA
The received packet is received through this antenna.
RSSI
Received Signal Strength Indicator.
The RSSI is a measure of the RF energy received by the PHY.
SQ
Signal Quality.
The SQ is a measure of the quality of BAKER code lock, providing an
effective measure during the full reception of a PLCP preamble and header.
FOT
Final frequency offset estimate (*2.44kHz), s(8.0)
FOT x 2.44kHz.
PWdB
Received Power in dB at flag_gi2 up, s(8.1)
RxPower=PWdB/2-42dBm.
CFO_Bias
Frequency difference between final frequency offset tracking and coarse
frequency offset estimation (FOT-CFOE) x 2.44kHz.
SNR_LONG2END Measured SNR in dB by the difference between LONG1 and LONG2, s(8.2)
SnrLong = SNR_LONG2END/4dB.
NUM_MCSI
Number of MCSI (Masked-CSI subcarriers).
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Datasheet
9.2.
Loopback Operation
Loopback mode is normally used to verify that the logic operations have performed correctly. In loopback
mode, the RTL8187SE takes frames from the transmit descriptor and transmits them up to internal Rx logic.
The loopback function does not apply to an external PHYceiver.
9.3.
QoS Functions
The RTL8187SE supports WMM, APSD, and IEEE 802.11e functions.
9.4.
LED Functions
The RTL8187SE supports 2 LED signals in 4 configurable operation modes.
Software Control Mode: In this mode, LED can be totally controlled by software.
Tx/Rx Active Mode: Active when transmission or reception occurs. Can be configured as high active or
low active.
Tx Active Mode: Active while transmitting. Can be configured as high active or low active.
Rx Active Mode: Active while receiving. Can be configured as high active or low active.
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Datasheet
10.
Application Diagram
Figure 5. Application Diagram
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Datasheet
11. Electrical Characteristics
11.1. Temperature Limit Ratings
Parameter
Storage Temperature
Ambient Operating Temperature
Junction Temperature
11.2.
Symbol
VDD33
VDD18
Voh
Table 27. Temperature Limit Ratings
Minimum
Maximum
-55
125
70
125
Units
DC Characteristics
Table 28. DC Characteristics
Parameter
Conditions
Minimum
3.3V Supply Voltage
3.0
1.8V Supply Voltage
1.7
Minimum High Level Output Voltage
Ioh=-8mA
0.9*Vcc
Vol
Maximum Low Level Output Voltage
Vih
Typical
3.3
1.8
Maximum
3.6
1.9
Vcc
Units
Iol=8mA
0.1*Vcc
Minimum High Level Input Voltage
0.5*Vcc
Vcc+0.5
Vil
Maximum Low Level Input Voltage
-0.5
0.3*Vcc
Iin
Input Current
Vin=Vcc or GND
-1.0
1.0
A
Ioz
Tri-State Output Leakage Current
Vout=Vcc or GND
-10
10
A
Icc
Average Operating Supply Current
Iout=0mA
242
mA
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Datasheet
11.3.
11.3.1.
AC Characteristics
Serial EEPROM Interface Timing
(93C46(64*16)/93C56(128*16))
EESK
EECS
EEDI
tcs
(Read)
An
A2
A1
A0
(Read)
EEDO High Impedance
Dn
D1
D0
EESK
EECS
EEDI
tcs
(Write)
An
...
A0
Dn
...
D0
(Write)
EEDO High Impedance
BUSY
READY
twp
tsk
EESK
tskh
EECS
tcss
tdis
tskl
tcsh
tdih
EEDI
tdos
tdoh
EEDO (Read)
EEDO
tsv
STATUS VALID
(Program)
Figure 6. Serial EEPROM Interface Timing
Symbol
tcs
twp
tsk
tskh
tskl
tcss
tcsh
tdis
tdih
tdos
tdoh
tsv
Table 29. EEPROM Access Timing Parameters
Parameter
Minimum
Typical
Minimum CS Low Time
9346/9356
1000/250
Write Cycle Time
9346/9356
SK Clock Cycle Time
9346/9356
4/1
SK High Time
9346/9356
1000/500
SK Low Time
9346/9356
1000/250
CS Setup Time
9346/9356
200/50
CS Hold Time
9346/9356
0/0
DI Setup Time
9346/9356
400/50
DI Hold Time
9346/9356
400/100
DO Setup Time
9346/9356
2000/500
DO Hold Time
9346/9356
CS to Status Valid
9346/9356
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Maximum
10/10
2000/500
1000/500
Units
ns
ms
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
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Datasheet
11.4.
11.4.1.
PCI Express Bus Parameters
Differential Transmitter Parameters
Symbol
UI
VTX-DIFFp-p
VTX-DE-RATIO
TTX-EYE
TTX-EYE-MEDIANto-MAX-JITTER
TTX-RISE, TTX-FALL
VTX-CM-ACp
VTX-CM-DCACTIVEIDLEDELTA
Table 30. Differential Transmitter Parameters
Parameter
Min
Unit Interval
399.88
Differential Peak to Peak Output Voltage
0.800
De-Emphasized Differential Output Voltage (Ratio)
-3.0
Minimum Tx Eye Width
0.75
Maximum time between the jitter median and
maximum deviation from the median
D+/D- Tx Output Rise/Fall Time
0.125
RMS AC Peak Common Mode Output Voltage
Absolute Delta of DC Common Mode Voltage During
L0 and Electrical Idle
Typical
400
-3.5
Max
400.12
1.2
-4.0
0.125
Units
ps
dB
UI
UI
20
100
UI
mV
mV
VTX-CM-DCLINE- DELTA
Absolute Delta of DC Common Mode Voltage between
25
mV
D+ and DVTX-IDLE-DIFFp
Electrical Idle Differential Peak Output Voltage
20
mV
VTX-RCV-DETECT
The amount of voltage change allowed during
600
mV
Receiver Detection
VTX-DC-CM
The TX DC Common Mode Voltage
3.6
ITX-SHORT
TX Short Circuit Current Limit
90
mA
TTX-IDLE-MIN
Minimum Time Spent in Electrical Idle
50
UI
TTX-IDLE- SETTO-IDLE
Maximum time to transition to a valid Electrical Idle
20
UI
after sending an Electrical Idle ordered set
Maximum time to transition to valid TX specifications
20
UI
TTX-IDLE-TOTOafter leaving an Electrical Idle condition
DIFF-DATA
RLTX-DIFF
Differential Return Loss
10
dB
RLTX-CM
Common Mode Return Loss
dB
ZTX-DIFF-DC
DC Differential TX Impedance
80
100
120
LTX-SKEW
Lane-to-Lane Output Skew
500+2UI
ps
CTX
AC Coupling Capacitor
75
200
nF
Tcrosslink
Crosslink Random Timeout
ms
Note1: Refer to PCI Express Base Specification, rev.1.1, for correct measurement environment setting of each parameter.
Note2: The data rate can be modulated with an SSC (Spread Spectrum Clock) from +0 to -0.5% of the nominal data rate
frequency, at a modulation rate in the range not exceeding 30 kHz – 33 kHz. The +/- 300 ppm requirement still holds, which
requires the two communicating ports be modulated such that they never exceed a total of 600 ppm difference.
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Datasheet
11.4.2.
Differential Receiver Parameters
Table 31. Differential Receiver Parameters
Parameter
Min.
Typical
Max.
Units
Unit Interval
399.88
400
400.12
ps
Differential Input Peak to Peak Voltage
0.175
1.200
Minimum Receiver Eye Width
0.4
UI
Maximum time between the jitter median and maximum
0.3
UI
deviation from the median
MAX-JITTER
VRX-CM-ACp
AC Peak Common Mode Input Voltage
150
mV
RLRX-DIFF
Differential Return Loss
10
dB
RLRX-CM
Common Mode Return Loss
dB
ZRX-DIFF-DC
DC Differential Input Impedance
80
100
120
ZRX--DC
DC Input Impedance
40
50
60
ZRX-HIGH-IMP-DC
Powered Down DC Input Impedance
200k
VRX-IDLE-DET-DIFFp-p Electrical Idle Detect Threshold
65
175
mV
Unexpected Electrical Idle Enter Detect Threshold
10
ms
TRX-IDLE-DETIntegration Time
DIFFENTERTIME
LRX-SKEW
Total Skew
20
ns
Note: Refer to PCI Express Base Specification, rev.1.1, for correct measurement environment setting of each parameter.
Symbol
UI
VRX-DIFFp-p
TRX-EYE
TRX-EYE-MEDIAN-to-
11.4.3.
REFCLK Parameters
Symbol
Rise Edge Rate
Fall Edge Rate
VIH
VIL
VCROSS
VCROSS DELTA
VRB
TSTABLE
TPERIOD AVG
TPERIOD ABS
TCCJITTER
VMAX
VMIN
Duty Cycle
Table 32. REFCLK Parameters
100MHz Input
Min
Max
Rising Edge Rate
0.6
4.0
Falling Edge Rate
0.6
4.0
Differential Input High Voltage
+150
Differential Input Low Voltage
-150
Absolute Crossing Point Voltage
+250
+550
Variation of VCROSS Over All Rising
+140
Clock Edges
Ring-Back Voltage Margin
-100
+100
Time before VRB is Allowed
500
Average Clock Period Accuracy
-300
+2800
Absolute Period (Including Jitter and
9.847
10.203
Spread Spectrum)
Cycle to Cycle Jitter
150
Absolute Max Input Voltage
+1.15
Absolute Min Input Voltage
-0.3
Duty Cycle
40
60
Parameter
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Units
Note
V/ns
V/ns
mV
mV
mV
mV
2, 3
2, 3
1, 4, 5
1, 4, 9
mV
ps
ppm
ns
2, 12
2, 12
2, 10, 13
2, 6
ps
1, 7
1, 8
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RTL8187SE
Datasheet
Symbol
Parameter
100MHz Input
Min
Max
20
Rise-Fall Matching
Units
Note
Rising edge rate (REFCLK+) to falling
1, 14
edge rate (REFCLK-) matching
ZC-DC
Clock Source DC Impedance
40
60
1, 11
Note1: Measurement taken from single ended waveform.
Note2: Measurement taken from differential waveform.
Note3: Measured from -150 mV to +150 mV on the differential waveform (derived from REFCLK+ minus REFCLK-). The
signal must be monotonic through the measurement region for rise and fall time. The 300 mV measurement window is
centered on the differential zero crossing.
Note4: Measured at crossing point where the instantaneous voltage value of the rising edge of REFCLK+ equals the falling
edge of REFCLK-.
Note5: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing.
Refers to all crossing points for this measurement.
Note6: Defines as the absolute minimum or maximum instantaneous period. This includes cycle to cycle jitter, relative PPM
tolerance, and spread spectrum modulation.
Note7: Defined as the maximum instantaneous voltage including overshoot.
Note8: Defined as the minimum instantaneous voltage including undershoot.
Note9: Defined as the total variation of all crossing voltages of Rising REFCLK+ and Falling REFCLK-. This is the
maximum allowed variance in VCROSS for any particular system.
Note10: Refer to Section 4.3.2.1 of the PCI Express Base Specification, Revision 1.1 for information regarding PPM
considerations.
Note11: System board compliance measurements must use the test load card described in Figure16. REFCLK+ and
REFCLK- are to be measured at the load capacitors CL. Single ended probes must be used for measurements requiring
single ended measurements. Either single ended probes with math or differential probe can be used for differential
measurements. Test load CL = 2 pF.
Note12: TSTABLE is the time the differential clock must maintain a minimum ±150 mV differential voltage after rising/falling
edges before it is allowed to droop back into the VRB ±100 mV differential range. See Figure 15.
Note13: PPM refers to parts per million and is a DC absolute period accuracy specification. 1 PPM is 1/1,000,000th of
100.000000 MHz exactly or 100 Hz. For 300 PPM then we have a error budget of 100 Hz/PPM * 300 PPM = 30 kHz. The
period is to be measured with a frequency counter with measurement window set to 100 ms or greater. The ±300 PPM
applies to systems that do not employ Spread Spectrum or that use common clock source. For systems employing Spread
Spectrum there is an additional 2500 PPM nominal shift in maximum period resulting from the 0.5% down spread resulting
in a maximum average period specification of +2800 PPM
Note14: Matching applies to rising edge rate for REFCLK+ and falling edge rate for REFCLK-. It is measured using a ±75
mV window centered on the median cross point where REFCLK+ rising meets REFCLK- falling. The median cross point is
used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The Rise Edge Rate of
REFCLK+ should be compared to the Fall Edge Rate of REFCLK-, the maximum allowed difference should not exceed
20% of the slowest edge rate.
Note15: Refer to PCI Express Card Electromechanical Specification, rev.1.1, for correct measurement environment setting
of each parameter.
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Datasheet
Figure 7. Single-Ended Measurement Points for Absolute Cross Point and Swing
Figure 8. Single-Ended Measurement Points for Delta Cross Point
Figure 9. Single-Ended Measurement Points for Rise and Fall Time Matching
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Datasheet
Figure 10. Differential Measurement Points for Duty Cycle and Period
Figure 11. Differential Measurement Points for Rise and Fall Time
Figure 12. Differential Measurement Points for Ringback
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Datasheet
Figure 13. Reference Clock System Measurement Point and Loading
11.4.4.
Symbol
TPVPERL
TPERST-CLK
TPERST
TFAIL
TWKRF
Auxiliary Signal Timing Parameters
Table 33. Auxiliary Signal Timing Parameters
Parameter
Min
Power Stable to PERSTB Inactive
100
REFCLK Stable before PERSTB Inactive
100
PERSTB Active Time
100
Power Level Invalid to PWRGD Inactive
LANWAKEB Rise/Fall Time
Max
500
100
Units
ms
µs
µs
ns
ns
Figure 14. Auxiliary Signal Timing
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Datasheet
12.
Mechanical Dimensions
Note: The RTL8187SE Exposed Pad Size is type 3.
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Track ID: JATR-1076-21 Rev. 1.0
RTL8187SE
Datasheet
13.
Ordering Information
Table 34. Ordering Information
Part Number
Package
RTL8187SE-GR
64-Pin E-pad QFN with Green Package
Note: See page 7 for Green package identification.
Status
Production
Federal Communication Commission Interference Statement This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to
Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates,
uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications.
However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception,
which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one of the following measures:
Reorient or relocate the receiving antenna.
Increase the separation between the equipment and receiver.
Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
Consult the dealer or an experienced radio/TV technician for help.
Any changes or modifications not expressly approved by the party responsible for compliance could void the user’s authority to operate this equipment.
For product available in the USA/Canada market, only channel 1~11 can be operated. Selection of other channels is not possible. This device and its antenna(s) must not
be co-located or operation in conjunction with any other antenna or transmitter. FCC Radiation Exposure Statement: This equipment complies with FCC radiation exposure
limits set forth for an uncontrolled environment. This equipment should be installed and operated with minimum distance 20cm between the radiator & your body.
IMPORTANT NOTE: This module is intended for OEM integrator. The OEM integrator is still responsible for the FCC compliance requirement of the end
product, which integrates this module. 20cm minimum distance has to be able to be maintained between the antenna and the users for the host this module
is integrated into. Under such configuration, the FCC radiation exposure limits set forth for an population/uncontrolled environment can be satisfied. Any
changes or modifications not expressly approved by the manufacturer could void the user's authority to operate this equipment. USERS MANUAL OF THE
END PRODUCT: In the users manual of the end product, the end user has to be informed to keep at least 20cm separation with the antenna while this end
product is installed and operated. The end user has to be informed that the FCC radio-frequency exposure guidelines for an uncontrolled environment can
be satisfied. The end user has to also be informed that any changes or modifications not expressly approved by the manufacturer could void the user's
authority to operate this equipment. If the size of the end product is smaller than 8x10cm, then additional FCC part 15.19 statement is required to be
available in the users manual: This device complies with Part 15 of FCC rules. Operation is subject to the following two conditions: (1) this device may not
cause harmful interference and (2) this device must accept any interference received, including interference that may cause undesired operation. LABEL
OF THE END PRODUCT: The final end product must be labeled in a visible area with the following " Contains TX FCC ID: TX2-RTL8187SE ". If the size of
the end product is larger than 8x10cm, then the following FCC part 15.19 statement has to also be available on the label: This device complies with Part
15 of FCC rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference and (2) this device must accept any
interference received, including interference that may cause undesired operation.
This Class B digital apparatus complies with Canadian ICES-003. Cet appareil numérique de la classe B conforme á la norme NMB-003 du Canada.
Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, including interference that
may cause undesired operation of the device. For product available in the USA/Canada market, only channel 1~11 can be operated. Selection of other channels is not
possible. This device and its antenna(s) must not be co-located or operation in conjunction with any other antenna or transmitter.To reduce potential radio interference to
other users, the antenna type and its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p) is not more than that permitted for successful
communication. IC Radiation Exposure Statement: This equipment complies with IC RSS-102 radiation exposure limits set forth for an uncontrolled environment. This
equipment should be installed and operated with minimum distance 20cm between the radiator & your body.
IMPORTANT NOTE: This module is intended for OEM integrator. The OEM integrator is still responsible for the IC compliance requirement of the end product, which integrates this
module. 20cm minimum distance has to be able to be maintained between the antenna and the users for the host this module is integrated into. Under such configuration, the IC
RSS-102 radiation exposure limits set forth for an population/uncontrolled environment can be satisfied. Any changes or modifications not expressly approved by the manufacturer could
void the user's authority to operate this equipment. USERS MANUAL OF THE END PRODUCT: In the users manual of the end product, the end user has to be informed to keep at least
20cm separation with the antenna while this end product is installed and operated. The end user has to be informed that the IC radio-frequency exposure guidelines for an uncontrolled
environment can be satisfied. The end user has to also be informed that any changes or modifications not expressly approved by the manufacturer could void the user's authority to
operate this equipment. IC statement is required to be available in the users manual: This Class B digital apparatus complies with Canadian ICES-003. Operation is subject to the
following two conditions: (1) this device may not cause harmful interference and (2) this device must accept any interference received, including interference that may cause undesired
operation. LABEL OF THE END PRODUCT: The final end product must be labeled in a visible area with the following " Contains TX IC : 6317A-RTL8187SE".
Hereby, Realtek, declares that this device is in compliance with the essential requirement and other relevant provisions of the R&TTE Driective 1999/5/EC. This device will
be sold in the following EEA countries：Austria, Italy, Belgium, Liechtenstein, Denmark, Luxembourg, Finland, Netherlands, France, Norway, Germany, Portugal, Greece,
Spain, Iceland, Sweden, Ireland, United Kingdom, Cyprus, Czech Republic, Estonia, Hungary, Latvia, Lithuania, Malta, Slovakia, Poland, Slovenia Bulgaria, Romania.
Realtek Semiconductor Corp.
HeadqµArters
No. 2, Innovation Road II, Hsinchu Science Park,
Hsinchu 300, Taiwan.
Tel: 886-3-5780211 Fax: 886-3-5776047
www.realtek.com.tw
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w/PCI Express Interface
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Track ID: JATR-1076-21 Rev. 1.0

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