Baron Services DSSR-250C Pulsar Digital Solid-State Radar System User Manual

Baron Services Inc Pulsar Digital Solid-State Radar System

UserManual.wiki >

Baron Services >

DSSR-250C User Manual >

Hardware Installation

Hardware InstallationRVP8 User’s ManualSeptember 20052–32.2.2 IFD Revision HistoryThere have been several hardware revisions of the IFD module since its introduction initiallywith the RVP7. Table 2–1 summarizes the differences among all of the versions that have beenmanufactured so far. The remainder of this chapter covers only the 14-bit units, although theprevious generation 12-bit units are compatible with the RVP8 as well.Table 2–1: Differences Among Versions of the IFDRev.B Rev.C Rev.D Rev.E & HigherA/D Chip Analog Devices AD9042, 12–Bits AD6644, 14–Bits AD6645, 14–BitsNominal IFSample Rate 36MHz 72MHzIF Inputs Single IF Input Channel Dual IF InputsA/D NoiseDensity –76dBm/MHz –82dBm/MHz –85dBm/MHzDynamicRange 86dB at 0.5MHz 93dB at 0.5MHz 96dB at 0.5MHzLink to Rx Coax uplink, Fiber downlink Integrated CAT-5EUpgradability FPGA chips must be manually reprogrammed ReFlashable via Rx-LinkInput SignalLevel A/D saturation at +4.5dBm A/D saturation at +6.0dBmExt-Clock No Yes (shared with AFC connector)NoiseGeneratorNone. The A/D dither power mustbe supplied from wideband thermalnoise in the RF/IF chain.Built-in noise source supplies A/D dither power in the200–900KHz range.Power Supplies +5.17V, +12V, –12V +5.23V Primarily.+12/15V required only foranalog AFC output+5.33V Primarily.+12/15V required forAFC, Hi-DAFC or stableVCXO (recommended). –12/15V required only foranalog AFC output.Jumpers(Table 2–7) None AFC/Clock I/O AFC/Clock I/O,Dither and ConfigSelectionsAFC/Clock I/O, JTAG,DAFC/Clock and ConfigSelectionsUplinkProtocols AFC-16 AFC-16 &PLL-16 Supports full set of protocols defined in Section 2.5.1FirstProduction March 1997 April 1998 December 2000 August 2004

Hardware InstallationRVP8 User’s ManualSeptember 20052–42.2.3 IFD Power, Size and Mounting ConsiderationsThe IFD is a compact sealed module with dimensions 23.6 x 10.9 x 3.0 cm. (9.3 x 4.3 x 1.2 in).The unit is designed to be mounted on edge such that the 23.6 x 3.0 cm. surface is flush on theback of the receiver cabinet with 10.9 cm. protrusion into the cabinet. The unit is typicallyplaced where a traditional LOG receiver would be installed. The IFD is cooled by directconduction through its metal enclosure. It should be positioned so that air can freely convectaround it, or bolted to a larger surface that will conduct the heat away.The power supply module is separate and can be mounted nearby in the radar cabinet, or it canbe attached directly to the IFD using a special mounting bracket. The power supply and bracketwill add 3.3 cm. (1.3 in) of overall width to the receiver module.The power supply is a low noise, low ripple, switching unit; the input voltage range is 100–240VAC 47–63 Hz, autoranging. The IFD has an internal 3-stage power supply input filter tominimize interference from the power cable. Nonetheless, it is still good practice to insure thatthe four supply wires (+5V, –12V, +12V, and Ground) be kept short and twisted together. Aferrite choke around the supply wires near the terminal strip is also recommended.Important: The inductive filtering components inside the IFD introduce avoltage drop in the +5V supply. To produce the correct internal voltage, thesupply voltage measured at the external terminal block should be 5.33V forRev.E and later, 5.23V for Rev.D, and 5.17V for Rev.C and earlier boards.Important: The voltage drop across the inductive filtering components causesthe ground terminal of the power supply to float several tenths of a volt abovechassis ground. For this reason, the IFD power supply should never be tappedto supply power to other nearby equipment.Mounting space should also be reserved for the external analog anti-alias filters. These filterscan be mounted in the radar cabinet itself, or they can be attached directly to the IFD on theopposite side of the power supply. The filters and mounting bracket will add 2.0 cm. (0.8 in) ofoverall width.The 72MHz CAT-5E IFD (Rev.F) represents a factor–of–two improvement in A/D sampling rateand communications bandwidth between the IFD and RVP8/Rx card. This provides importantadvantages in the performance of your radar system, but it does also place greater demands onthe connecting link. The CAT-5E cable carries real–time 1.080MBaud downlink serial data onthree of its four twisted pairs, and uses the fourth pair for uplink communication. The data rateon each downlink pair actually exceeds the data rate for GigaBit ethernet, hence very highquality cable must be used, and maximum cable length is limited to 25-meters. There is also aminimum cable length of 2-meters.We recommend using a shielded CAT–5E cable (certified to >= 350MHz) having shielded RJ45plugs on each end. The Rx board provides a DC return path for the cable shield, while the IFDprovides an AC GND only (isolated to 2KV). This design prevents ground loop currents fromflowing between units, even when they’re plugged into different AC/Mains.

Hardware InstallationRVP8 User’s ManualSeptember 20052–52.2.4 IFD I/O SummaryThe connectors on the IFD are labelled and described below for each hardware revision.Table 2–2: IFD Connectors (All Revisions)IFD I/O SummaryConnectorLabelStyle Description ReferenceJ1IFĆINSMA IF signal from LNA/mixer; via an antiĆaliasing filtercentered at IF (supplied by SIGMET). 50W, + 6.5 dBmmax2.2.62.2.72.2.82.2.10J2BURST(COHO)SMA IF Tx sample from waveguide tap and mixer; via anantiĆaliasing filter centered at IF (supplied by SIGĆMET). 50W, +6.5 dBm max2.2.6J3AFC(CLK)SMA AFC output (+-10V) or reference clock input for coĆherent systems (2-60 MHz -10 to 0 dBm). The funcĆtion of the connector is controlled by jumper selecĆtion within the IFD.2.2.11 AFC2.2.12 CLKSince they share the same connector, analog AFC output and reference clock input can not beused simultaneously. However, this is a very rare requirement since an analog AFC output isused for magnetron systems and a reference clock input is typically used for fully coherent TWTand Klystron systems.Table 2–3: IFD Connectors (Rev.A–Rev.D)IFD I/O SummaryConnectorLabelStyle Description ReferenceJ4UPLINKSMA/BNC Connects to the RVP8/Rx PCI card by 75 Ohmshielded cable. The connector is SMA with an SMA/BNC adapter provided.2.2.13J5FIBERĆOUTST 62.5/125 micron multimode optical cable terminatedin type ST connectors. IFD cam be located up to100m from the RVP8/Rx PCI card.2.2.13Table 2–4: IFD Connectors (Rev.E & Greater)IFD I/O SummaryConnectorLabelStyle Description ReferenceJ4DAFC(CLK)SMA Synthesized legacy coax uplink stream for backwardcompatibility, or Expansion Clock input or output.2.2.13J5RxĆLinkRJĆ45 Connects to the RVP8/Rx PCI card via CATĆ5E cableup to 25Ćmeters in length.2.2.13

Hardware InstallationRVP8 User’s ManualSeptember 20052–62.2.5 IFD Adjustments and Test/Status IndicatorsThe IFD is packaged in a tight metal enclosure for maximum noise immunity. The onlyadjustments on the module are the internal gain and offset pots that adjust the AFC analogoutput. Two switches on the unit provide standalone test features to verify the proper functioningof the IFD and to assist with setting the voltage span of the AFC DAC.Table 2–5: IFD Toggle Switch SettingsSW1 SW2 Function A A AFC Test Low Voltage A B AFC Test Midpoint Voltage A C AFC Test High Voltage B A Swap Burst and IF Input Signals B B Normal Operation (also labeled as “run”) B C Reserved (downlink test pattern) C A Reserved C B Reserved (downlink test pattern) C C Reserved (downlink test pattern)Two LEDs provide status information for the IFD itself, as well as status of the communicationlink(s) to the RVP8/Rx PCI card. These LEDs have the same interpretation across all revisionsof the IFD. For Rev.B through Rev.D the words “uplink” and “downlink” refer to the physicalcoax uplink and fiber downlink cables. For Rev.E and higher, those words refer to conceptuallysimilar uses of the four twisted pairs within the integrated CAT-5E link.Table 2–6: IFD LED Indicator InterpretationsRed (Uplink) Green (Ready) Meaning Blink Blink Reset sequence (powerup, or from uplink) Blink Off Uplink is dead (no uplink protocol from RVP8/Rx) On Off Uplink is alive, but downlink is dead On On Normal Operation (IFD and Main are both okay)For IFDs at Rev.E and higher, the two LEDs on the RJ-45 connector also convey status about theCAT-5E link itself. Green indicates that valid clock and framing waveforms are present on theuplink. Yellow indicates that the RVP8/Rx card is receiving valid data from the IFD, includingthe IFD’s report of the uplink being okay. These LEDs show valid status at all times (not justwhen the RVP8 software is running) and thus, both indicators should be illuminated wheneverthe CAT-5E cable is connected. Moreover, the Green/Yellow interpretation is consistent at boththe IFD and RVP8/Rx ends: green indicates the reception of proper low-level electrical and

Hardware InstallationRVP8 User’s ManualSeptember 20052–7framing protocols, and yellow indicates that the green LED is ON at the other end, i.e., that theother end is receiving our transmissions correctly and is able to communicate that informationback to us.The internal jumper settings are summarized in the following table. Please also refer to Sections2.2.11 and 2.2.12 for more information on setting up the AFC or External Clock options.Table 2–7: IFD Internal Jumper SettingsRev.B Rev.C Rev.D Rev.E and HigherJP1 N/A AB: AFC Voltage OutputBC: External Clock Input, 50W TerminationOpen: External Clock Input, No TerminationJP2 N/A Reserved (Open) AB: Normal JTAG controlBC: Factory reservedJP3 N/A AB: UnusedBC: External ClockOpen: AFC Voltage OutputPower Supply to OscillatorUse wirewrap, not jumperAB: Regulated from +12VBC: Direct from +5VJP4 N/A AB: Dither Applied to BurstBC: No Dither on Burst AB: Oscillator is a VCXOBC: Oscillator is fixed XOJP5 N/A Reserved for factory testsMust be left openJP6 N/A J4 Protocol SelectorAB: Legacy DAFC outputBC: Auxiliary CLK In/OutJP7 N/A J4 DAFC Output LevelAB: +5V SignalingBC: +12V Signaling

Hardware InstallationRVP8 User’s ManualSeptember 20052–82.2.6 IFD Input A/D Saturation LevelsThere are two analog signals that must be supplied to the IFD:SIF receiver signalSIF Tx Sample (Burst Pulse) for magnetron, or COHO reference for klystron.Both of these inputs are on SMA connectors. The IF signal should be driven by the front-endmixer/LNA/IF-Amp. components, similar to the way that a LOG receiver would normally beinstalled. The magnetron burst pulse or klystron COHO reference is also derived in the samemanner as a traditional analog receiver.Note: Even for fully coherent Klystron and TWT systems, SIGMETrecommends the use of an actual IF Tx sample. If this is not possible, then theCOHO itself may be used instead. If there is phase modulation, then thephase-shifted COHO should be input.The A/D input saturation level for both the IF-Input and Burst-Input is +6 dBm (4.5 dBm forRev.C or earlier). In almost all installations an external anti-alias filter is installed on both ofthese inputs. These filters (if supplied by SIGMET) are mounted externally on one side of theIFD, and have an insertion loss of approximately 1–2dB. Thus, the input saturation level will be+8dBm measured at the filter inputs.For the burst pulse or COHO reference it is important not to exceed the A/D saturation level.This reference signal should be strong enough so that most of the bits in the A/D converter areused effectively, but it should also allow a few deciBels below the saturation level for safety.The recommended power level is in the range –12 to +1 dBm, measured as described in sectionD.14. This is important for making a precise phase measurement on each pulse.In contrast, for the IF receiver input it is permissible (in fact desirable) to occasionally exceedthe A/D input saturation level at the strongest targets. The RVP8 employs a statisticallinearization algorithm to derive correct power levels from targets that are as much as 6dB abovesaturation. The actual IF signal level should be established by weak-signal and noiseconsiderations (see below), rather than by working backwards from the saturation level.

Hardware InstallationRVP8 User’s ManualSeptember 20052–92.2.7 IF Bandwidth and Dynamic RangeThe RVP8 performs best with a wide bandwidth IF input signal. This is because a widebandsignal can be made free of phase distortions within the (relatively narrow) matched passband ofthe received signal. The RVP8 uses an external analog anti-aliasing filter at each of its IF andBurst inputs. The purpose of these filters is to block frequencies that would otherwise alias intothe matched filter passband. The anti-alias filters have a nominal passband width of 14 MHzcentered at 30MHz, i.e. from 23MHz to 37MHz. This is the recommended operating bandwidthfor the IF signal, although the RVP8 will still work successfully with lesser IF bandwidth.At the 36MHz sampling rate the quantization noise introduced by LSB uncertainties is spreadover an 18MHz bandwidth. For an ideal 14-bit A/D converter that saturates at +6dBm theeffective quantization noise level would be:)6dBm *20log10(214)*10log10(18MHz1MHz )+*90dBm (at 1MHz BW)If samples from this ideal converter were processed with a digital filter having a bandwidth of1MHz, then an input signal at –90dBm would have a signal-to-noise ratio of 0dB. A narrowerFIR passband (corresponding to a longer transmitted pulse) would decrease the quantizationnoise even further, so that 0dB SNR would be achieved at even lower input power.In practice, the 14-bit A/D converter used inside the IFD does not behave quite this well. TheAnalog Devices AD6644 chip has been measured to have a wideband SNR of 76dB, i.e., 8dBless than the 84dB range expected for an ideal converter. The above calculation for noisedensity thus becomes:)6dBm *76dB *10log10(18MHz1MHz )+*82dBm (at 1MHz BW)Indeed, the RVP8’s receiver power monitor described in Section 4.5 will show a filtered powerlevel of approximately –82dBm when the FIR bandwidth is 1MHz and the IFD inputs areterminated in 50–Ohms.The inverse correspondence between filter bandwidth and the 0dB SNR signal level leads to aninteresting and useful property of wideband digital receivers: they can operate over a dynamicrange that is much greater than the inherent SNR of their A/D converter would imply. If thisparticular A/D chip were performing direct conversion at “base band” it would have a dynamicrange of only 76dB. However, by utilizing the extra bandwidth of the converter, the RVP8 isable to extend the dynamic range to approximately 100dB.To understand this, begin with the 88dB interval between the converter’s +6dBm saturation leveland the –82dBm 0dB SNR level at 1MHz bandwidth. Add to this:S6dB for the statistical linearization that is performed on signals that exceed the saturationlevel. The RVP8 can recover signal power accurately even when the A/D converter isdriven beyond saturation. Velocity data will also be valid, but spectral width may beoverestimated.S4dB for usable dynamic range below the 0dB SNR level. In practice, a coherent signal at–4dB SNR can easily be measured when 25 or more pulses are used.

Hardware InstallationRVP8 User’s ManualSeptember 20052–10Thus, the overall dynamic range at 1MHz bandwidth (approx. 1 msec transmit pulse) is 88+6+4= 98dB. For a 0.5 msec pulse the dynamic range would be reduced to 95dB; but it wouldincrease to 101dB for a 2.0 msec pulse. An actual calibration curve demonstrating thisperformance is shown in Figure 2–1, for which the RVP8’s digital bandwidth was set to0.53MHz and external signal generator steps of 1dB were used over the full operating range.Figure 2–1: Calibration Plot for a Stand-alone 14-Bit IFD–100–90–80–70–60–50–40–30–20–1001020–100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 10 201-dB Detection ThresholdInput Power in dBm Measured at IFD IF-Input1-dB Compression PointOverall Dynamic Range of 101dB

Hardware InstallationRVP8 User’s ManualSeptember 20052–112.2.8 IF Gain and System PerformanceThe previous discussion was concerned with measuring the dynamic range of a stand-alone IFD.We will now examine how the unit performs in the context of a complete radar receiver. Weassume that an LNA/Mixer has already been selected that offers an appropriate balance betweenprice and noise figure. Having chosen these front-end components, the only parameter thatremains to be determined is the total RF/IF gain between the antenna waveguide and the IFD.Assume that the thermal noise (kT) of the system is –114dBm/MHz, and that the noise figure ofthe LNA/Mixer is 2dB. We wish to bring this –112dBm/MHz noise level up into the workingrange of the IFD so that the received echoes can be optimally processed. However, in trying toselect the required gain, we realize that we must make a tradeoff between preserving the receiversensitivity that has been established by the LNA, and preserving the overall dynamic range ofthe IFD. This is the exact same tradeoff that is made in traditional multi-stage analog receiversystems that include a wide dynamic range LOG receiver.012345678910012345678910Reduction of Receiver Sensitivity (dB)Reduction of IFD Dynamic Range (dB)Figure 2–2: Tradeoff Between Dynamic Range and SensitivityRecommendedOperating RegionPower Ratio R = 10log10( NLNA / NIFD )The solid red curve in Figure 2–2 shows that these two variables interact in a symmetric manner,so that any operating point (x,y) is always matched by a dual operating point at (y,x). Tounderstand the construction of this plot, let NIFD represent the stand-alone (terminated input)

Hardware InstallationRVP8 User’s ManualSeptember 20052–12noise power of the IFD over some bandwidth. Similarly, let NLNA represent the LNA/Mixerthermal noise power over that same bandwidth, and after amplification by all RF and IF stages.Note that NIFD is primarily due to the quantization noise that is introduced by the A/D converter,whereas NLNA has its origins in the fundamental thermal noise of the receiving system. Thereduction of receiver sensitivity is the amount by which the LNA thermal noise is increased overthe original level established by the front-end components:DSensitivity +10 log10(NLNA )NIFD )*10 log10(NLNA )+10 log10ǒ1)NIFDNLNAǓLikewise, the reduction of RVP8 dynamic range is the amount by which the IFD quantizationnoise is increased over its stand-alone value:DDynamicRange +10 log10(NLNA )NIFD )*10 log10(NIFD )+10 log10ǒ1)NLNANIFDǓNote that both of these quantities depend only on the ratio of the two powers; hence, the twoequations define a parametric relationship in the dimensionless variable R+(NLNA ńNIFD ).Figure 2–2 was created by sweeping the value of R from 1/9 to 9. The solid red curve shows thelocus of ( DDynamicRange,DSensitivity ) points, and the dashed green curve shows R itself(expressed in dB) as a function of DDynamicRange. For example, when the LNA noise poweris equal to the IFD noise power, R is 1.0 (0dB) and there will be a 3dB reduction in bothsensitivity and dynamic range.The recommended operating region is the portion of the curve that limits the loss of sensitivityto between 1.4dB and 0.65dB. The attendant loss of dynamic range will fall between 5.5dB and8.5dB respectively. Each axis of the plot has an important physical interpretation within theradar system.SThe horizontal axis is equivalent to the increase in the RVP8’s report of filtered powerwhen the IF-Input coax cable is connected versus disconnected. This is an easy quantityto measure, and thus provides a simple way to check the overall gain of theLNA/Mixer/IF components.SThe vertical axis is equivalent to a worsening of the LNA/Mixer noise figure. This canalso be interpreted as the amount of transmit power that is, in some sense, “wasted” whenobserving very weak echoes. If you have installed an expensive LNA with a very lownoise figure, then you will want to pick an operating point that makes the most ofpreserving that investment.Figure 2–2 can be used to calculate the net gain that is required by the front-end components,and to predict the final system performance:1. Choose an operating point that balances your need for sensitivity versus dynamicrange. For this example, we will allow a 1dB loss of sensitivity from thetheoretical limit of the LNA/Mixer, and will assume a bandwidth of 0.5MHz.2. For a 1dB loss of sensitivity, the DDynamicRange is first determined from thesolid red curve as 7dB. The required noise ratio R is then read vertically on thedashed green curve as 6.1dB.

Hardware InstallationRVP8 User’s ManualSeptember 20052–133. Thus, the RF/IF gain must bring the front-end thermal noise at –112dBm/MHz upto a level that is 6.1dB higher than the IFD noise density of –82dBm/MHz. Thegain is therefore (–82dBm/MHz + 6dB) – (–112dBm/MHz) = 36dB. Note thatthis gain does not depend on bandwidth, and therefore will be correct for allpulsewidth/bandwidth combinations.4. The dynamic range for the complete system at 0.5MHz bandwidth may now becalculated as 101dB – 7dB = 94dB.5. After assembling all of the RF and IF components we can check whether weachieved the correct gain by verifying a 7dB rise (independent of bandwidth) inRVP8 filtered power when the IF-Input cable is connected versus disconnected.Keep in mind when designing your RF and IF components that the final amplifier driving theIFD must be capable of driving up to, perhaps, +12dBm, so that signals above saturation can stillbe correctly measured.2.2.9 IF Gain Based on System Noise FigureThe previous section described how to compute the front-end RF/IF gain based on the desiredtradeoff of dynamic range versus sensitivity. Since arriving at the proper gain is so important,we present an alternate but equivalent approach based on system noise figure.Every amplifier can be partially characterized by its gain “G” and noise figure “F”. Gain ismeasured quite simply by injecting a test signal at the mid-power range of the amplifier andmeasuring the ratio of Output/Input power. Noise figure is a little trickier, and is measured byterminating the input of the amplifier, measuring the output power within some prescribedbandwidth, and then dividing by the thermal noise power expected over that same bandwidthfrom an ideal amplifier having the same gain. For example, suppose that an amplifier with again of 20dB delivers –90dBm of output power within a 1MHz bandwidth when its input isterminated. We would expect the Boltzman thermal input noise at –114dBm/MHz to produce–94dBm from an ideal 20dB amplifier under the same conditions. The noise figure of the realamplifier is therefore +4dB, i.e., –90 minus –94.Although the above definitions are typically applied to linear analog amplifiers, these sameterms can be applied to hybrid analog/digital systems such as the RVP8.STo calculate the gain of the RVP8/IFD we apply a calibrated mid-power signal generatordirectly to its IF-Input and use the Pr plot (Section 4.5) to print the measured power. Fora wide range of analog input power levels the RVP8 will report the exact same measureddigital power; hence the overall analog/digital gain is 1.0 (0 dB).STo calculate the noise figure of the RVP8/IFD, we set the receiver bandwidth to 1MHz(Section 4.4.2), terminate the IF-Input in 50-Ohms, and again use the Pr plot, this time toexamine the in-band thermal noise power. For the Rev.D IFD this measured noise levelwill be around –82dBm. Since an ideal unity gain amplifier would have produced anoise power of –114dBm in an equivalent bandwidth, the noise figure of the RVP8/IFDis 32dB.

Hardware InstallationRVP8 User’s ManualSeptember 20052–14When two amplifiers are cascaded so that the output of the first drives the input of the second,the overall gain is the product of the two linear gains G1lin and G2lin, and the overall noise figure iscomputed from the two noise factors F1lin and F2lin as:NoiseFigure +10 log10ƪF1lin )ǒF2lin *1G1lin Ǔƫwhere the two noise factors are simply the linear representations of the noise figures that wereexpressed in deciBels:NoiseFigure +10 log10[NoiseFactor ] .Suppose that our first amplifier is an LNA/Preamp with a 2dB noise figure (noise factor 1.58),and we want to know what gain it must have such that, when cascaded into the RVP8/IFD, theoverall noise figure will be 3dB. The 32dB noise figure of the IFD is equivalent to a noisefactor of 1585, hence we have:3dB +10 log10ƪ1.58 )ǒ1585 *1G1lin Ǔƫfrom which we solve G1lin +3771, i.e., 35.8dB. This agrees with the 36dB of gain that wascomputed in the example of the previous section for the same RF/IF components and desiredoverall performance.2.2.10 Choice of Intermediate FrequencyThe RVP8 does not assume any particular relationship between the A/D sample clock and thereceiver’s intermediate frequency. You may operate at any IF that is at least 2MHz away fromany multiple of half the 35.9751MHz sampling rate (nominally 18, 36, 54, 72 MHz). The validfrequency bands are thus:6-16MHz, 20-34 MHz, 38-52 MHz, 56-70 MHzThere are many reasons for staying clear of the Nyquist frequency multiples. Most of theseconsiderations would apply to all types of digital processors, and are not specific to the RVP8.As an example of what can go wrong at the Nyquist frequencies, suppose that an intermediatefrequency of 35MHz was used. This is only 1MHz away from the (approximately) 36MHzsampling rate. The external anti-alias filter must now be designed much more carefully since aspurious input signal at 37MHz would be aliased into the valid 35MHz band. If the valid signalbandwidth were 2MHz, then the anti-alias filter would have the difficult task of passing34–36MHz free of distortion while rejecting everything above 36MHz. The filter’s transitionzone would have to be very sharp, and this is difficult to achieve.Another problem that would arise with a 35MHz IF on a magnetron system would be the RVP8’scomputation of AFC. If the processor can not distinguish 37MHz from 35MHz, then it can nottell the difference between the STALO being correctly on frequency, versus being 2MHz toohigh. The symmetric AFC tracking range would be reduced to the very small interval34–36MHz.

Hardware InstallationRVP8 User’s ManualSeptember 20052–15For similar reasons (i.e., transition band width), the digital FIR filter itself also becomes difficultto design when its passband is near a Nyquist multiple. But there is an additional constraint thatthe digital filter should have a very large attenuation at DC. This is so that fixed offsets in theA/D converter do not propagate into the synthesized “I” and “Q” data. Since 36MHz is aliasedinto DC, we are left with the contradictory requirements of a zero very close to the edge of thefilter’s passband.2.2.11 IFD Analog AFC Output Voltage (Optional)An analog AFC voltage is produced by a 16-bit DAC whose output limits are –10V to +10V.Gain and Offset potentiometers on the IFD module set the actual operating span within theselimits. Use the switch settings described below to force the low, center, and high voltages to beoutput, and then adjust the two potentiometers so that the desired voltage span is achieved. TheOffset adjustment is independent of the Gain adjustment. Hence, a good strategy is to first setthe switches for the midpoint voltage, and adjust the Offset potentiometer so that the center IFfrequency is produced by the STALO mixer. Then, adjust the Gain potentiometer for the desiredtuning range around that center point. The midpoint voltage will not change as you vary theoverall span.AFC voltage output is always enabled on Rev.B (and earlier) IFD boards. On Rev.C (and later)boards, the AFC function shares the same connector with the optional reference clock input (SeeSection 2.2.12). AFC can be enabled on a Rev.C board as follows:SRemove U14SInstall U11, U12, U13SSet JP1 to its AB position, which is also labeled “AFC”.SInstall fixed frequency stable 35.975MHz oscillator at U5.The instructions are similar for a Rev.D board except that you do not need to remove U14, andyou must check that no jumper has been placed on JP3/BC (See Table 2–7).Additional information about using AFC can be found in Sections 2.4, 3.2.6, and 5.1.3.2.2.12 IFD Reference Clock Input (Optional)When the RVP8 is used in a klystron system, or in any type of synchronous radar, the radarCOHO is supplied to the IFD so that the processor can digitally lock to it. The COHO phase ismeasured at the beginning of each transmitted pulse, and is used to lock the subsequent (I,Q)data for that pulse. The COHO phase is measured relative to the IFD’s own internal stablesampling clock, which is nominally 35.975MHz. The internal sampling clock itself is notaffected by the application of the COHO. Rather, A/D samples of the COHO are obtained at thefixed sampling rate, and the (I,Q) data are digitally locked downstream in the RVP8 IF-to-I/Qprocessing chain (see Figure 1–3). The procedure is identical to the manner in which phase isrecovered in a magnetron system, except that the COHO signal is used in place of a sample ofthe transmit burst.

Hardware InstallationRVP8 User’s ManualSeptember 20052–16There are two special concerns that may come up when the RVP8 is used in the above mannerwithin a synchronous radar system. Both concerns are the result of the IFD’s sampling clockbeing asynchronous with the radar system clock.SRVP8 Generates the Radar TriggerThe trigger signals supplied by the RVP8 are synchronous with the IFD data samplingclock. This is accomplished by a clock recovery PLL on the RVP8/Rx that provideson-board timing which is identical to the sampling clock in the IFD. However, since theIFD sampling clock is asynchronous with the radar clock(s), the RVP8 trigger outputs arelikewise asynchronous. The result is that each transmitted pulse envelope will betriggered independently of the COHO phase. The transmitted pulse is still synchronous–– but the precise alignment of the amplitude modulated envelope will vary.SIn almost all cases, the exact placement of the transmitter’s amplitude envelope does notaffect the overall system stability, nor the ability of the RVP8 to reject ground clutter andto process multi-mode return signals. For this reason, a synchronous radar system that istriggered using the RVP8 triggers will still perform optimally using the standard digitalCOHO locking techniques. In spite of this, however, some system designers may stillprefer that the amplitude envelope itself be locked to the COHO.SRVP8 Receives the Existing Radar TriggerWhen an external trigger is supplied to the RVP8, the processor synchronizes its internalrange bin selection circuitry to that external trigger. The placement of the range binsthemselves, however, is always synchronous with the IFD’s 35.975MHz acquisitionclock. The result is that 27.8ns of jitter is introduced in the placement of the RVP8’srange bins relative to the transmitted pulse itself.SThe effect of this synchronization jitter is that targets appear to be fluctuating in range byapproximately 4.2 meters. Although this is small relative to the range bin spacing itself,and thus does not affect the range accuracy of the data, the effect on overall systemstability is more severe. Using both numerical modeling and actual field measurements,we have found that sub-clutter visibility of a msec pulse may be limited to approximately43dB as a result of this 27.8ns range jitter. This falls quite short of the usual expectationsof a synchronous radar system in which clutter rejection of 55–60dB should beattainable.The solution to either of the above concerns is to provide some means for the IFD’s internalsampling clock to be phase locked to the radar system. If the RVP8 provides the radar triggers,then those triggers would become synchronous with the radar COHO; and if the RVP8 receivesan external trigger, then its range bin clock would be synchronous with that external trigger, andthus, there will be no synchronization jitter in the range bins.Beginning with Rev. C, the IFD offers the option of locking its sampling clock to an externalsystem clock reference. This results in an RVP8 that is fully synchronous with the existing radartiming. Rather than being derived from a fixed-frequency oscillator, the phase locked IFDsampling clock is driven by a custom Voltage-Controlled-Crystal-Oscillator (VCXO). Thisoscillator can have a center frequency in the 33.5 to 39.5MHz range, which is any rationalmultiple P/Q of twice the input reference frequency, where P and Q are integers between 1 and

Hardware InstallationRVP8 User’s ManualSeptember 20052–17128 (See also, Section 3.2.6). The tuning range of the VCXO is purposely kept very narrow (toimprove the clock stability), and is restricted to approximately +/–50ppm. Thus, the inputreference clock frequency (range 2–60MHz) must be precisely specified so as to stay withinthese limits. The reference clock input power level level should be between –10 and 0dBm.Use the following configuration to allow a Rev.C IFD to lock its sampling clock to an externalreference:SInstall U14SRemove U11, U12, U13SSet JP1 to its BC position to terminate the reference input in 50W, or leave the jumperopen to achieve a high-impedance input (approx. 5KW).SInstall custom Voltage-Controlled-Crystal-Oscillator (VCXO) at U5. Please contactSIGMET for assistance in specifying this device.For a Rev.D board the instructions are similar except that you do not need to remove anycomponents, and should place a jumper on JP3/BC (See Table 2–7).Note: As described in the previous section, for Rev.C boards U14 Must BeRemoved whenever the VCXO phase lock mode is not being used, i.e., when afree-running crystal is installed.2.2.13 Communications Between the IFD and RVP8/Rx For all revisions of the IFD hardware, the RVP8 software measures the round trip cable delayseach time it boots up and then uses that information to correct for range and timing offsets due tocable length.In the Rev.A through Rev.D IFD modules there are two cable links between the IFD and theRVP8/Rx PCI card. These cables can be any length up to 100 meters apiece.SCopper coax uplink from the RVP8/Rx board. This cable provides timing informationfor the burst pulse window, and 16-bit data for setting the AFC output level. The uplinkinput from the RVP8/Rx is an SMA connector from a 75W shielded cable (e.g., RG59cable). This cable is electrically isolated from the receiver’s ground (40KW isolation) sothat any noise or ground loops picked up by the cable will not be coupled into thereceiver circuitry. Details of the uplink protocol can be found in Section 2.5.1.SOptical fiber downlink to the RVP8/Rx board. The receiver and burst pulse data samplesare encoded into a 540MHz 8B/10B serial stream. The downlink operates at the infraredwavelength of 850nm, using a 62.5/125 micron multimode optical cable terminated intype ST connectors.In the Rev.E and higher IFD modules there is a single CAT-5E cable (quad twisted pair) withRJ-45 connectors that links the IFD to the RVP8/Rx PCI card. This cable carries GigaBit ratedata and should be of high quality construction. The cable length can be up to 75 feet, but aminimum length of six feet is also recommended. Electrical isolation at the IFD side is >2KV

Hardware InstallationRVP8 User’s ManualSeptember 20052–18for the data pairs and outer cable shield. In most radar applications it is highly recommendedthat shielded twisted pair cable be used rather than the more common unshielded variety. TheDC shield ground is established only at the RVP8/Rx side to avoid ground loops between theIFD and PCI chassis.Three of the four CAT-5E twisted pairs are used as dedicated downlink channels, and the fourthpair carries a dedicated uplink channel. Thus, each driver/receiver operates in a single directiononly, i.e., the data direction is fixed on each wire pair. The RJ-45 connector on both the IFD andRx cards is a Gigjack T12 (JK0-0016 from Pulse Engineering, www.pulseeng.com).SThe three downlink channels are identical and use RJ-45 line pairs MX1, MX2 and MX3.Each line is driven from the PECL outputs of a Cypress CY7B923 “Hotlink” transmittervia 33W series resistors. Each transmitter chip produces an independent 360MBaud datastream using 8B/10B encoding, yielding an aggregate line rate of 1080MBaud (payloadrate of 864MBaud). The spectral characteristics of each downlink twisted pair can bepredicted entirely from this baud rate and encoding technique. Maximum differentialdelay (propagation skew) among the three downlink pairs must be less than 25ns.SThe single uplink channel uses RJ-45 line pair MX4, and is driven by a PECL transmitterhaving 33W series output resistors. The uplink data rate is 72MBaud, and is presented ina manner having nearly the same spectral characteristics as Manchester encoding.The exact content of the four CAT-5E data streams is beyond the scope of this manual, but theabove descriptions should be sufficient to understand the bandwidth and electrical properties ofthe signals on each twisted pair. This information is applicable for cable selection, or toward thedesign of a repeater to carry the CAT-5E signals over different media.2.2.14 Summary of Crystal and Filter ConfigurationsThe RVP8/Rx, RVP8/Tx and IFD can operate in many different clocking and samplingconfigurations, depending on the requirements of the radar in which they are installed. Thefollowing summary describes how to setup the crystals and filters in your equipment.Step 1. Choose the Intermediate FrequencyCustom analog bandpass filters are installed in the RVP8/Tx and IFD to match to the radar’sIntermediate Frequency. The RVP8/Tx filters are soldered directly onto the PCI card and are notreally meant to be changed by the user. The IFD filters, however, attach via coax cables and arelocated on a serviceable mounting plate attached to the IFD.Simply verify that the center frequency of all of your bandpass filters match the IF of your radar.Our standard filter frequencies are: 16MHz, 30MHz, 57.5MHz, and 60MHz.Step 2. Choose Clock Locking OptionsThe RVP8 acquisition and trigger clocks can operate as free-running oscillators, or they can bephase locked to an external reference signal.SFor simple magnetron radars there is generally no system reference clock, and thefree-running clock mode is therefore appropriate. However, if a synthesized STALO is

Hardware InstallationRVP8 User’s ManualSeptember 20052–19being used as the RF source, then you may want to lock your RVP8 to the STALO’s ownreference clock (generally 10MHz). For dual-pol magnetron systems you must lock theRVP8 in this manner to measure differential phase.SFor klystron and other synchronous radars there will always be some kind of referenceclock in the system. In the simplest case of a single-pol radar in which the RVP8 firesthe transmitter directly, you may be able to get away with using free-running clocks.However, in virtually all cases it is best to lock the RVP8 to (one of) the radar’s existingtiming reference(s).The following table lists the different clock modes for the RVP8/Rx, RVP8/Tx, and IFD. Thefrequency of the required crystal oscillator is given, along with the type that is required. TheVF155 oscillators are general purpose units, VFAC170 is low-jitter free-running, and VF940 islow-jitter Voltage Controlled Crystal Oscillator (VCXO).Table 2–8: Clock Locking Component OptionsLock Mode RVP8/Rx RVP8/Tx IFDU16: 26.983 (VF155) U9 : 80.944 (VF940) 35.975 (VFAC170)Free-Running The IFD is free-running, and the Rx and Tx cards lock to it. Use this mode for simplemagnetron radars in which there is no system reference clock.U16: 26.983 (VF155) U9 : 81.000 (VF940) 36.000 (VF940)N-MHz ExternalReference A reference clock at some integer N-MHz is applied to both the IFD and Tx inputs, bothof which lock directly to it. This is the recommended hookup for klystron radars ormagnetron radars that use a synthesized STALO derived from, e.g., 10MHz.57 5491 MHzU16: 26.983 (VF155) U9 : 80.928 (VF940) 35.968 (VF940)57.5491-MHzWSR88D COHO For NEXRAD systems, the COHO is fed directly into both the IFD and Tx inputs. TheIFD sampling rate is 5/8 of the COHO frequency, and the Tx rate is 45/32.31 0703 MHzU16: 27.186 (VF155) N/A 36.248 (VF940)31.0703-MHzASR-9 COHO These special frequencies are used for the ASR-9 surveillance radars. The IFD locks to7/6 times the COHO frequency of the radar.

Hardware InstallationRVP8 User’s ManualSeptember 20052–202.3 RVP8 Chassis2.3.1 RVP8 Chassis OverviewThe RVP8 main chassis can assume a variety of forms depending on the customer requirements.Appendix C describes a standard SIGMET system. A typical unit supplied by SIGMETcontains at least the following:SA dual CPU on either motherboard or SBC in a passive PCI backplaneSRVP8/Rx CardSI/O-62 Card and Connector PanelThe system is also shipped with an integrated hard disk drive (HDD), 1.44 MB floppy (FDD)and CDRW unit. Note some installations may use a flash disk drive instead of an HDD. There isan LED display panel on the front of the chassis that is used to report system status.2.3.2 Power Requirements, Size and Physical MountingWARNING: The Main Chassis redundant power supplies are NOT auto-ranginglike the IFD. These are factory configured for the expected voltage, but shouldbe VERIFIED by the customer before power is applied to the system.There a three redundant power suppliesThe standard SIGMET chassis is a 19” EIA 4U rackmount unit, 17” (43 cm) deep. The chassis isusually mounted in a nearby equipment rack on rack slides (provided as standard). Theconnector panel is usually mounted on either the front or the rear of the same rack. The standardcable provided to connect the I/O-62 card in the main chassis to the connector panel is 6 feetlong (1.8 m) .The power requirements are 100–240 VAC 47–63 Hz. The IFD is autoranging, i.e., there are noswitches or jumpers that must be set. However, the main chassis is not. To check that the powersupply is properly configured for your line voltage, follow the procedure in Section C.1.3.

Hardware InstallationRVP8 User’s ManualSeptember 20052–212.3.3 Main Chassis Direct Connections The direct connections to the RVP8 chassis are made either to theback of the unit to PCI cards (e.g., left) or to the remote connectorpanel. The direct connections are summarized in the table below.Table 2–9: Direct Connections to RVP8 Main ChassisIFD I/O SummaryConnectorLabelStyle DescriptionRx Card ConnectionsUplink BNC COAX uplink to IFD (75ĆOhm shielded cable) For IFDFiber ST Fiberoptic downlink from IFD (orange cable) Rev.AĆDIFDĆLink RJĆ45 CATĆ5E (UTP) link between IFD and RVP8/Rx For IFDMiscĆI/O DB9F Four RSĆ422 I/O lines for future expansion Rev.ETRĆ1 / LOG BNC Trigger outputs (5 or 12V, 75ĆOhm) or preĆtrigger input (1.8V threshĆold 75 Ohm) Jumpers on the card select the functionTRĆ2 /PreTrigger InBNC old, 75ĆOhm) Jumpers on the card select the function.SBC or Motherboard ConnectionsNetwork RJĆ45 10/100/1000 BaseT TCP/IPKeyboard PS/2 Standard PC KeyboardMouse PS/2 Standard PC MouseMonitor VGA Standard PC Video MonitorI/OĆ62 Connections<no label> DBĆ62F SIGMETĆsupplied cable to IO62/CP remote panelOptional Tx CardIF Out 1 BNC Two independently synthesized IF output waveforms, up to +12dBminto 50 Ohm 8 75MHzIF Out 2 BNC into 50ĆOhm, 8Ć75MHz.CLK BNC Optional input or output reference clock (50ĆOhm)Misc DBĆ9F Four optional RSĆ422 clocks or control lines

Hardware InstallationRVP8 User’s ManualSeptember 20052–22Depending on the installation, the jumpers on the I-O 62, Rx and Tx Cards may requireconfiguration. These are described in Appendix C.2.3.4 External Pre-Trigger Input Users may supply the RVP8 with their own CMOS-Level pre-trigger for installations in whichadequate trigger control already exists. The trigger input is provided directly on the Rx Card(bottom BNC connector on the card panel labeled “TR-2 / In). See Appendix C for instructionson how to set the Rx card jumpers to enable a pre–trigger input.The trigger input uses CMOS levels (1.5V max low, 2.5V min high) for improved noiseimmunity. The trigger input may also be driven as high as +100V or as low as –100V withoutdamage. This makes it easier to connect to existing high-voltage trigger distribution systems.The rising or falling edge of this external “TRIGIN”signal is interpreted by the RVP8 as thepretrigger point; the actual pulsewidth of the signal does not matter. The delay to range zero isconfigured via the TTY Setups. The other trigger outputs are then synchronized to the inputtrigger. The synchronization jitter between the user pretrigger and the other trigger outputs isless than 0.014 microseconds.Trigger jitter can be improved in the case of coherent systems, by phase locking the IFD to thesame reference clock used to generate the external triggers (typically the COHO). This providesapproximately 10 dB of additional phase stability.The RVP8’s response to a missing external trigger is that the processor will insert fake (software)”triggers” at a rate of 250Hz whenever the trigger input is missing for more than 0.100 seconds.These fake triggers will keep the RVP8’s internal code and external outputs running in spite ofthe missing input (the data values will all be zero, and the ”no trigger” bit will be set in GPARMimmediate status word #1). Normal operation automatically resumes as soon as the externaltrigger is restored.2.3.5 Connector Panel I/O Connections Most of the connections between the radar and the RVP8 are made using the RVP8 ConnectorPanel which connects to the I/O-62 by 1.8m (6 foot) cable. The panel is usually mounted on thefront or the back of the same 19” EIA rack that contains the RVP8 chassis. The I/O-62 cablemay be plugged into either the front or the back of the connector panel to optimize the cable run.The Connector Panel uses a DC–DC converter to convert 12V unregulated input from the PCIcard into regulated +5V, +3.3V, and +/–12V to run the main electronics on the panel. The LEDson the panel are described below:

Hardware InstallationRVP8 User’s ManualSeptember 20052–23SEXT LED indicates that the 12V input power is presentSINT LED indicates that +3.3V is presentSGO LED indicates that the panel is properly communicating with the PCI card. It willblink slowly when communication is absent and very rapidly during the BRIEF timesthat the backpanel firmware are being updated with an rdaflash command. It will besolid when the panel is being used by the RCP8 software.The table in Section 1.9.5 provides a summary of the I/O for each connector. Detailed pin–outassignments are given in Appendix C. Descriptions of the various signals are provided below.J1 & J4- AZ/EL Input: TTL parallel anglesThirty two TTL-Level input lines. These are sampled by the RVP8, and the bits accompanyeach processed output ray (See PROC command, Section 6.7). The inputs can also be readdirectly via the GPARM command (See Section 6.9). The RVP8 supports an antennasynchronizing mode and inserts the AZ and EL start and stop angles into the ray header of eachradial (nominally 1 degree). Whenever antenna angle data are required, the processor reads theazimuth lines up to ten times in a row (spaced by 0.5 msec) until two successive values compareequal. This is done so that unsynchronized input data will be latched in a valid state. If after tenretries the lines were never observed in a consistent state, then the last observed state is used.Sampling for elevation is identical.The format can be BCD or binary angle. Detailed pin assignments are given in Appendix B.J2 & J5- AZ/EL Output: TTL parallel anglesThese provide output of the AZ and EL angles in TTL BCD or binary angle format. Detailed pinassignments are given in Appendix B. This feature could output the parallel angles to a separateantenna controller for example.J3- PHASE OUT: 8-bit RS422 phase shifter control output Can be used as differential RS422 or as single–ended TTL. This is used to control a phaseshifter for coherent systems that use phase modulation, but do not have a Tx card. This istypically used for legacy systems.J6- RELAY: Control for external equipmentOften, external equipment in the radar will require relay control (e.g., power on, radiate on,environmental systems, reset lines, slow polarization switch). This connector has connections for3 internal relays that are on the connector panel itself. The maximum current through the relaycontacts is 0.5 A continuous. The switching load is 0.25 A and 100V, with the additionalconstraint that the total power not exceed 4VA.

Hardware InstallationRVP8 User’s ManualSeptember 20052–24If larger current and voltage loads are required, then the connector panel relays can be used toswitch external relays provided by the customer. Another alternative is to use the additional 4,12V relay signals (up to 200mA) that are also supported on this connector.Hazard: External relays must be equipped with proper diode protection againstback-EMF or damage to the I/O-62 and or the connector panel might result.J7 SPARE: Configurable 20 lines of TTL I/O This connector supports 20 lines of TTL each of which can be configured as either input oroutput via the softplane.conf file.J8 SPARE: Analog Inputs10 differential analog inputs, up to ±20V max multiplexed into a single A/D convertor samplingeach at >1000 Hz. This can be used for monitoring environmental systems at the radar site.J9- MISC: RS422 I/O, D/A and A/D 7 additional RS422 lines, each configurable to be either input or output, and 2 each dedicated(non–multiplexed) A/D inputs (±580V with pot adjust) and D/A outputs (±10V). The RS422lines are convenient for high-speed polarization switch control.J10-11: RS232C I/OThese two connectors can be used for serial angle input. The most common format is the RCV01format, although custom formats from antenna/pedestal manufacturers such as Orbit, Andrewand Scientific Atlanta are also supported.J12: S-D- AZ and EL synchro input For systems that have synchros, the RVP8 can accept a direct synchro input from both AZ andEL. The nominal voltage and frequency are 100V @ 60 Hz. S/D conversion is performed in theI/O-62.J13-14: TP1 & TP2: Programmable test point scope outputs Am exciting feature of the RVP8 is the programmable test points. These are usually used toconnect to an oscilloscope. The user can then specify what is output to the test points in the formof an analog voltage for display on the scope. Some examples are:S“LOG” receiver power output (an old–time radar A–Scope)SBurst pulseSAnalog input monitorThe advantage of using the test points is that technicians can leave them permanently connectedto a rackmount oscilloscope and then select what is displayed. This saves time and reducescabling errors when test switching cables.

Hardware InstallationRVP8 User’s ManualSeptember 20052–25J15-18: TRIG1-4- Output triggersThe waveforms appearing on the four trigger outputs are programmed by the user to meet theradar’s exact timing needs. These correspond to the trigger generators TGEN1, TGEN2,TGEN3 and TGEN4. More triggers can be configured on the “SPARE” connectors if they arerequired. All lines may be setup and used independently and can contain, for example,pre-trigger pulses, calibration gates, range strobes, scope triggers, etc. The triggers are driven at+12V into 75W and can be independently-timed at rates between 50Hz and 20000Hz with betterthan 0.02% accuracy. For dual-PRF velocity unfolding applications, the RVP8 trigger generatormust be used as opposed to an externally supplied pre-trigger (see next section).The timing of the triggers is phase-locked to the sample clock in the IFD, which can be phaselocked to the COHO of a coherent system. For coherent systems that do not sample the actualtransmit pulse (for phase correction), this is recommended.The trigger waveforms are configurable in software using the “mt” commands. This sets thetrigger timing, trigger sense (active high or active low pulse) and the minimum and maximumPRF for each pulse width. See sections 3.2.4.It is sometimes useful to dedicate one of the TRIG outputs to trigger anoscilloscope.See Section XXX for a description of how to configure an input pre–trigger from an externalsource such as an existing radar trigger system.Selectable input pre-triggerUsers may supply the RVP8 with their own CMOS-Level pre-trigger for installations in whichadequate trigger control already exists. The trigger input is provided directly on the Rx Card(bottom BNC connector on the card panel). The trigger input uses CMOS levels (1.5V max low,2.5V min high) for improved noise immunity. The trigger input may also be driven as high as+100V or as low as –100V without damage. This makes it easier to connect to existinghigh-voltage trigger distribution systems. The rising or falling edge of this external“TRIGIN”signal is interpreted by the RVP8 as the pretrigger point; the actual pulsewidth of thesignal does not matter. The delay to range zero is configured via the TTY Setups. The othertrigger outputs are then synchronized to the input trigger. The synchronization jitter between theuser pretrigger and the other trigger outputs is less than 0.014 microseconds.Trigger jitter can be improved in the case of coherent systems, by phase locking the IFD to thesame reference clock used to generate the external triggers (typically the COHO). This providesapproximately 10 dB of additional phase stability.The RVP8’s response to a missing external trigger is that the processor will insert fake (software)”triggers” at a rate of 250Hz whenever the trigger input is missing for more than 0.100 seconds.These fake triggers will keep the RVP8’s internal code and external outputs running in spite ofthe missing input (the data values will all be zero, and the ”no trigger” bit will be set in GPARMimmediate status word #1). Normal operation automatically resumes as soon as the externaltrigger is restored.

Hardware InstallationRVP8 User’s ManualSeptember 20052–262.3.6 Power-Up DetailsWARNING: The Main Chassis redundant power supplies are NOT auto-ranginglike the IFD. These are factory configured for the expected voltage, but shouldbe VERIFIED by the customer before power is applied to the system.When the RVP8 is powered–up or reset, the host Linux PC goes through an automated bootprocess that ultimately starts the RVP8 application. The RVP8 then runs extensive internaldiagnostics. In most cases, there is no display connected to the RVP8 to monitor the bootsequence. For troubleshooting it is useful to connect a display to view any error messages.The RDA front panel display shows the status of the Linux boot sequence and summary status ofthe diagnostic self-tests. During the Linux boot stage, the front panel shows the following whichindicates how much time has elapsed since the start of the boot process. –––––––––––––––––––––––––––––––| SIGMET Inc. Open RDA || Boot < 00:24 > | –––––––––––––––––––––––––––––––After the Linux boot process is complete, the RVP8 runs its internal self-tests during which thefront panel display appears as follows. –––––––––––––––––––––––––––––––| RVP8 V4.3 Starting || Running Diagnostics | –––––––––––––––––––––––––––––––After successful completion of the self-tests, the display will show the following, –––––––––––––––––––––––––––––––| RVP8 V4.3 Starting || Diagnostics Pass | –––––––––––––––––––––––––––––––and then switch to the standard operational display which shows the current azimuth andelevation, the major mode, the number of range bins, the PRF and XXX: –––––––––––––––––––––––––––––––| 179.23 AZ/EL 14.96 || FFT 1646 1800 Hz x1 | –––––––––––––––––––––––––––––––In the event that the diagnostics do not pass, then the display will indicate the number of teststhat “Fail”. Note that the “dspx –nochat” utility “gparm” command or the “v” command in theTTY setups can be used to learn the details of the failures.

$Hardware InstallationRVP8 User’s ManualSeptember 20052–272.3.7 Socket Interface The RVP8 as shipped is configured to listen on a network port. It is ready to interface to a hostcomputer via the network using a program called DspExport. It is also ready to run somecommands on the RVP8 itself. The RVP8 comes with some built–in SIGMET supplied utilitiessuch as setup, dspx and ascope. These utilities are described in the IRIS Utilities Manual.Because the RVP8 can only have one program controlling it at a time, use of a local programlike dspx will block network access, and vice versa.How DspExport WorksDspExport is a daemon program which is normally configured to run all the time. When itreceives a socket connection request it will establish a connection to the RVP8. At this point,multiple connections are allowed. It will only handle the “INFO”, “SETU” and “OPEN”commands. Once the “OPEN” command is sent, an exclusive connection for I/O to the RVP8 isestablished. If a second OPEN request comes in while the first is still active, it will fail, andreturn the message “Device allocated to another user”. To see if it is running on your RVP8, trytyping$ ps –aef | grep DspExportDuring development, it can always be started up manually by typing “DspExport” at a shellprompt. It can be started with the “–v” option for more detailed logging. It defaults to usingport 30740. If you wish to use another port, start it with an option such as “–port:12345”. Thecommand line option “–help” lists these options.Source ExamplesThe source code for DspExport and for the dsp library is supplied on the RVP8 release cdrom.This can be optionally installed as part of the upgrade procedure as discussed in SoftwareInstallation manual. You will find DspExport in ${IRIS_ROOT}utils/dsp, and you will findthe dsp library in ${IRIS_ROOT}libs/dsp. In the library, you will find example code whichtalks to DspExport in file OpenSocket.c, dsp_read.c and dsp_write.c. Search for the string“SOCKET”, and you can see how the code differs between SCSI interface and socket interface.Socket protocolThe socket interface basically supports all the “Host Computer Commands” in chapter 6. Thereare a few layers of formatting on top of that. All messages going both ways consist at the lowestlevel of an 8-character decimal ASCII number, followed by a block of data. The decimalnumber indicates how many bytes follow. Generally, all data transfers are initiated by the hostcomputer by sending a block of data which consists of a command word followed by the “|”character, followed by optional data.It will respond to all commands with either an “Ack|” indicating acknowledgment that thecommand was OK, or “Nak|” indicating that there was an error. For Nak, the reply will alwaysinclude a string indicating what the error was. For Ack there is optional data following.On initial socket connection request DspExport will provide a response of either Nak indicatingthe connection failed, and why, or Ack followed by some connection information. This Ackstring is in the form of name/value pairs, and will look something like:$