Dialog Semiconductor SC14S DECT Module User Manual SC14SPNODE SF 1V6

Dialog Semiconductor BV DECT Module SC14SPNODE SF 1V6

user manual SPNODE

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Document ID2324865
Application IDQ9a+vM9vZzOP8gqflsnyIQ==
Document Descriptionuser manual SPNODE
Short Term ConfidentialNo
Permanent ConfidentialNo
SupercedeNo
Document TypeUser Manual
Display FormatAdobe Acrobat PDF - pdf
Filesize58.5kB (731280 bits)
Date Submitted2014-07-14 00:00:00
Date Available2013-10-22 00:00:00
Creation Date1997-02-03 11:26:52
Producing SoftwareAcrobat Elements 9.0.0 (Windows)
Document Lastmod2014-07-01 13:26:45
Document TitleSC14SPNODE_SF_1V6.fm
Document CreatorFrameMaker 9.0
Document Author: ssato

DATASHEET
SC14SPNODE SF
DECT Module with integrated Antenna and FLASH
General description
The SC14SPNODE SF is a member of the Cordless
Module family with an integrated radio transceiver and
baseband processor in a single package. It is designed
for voice and data applications in the DECT frequency
band.
RF range: 1870 MHz to 1930 MHz
Receiver sensitivity < -93 dBm
Transmit power
• EU: 24 dBm: 1881MHz - 1897MHz
SC14SPNODE SF
JUL 1, 2014 V1.6
• USA: 20 dBm: 1921MH - 1928MHz
• JP: 23 dBm: 1895MHz - 1903MHz
Features
Power supply voltage: 2.1 V to 3.45 V
Supports NiMH and Li-Ion batteries
Small form factor (19.6 mm x 18.0 mm x 2.7 mm)
Program memory available for custom software.
16 Mbit Flash embedded
Operating temperature range: -40 °C to +85 °C
Ultra Low Power, sleep current < 3 A
n ETSI (EU-DECT) and FCC (DECT 6.0) certified
n J-DECT pre-certified
________________________________________________________________________________________________
SC14
SPNODE
Actuator
SC14
CVMDECT
© 2012 Dialog Semiconductor B.V.
VoIP
PSTN
Interface
PSTN
LCD
SC14
CVMDECT
PCM
Interface
SC14
SPNODE
www.dialog-semiconductor.com
DECT Module with integrated Antenna and FLASH
Sensor
System diagram
1.0 Connection diagram. . . . . . . . . . . . . . . . . . . . . . . . 3
5.5 SAFETY REQUIREMENTS . . . . . . . . . . . . . . 26
1.1 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . 4
6.0 Package information . . . . . . . . . . . . . . . . . . . . . . 27
2.0 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6.1 SOLDERING PROFILE . . . . . . . . . . . . . . . . . . 27
2.1 SCOPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6.2 MOISTURE SENSITIVITY LEVEL (MSL) . . . . 27
2.2 REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . 9
6.3 COPPER PAD, SOLDER OPENING AND STEN-
2.3 GLOSSARY AND DEFINITIONS . . . . . . . . . . . 9
CIL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.4 BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . 10
6.4 MECHANICAL DIMENSIONS . . . . . . . . . . . . . 30
2.5 POWER SUPPLY . . . . . . . . . . . . . . . . . . . . . . 10
7.0 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . 31
SC14SPNODE SF
Table of Contents
2.6 ANTENNA OPERATION . . . . . . . . . . . . . . . . . 10
2.6.1 Internal antenna only . . . . . . . . . . . . . . . 10
2.6.2 Internal and external antenna with FAD 11
2.7 BATTERY MANAGEMENT . . . . . . . . . . . . . . . 11
2.8 EMBEDDED QSPI FLASH . . . . . . . . . . . . . . . 11
3.0 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 GENERAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . 12
3.3 OPERATING CONDITIONS . . . . . . . . . . . . . . 13
3.4 DIGITAL INPUT/OUTPUT PINS . . . . . . . . . . . 13
3.5 ULTRA LOW ENERGY (ULE) I/O PIN . . . . . . 14
3.6 SUPPLY CURRENTS . . . . . . . . . . . . . . . . . . . 14
DECT Module with integrated Antenna and FLASH
3.7 ANALOG FRONT END . . . . . . . . . . . . . . . . . . 15
3.8 BATTERY MANAGEMENT . . . . . . . . . . . . . . . 19
3.9 BASEBAND PART . . . . . . . . . . . . . . . . . . . . . 19
3.10 RADIO (RF) PART . . . . . . . . . . . . . . . . . . . . 20
3.11 RF POWER SUPPLY . . . . . . . . . . . . . . . . . . 21
3.12 RF CHANNEL FREQUENCIES . . . . . . . . . . 22
4.0 Design guidelines. . . . . . . . . . . . . . . . . . . . . . . . . 23
4.1 PCB DESIGN GUIDELINES . . . . . . . . . . . . . . 23
4.2 MODULE PLACEMENT ON THE MAIN BOARD
24
4.3 PATTERN FOR PIN 79 ON THE MAIN BOARD.
24
4.4 PRECAUTIONS REGARDING UNINTENDED
COUPLING . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.0 Notices to OEM. . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1 FCC REQUIREMENTS REGARDING THE END
PRODUCT AND THE END USER . . . . . . . . . 25
5.2 IC REQUIREMENTS REGARDING THE END
PRODUCT AND THE END USER . . . . . . . . . 25
5.3 PRECAUTIONS REGARDING UNINTENDED
COUPLING . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.4 END APPLICATION APPROVAL . . . . . . . . . . 26
© 2012 Dialog Semiconductor B.V.
Jul 1, 2014 v1.6
SC14SPNODE SF
Connection diagram
79
GND
P0
RFP0
P0n
RFP0n
TP1
78
GND
77
GND
76
GND
75
RF0
74
GND
GND
73
RF1
VREFp
72
GND
MICp/CIDINn
71
GND
MICn/CIDOUT
70
GND
MICh/LINEIN
10
69
PARADET/P3[4]
VREFm
11
68
RINGOUT/RINGING/P3[5]
LSRp/LINEOUT/AGND
12
67
RINGn/P3[6]
LSRn/LINEOUT/AGND
13
66
RINGp/P3[7]
GND
14
65
CIDINp/P3[2]
ADC0/P3[3]
15
64
VBATIN
ADC1/INT0/P1[0]
16
63
VBATIN
SOCp
17
62
VBATSW
SOCn
18
61
VDDOUT
DC_SENSE
19
60
GND
81
82
80
GND
P2[0]/ECZ1/PWM0/LED3
58
P2[1]/ECZ2/PWM1/LED4
CHARGE_CTRL
22
57
CLK100/P2[2]/PCM_CLK
CHARGE/P1[7]
23
56
DP2/P2[3]/SDA1/PCM_DI
DP1/PAOUTp/P3[1]
24
55
DP3/P2[4]/SCL1/PCM_DO
VDDPA
25
54
SF/P2[5]/PCM_FSC
CP_VOUT1
26
53
JTAG
DP0/PAOUTn/P3[0]
27
52
RSTn
88
46
47
48
49
50
51
P0[1]/PWM0/URX
P0[0]/UTX
GND
GND
GND
86
45
P0[2]/SDA2/UTX2
39
44
38
WTF_IN/P2[6]
GND
37
GND
43
36
LE/INT1/P1[1]
P0[3]/SCL2/URX2
35
SK/INT2/P1[2]
42
34
SIO/INT3/P1[3]
P0[4]/SPI_EN
33
TDOD/INT4/P1[4]
41
32
VDDE/RDI/INT5/P1[5]
P0[5]/SPI_CLK
31
BXTAL/INT7/P2[7]
40
30
ULP_PORT
P0[6]/SPI_DO
29
ULP_XTAL
28
GND
PON/P1[6]
84
83
87
59
21
85
20
Figure 1 Connection diagram (top view, leads face down)
Order numbers:
SC14SPNODE SF01T (tray, MPQ = 600 pcs)
© 2012 Dialog Semiconductor B.V.
Jul 1, 2014 v1.6
DECT Module with integrated Antenna and FLASH
DC_I
DC_CTRL
P0[7]/PWM1SPI_DI
1.0
SC14SPNODE SF
1.1 PIN DESCRIPTION
Table 1: Pin description
Pin
Module
Pin name
(Note 1)
GND
P0
Hi-Z
RFP0
Hi-Z
Control port for FAD. See 2.6
P0n
Hi-Z
Control port for FAD. See 2.6
RFP0n
Hi-Z
Control port for FAD. See 2.6
GND
Ground
VREFp
Positive microphone supply voltage
CIDINn
INPUT. Caller-id opamp negative input with switchable input protection enabled from start-up.
INPUT. Positive microphone input.
IO
OUTPUT. Caller-id opamp output to ADC.
INPUT. Negative microphone input.
In/
Out
Iout
Reset
Drive
State Description
(mA) (Note 2)
MICp
Ground
Control port for FAD. See 2.6
CIDOUT/
MICn
10
MICh/
LINEIN
INPUT. Headset microphone input with fixed input protection
INPUT. Line interface input with fixed input protection
11
VREFm
Negative microphone reference. This pin must also be connected to
GND ground, but make sure that the microphone ground is directly
routed to VREFm (VREFm is the star point).
12
LSRp/
LINEOUT/
AGND
OUTPUT. Positive loudspeaker output
OUTPUT. To Line interface.
OUTPUT. Buffered analog ground (0.9 V) if LSRP_MODE = 00.
13
LSRn/
LINEOUT/
AGND
OUTPUT. Negative loudspeaker output.
OUTPUT. To Line interface.
OUTPUT. Buffered analog ground (0.9 V) if LSRN_MODE = 00.
14
GND
Ground
15
P3[3]/
ADC0
IO
INPUT/OUTPUT with selectable pull up/down resistor.
INPUT. ADC0 input to ADC with programmable input protection
enabled from reset. (Note 4)
16
P1[0]/
INT0/
ADC1
IO
I-PU
INPUT/OUTPUT with selectable pull up/down resistor.
INPUT. Keyboard input interrupt.
INPUT. ADC1 input to ADC with programmable input protection
enabled from reset. (Note 4)
17
SOCp
Battery State Of Charge positive input.
Connect to GND if not used.
18
SOCn
Battery State Of Charge negative input. Star point connected to the
SOC resistor. Connect to GND if not used.
19
DC_SENCE
INPUT. Voltage sense input. Connected via a resistor divider to the
output of the DC/C converter. Maximum 1.27 V
Connect to GND if not used.
20
DC_I
Current sense input of DC/DC converter. Connect to GND if not
used
21
DC_CTRL
© 2012 Dialog Semiconductor B.V.
O-PD OUTPUT. Switching clock for the DC/DC converter, this pad is sup(fixed plied with VBAT.
100k Leave unconnected if not used.
pulldown)
Jul 1, 2014 v1.6
DECT Module with integrated Antenna and FLASH
Pin
Module
Pin name
(Note 1)
22
CHARGE_CTRL
O-0
ANALOG OUTPUT. Charge control pin. Supplied by internal VBAT
if device is off else from AVD.
Leave unconnected if not used.
23
CHARGE / P1[7]
I-PD
(270k
fixed
pulldown)
INPUT. Charger connected indication and supply voltage for power
management. Switches on the device if voltage > Vih_a3pad. Must
be connected to charger via resistor R>(Vcharger_max-3 V)/10 mA
(round to next largest value in range). An internal 10 ms hold circuit
keeps device on if the charger voltage ripple momentarily drop
below Vil_charge. This eliminates the use of expensive ripple filter.
If used as port pin, the maximum input switching speed of this pin is
100 kHz. Leave unconnected if not used.
24
PAOUTp
P3[1]
DP1
IO
500
25
VDDPA
CLASSD Audio Amplifier supply voltage up to 3.45 V.
GND or leave unconnected if PAOUT/P3[1:0] ports are not used.
26
CP_VOUT1
Charge Pump Output 1.
A capacitor of 1 F to GND is internally connected to this pin.
27
PAOUTn
P3[0]
DP0
IO
500
28
GND
29
PON/
P1[6]
30
ULP_XTAL
32.768 kHz XTAL clock input. Connect to GND if not used. (Note 7)
31
ULP_PORT
Ultra Low Power Port Pin. Connect to GND if not used. (Note 7)
32
P2[7]/
INT7
BXTAL
IO
I-PU
INPUT/OUTPUT with selectable pull up/down resistor.
INPUT. Keyboard Interrupt.connected to P1[2] or P2[7].
OUTPUT. Digital buffered Xtal oscillator. This pin is not optimized
as reference clock for external RF devices.
33
P1[5]/
INT5/
RDI/
VDDE
IO
O-1
INPUT/OUTPUT with selectable pull up/down resistor.
INPUT. Keyboard input interrupt.
INPUT. BMC Receive data (for monitoring/external radio).
OUTPUT. P1[5] Used for supply of external EEPROM
34
P1[4]/
IO
1/2
I-PD
INPUT/OUTPUT with selectable pull up/down resistor.
1 mA or 2 mA mode used to bias external NPN transistor without
external resistor.
INPUT. Keyboard input interrupt.
OUTPUT. BMC transmit digital data.
IO
1/2
I-PD
INPUT/OUTPUT with selectable pull up/down resistor.
1 mA or 2 mA mode used to bias external NPN transistor without
external resistor.
INPUT. Keyboard input interrupt.
INPUT/OUTPUT. MicroWire data (for monitoring/external radio).
IO
I-PD
INPUT/OUTPUT with selectable pull up/down resistor.
INPUT. Keyboard input interrupt.
OUTPUT. MicroWire clock (for monitoring/external radio).
In/
Out
Iout
Reset
Drive
State Description
(mA) (Note 2)
O-0 (5k OUTPUT. CLASSD positive output to loudspeaker.
fixed OUTPUT. General purpose output.
pull- OUTPUT. DIP port DP1
down)
O-0 (5k OUTPUT. CLASSD negative output to loudspeaker.
fixed OUTPUT. General purpose output.
pull- OUTPUT. DIP port DP0
down)
INT3/
SIO
36
P1[2]/
INT2/
SK
© 2012 Dialog Semiconductor B.V.
Jul 1, 2014 v1.6
DECT Module with integrated Antenna and FLASH
P1[3]/
Ground
I (270k INPUT. Power on, Switches on the device if Voltage > Vih_a3pad.
fixed May be directly connected to VBAT. If used as port pin, the maxipull- mum input switching speed of this pin is 100 kHz.
down)
INT4/
TDOD
35
SC14SPNODE SF
Table 1: Pin description (Continued)
Pin
Module
Pin name
(Note 1)
In/
Out
Iout
Reset
Drive
State Description
(mA) (Note 2)
37
P1[1]/
INT1/
LE
38
GND
39
P2[6]/
WTF_IN
IO
I-PU
INPUT/OUTPUT with selectable pull up/down resistor.
OUTPUT. Gen2DSP enable signal used to monitor DSP load
40
P0[7]/
SPI_DI/
PWM1
IO
I-PU
INPUT/OUTPUT with selectable pull up/down resistor.
INPUT. SPI data input.
OUTPUT. Timer 0 PWM 1 output.
41
P0[6]/
SPI_DO
IO
I-PU
INPUT/OUTPUT with selectable pull up/down resistor.
OUTPUT. SPI data output.
42
P0[5]/
SPI_CLK
IO
I-PU
INPUT/OUTPUT with selectable pull up/down resistor.
INPUT/OUTPUT. SPI clock.
43
P0[4]/
SPI_EN
IO
I-PU
INPUT/OUTPUT with selectable pull up/down resistor.
INPUT/OUTPUT. SPI clock enable. Active low.
44
P0[3]/
SCL2/
IO
I-PU
INPUT/OUTPUT with selectable pull up/down resistor.
INPUT/OUTPUT. ACCESS bus 2 clock with programmable Pushpull or open drain. In open drain mode, SCL2 is monitored to support bit stretching by a slave.
INPUT. UART2 receive data
IO
I-PU
INPUT/OUTPUT with selectable pull up/down resistor.
INPUT/OUTPUT. ACCESS bus 2 data with programmable.
Push-pull or open drain.
OUTPUT. UART2 transmit data
IO
I-PU
URX2
45
GND
46
P0[2]/
SDA2/
Ground
Ground
47
P0[1]/
URX/
PWM0
IO
I-PD
(10k)
INPUT/OUTPUT with selectable pull up/down resistor.
INPUT. UART receive data.
OUTPUT. Timer 0 PWM0
48
P0[0]/
UTX
I-PU
INPUT/OUTPUT with selectable pull up/down resistor.
OUTPUT. UART transmit data.
49
GND
Ground
50
GND
Ground
51
GND
Ground
52
RSTn
53
JTAG
IO
I-PU
JTAG-SDI+; one wire Debug interface with open-drain.
Requires external 1 k Pull-up to VDD.
54
P2[5]/
PCM_FSC/
SF
IO
I-PU
INPUT/OUTPUT with selectable pull up/down resistor.
INPUT/OUTPUT. PCM Frame Sync.
OUTPUT. S-field Sync found signal indicating the 00 or 11 preamble to unique word transition with 96 ns resolution. Used for debugging purposes.
55
P2[4]/
SCL1/
IO
I-PU
INPUT/OUTPUT with selectable pull up/down resistor.
INPUT / OUTPUT. ACCESS bus 1 clock with programmable Pushpull or open drain. In open drain mode, SCL1 is monitored to support bit stretching by a slave.
OUTPUT. PCM data output.
OUTPUT. DIP port DP3.
PCM_DO/
DP3
© 2012 Dialog Semiconductor B.V.
I-PU Active low Reset input with Schmitt-trigger input, open-drain output
(200k and pull up resistor to internal VDD. Input may not exceed 2.0 V. An
pull-up) internal capacitor of 47 nF is mounted on this pin.
Jul 1, 2014 v1.6
DECT Module with integrated Antenna and FLASH
UTX2
INPUT/OUTPUT with selectable pull up/down resistor.
INPUT. Keyboard input interrupt.
INPUT. MicroWire latch enable. (for monitoring/external radio).
SC14SPNODE SF
Table 1: Pin description (Continued)
Pin
56
Module
Pin name
(Note 1)
P2[3]/
SDA1/
In/
Out
Iout
Reset
Drive
State Description
(mA) (Note 2)
IO
I-PU
INPUT/OUTPUT with selectable pull up/down resistor.
INPUT / OUTPUT. ACCESS bus 1 data with programmable Pushpull or open drain.
INPUT. PCM data input.
OUTPUT. DIP port DP2.
PCM_DI/
DP2
57
P2[2]/
PCM_CLK/
CLK100
I/O
I-PD
INPUT/OUTPUT with selectable pull up/down resistor.
INPUT/OUTPUT. PCM clock.
OUTPUT. DIP 100 Hz output.
58
P2[1]/
ECZ2/
PWM1/
LED4
IO
INPUT/OUTPUT with selectable pull up/down resistor.
OUTPUT. Gen2DSP output port.
OUTPUT. Timer 0 PWM 1 output.
LED4: 2.5 mA/5 mA LED current sink.
59
P2[0]/
ECZ1/
PWM0/
LED3
IO
INPUT/OUTPUT with selectable pull up/down resistor.
OUTPUT. Gen2DSP output port.
OUTPUT. Timer 0 PWM 0 output.
LED3: 2.5 mA/5 mA LED current sink.
60
GND
Ground
61
VDDOUT
Test purpose only. Must be left unconnected. See 2.5
62
VBATSW
63
VBATIN
Main supply voltage < 3.45 V. See 2.5
64
VBATIN
Main supply voltage < 3.45 V. See 2.5
65
P3[2]/
CIDINp/
IO
INPUT/OUTPUT with selectable pull up/down resistor.
INPUT. Caller-id opamp positive input with switchable input protection enabled from start-up.
66
P3[7]/
RINGp
IO
INPUT/OUTPUT with selectable pull up/down resistor.
ANALOG INPUT. Positive ringing signal opamp input with switchable input protection.
67
P3[6] /
RINGn
IO
INPUT/OUTPUT with selectable pull up/down resistor.
ANALOG INPUT. Negative ringing signal opamp input with switchable input protection.
68
P3[5]/
RINGOUT/
RINGING
IO
INPUT/OUTPUT with selectable pull up/down resistor.
OUTPUT. Ringing opamp output to ADC.
INPUT. Ringer signal detection input to capture timers and ADC.
69
P3[4]/
PARADET
IO
INPUT/OUTPUT with selectable pull up/down resistor.
ANALOG INPUT. Parallel set detection input to ADC with switchable input protection.
70
GND
Ground
71
GND
Ground
72
GND
Ground
73
RF1
RF signal for external antenna. See 2.6
74
GND
Ground
75
RF0
RF signal for external antenna. See 2.6
76
GND
Ground
77
GND
Ground
78
GND
Ground
79
TP1
Tuning point for internal antenna. Follow instructions of section 4.3.
80
GND
Ground
Test purpose only. Must be left unconnected. See 2.5
Jul 1, 2014 v1.6
DECT Module with integrated Antenna and FLASH
© 2012 Dialog Semiconductor B.V.
SC14SPNODE SF
Table 1: Pin description (Continued)
Pin
Module
Pin name
(Note 1)
81-88 TP2 to TP9
In/
Out
Iout
Reset
Drive
State Description
(mA) (Note 2)
NC
Must be left unconnected. See section 4.1 and Figure 15.
Note 1:
“NC” means: leave unconnected.
Note 2:
All digital inputs have Schmitt trigger inputs. After reset all I/Os are set to input and all pull-up or pull-down resistors are enabled unless oth-
“GND” means internally connected to the module ground plane. Every GND pin should be connected to the main PCB.ground plane.
SC14SPNODE SF
Table 1: Pin description (Continued)
erwise specified.
PU = Pull-up resistor enabled, PD = Pull-down resistor enabled, I = input,
O = output, Hi-Z = high impedance, 1 = logic HIGH level, 0 = logic LOW level
Refer also to Px_DIR_REGs for INPUT/OUTPUT and Pull-up/Pull-down configurations
Note 3:
Back drive protected pins allow always interfacing with devices up to a supply voltage of 3.45 V.
If PAD_CTRL_REG[xxx_OD] bit is set then
1) the internal Pull-up resistors are always disabled to prevent currents from 1.8 V < Vin < 3.45 V to VDD.
2) If port is set to output, the output is always configured as open drain to allow the output level to reach Vin >1.8 V. The external pull-up
resistor value determines the rise time of the signal.
Note 4:
For base station applications with high line input voltages, an input protection on all ADC inputs can be enabled with
AD_CTRL_REG[ADCx_PR_DIS] =’0’. To limit the input current as specified in chapter “specifications”, an external resistor must placed in
series with the ADC inputs. With the input protection enabled, the ADC is linear from 0 to 0.9 V. With ADCx_PR_DIS=’1’ the ADC0 and
ADC1 are linear from 0 V to 1.8 V.
Note 5:
In digital mode extra static VDDPA current will flow (See Supply currents (indicative value) (table 9, page 14)). So the digital mode is not
recommended in portable applications.The reason for this output overvoltage protection is that a speaker is an inductor (which can store
energy). In case the battery is removed from the handset while handsfree speaker is active, the battery voltage could become too high
when the inductor releases its energy to the battery (which is not present anymore as a buffer). To prevent this electrical overstress situation, the overvoltage protection is added.
Note 6:
Note 7:
This pin description describes all function that is supported by hardware. Supported pin function depends on installed software.
All ULP pins use snap-back devices as ESD protection, which (when triggered) have a holding voltage below the typical battery voltage.
This means that the snap-back device of a ULP pin may remain conductive, when triggered while the pin is directly connected to the battery
© 2012 Dialog Semiconductor B.V.
Jul 1, 2014 v1.6
DECT Module with integrated Antenna and FLASH
voltage. If any of the ULP pins are directly or indirectly electrically accessible on the outside of the application, system level ESD precautions must be taken to ensure that the snap-back device is not triggered while in active mode, to prevent the chip from being damaged.
Introduction
EMC
Equipment Manufacturer’s Code
ESD
ElectroStatic Discharge
FAD
Fast Antenna Diversity
FP
Fixed Part
GAP
General Access Profile (DECT)
IPEI
International Portable Equipment Identity
(ETSI EN 300 175-6)
IWU
Inter Working Unit (ETSI EN 300 175-1)
MCU
Micro Controller Unit
MMI
Man Machine Interface (keypad, LCD,
buzzer, microphone, earpiece, speaker,
headset)
NSMD
Non Solder Mask Defined (pad)
NTP
Normal Transmitted Power
• ETSI certified
OTP
One Time Programmable
• ETSI 300 444 (DECT GAP) compliant
PCB
Printed Circuit Board without
components
PP
Portable Part
PSTN
Public Switched Telephone Network
2.1 SCOPE
The SC14SPNODE SF is a programmable DECT module for voice and data services, Ultra Low Energy
(ULE) sensor applications and actuator applications.
This module includes a fully integrated DECT RF and
baseband processor, 16 Mbit QSPI FLASH, one internal antenna, two antenna switches and a 20.736 MHz
crystal. Customer end products can be designed by
adding just a few components to this module.
Customer and Dialog software are stored in the internal 16 Mbit QSPI FLASH.
Dialog standard software for the SC14SPNODE supports:
• EU-DECT (CAT-iq V2.0, V3.0), DECT6.0 for
North American and Japan DECT.
• FCC approved, Japan DECT pre-certified
The end product must undergo certification testing
again if other software than Dialog standard software
stack is used.
Radio Frequency
RFPI
Radio Fixed Part Identity (ETSI EN 300
175-6)
• Wireless sensor application with ULE
RLR
Receive Loudness Rating
• Wireless actuator application with ULE
RSSI
Radio Signal Strength Indication (ETSI
EN 300 175-1)
Sidetone
Feedback of microphone signal to
earpiece
SLR
Sending Loudness Rating
SPI
Serial Peripheral Interface Bus
TDD
Time Division Duplex
UART
Universal Asynchronous Receiver and
Transmitter
ULE
Ultra Low Energy
VES
Virtual EEPROM Storage
• Cordless Voice module application
2.2 REFERENCES
1. AN-D-207, External Antenna design guidelines
for the SC14 Module, Dialog Semiconductor,
Application note
2. AN-D-174, SC14480 Battery Management;
using the State of Charge function, Dialog Semiconductor, Application Note
3. MX25U1635E, Macronix, Data sheet
4. Dialog Semiconductor web page to get software
release information: http://www.dialog-semiconductor.com/products/short-range-wireless-technology/software-stacks
5. AN-D-204, RF settings in Natalie, Dialog Semiconductor, Application note
2.3 GLOSSARY AND DEFINITIONS
AFE
Analog Front End
CAT-iq
Cordless Advanced Technology, Internet
and Quality
Codec
Coder and Decoder converts analog
signals to digital signals and vice versa
CVM
Cordless Voice Module
DECT
Digital Enhanced Cordless Telephone
© 2012 Dialog Semiconductor B.V.
Jul 1, 2014 v1.6
DECT Module with integrated Antenna and FLASH
RF
Dialog will provide the following standard software
stacks:
SC14SPNODE SF
2.0
SC14SPNODE SF
2.4 BLOCK DIAGRAM
Power supply
XTAL
20.736
MHz
PLL
(165.888
MHz)
SC14SPNODE
Non Shared/
Cache/Trace
RAM 16+4kByte
CR16Cplus
(82.944 MHz)
ULE
LDO
JTAG
/SDI
APB bridge
GPIO 0-3
Cache
Controller
DCDC
10 bit ADC
2 x ACCESS
Charge Pump
doubler
GPIOs
UART
PCM / I2S
AFE
16Mbit
FLASH
QSPI
8/16 kHz
CODEC
48/2 kByte
Gen2DSP
ROM/RAM
32kByte
Shared
RAM
Gen2DSP
82 MIPS
DIP
8/16 kHz
DMA
UART
SPI
Radio
Transceiver
TX/RX
SW
DIP RAM
ANT
SW
PA
Class-D
Figure 2 SC14SPNODE hardware block diagram
2.5 POWER SUPPLY
RF1
P0n
TP1
Internal antenna
RFP0n
VDDOUT
TX
VBATIN
100n
1U0
100n
RX
UPL_MAIN_CTRL
ULP_BAT
TX BALUN
P0
LDO_CTRL
VDD
RFP0
ADD
RF_SUPPLY
RF_SUPPLY_PA
RF0
Internal
FLASH VDD
CP_BAT
VBAT
Figure 4 Internal circuit of the antenna part
Figure 3 Internal circuit of the power supply
Re-certification of the SC14SPNODE SF is required if
at least one external antenna is added. On request,
Dialog Semiconductor can provide a pre-certified PCB
layout for an external antenna circuit.
Figure 3 shows the internal power supply circuit of the
SC14SPNODE SF.
2.6 ANTENNA OPERATION
Figure 4 shows the internal antenna circuit of the
SC14SPNODE SF. Pin RF0 is used for two external
antennas and can also be used for RF test purposes,
so it is recommended to add a 10 pF capacitor as
reserve pattern even when the two external antennas
are not used.
© 2012 Dialog Semiconductor B.V.
RF1 is also recommended to use and can be connected to the RF cable to be able to do the JPN DECT
type approval test.
2.6.1 Internal antenna only
The FAD function is not enabled if only the internal
antenna is used. In this case RFP0, RFP0n, P0 and
P0n must be left unconnected.
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DECT Module with integrated Antenna and FLASH
VBATSW
The SOC circuit is used to very accurately determine
the amount of charge in rechargeable batteries as well
as the discharge state of Alkaline batteries. This information is essential for the battery charging algorithm
and necessary for battery status indication to the user.
Detailed information can be found in AN-D-174 (see
Reference [2]).
Figure 5 shows one external antenna that is connected
to RF1 of the SC14SPNODE SF. This configuration
supports the FAD function. In this case pins RFP0,
RFP0n, P0 and P0n must be left unconnected. The
software patch code is not needed if the
SC14SPNODE SF is operated as FP.
V supply
SC14SPNODE SF
2.6.2 Internal and external antenna with FAD
V B A T IN
LD O
SOCp
SOCn
CHARGE
1k
RF1
CHARGE_CTRL
External
Antenna
SO C
SC 14S P N O D E
Figure 5 One external antenna
Figure 7 Base station (FP) application
2.7 BATTERY MANAGEMENT
V supply
V B A T IN
1k
0.1
CHARGE_CTRL
SOCn
100
SOCp
CHARGE
1k
2.8 EMBEDDED QSPI FLASH
The SC14SPNODE SF has a QSPI FLASH with type
number MX25U1635E as embedded FLASH. Please
refer to Reference [3] for detailed specifications.
SOC
S C 14SP N O D E
The MX25U1635E has an OTP area, a part of which
has already been factory programmed by Dialog for
tuning purposes.
Figure 6 Handset (PP) application with 2x NiMH
Table 2 shows the production parameters and the relation between the SC14SPNODE SF register address
and the OTP address.
Figure 6 shows a handset application with NiMH. SOC
(State Of Charge) is used to measure the amount of
charge in the rechargeable batteries.
The OTP addresses from 0x020 to 0x1FF are available
for write access before locking the OTP.
Figure 7 shows an FP application. The FP uses an
external LDO, so the SOC pins are not used and can
be connected to GND.
Table 2: SC14SPNODE production parameters
Register name
SC14SPNODE address
OTP address
Alignment Spec.
RF_BURST_MODE_CTRL_REG[MODINDEX]
0xFF7053[5:0]
0x05
340 kHz to 370 kHz
20.736 MHz +/- 1 ppm
CLK_FREQ_TRIM_REG (lsb)
0xFF400A
0x06
CLK_FREQ_TRIM_REG (msb)
0xFF400B
0x07
BANDGAP_REG
0xFF4810
0x08
© 2012 Dialog Semiconductor B.V.
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DECT Module with integrated Antenna and FLASH
Pin CHARGE_CTRL is driven high when either
“sensed voltage on the VBAT pin” is lower than the
voltage setting (defined by the module hardware) or
“sensed current via SOCp” is lower than the current
setting (defined by the module hardware). Pin
CHARGE_CTRL can drive up to 500 A as source current (see Table 19).
Specifications
All MIN/MAX specification limits are guaranteed by design, or production test, or statistical methods unless
note 8 is added to the parameter description. Typical values are informative.
Note 8:
This parameter will not be tested in production. The MIN/MAX values are guaranteed by design and verified by characterization.
3.1 GENERAL
Table 3: SC14SPNODE SF module
ITEM
CONDITIONS
Dimensions
lxwxh
Weight
UNIT
18.0 x 19.6 x 2.7
mm
1.5
-40 to +85
°C
1870 to 1930
MHz
- typical outdoor
350
- typical indoor
75
2.10 to 3.45
0.1
mm
Temperature range
Frequency range
According to DECT standard
Antenna range
According to DECT standard; (Note 9)
Standards compliancy
ETS 300 444 (DECT GAP), former TBR2214
FCC part 15
Power supply
2 cell NiCd/NiMH
Note: for 1 Li-Ion battery an external LDO is required.
Maximum PCB warpage
For entire reflow range
Note 9:
VALUE
SC14SPNODE SF
3.0
The resulting range is very dependent of the mechanical design. Dialog Semiconductor is not responsible for this design and as such Dialog
Semiconductor is not responsible for the resulting performance range of the final product.
Table 4: Absolute Maximum Ratings (Note 10)
PARAMETER
DESCRIPTION
MAX
UNIT
Vbat_max
Max voltage on pin VBATIN, VDDPA
CONDITIONS
MIN
3.45
Vpon_max
Max voltage on pin PON
5.5
Vled_max
Max voltage on pin LED4, LED3
3.6
Vdig_bp_max
Max voltage on digital pins with back drive
protection; ports P0 and P2 (except P2.6)
3.6
Vdig_max
Max voltage on other digital pins
2.0
Vana_max
Max voltage on analog pins
2.2
Vesd_hbm
ESD voltage according to human body
model; all pins
2000
Vesd_mm
ESD voltage according to machine model;
all pins
150
Note 10: Absolute maximum ratings are those values that may be applied for maximum 50 hours.
Beyond these values, damage to the device may occur.
© 2012 Dialog Semiconductor B.V.
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DECT Module with integrated Antenna and FLASH
3.2 ABSOLUTE MAXIMUM RATINGS
Table 5: Operating Conditions (Note 11)
PARAMETER
DESCRIPTION
CONDITIONS
Vbat
Supply voltage on pin VBATIN
Vdd_pa
CLASSD supply voltage on pin VDDPA
Vpon
Vdig_bp
Vdig
Voltage on other digital pins
Vana
Voltage on analog pins
Icharge
Current through pin CHARGE
Ipa
Current through pin PAOUTp, PAOUTn
Iout_vrefp
Output current through pin VREFp
TA
Ambient temperature
MIN
MAX
UNIT
2.1
3.45
2.1
3.45
Voltage on pin PON
5.5
Voltage on digital pins with back drive
protection; ports P0 and P2 (except P2.6)
3.45
VDD = 1.8 V
1.98
AVD = 1.8 V
2.1
Rseries >
(Vcharge-3 V)/
10 mA
10
mA
500
mA
mA
+85
°C
(Note 12)
(Note 13)
-40
TYP
SC14SPNODE SF
3.3 OPERATING CONDITIONS
Note 11: Within the specified limits, a life time of 10 years is guaranteed.
Note 12: A life time of 10 years of the CLASS-D amplifier is guaranteed if switched on for 10% of the time.
Note 13: Within this temperature range full operation is guaranteed.
3.4 DIGITAL INPUT/OUTPUT PINS
Table 6: Digital input levels
DESCRIPTION
CONDITIONS
Vil_dig
Logic 0 input level; all digital
input pins except PON,
CHARGE and RSTn
VDD = 1.8 V
Vil_pon
Vil_charge
Vil_rst
Logic 0 input level; pin RSTn
VDD = 1.8 V
Vih_dig
Logic 1 input level; all digital
input pins except PON,
CHARGE and RSTn
VDD = 1.8 V
Vih_pon
Vih_charge
Vih_rst
Logic 1 input level; pin RSTn VDD = 1.8 V
MIN
TYP
MAX
UNIT
0.3*VDD
Logic 0 input level; pin PON
0.9
Logic 0 input level; pin
CHARGE
0.9
0.2*VDD
0.7*VDD
Logic 1 input level; pin PON
1.5
Logic 1 input level; pin
CHARGE
1.5
0.8*VDD
Table 7: Digital output levels
PARAMETER
DESCRIPTION
CONDITIONS
Vol_dig
Logic 0 output level
VDD = 1.8 V; Iout =
2, 4, 8 mA (Note 14)
Voh_dig
Logic 1 output level
VDD = 1.8 V; Iout =
2, 4, 8 mA (Note 14)
MIN
0.8*VDD
TYP
MAX
UNIT
0.2*VDD
Note 14: For output drive capability, see section "Pin Description" on page 4.
© 2012 Dialog Semiconductor B.V.
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DECT Module with integrated Antenna and FLASH
PARAMETER
Table 8: ULP_PORT specifications
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNITS
Vil_ulp
Logic 0 input level; pin
ULP_PORT
Vbat = 2.1 V to
3.45 V
0.2*Vbat
Vih_ulp
Logic 1 input level; pin
ULP_PORT
Vbat = 2.1 V to
3.45 V
Vol_ulp
Logic 0 output level; pin
ULP_PORT
Iout = 1 mA,
Vbat = 2.4 V
Voh_ulp
Logic 1 output level; pin
ULP_PORT
Iout = 1 mA,
Vbat = 2.4 V
Ipull_up_ulp
Input current with pull up
enabled; pin ULP_PORT
Vin = GND
2.5
A
Ipull_down_ulp
Input current with pull down
enabled; pin ULP_PORT
Vin = Vbat; Vbat =
2.1 V to 3.45 V
2.5
A
0.8*Vbat
0.2*Vbat
0.8*Vbat
SC14SPNODE SF
3.5 ULTRA LOW ENERGY (ULE) I/O PIN
3.6 SUPPLY CURRENTS
Table 9: Supply currents (indicative value)
DESCRIPTION
CONDITIONS
Iavd_pa
CLASSD normal
mode supply current
at AVD
CLASSD_PD=0
Iavd_paport
CLASSD digital port
mode supply current
at AVD
(P3_0_MODE = 00 or P3_1_MODE
= 00) and CLASSD_PD=1.
(Note 15)
MIN
TYP
MAX
Unit
3.5
mA
A
Note 15: PAOUTp and PAOUTn have internal fixed resistors connected to VSSPA. The values are 5 k if CLASSD[CLASSD_VOUT] = 01, else
6 k. So in digital mode with a ‘1’ on output a small static current will flow.
© 2012 Dialog Semiconductor B.V.
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DECT Module with integrated Antenna and FLASH
PARAMETER
Table 10: Microphone amplifier
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
Vmic_0dB_unt
Untrimmed differential RMS input voltage between MICp
and MICn (0 dBm0
reference level)
(Note 8)
0 dBm0 on COUT
(Note 17)
MIC_GAIN[3:0] = 0,
@ 1020 Hz;
Tolerance:
• 13% when untrimmed
(BANDGAP_REG=8)
(Note 16)
114
131
149
mV
75
150
SC14SPNODE SF
3.7 ANALOG FRONT END
• 6% when trimmed
(Note 18)
Rin_mic
Resistance of activated microphone
amplifier inputs
(MICp, MICn and
MICh) to internal GND
(Note 8)
Vmic_offset
Input referred DC-offset (Note 8)
MIC_GAIN[3..0] = 1111
3 sigma deviation limits
-2.6
k
+2.6
mV
Note 16: BANDGAP_REG will be tuned at the factory.
Note 17: 0 dBm0 on COUT = -3.14 dB of max PCM value. COUT is CODEC output in test mode
Note 18: Trimming possibility is foreseen. At system production the bandgap reference voltage can be controlled within 2% accuracy and data can
be stored in Flash. Either AVD or VREF can be trimmed within 2% accuracy. If AVD is trimmed VREF will be within 2% accuracy related to
either AVD. Or vice versa VREF can be trimmed. For Vref trimming measure VREFp, VREFm) and update BANDGAP_REG[3..0].
PARAMETER
DESCRIPTION
CONDITIONS
Vmic_cm_level
MICp and MICn common mode voltage
MICp and MICn are set to
GND with internal resistors
(Rin_mic). If DC coupled
the input voltage must be
equal to this voltage.
MIN
TYP
MAX
UNIT
(0.9 V/1.5)*
VREFp
Table 12: Microphone supply voltages
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
Vref_unt
VREFp-VREFm
untrimmed
(Note 19)
ILOAD = 0 mA
BANDGAP_REG = 8
(Note 18)
1.41
1.5
1.59
Rout_vrefp
VREFp output
resistance
Figure 8
Nvrefp_idle
Peak noise on
VREFp-VREFm
(Note 8)
CCITT weighted
PSRRvrefp
Power supply rejection Vref output
(Note 8)
See Figure 8, AVD to
VREFp/m, f = 100 Hz to 4 kHz
BANDGAP_REG[5:4] = 3

-120
40
dBV
dB
Note 19: Vrefm is a clean ground input and is the 0 V reference.
© 2012 Dialog Semiconductor B.V.
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Jul 1, 2014 v1.6
DECT Module with integrated Antenna and FLASH
Table 11: Microphone amplifier (Operating Condition)
PARAMETER
DESCRIPTION
Cload_vrefp
Iout_vrefp
Rout_vrefp
MAX
UNIT
VREFp (parasitic) load
capacitance
20
pF
VREFp output current
mA
VREFp
CONDITIONS
MIN
TYP
SC14SPNODE SF
Table 13: VREFp load circuit
Iout_vrefp
Cload_vrefp
VREFm
Figure 8 VREFp load circuit
Table 14: LSRp/LSRn outputs
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
Vlsr_0dB_unt
Untrimmed differential RMS output voltage between LSRp
and LSRn in audio
mode (0 dBm0 reference level)
0 dBm0 on CIN (Note 20),
LSRATT[2:0] = 001,
@ 1020 Hz Load circuit A (see
Figure 9, Table 15) with RL1=
 , Cp1 or load circuit B (see
Figure 10) with RL2, Cp2 and
Cs2
621
714
807
mV
Tolerance:
• 13% when untrimmed
(BANDGAP_REG=8)
• 6% when trimmed
(Note 18)
Rout_lsr
Resistance of activated loudspeaker
amplifier outputs
LSRp and LSRn
Vlsr_dc
DC offset between
LSRp and LSRn
(Note 8)

LSRATT[2:0] = 3
RL1 = 28 
3 sigma deviation limits
-20
20
mV
Note 20: 0 dBm0 on CIN = -3.14 dB of max PCM value.
© 2012 Dialog Semiconductor B.V.
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Jul 1, 2014 v1.6
DECT Module with integrated Antenna and FLASH
PARAMETER
PARAMETER
DESCRIPTION
CONDITIONS
Cp1_Rl1_inf
Load capacitance
Cp1_Rl1_1k
Load capacitance
Rl1
Load resistance
Cp2
Parallel load
capacitance
Cs2
Serial load capacitance
Rl2
Load resistance
MIN
TYP
MAX
UNIT
see Figure 9, RL1 = 
30
pF
see Figure 9, RL1 1 k
100
pF
30
pF
30
F

28
see Figure 10

600
LSRp
SC14SPNODE SF
Table 15: LSRp/LSRn load circuits
LSRp
RL2
RL1
Cp2
Cp1
Cs2
LSRn
LSRn
Figure 10 Load circuit B: Piezo loudspeaker
Figure 9 Load circuit A: Dynamic loudspeaker
Table 16: PAOUTp, PAOUTn outputs
DESCRIPTION
CONDITIONS
Vpa_4v
Differential rms output
voltage between
PAOUTp and PAOUTn
Trimmed bandgap
input = 0 dBm0, 1 kHz
(Note 17)
Output low-pass filtered
CLASSD_VOUT = 0
0.985
Vrms
As above
CLASSD_VOUT = 1
1.478
Vrms
Vpa_6v
Zload_pa_4v
Zload_pa_6v
Speaker impedance,
connected between
PAOUTp and PAOUTn
MIN
With these values, the peak currents stays within the operating
range.
TYP
MAX
UNIT


Table 17: PAOUTp, PAOUTn outputs (Note 21)
PARAMETER
DESCRIPTION
CONDITIONS
Rout_pa
Differential output
resistance between
PAOUTp and PAOUTn
See (Note 21)
MIN
TYP
MAX
UNIT

Note 21: Clipping of the outputs occurs when the VDDPA drops and the following conditions becomes true. If CLASSD_CTRL_REG[CLASSD_CLIP]
is not equal to zero then upon a programmable number of clipping occurrences a CLASSD_INT is generated:
The software can stop clipping by reducing the gain via the GENDSP:
Clipping occurs if
© 2012 Dialog Semiconductor B.V.
peak
 LowPassFiltered  PAOUTp – PAOUTm  - ------------------------------------------Zload
---------------------------------------------------------------------------------------------------------------------
VDDPA – VSSPA
Zload + Rout_pa
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Jul 1, 2014 v1.6
DECT Module with integrated Antenna and FLASH
PARAMETER
PARAMETER
DESCRIPTION
CONDITIONS
C_VDDPA
Decoupling capacitor on
VDDPA
Required when Class-D is used
and guaranteed life time.
(see Figure 11)
MIN
TYP
MAX
UNIT
F
Cs_PAOUT
Snubber capacitor (to
reduce ringing at
PAOUTp/n)
Required when Class-D is used
to prevent EMI and guaranteed
life time. (see Figure 11)
nF
Rs_PAOUT
Snubber resistor (to
reduce ringing at
PAOUTp/n)
Required when Class-D is used
to prevent EMI and guaranteed
life time. (see Figure 11)

SC14SPNODE SF
Table 18: PAOUTp, PAOUTn external components
PAOUTp
Rs_PAOUT
Cs_PAOUT
VDDPA
C_VDDPA
VSS/GND
PAOUTn
Rs_PAOUT
Efficiency 75% at 300 mW@2 V, 500 mW@2.5 V into a 4  transducer.
2.5 V (= VBAT)
VDDPA
GND (2x)
DUT
1 F ceramic
dummy load
(models typical speaker)
resistors reduce
influence from
measurement on
DUT
100 
PAOUTp
15 H
4
PAOUTn
AP-system2, settings:
bw = <10 Hz until 30 kHz
filter = A-weighting
detection = 4/s RMS
input = high-ohmic
in
in
out
15H
100 
AP AUX-0025
passive switching amplifier measurement filter
Figure 12 CLASS-D amplifier measurement setup
© 2012 Dialog Semiconductor B.V.
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Jul 1, 2014 v1.6
DECT Module with integrated Antenna and FLASH
Figure 11 Class-D external components
Table 19: CHARGE_CTRL pin
PARAMETER
DESCRIPTION
CONDITIONS
MIN
Voh_charge_ctrl
Drive capability of pin
CHARGE_CTRL
sourcing 500 A
1.6
Vol_charge_ctrl
TYP
MAX
UNIT
sinking 100 A
0.2
MAX
UNIT
+100
mV
Table 20: State of charge circuit (SoC) (Operating condition)
DESCRIPTION
CONDITIONS
MIN
Vsocp_socn
Input voltage
between SOCp and
SOCn
With the prescribed 0.1  sense
resistor this results in the usable current range
-100
-1000 mA
TYP
SoC_asym_err
ex
tra
po
la
io
10
Counter ticks/s
PARAMETER
SC14SPNODE SF
3.8 BATTERY MANAGEMENT
-100 mA
100 mA
1000 mA
input current
Figure 13 State of charge (SOC) counter accuracy
3.9 BASEBAND PART
Table 21: Baseband specifications
PARAMETER
DESCRIPTION
CONDITIONS
Fbit_uart
Serial interface bit rate
Fbit_flash
MAX
UNIT
UART; Interface for external
microprocessor or PC
115.2
kbit/s
Flash download bit rate
Via UART
115.2
kbit/s
Ibat_stdby_fp
Standby supply current
FP application (3.3 V)
55
60
mA
Ibat_act_fp
Active supply current
FP application (3.3 V)
65
70
mA
Ibat_stdby_pp
Standby supply current
PP application (3.3 V)
4.5
mA
Ibat_act_pp
Active supply current
PP application (3.3 V)
30
40
mA
© 2012 Dialog Semiconductor B.V.
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MIN
TYP
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DECT Module with integrated Antenna and FLASH
SoC_sym_err: A - |B|
Table 22: Radio specifications
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
P_Rx
Receiver sensitivity
BER = 0.001; TA = 25 °C
-93
-92
-89
dBm
P_Rx_T
Receiver sensitivity, full
temperature range
BER = 0.001;
-40 °C TA 85 °C
-94
-87
dBm
IPL
Intermodulation performance level (EN 301 406
section 4.5.7.6)
TA = 25 °C;
Pw = -80 dBm;
f = 2 channels
-35
NTP
Normal transmitted power
DECT: 250 mW
24
26
dBm
J-DECT: 10 mW average per
frame for each slot
23
24.5
dBm
20.0
dBm
dB
dBm
DECT6.0: 100 mW (max
peak)
dPrfpa_T
RFPA power variation, full
temperature range
-40 °C TA +85 °C
Fbit
Bit rate
GFSK modulation
BW_Tx
Transmitter bandwidth
DECT GFSK;
NTP = 20 dB
SC14SPNODE SF
3.10 RADIO (RF) PART
Standards compliancy: ETS 301 406 (former TBR6).
2.5
1.152
Mbit/s
1.728
MHz
Table 23: RFPA preferred settings for various power modes (PP application)
Register / Parameter
HPM/U
(USA)
HPM
(Europe)
HPM/J
(Japan)
0x3D
RF_BBADC_CTRL_REG
0x0380
0x03A0
0x0398
0x39
RF_PA_CTRL1_REG
0x09A0
0x0CF0
0x2CE0
0x3B
RF_TEST_MODE2_REG
0x0056
0x0062
0x0068
0x05
RF_PLL_CTRL2_REG[MODINDEX]
0x25
0x25
0x23
0x23
Upper RSSI threshold
0x2C
N/A
0x28
0x24
Lower RSSI threshold
0x22
N/A
0x1E
© 2012 Dialog Semiconductor B.V.
20
Jul 1, 2014 v1.6
DECT Module with integrated Antenna and FLASH
Address
(VES)
Table 24: Requirements for linear supply regulator
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
VBAT IN
Voltage at VBAT SW
Unloaded VB
Loaded VB-V1-V2-V3
2.1
3.45
V1
Settling time
I = 50 mA
20
mV
V2
Receive period
I = 130 mA
100
mV
V2
Transmit period
I = 550 mA
200
mV
V3
Drop during transmit
25
mV
SC14SPNODE SF
3.11 RF POWER SUPPLY
DECT Module with integrated Antenna and FLASH
Figure 14 RF power supply
© 2012 Dialog Semiconductor B.V.
21
Jul 1, 2014 v1.6
SC14SPNODE SF
3.12 RF CHANNEL FREQUENCIES
Table 25: RF frequencies and channel numbers
Frequency
(MHz)
DECT
CH
1881.792
1883.520
1885.248
1886.976
1888.704
1890.432
1892.160
1893.888
1895.616
1897.344
J-DECT
CH
DECT6.0
CH
1899.072
10
1900.800
11
1902.528
12
1923.264
1924.992
1926.720
1928.448
DECT Module with integrated Antenna and FLASH
1921.536
RF setting values must be followed according to
AN-D-204 when DECT country mode was changed.
© 2012 Dialog Semiconductor B.V.
22
Jul 1, 2014 v1.6
Design guidelines
purposes. In order to avoid any interference or disturbance the area around these signal pins must be
kept clear of any signal and/or GND. The recommended clearance is at least 1 mm as shown in Figure 15.
4.1 PCB DESIGN GUIDELINES
• Because of the presence of the digital radio frequency burst with 100 Hz time division periods (TDD
noise), supply ripple and RF radiation, special attention is needed for the power supply and ground PCB
layout.
• Power supply considerations
Both high and low frequency bypassing of the supply
line connections should be provided and placed as
close as possible to the SC14SPNODE. In order to
get the best overall performance for both FP and PP
applications, a number of considerations for the PCB
has to be taken into account.
• Supply lines should be placed as far as possible
away from sensitive audio circuits. If it is necessary to cross supply lines and audio lines, it
should be done with right angles between supply
and audio lines/circuits (microphone, ear-speaker,
speakerphone, etc.)
1.0mm
GND Pattern
• Ground plane considerations
In order to achieve the best audio performance
and to avoid the influence of power supply noise,
RF radiation, TDD noise and other noise sources,
it is important that the audio circuits on both FP
and PP applications boards are connected to the
VREFM pin on the SC14SPNODE with separate
nets in the layout.
It is advised to provide the following audio circuits
with separate ground nets connected to the
VREFM pin:
1.0mm
Test
pattern
0.6mm
0.9mm
• Make angle breaks on long supply lines to avoid
resonances at DECT frequencies. Maximum
80 mm before an angle break is recommended.
Figure 15 Clearance around test patterns
DECT Module with integrated Antenna and FLASH
• Microphone(s)
• Headset microphone and speaker
• Speakerphone (signal grounds)
Depending on the layout it may also be necessary to
bypass a number of the audio signals listed above to
avoid humming, noise from RF radiation and TDD
noise. It is also important to choose a microphone of
appropriate quality with a high RF immunity (with builtin capacitor).
• ESD performance
Besides TDD noise, the ESD performance is important for the end-application. In order to achieve a
high ESD performance supply lines should be
placed with a large distance from charging terminals,
display, headset connector and other electrical terminals with direct contact to the ESD source.
On a two-layer PCB application it is important to
keep a simulated one layer ground. With a stable
ground ESD and TDD noise performance will always
improve.
• Clearance around test patterns
Pin number 81 to 88 are used for production test
© 2012 Dialog Semiconductor B.V.
SC14SPNODE SF
4.0
23
Jul 1, 2014 v1.6
Place the module at the edge of the main-board as
shown in Figure 16.
If the module has to be placed away from the edge of
the main-board, then avoid conducting areas in front of
the antennas and make a cut-out in the main board
underneath the antennas as shown in the figure.
Keep a distance of at least 10 mm from the antenna
elements to conducting objects and at least 5 mm to
non-conducting objects.
See Figure 18 and Figure 21 for the detailed package
outline.
Keep in mind that electrical shielding objects, even
partly surrounding the antennas, will normally cause a
significant degradation of the coverage.
N o P C B a re a
SC14SPNODE SF
4.2 MODULE PLACEMENT ON THE MAIN BOARD
In order to ensure FCC compliance, proper coverage
and to avoid detuning of the antennas, it is required to
place the module on the main board free from other
surrounding materials.
> 10 m m
> 10 m m
> 10 m m
79
a n te n n a e x te n s io n
GND
M o d u le
M a in b o a rd
78
GND
77
76
GND
DECT Module with integrated Antenna and FLASH
Figure 16 Module placement on the main board (top view)
4.3 PATTERN FOR PIN 79 ON THE MAIN BOARD
The copper pattern for pin 79 on the main board is very
important because it is part of the internal antenna of
the module. It is used to extend the internal antenna for
optimum RF performance.
The PCB pattern shown in Figure 19 under “pads C”
for pin 79 on the main board was used during module
certification.
4.4 PRECAUTIONS REGARDING UNINTENDED
COUPLING
The SC14SPNODE includes an internal antenna, so by
integration on the main board precautions shall be
taken in order to avoid any kind of coupling from the
main board to the RF part of the module.
If there is any doubt about this, a brief radio test should
be performed.
© 2012 Dialog Semiconductor B.V.
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Jul 1, 2014 v1.6
Notices to OEM
• Increase the separation between the equipment and
receiver
The end product has to be certified again if it has
been programmed with other software than Dialog
standard software stack for portable part and/or
uses one or two external antenna(s).
• Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
• Consult the dealer or an experienced radio/TV technician for help.
5.1 FCC REQUIREMENTS REGARDING THE END
PRODUCT AND THE END USER
The end product that the module is integrated into must
be marked as follows:
Privacy of communications may not be ensured when
using this phone.
5.2 INDUSRY CANADA REQUIREMENTS REGARDING THE END PRODUCT AND THE END USER
The host device shall be properly labelled to identify
the modules within the host device. The Industry Canada certification label of a module shall be clearly visible at all times when installed in the host device,
otherwise the host device must be labelled to display
the Industry Canada certification number of the module, preceded by the words "Contains transmitter module", or the word "Contains", or similar wording
expressing the same meaning, as follows:
“Contains Transmitter Module FCC ID: Y82-SC14S /
IC: 9576A-SC14S”
The literature provided to the end user must include the
following wording:
FCC compliance statement
This device complies with Part 15 of the FCC Rules.]
for only portable part.
Operation is subject to the following two conditions:
(1) this device may not cause harmful interference, and
(2) this device must accept any interference received,
including interference that may cause undesired operation of the device.
Contains transmitter module IC: 9576A-SC14S
Son fonctionnement est soumis aux deux conditions
suivantes: (1) cet appareil ne doit pas causer d’interférences nuisibles et (2) appareil doit accepter toute
interférence reçue, y compris les interférences qui peuvent perturber le fonctionnement.
Changes or modifications to the equipment not
expressly approved by the Party responsible for compliance could void the user's authority to operate the
equipment.
Contient le module d'émission IC: 9576A-SC14S
This device complies with Industry Canada licenceexempt RSS standard(s). Operation is subject to the
following two conditions: (1) this device may not cause
interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device.
NOTE: This equipment has been tested and found to
comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are
designed to provide reasonable protection against
harmful interference in a residential installation.
This equipment generate, uses and can radiate radio
frequency energy and, if not installed and used in
accordance with the instructions, may cause harmful
interference to radio communications. However, there
is no guarantee that interference will not occur in a particular installation.
Le présent appareil est conforme aux CNR d'Industrie
Canada applicables aux appareils radio exempts de
licence. L'exploitation est autorisée aux deux conditions suivantes : (1) l'appareil ne doit pas produire de
brouillage, et (2) l'utilisateur de l'appareil doit accepter
tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.
If this equipment does cause harmful interference to
radio or television reception, which can be determined
by turning the equipment off and on, the user is
encouraged to try to correct the interference by one or
more of the following measures:
CAN ICES-3 (B)/NMB-3(B)
• Reorient or relocate the receiving antenna
25
Jul 1, 2014 v1.6
DECT Module with integrated Antenna and FLASH
L'appareil hôte doit être étiqueté comme il faut pour
permettre l'identification des modules qui s'y trouvent.
L'étiquette de certification d'Industrie Canada d'un
module donné doit être posée sur l'appareil hôte à un
endroit bien en vue en tout temps. En l'absence d'étiquette, l'appareil hôte doit porter une etiquette donnant
le numéro de certification du module d'Industrie Canada, précédé des mots " Contient un module d'émission ", du mot " Contient " ou d'une formulation
similaire exprimant le même sens, comme suit :
Module transmetteur ID IC: 9576A-SC14S.
© 2012 Dialog Semiconductor B.V.
SC14SPNODE SF
5.0
SC14SPNODE SF
5.3 PRECAUTIONS REGARDING UNINTENDED
COUPLING
Integration on the main board precautions shall be
taken in order to avoid any kind of coupling from the
main board to the RF part of the module. If there is any
doubt about this, a radio short test should be performed.
5.4 END APPLICATION APPROVAL
The module is intended to be used in an end application. Type approval concerning the end product, except
for the module, should off cause be done. Please contact a test-house in order to clarify what is needed.
5.5 SAFETY REQUIREMENTS
This section provides of an overview of the safety
requirements you must adhere to when working with
the SC14SPNODE.
• The specific external power supply for the
SC14SPNODE has to fulfil the requirements according to clause 2.5 (Limited power source) of this
standard EN 60950-1:2006.
• Interconnection circuits shall be selected to provide
continued conformance to the requirements of
clause 2.2 for SELV (Safety Extra Low Voltage) circuits according to EN 60950-1:2006 after making
connections.
• Interface type not subjected to over voltages (i.e.
does not leave the building).
DECT Module with integrated Antenna and FLASH
• Requirements additional to those specified in this
standard may be necessary for:
• Equipment intended for operation in special environments (for example, extremes of temperature,
excessive dust, moisture or vibration, flammable
gases and corrosive or explosive atmospheres).
• Equipment intended to be used in vehicles, on
Board ships or aircraft, in tropical countries or at
altitudes greater than 2000 m.
• Equipment intended for use where ingress of
water is possible.
• Installation by qualified personnel only!
• The product is a component intended for installation
and use in complete equipment. The final acceptance of the component is dependent upon its installation and use in complete equipment.
© 2012 Dialog Semiconductor B.V.
26
Jul 1, 2014 v1.6
SC14SPNODE SF
6.0
Package information
6.1 SOLDERING PROFILE
The SC14SPNODE should be soldered using a standard reflow soldering profile and lead free solder paste
as shown below. Adjustments to the profile may be
necessary depending on process requirements.
DECT Module with integrated Antenna and FLASH
Figure 17 Reflow profile
6.2 MOISTURE SENSITIVITY LEVEL (MSL)
The MSL is an indicator for the maximum allowable
time period (floor life time) in which a moisture sensitive plastic device, once removed from the dry bag, can
be exposed to an environment with a maximum temperature of 30°C and a maximum relative humidity of
60% RH. before the solder reflow process.
The SC14SPNODE is qualified to MSL 3.
MSL Level
Floor Life Time
MSL 4
72 hours
MSL 3
168 hours
MSL 2A
4 weeks
MSL 2
1 year
MSL 1
Unlimited at 30°C/85%RH
© 2012 Dialog Semiconductor B.V.
27
Jul 1, 2014 v1.6
SC14SPNODE SF
6.3 COPPER PAD, SOLDER OPENING AND STENCIL
For the stencil a thickness of 0.122 mm is
recommended. Recommended copper pad, solder
mask opening and stencil are shown below.
DECT Module with integrated Antenna and FLASH
Figure 18 Pad dimensions
© 2012 Dialog Semiconductor B.V.
28
Jul 1, 2014 v1.6
SC14SPNODE SF
Figure 19 Copper pad, Solder mask opening and Stencil
DECT Module with integrated Antenna and FLASH
Figure 20 Solder stencil
© 2012 Dialog Semiconductor B.V.
29
Jul 1, 2014 v1.6
SC14SPNODE SF
6.4 MECHANICAL DIMENSIONS
DECT Module with integrated Antenna and FLASH
Figure 21 Package outline drawing
© 2012 Dialog Semiconductor B.V.
30
Jul 1, 2014 v1.6
SC14SPNODE SF
7.0
Revision history
Jul1, 2014
v1.6:
• Changed maximum RF output power for DECT 6.0
Apr 16, 2014 v1.5:
• Added an explanation for RF1 on 2.6
Feb 11, 2014 v1.4:
• Correct 6.3Copper pad, solder openinG and
STENCIL28
Feb 4, 2014
v1.3:
• Modified 6.3Copper pad, solder openinG and
STENCIL28
Nov 8, 2013
v1.2:
• Added section “5.2 INDUSTRY CANADA
REQUIREMENTS REGARDING THE END PRODUCT AND THE END USER”
Sept 12, 2013 v1.1:
• Ordering code for tray version corrected.
• Ordering code for tape-on-reel version removed.
July 10, 2013
v1.0: Initial version
DECT Module with integrated Antenna and FLASH
© 2012 Dialog Semiconductor B.V.
31
Jul 1, 2014 v1.6
Datasheet Status
Product Status
Definition
Advance Information
Formative or in Design
This data sheet contains the design specifications for product development. Specifications may change in any manner
without notice.
Preliminary
First Production
This data sheet contains preliminary data. Supplementary
data will be published at a later date. Dialog Semiconductor
reserves the right to make changes at any time without
notice in order to improve design and supply the best possible product.
No Identification Noted
Full production
This data sheet contains final specifications. Dialog Semiconductor reserves the right to make changes at any time
without notice in order to improve design and supply the best
possible product.
Obsolete
Not in Production
This data sheet contains specifications on a product that has
been discontinued by Dialog Semiconductor. The data-sheet
is printed for reference information only.
SC14SPNODE SF
Product Status Definitions
Dialog Semiconductor reserves the right to make changes without notice to any products herein to improve reliability, function or design. Dialog Semiconductor does not assume any liability arising out of the application or use of
any product or circuit described herein; neither does it convey any license under its patent rights, nor the right of others.
Life Support Policy
DIALOG’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNCIL OF DIALOG SEMICONDUCTOR. As used herein:
in a significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or system, or to
affect its safety or effectiveness.
Dialog Semiconductor does not assume any responsibility for use of any circuit described, no circuit patent licenses are implied, and Dialog
reserves the right, at any time without notice, to change said circuitry or specifications.
RoHS Compliance
Dialog Semiconductor complies to European Directive 2001/95/EC and from 2 January 2013 onwards to European
Directive 2011/65/EU concerning Restriction of Hazardous Substances (RoHS/RoHS2).
Dialog Semiconductor’s statement on RoHS can be found on the customer portal http:/portal.dialog-semiconductor.com. RoHS certificates from our suppliers are available on request.
Contacting Dialog Semiconductor
Germany Headquarters
Dialog Semiconductor GmbH
Phone: +49 7021 805-0
North America
Dialog Semiconductor Inc.
Phone: +1 408 727 3200
Singapore
Dialog Semiconductor Singapore
Phone: +65 64845419
United Kingdom
Dialog Semiconductor (UK) Ltd
Phone: +44 1793 757700
Japan
Dialog Semiconductor K. K.
Phone: +81 3 5425 4567
China
Dialog Semiconductor China
Phone: +852 2607 4271
The Netherlands
Dialog Semiconductor B.V.
Phone: +31 73 640 88 22
Taiwan
Dialog Semiconductor Taiwan
Phone: +886 226 580 388
Korea
Dialog Semiconductor Korea
Phone: +82 2 569 2301
© 2012 Dialog Semiconductor B.V.
32
Jul 1, 2014 v1.6
DECT Module with integrated Antenna and FLASH
1. Life support devices or systems are devices or
systems which,
(a) are intended for surgical implant into the
body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance with instructions for use provided in the
labelling, can be reasonably expected to result
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Creator Tool                    : FrameMaker 9.0
Modify Date                     : 2014:07:01 13:26:45+02:00
Create Date                     : 1997:02:03 11:26:52Z
Metadata Date                   : 2014:07:01 13:26:45+02:00
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Page Mode                       : UseOutlines
Page Count                      : 32
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EXIF Metadata provided by EXIF.tools
FCC ID Filing: Y82-SC14S

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