Nokia Solutions and Networks T5CT1 Cellular CDMA base station User Manual IHET5CT1 GLI3 Manual 4 of 6

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Document Title	IHET5CT1 GLI3 Manual 4 of 6

Chapter 6
Troubleshooting
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Troubleshooting
Overview
The information in this chapter addresses some of the scenarios likely to
be encountered by Customer Field Engineering (CFE) team members.
This troubleshooting guide was created as an interim reference document
for use in the field. It provides basic “what to do if” basic
troubleshooting suggestions when the BTS equipment does not perform
per the procedure documented in the manual.
Comments are consolidated from inputs provided by CFEs in the field
and information gained form experience in Motorola labs and
classrooms.
Cannot Log into Cell-Site
Follow the procedure in Table 6-1 to troubleshoot any Login Failure
problem during normal operation.
Table 6-1: Login Failure Troubleshooting Procedure
6-2
Step
Action
If MGLI3 LED is solid RED, it implies a hardware failure. Reset MGLI3 by re-seating it. If this
persists, install RGLI3 card in MGLI3 slot and retry. A Red LED may also indicate no Ethernet
termination at top of frame.
Verify that T1 is disconnected at the Channel Signaling Unit (CSU). If T1 is still connected,
verify the CBSC has disabled the BTS.
Try ‘ping’ing the MGLI3.
Verify the LMF is connected to the Primary LMF port (LAN A) in front of the BTS.
Verify the LMF was configured properly.
Verify the BTS-LMF cable is RG-58 (flexible black cable of less than 2.5 feet length).
Verify the Ethernet ports are terminated properly.
Verify a T-adapter is not used on LMF side port if connected to the BTS front LMF primary
port.
Try connecting to the I/O panel (back of frame). Use Tri-Ax to BNC adapter at the LMF port for
this connection.
10
Re-boot the CDMA LMF and retry.
11
Re-seat the MGLI3 and retry.
12
Verify IP addresses are configured properly.
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Cannot Communicate to Power Meter
Follow the procedure in Table 6-2 to troubleshoot a power meter
communication failure.
Table 6-2: Troubleshooting a Power Meter Communication Failure
Step
Action
Verify Power Meter is connected to LMF with GPIB adapter.
Verify cable setup as specified in Chapter 3.
Verify the GP-IB address of the Power Meter is set to 13. Refer to Test Equipment setup section
of Chapter 3 for details.
Verify that Com1 port is not used by another application.
Verify that the communications analyzer is in Talk&Listen, not Control mode.
Cannot Communicate to Communications Analyzer
Follow the procedure in Table 6-3 to troubleshoot a communication
analyzer failure.
Table 6-3: Troubleshooting a Communications Analyzer Communication Failure
Step
Action
Verify analyzer is connected to LMF with GPIB adapter.
Verify cable setup.
Verify the GPIB address is set to 18.
Verify the GPIB adapter DIP switch settings are correct. Refer to Test Equipment setup section
for details.
Verify the GPIB adapter is not locked up. Under normal conditions, only 2 green LEDs must be
‘ON’ (Power and Ready). If any other LED is continuously ‘ON’, then power-cycle the GPIB
Box and retry.
If a Hyperterm window is open for MMI, close it.
Verify the LMF GPIB address is set to 18
Verify the analyzer is in Talk and Listen not Control mode.
Code Download Failure
Follow the procedure in Table 6-4 to troubleshoot any code download
failure.
Table 6-4: Troubleshooting Code Download Failure
Step
Aug 2002
Action
Verify T1 is disconnected from the BTS at CSU.
Verify LMF can communicate with the BTS device using the Status function.
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Table 6-4: Troubleshooting Code Download Failure
Step
Action
Communication to MGLI3 must first be established before trying to talk to any other BTS
device. MGLI3 must be INS_ACT state (green).
Verify the card is physically present in the cage and powered-up.
If card LED is solid RED, it implies hardware failure. Reset card by re-seating it. If this persists,
replace card from another slot & retry.
NOTE
The card can only be replaced by a card of the same type.
Re-seat card and try again.
If BBX reports a failure message and is OOS_RAM, the code load was OK. Status it.
If the download portion completes and the reset portion fails, reset the device by selecting the
device and reset.
Cannot Download DATA to Any Device (Card)
Follow the procedure in Table 6-5 to troubleshoot any data download
failure.
Table 6-5: Troubleshooting Data Download Failure
Step
Action
Re-seat card and repeat code and data load procedure.
Verify the ROM and RAM code loads are of the same release by statusing the card. Refer to
Chapter 3, “Download the BTS” for more information.
Cannot ENABLE Device
Before a device can be enabled (placed in-service), it must be in the
OOS_RAM state (yellow on the LMF) with data downloaded to the
device. The color of the device on the LMF changes to green, once it is
enabled.
The three states that devices can be displayed:
 Enabled (green, INS)
 Disabled (yellow, OOS_RAM)
 Reset (blue, OOS_ROM)
Follow the procedure in Table 6-6 to troubleshoot device enable failure.
Table 6-6: Troubleshooting Device Enable (INS) Failure
6-4
Step
Action
Re-seat card and repeat code and data load procedure.
If CSM cannot be enabled, verify the CDF file has correct latitude and longitude data for cell
site location and GPS sync.
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Table 6-6: Troubleshooting Device Enable (INS) Failure
Step
Action
Ensure primary CSM is in INS_ACT state.
NOTE
MCCs will not go INS without the CSM being INS.
Verify 19.6608 MHz CSM clock; MCCs will not go INS otherwise.
The BBX should not be enabled for ATP tests.
If MCCs give “invalid or no system time,” verify the CSM is enabled.
LPA Errors
Follow the procedure in Table 6-7 to troubleshoot any LPA errors.
Table 6-7: LPA Errors
Step
Action
If LPAs continue to give alarms, even after cycling power at the circuit breakers, then connect an
MMI cable to the LPA and set up a Hyperterminal connection. Enter ALARMS in the
Hyperterminal window. The resulting LMF display may provide an indication of the problem.
(Call Field Support for further assistance.)
Bay Level Offset Calibration Failure
Follow the procedure in Table 6-8 to troubleshoot a BLO calibration
failure.
Table 6-8: Troubleshooting BLO Calibration Failure
Step
Aug 2002
Action
Verify the Power Meter is configured correctly (see the test equipment setup section) and
connection is made to the proper TX port.
Verify the parameters in the bts-#.cdf file are set correctly for the following bands:
For 1900 MHz:
BandClass=1; FreqBand=16
For 800 MHz:
BandClass=0; FreqBand=8
Verify that no LPA in the sector is in alarm state (flashing red LED). Reset the LPA by pulling
the circuit breaker, and after 5 seconds, pushing back in.
Re-calibrate the Power Meter and verify it is calibrated correctly with cal factors from sensor
head.
Verify GPIB adapter is not locked up. Under normal conditions, only 2 green LEDs must be
‘ON’ (Power and Ready). If any other LED is continuously ‘ON’, power-cycle (turn power off
and on) the GPIB Box and retry.
Verify sensor head is functioning properly by checking it with the 1 mW (0 dBm) Power Ref
signal.
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Table 6-8: Troubleshooting BLO Calibration Failure
Step
Action
If communication between the LMF and Power Meter is operational, the Meter display will
show “RES :’’
Verify the combiner frequency is the same as the test freq/chan.
Calibration Audit Failure
Follow the procedure in Table 6-9 to troubleshoot a calibration audit
failure.
Table 6-9: Troubleshooting Calibration Audit Failure
Step
Action
Verify Power Meter is configured correctly (refer to the test equipment setup section of chapter
3).
Re-calibrate the Power Meter and verify it is calibrated correctly with cal factors from sensor
head.
Verify that no LPA is in alarm state (rapidly flashing red LED). Reset the LPA by pulling the
circuit breaker, and, after 5 seconds, pushing back in.
Verify that no sensor head is functioning properly by checking it with the 1 mW (0 dBm) Power
Ref signal.
After calibration, the BLO data must be re-loaded to the BBX2s before auditing. Click on the
BBX(s) and select Device>Download BLO
Re-try the audit.
Verify GPIB adapter is not locked up. Under normal conditions, only 2 green LEDs must be
‘ON’ (Power and Ready). If any other LED is continuously ‘ON’, power-cycle (turn power off
and on) the GP-IB Box and retry.
Forward link problem
If the BTS passes the reduced ATP tests but has a forward link problem
during normal operation follow the procedure in Table 6-10 to
troubleshoot.
Table 6-10: Troubleshooting Forward Link Failure (BTS Passed Reduced ATP)
 Step
6-6
Action
Perform these additional TX tests to troubleshoot a forward link problem:
- TX mask
- TX rho
- TX code domain
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Cannot Perform Txmask Measurement
Follow the procedure in Table 6-11 to troubleshoot a TX Mask
Measurement failure.
Table 6-11: Troubleshooting TX Mask Measurement Failure
Step
Action
Verify that TX audit passes for the BBX(s).
If performing manual measurement, verify analyzer setup.
Verify that no LPA in the sector is in alarm state (flashing red LED). Re-set the LPA by pulling
the circuit breaker, and, after 5 seconds, pushing it back in.
Cannot Perform Rho or Pilot Time Offset Measurement
Follow the procedure in Table 6-12 to troubleshoot a rhoand pilot time
offset measurement failure.
Table 6-12: Troubleshooting Rho and Pilot Time Offset Measurement Failure
Step
Action
Verify presence of RF signal by switching to spectrum analyzer screen.
Verify PN offsets displayed on the analyzer is the same as the PN offset in the CDF file.
Re-load MGLI3 data and repeat the test.
If performing manual measurement, verify analyzer setup.
Verify that no LPA in the sector is in alarm state (flashing red LED). Reset the LPA by pulling
the circuit breaker, and, after 5 seconds, pushing back in.
If Rho value is unstable and varies considerably (e.g. .95,.92,.93), this may indicate that the
GPS is still phasing (i.e. trying to reach and maintain 0 freq. error). Go to the freq. bar in the
upper right corner of the Rho meter and select Hz. Press  and enter 10, to obtain an
average Rho value. This is an indication the GPS has not stabilized before going INS and may
need to be re-initialized.
Cannot Perform Code Domain Power and Noise Floor Measurement
Follow the procedure in Table 6-13 to troubleshoot code domain and
noise floor measurement failure.
Table 6-13: Troubleshooting Code Domain Power and Noise Floor Measurement Failure
Step
Aug 2002
Action
Verify presence of RF signal by switching to spectrum analyzer screen.
Verify PN offset displayed on analyzer is same as PN offset being used in the CDF file.
Disable and re-enable MCC (one or more MCCs based on extent of failure).
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Cannot Perform Carrier Measurement
Follow the procedure in Table 6-14 to troubleshoot carrier measurement
failure.
Table 6-14: Troubleshooting Carrier Measurement Failure
Step
Action
Perform the test manually, using the spread CDMA signal. Verify High Stability 10 MHz
Rubidium Standard is warmed up (60 minutes) and properly connected to test set-up.
Multi-FER Test Failure
Follow the procedure in Table 6-15 to troubleshoot multi-FER failure.
Table 6-15: Troubleshooting Multi-FER Failure
 Step
Action
Verify test equipment set up is correct for a FER test.
Verify test equipment is locked to 19.6608 and even second clocks. The yellow
LED (REF UNLOCK) must be OFF.
Verify MCCs have been loaded with data and are INS-ACT.
Disable and re-enable the MCC (one or more based on extent of failure).
Disable, re-load code and data, and re-enable MCC (one or more MCCs based on
extent of failure).
Verify antenna connections to frame are correct based on the directions messages.
Problem Description
Many of the Clock Synchronization Manager (CSM) boards may be
resolved in the field before sending the boards to the factory for repair.
This section describes known CSM problems identified in field returns,
some of which are field-repairable. Check these problems before
returning suspect CSM boards.
Intermittent 19.6608 MHz Reference Clock/GPS Receiver Operation
If having any problems with CSM board kit numbers, SGLN1145 or
SGLN4132, check the suffix with the kit number. If the kit has version
“AB,” then replace with version ‘‘BC’’ or higher, and return model AB
to the repair center.
No GPS Reference Source
Check the CSM boards for proper hardware configuration. RF-GPS
(Local GPS) - CSM kit SGLN1145, which should be installed in Slot l,
has an on-board GPS receiver; while kit SGLN4132, in Slot 2, does not
have a GPS receiver.
Remote GPS (R-GPS) - Kit SGLN4132ED or later, which should be
installed in both Slot 1 and Slot 2, does not have a GPS receiver. Any
incorrectly configured board must be returned to the repair center. Do not
attempt to change hardware configuration in the field. Also, verify the
GPS antenna is not damaged and is installed per recommended
guidelines.
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Checksum Failure
The CSM could have corrupted data in its firmware resulting in a
non-executable code. The problem is usually caused by either electrical
disturbance, or interruption of data during a download. Attempt another
download with no interruptions in the data transfer. Return CSM board
back to repair center if the attempt to reload fails.
GPS Bad RX Message Type
This is believed to be caused by a later version of CSM software (3.5 or
higher) being downloaded, via LMF, followed by an earlier version of
CSM software (3.4 or lower), being downloaded from the CBSC.
Download again with CSM software code 3.5 or higher. Return CSM
board back to repair center if attempt to reload fails.
CSM Reference Source Configuration Error
This is caused by incorrect reference source configuration performed in
the field by software download. CSM kit SGLN1145 and SGLN4132
must have proper reference sources configured (as shown below) to
function correctly.
CSM Kit No.
SGLN1145
SGLN4132ED
or later
Hardware Configuration
CSM Slot No.
Reference Source Configuration
With GPS Receiver
Primary = Local GPS
Backup = Either LFR or HSO
Without GPS Receiver
Primary = Remote GPS
Backup = Either LFR or HSO
Takes Too Long for CSM to Come INS
This may be caused by a delay in GPS acquisition. Check the accuracy
flag status and/or current position. Refer to the GSM system time/GPS
and LFR/HSO verification section in Chapter 3. At least 1 satellite
should be visible and tracked for the “surveyed” mode and 4 satellites
should be visible and tracked for the “estimated” mode. Also, verify
correct base site position data used in “surveyed” mode.
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C-CCP Backplane
The C-CCP backplane is a multi-layer board that interconnects all the
C-CCP modules. The complexity of this board lends itself to possible
improper diagnoses when problems occur.
Connector Functionality
The following connector overview describes the major types of
backplane connectors along with the functionality of each. This will
allow the Cellular Field Engineer (CFE) to:
 Determine which connector(s) is associated with a specific problem
type.
 Allow the isolation of problems to a specific cable or connector.
Primary “A” and Redundant “B” ISB (Inter Shelf Bus)
connectors
The 40 pin ISB connectors provide an interface bus from the master
GLI3 to all other GLI3s in the modem frame. Its basic function is to
provide clock synchronization from the master GLI3 to all other GLI3s
in the frame.
The ISB is also provides the following functions:
 Groom span line when a single span is used for multiple cages.
 Provide MMI connection to/from the master GLI3 to cell site modem.
 Provide interface between GLI3s and the AMR (for reporting BTS
alarms).
Span Line Connector
The span line input is an 8 pin RJ-45 connector that provides a primary
and secondary (if used) span line interface to each GLI3 in the C-CCP
shelf. The span line is used for MM/EMX switch control of the Master
GLI3 and also all the BBX traffic.
Power Input (Return A, B, and C connectors)
Provides a +27 Volt input for use by the power supply modules.
Power Supply Module Interface
Each power supply module has a series of three different connectors to
provide the needed inputs/outputs to the C-CCP backplane. These
include a VCC/Ground input connector, a Harting style multiple pin
interface, and a +15 V/Analog Ground output connector. The Transceiver
Power Module converts 27/48 Volts to a regulated +15, +6.5, +5.0 Volts
to be used by the C-CCP shelf cards.
GLI3 Connector
This connector consists of a Harting 4SU digital connector and a
6-conductor coaxial connector for RDM distribution. The connectors
provide inputs/outputs for the GLI3s in the C-CCP backplane.
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GLI3 Ethernet “A” and “B” Connections
These BNC connectors are located on the C-CCP backplane and routed
to the GLI3 board. This interface provides all the control and data
communications between the master GLI3 and the other GLI3, between
gateways, and for the LMF on the LAN.
BBX2 Connector
Each BBX connector consists of a Harting 2SU/1SU digital connector
and two 6-conductor coaxial connectors. These connectors provide DC,
digital, and RF inputs/outputs for the BBXs in the C-CCP backplane.
CIO Connectors
 RX RF antenna path signal inputs are routed through RX Tri-Filters
(on the I/O plate), and via coaxial cables to the two MPC modules the six “A” (main) signals go to one MPC; the six “B” (diversity) to
the other. The MPC outputs the low-noise-amplified signals via the
C-CCP backplane to the CIO where the signals are split and sent to
the appropriate BBX.
 A digital bus then routes the baseband signal through the BBX, to the
backplane, then on to the MCC slots.
 Digital TX antenna path signals originate at the MCC24s. Each
output is routed from the MCC slot via the backplane appropriate
BBX.
 TX RF path signal originates from the BBX, through the backplane to
the CIO, through the CIO, and via multi-conductor coaxial cabling to
the LPAs in the LPA shelf.
C-CCP Backplane Troubleshooting Procedure
The following table provides a standard procedure for troubleshooting
problems that appear to be related to a defective C-CCP backplane. The
table is broken down into possible problems and steps which should be
taken in an attempt to find the root cause.
NOTE
It is important to note that all steps be followed before replacing
ANY C-CCP backplane.
Digital Control Problems
No GLI3 Control via LMF (all GLI3s)
Follow the procedure in Table 6-16 for problems with GLI3 control.
Table 6-16: No GLI3 Control via LMF (all GLI3s)
Step
Action
Check the ethernet for proper connection, damage, shorts, or opens.
Verify C-CCP backplane Shelf ID DIP switch is set correctly.
Visually check the master GLI3 connector (both board and backplane) for damage.
Replace the master GLI3 with a known good GLI3.
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No GLI3 Control through Span Line Connection (All
GLI3s)
Follow the procedure in Table 6-17 for problems with GLI3 control.
Table 6-17: No GLI3 Control through Span Line Connection (Both GLI3s)
Step
Action
Verify C-CCP backplane Shelf ID DIP switch is set correctly.
Verify that the BTS and GLI3s are correctly configured in the OMCR/CBSC data base.
Visually check the master GLI3 connector (both board and backplane) for damage.
Replace the master GLI3 with a known good GLI3.
Check the span line inputs from the top of the frame to the master GLI3 for proper connection and
damage.
MGLI3 Control Good - No Control over Co-located GLI3
Follow the procedure in Table 6-18 for problems with GLI3 control.
Table 6-18: MGLI3 Control Good - No Control over Co-located GLI3
Step
Action
Verify that the BTS and GLI3s are correctly configured in the OMCR CBSC data base.
Check the ethernet for proper connection, damage, shorts, or opens.
Visually check all GLI3 connectors (both board and backplane) for damage.
Replace the remaining GLI3 with a known good GLI3.
No AMR Control (MGLI3 good)
Follow the procedure in Table 6-19 for problems with AMR control.
Table 6-19: MGLI3 Control Good - No Control over AMR
Step
Action
Visually check the master GLI3 connector (both board and backplane) for damage.
Replace the master GLI3 with a known good GLI3.
Replace the AMR with a known good AMR.
No BBX Control in the Shelf
Follow the procedure in Table 6-20 for problems with co-located GLI3.
Table 6-20: MGLI3 Control Good - No Control over Co-located GLI3s
Step
6-12
Action
Visually check all GLI3 connectors (both board and backplane) for damage.
Replace the remaining GLI3 with a known good GLI3.
Visually check BBX connectors (both board and backplane) for damage.
Replace the BBX with a known good BBX.
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No (or Missing) Span Line Traffic
Follow the procedure in Table 6-21 for problems with span line traffic.
Table 6-21: BBX Control Good - No (or Missing) Span Line Traffic
Step
Action
Visually check all GLI3 connectors (both board and backplane) for damage.
Replace the remaining GLI3 with a known good GLI3.
Visually check all span line distribution (both connectors and cables) for damage.
If the problem seems to be limited to 1 BBX, replace the BBX with a known good BBX.
No (or Missing) MCC24 Channel Elements
Follow the procedure in Table 6-22 for problems with channel elements.
Table 6-22: No MCC-1X/MCC24E/MCC8E Channel Elements
Step
Action
Verify channel elements on a co-located MCC of the same
MCC8E = 0; MCC24E = 2; MCC-1X = 3)
type (CDF MccType codes:
Check MCC connectors (both module and backplane) for damage.
If the problem seems to be limited to one MCC, replace it with a known good MCC of the same
type.
If no channel elements on any MCC, verify clock reference to CIO.
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DC Power Problems
WARNING
Potentially lethal voltage and current levels are routed to the
BTS equipment. This test must be carried out with a second
person present, acting in a safety role. Remove all rings, jewelry,
and wrist watches prior to beginning this test.
No DC Input Voltage to Power Supply Module
Follow the procedure in Table 6-23 for problems with DC input voltage.
Table 6-23: No DC Input Voltage to Power Supply Module
Step
Action
Verify DC power is applied to the BTS frame. Verify there are no breakers tripped.
* IMPORTANT
If a breaker has tripped, remove all modules from the applicable shelf supplied by the breaker and
attempt to reset it.
- If breaker trips again, there is probably a cable or breaker problem within the frame.
- If breaker does not trip, there is probably a defective module or sub-assembly within the
shelf.
Verify that the C-CCP shelf breaker on the BTS frame breaker panel is functional.
Use a voltmeter to determine if the input voltage is being routed to the C-CCP backplane by
measuring the DC voltage level on the PWR_IN cable.
- If the voltage is not present, there is probably a cable or breaker problem within the frame.
- If the voltage is present at the connector, reconnect and measure the level at the “VCC” power
feed clip on the distribution backplane. If the voltage is correct at the power clip, inspect the
clip for damage.
If everything appears to be correct, visually inspect the power supply module connectors.
Replace the power supply module with a known good module.
If steps 1 through 4 fail to indicate a problem, the C-CCP backplane failure (possibly an open
trace) has occurred.
No DC Voltage (+5, +6.5, or +15 Volts) to a Specific GLI3,
BBX2, or Switchboard
Follow the procedure in Table 6-24 for problems with DC input voltage.
Table 6-24: No DC Input Voltage to any C-CCP Shelf Module
Step
Action
Verify steps outlined in Table 6-23 have been performed.
Inspect the defective board/module (both board and backplane) connector for damage.
Replace suspect board/module with known good board/module.
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Follow the procedure in Table 6-25 for problems with DC input voltage.
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Table 6-25: No DC Input Voltage to any C-CCP Shelf Module
Step
Action
Inspect all Harting Cable connectors and back-plane connectors for damage in all the affected
board slots.
Perform steps outlined in the RF path troubleshooting flowchart in this manual.
RFDS
The RFDS is used to perform Pre-Calibration Verification and
Post-Calibration Audits which limit-check the RFDS-generate and
reported receive levels of every path from the RFDS through the
directional coupler coupled paths. In the event of test failure, refer to the
following tables.
All tests fail
Follow the procedure in Table 6-26 for problems with RFDS.
Table 6-26: RFDS Fault Isolation - All tests fail
Step
Action
Check the calibration equipment for proper operation by manually setting the signal generator output
attenuator to the lowest output power setting and connecting the output port to the spectrum analyzer
rf input port.
Set the signal generator output attenuator to -90 dBm, and switch on the rf output. Verify that the
spectrum analyzer can receive the signal, indicate the correct signal strength, (accounting for the cable
insertion loss), and the approximate frequency.
Visually inspect RF cabling. Make sure each directional coupler forward and reflected port connects to
the RFDS antenna select unit on the RFDS.
Check the wiring against the site documentation wiring diagram or the BTS Site Installation manual.
Verify RGLI and TSU have been downloaded.
Check to see that all RFDS boards show green on the front panel indicators. Visually check (both
board and backplane) for damage.
Replace any boards that do not show green with known good boards one at a time in the following
order. Re-test after each is replaced.
- RFDS ASU board.
- RFDS Transceiver board.
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68P09255A57-2
All RX and TX paths fail
If every receive or transmit path fails, the problem most likely lies with
the rf converter board or the transceiver board. Refer to Table 6-27 for
fault isolation procedures.
Table 6-27: RFDS Fault Isolation - All RX and TX paths fail
Step
Action
Visually check the master RF converter board (both board and backplane) for damage.
Replace the RF converter board with a known good RF converter board.
Visually check RXCVR TSU (both board and backplane) for damage.
Replace the TSU with a known good TSU.
All tests fail on a single antenna
If all path failures are on one antenna port, forward and/or reflected,
follow the procedures in Table 6-28 checks.
Table 6-28: RFDS Fault Isolation - All tests fail on single antenna path
Step
Action
Visually inspect the site interface cabinet internal cabling to the suspect directional coupler antenna
port.
Verify the forward and reflected ports connect to the correct RFDS antenna select unit positions on the
RFDS backplane. Refer to the installation manual for details.
Visually check ASU connectors (both board and backplane) for damage.
Replace the ASU with a known good ASU.
Replace the RF cables between the affected directional coupler and RFDS.
NOTE
Externally route the cable to bypass suspect segment.
Module Status Indicators
Each of the non-passive plug-in modules has a bi-color (green & red)
LED status indicator located on the module front panel. The indicator is
labeled PWR/ALM. If both colors are turned on, the indicator is yellow.
Each plug-in module, except for the fan module, has its own alarm
(fault) detection circuitry that controls the state of the PWR/ALM LED.
The fan TACH signal of each fan module is monitored by the AMR.
Based on the status of this signal the AMR controls the state of the
PWR/ALM LED on the fan module.
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Troubleshooting
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LED Status Combs All Modules (except GLI3, CSM, BBX2, MCC8/24E)
PWR/ALM LED
The following list describes the states of the module status indicator.
 Solid GREEN - module operating in a normal (fault free) condition.
 Solid RED - module is operating in a fault (alarm) condition due to
electrical hardware failure.
Note that a fault (alarm) indication may or may not be due to a complete
module failure and normal service may or may not be reduced or
interrupted.
DC/DC Converter LED Status Combinations
The PWR CNVTR has its own alarm (fault) detection circuitry that
controls the state of the PWR/ALM LED.
PWR/ALM LED
The following list describes the states of the bi-color LED.
 Solid GREEN - module operating in a normal (fault free) condition.
 Solid RED - module is operating in a fault (alarm) condition due to
electrical hardware problem.
CSM LED Status Combinations
PWR/ALM LED
The CSMs include on-board alarm detection. Hardware and
software/firmware alarms are indicated via the front panel indicators.
After the memory tests, the CSM loads OOS-RAM code from the Flash
EPROM, if available. If not available, the OOS-ROM code is loaded
from the Flash EPROM.
 Solid GREEN - module is INS_ACT or INS_STBY no alarm.
 Solid RED - Initial power up or module is operating in a fault (alarm)
condition.
 Slowly Flashing GREEN - OOS_ROM no alarm.
 Long RED/Short GREEN - OOS_ROM alarm.
 Rapidly Flashing GREEN - OOS_RAM no alarm or
INS_ACT in DUMB mode.
Aug 2002
Short RED/Short GREEN - OOS_RAM alarm.
Long GREEN/Short RED - INS_ACT or INS_STBY alarm.
Off - no DC power or on-board fuse is open.
Solid YELLOW - After a reset, the CSMs begin to boot. During
SRAM test and Flash EPROM code check, the LED is yellow. (If
SRAM or Flash EPROM fail, the LED changes to a solid RED and
the CSM attempts to reboot.)
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Figure 6-1: CSM Front Panel Indicators & Monitor Ports
SYNC
MONITOR
PWR/ALM
Indicator
FREQ
MONITOR
FW00303
. . . continued on next page
FREQ Monitor Connector
A test port provided at the CSM front panel via a BNC receptacle allows
monitoring of the 19.6608 MHz clock generated by the CSM. When
both CSM 1 and CSM 2 are in an in-service (INS) condition, the CSM 2
clock signal frequency is the same as that output by CSM 1.
The clock is a sine wave signal with a minimum amplitude of +2 dBm
(800 mVpp) into a 50 Ω load connected to this port.
SYNC Monitor Connector
A test port provided at the CSM front panel via a BNC receptacle allows
monitoring of the “Even Second Tick” reference signal generated by the
CSMs.
At this port, the reference signal is a TTL active high signal with a pulse
width of 153 nanoseconds.
MMI Connector - Only accessible behind front panel. The
RS-232 MMI port connector is intended to be used primarily in
the development or factory environment, but may be used in the
field for debug/maintenance purposes.
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GLI3 LED Status Combinations
The GLI3 module has indicators, controls and connectors as described
below and shown in Figure 6-2.
The indicators and controls consist of:
 Four LEDs
 One pushbutton
ACTIVE LED
Solid GREEN - GLI3 is active. This means that the GLI3 has shelf
control and is providing control of the digital interfaces.
Off - GLI3 is not active (i.e., Standby). The mate GLI3 should be
active.
MASTER LED
 Solid GREEN - GLI3 is Master (sometimes referred to as MGLI3).
 Off - GLI3 is non-master (i.e., Slave).
ALARM LED
 Solid RED - GLI3 is in a fault condition or in reset.
 While in reset transition, STATUS LED is OFF while GLI3 is
performing ROM boot (about 12 seconds for normal boot).
 While in reset transition, STATUS LED is ON while GLI3 is
performing RAM boot (about 4 seconds for normal boot).
 Off - No Alarm.
STATUS LED
 Flashing GREEN- GLI3 is in service (INS), in a stable operating
condition.
 On - GLI3 is in OOS RAM state operating downloaded code.
 Off - GLI3 is in OOS ROM state operating boot code.
SPANS LED
 Solid GREEN - Span line is connected and operating.
 Solid RED - Span line is disconnected or a fault condition exists.
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GLI3 Pushbuttons and Connectors
RESET Pushbutton - Depressing the RESET pushbutton
causes a partial reset of the CPU and a reset of all board devices.
GLI3 will be placed in the OOS_ROM state
MMI Connector - The RS-232MMI port connector is intended
to be used primarily in the development or factory environment
but may be used in the field for debug/maintenance purposes.
Figure 6-2: GLI3 Front Panel Operating Indicators
LED
OPERATING STATUS
Pressing and releasing the switch resets all functions on the GLI3.
ALARM
OFF − operating normally
ON − briefly during power−up when the Alarm LED turns OFF
SLOW GREEN − when the GLI3 is INS (in−service)
Span
OFF − card is powered down, in initialization, or in standby
GREEN − operating normally
YELLOW − one or more of the equipped initialized spans is receiving
a remote alarm indication signal from the far end
RED − one or more of the equipped initialized spans is in an alarm
state
An RS−232, serial, asynchronous communications link for use as
an MMI port. This port supports 300 baud, up to a maximum of
115,200 baud communications.
MMI
STATUS
OFF − operating normally
ON − briefly during power−up when the Alarm LED turns OFF
SLOW GREEN − when the GLI3 is INS (in−service)
ACTIVE
Shows the operating status of the redundant cards. The redundant
card toggles automatically if the active card is removed or fails
ON − active card operating normally
OFF − standby card operating normally
6-20
100BASE-T to
BTS Packet Router
or Expansion cage
100BASE-T
Auxiliary Monitor
Port
Dual 100BASE-T
in a single RJ45
to Redundant
(Mate) GLI3
Reset Switch
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Span (LED)
Alarm (LED)
MMI Port
ACT
RESET
STA
Supports the cross−coupled ethernet circuits to the mate GLI using a
standard ethernet straight cable.
SPAN
GLI
MMI
Wired as an ethernet hub for direct connection to a personal comput−
er with a standard ethernet cable. It allows connection of ethernet
7sniffer" when the ethernet switch is properly configured for port mon−
itoring.
ALARM
RESET
AUX
GLI
Connects to either a BPR or expansion cage and is wired as an
ethernet hub.
AUX
BPR B
BPR B
Connects to either a BPR or expansion cage and is wired as an
ethernet hub.
BPR A
BPR A
Active (LED)
Status (LED)
ti-CDMA-WP-00064-v01-ildoc-ftw
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Troubleshooting
68P09255A57-2
BBX LED Status Combinations
PWR/ALM LED
The BBX module has its own alarm (fault) detection circuitry that
controls the state of the PWR/ALM LED.
The following list describes the states of the bi-color LED:
Solid GREEN - INS_ACT no alarm
Solid RED Red - initializing or power-up alarm
Slowly Flashing GREEN - OOS_ROM no alarm
Long RED/Short GREEN - OOS_ROM alarm
Rapidly Flashing GREEN - OOS_RAM no alarm
Short RED/Short GREEN - OOS_RAM alarm
Long GREEN/Short RED - INS_ACT alarm
MCC LED Status Combinations
The MCC module has LED indicators and connectors as described
below. See Figure 6-3. Note that the figure does not show the connectors
as they are concealed by the removable lens.
The LED indicators and their states are as follows:
PWR/ALM LED
 RED - fault on module
ACTIVE LED
 Off - module is inactive, off-line, or not processing traffic.
 Slowly Flashing GREEN - OOS_ROM no alarm.
 Rapidly Flashing Green - OOS_RAM no alarm.
 Solid GREEN - module is INS_ACT, on-line, processing traffic.
PWR/ALM and ACTIVE LEDs
 Solid RED - module is powered but is in reset or the BCP is inactive.
MMI Connectors
 The RS-232 MMI port connector (four-pin) is intended to be used
primarily in the development or factory environment but may be used
in the field for debugging purposes.
 The RJ-11 ethernet port connector (eight-pin) is intended to be used
primarily in the development environment but may be used in the field
for high data rate debugging purposes.
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Figure 6-3: MCC24/8E Front Panel LEDs and LED Indicators
PWR/ALM
PWR/ALM LED
LED
COLOR
OFF − operating normally
ON − briefly during power−up and during failure
=conditions
An alarm is generated in the event of a failure
PWR/ALM
LENS
(REMOVABLE)
ACTIVE
RED
GREEN
RED
ACTIVE
ACTIVE LED
OPERATING STATUS
RAPIDLY BLINKING − Card is code−loaded but
=not enabled
SLOW BLINKING − Card is not code−loaded
ON − card is code−loaded and enabled
=(INS_ACTIVE)
ON − fault condition
SLOW FLASHING (alternating with green) − CHI
=bus inactive on power−up
FW00224
LPA Shelf LED Status Combinations
LPA Module LED
Each LPA module contains a bi-color LED just above the MMI
connector on the ETIB module. Interpret this LED as follows:
 GREEN — LPA module is active and is reporting no alarms (Normal
condition).
 Flashing GREEN/RED — LPA module is active but is reporting an
low input power condition. If no BBX is keyed, this is normal and
does not constitute a failure.
 Flashing RED — LPA is in alarm.
Span Problems
(No Control Link)
Follow the procedure in Table 6-29 when troubleshooting a control link
failure.
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Table 6-29: Troubleshooting Control Link Failure
Step
Action
Verify the span settings using the span view command on the active master GLI3 MMI
port. If these are set correctly, verify the edlc parameters using the show command. Any
alarms conditions indicate that the span is not operating correctly.
- Try looping back the span line from the DSX panel back to the mobility manager
(MM) and verify that the looped signal is good.
- Listen for control tone on appropriate timeslot from base site and MM.
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Troubleshooting
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Notes
6-24
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A
Appendix A
System Data
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Site Operation Verification
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Site Operation Verification
Verification of Test Equipment Used
Table A-1: Verification of Test Equipment Used
Manufacturer
Model
Serial Number
Comments:________________________________________________________
__________________________________________________________________
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Site Checklist
Table A-2: Site Checklist
OK
Parameter
Specification
Deliveries
Per established procedures
Floor Plan
Verified
Inter Frame Cables:
Ethernet
Frame Ground
Power
Per procedure
Per procedure
Per procedure
Factory Data:
BBX
Test Panel
RFDS
Per procedure
Per procedure
Per procedure
Site Temperature
Dress Covers/Brackets
Aug 2002
Comments
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Site Operation Verification
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Preliminary Operations
Table A-3: Preliminary Operations
OK
Parameter
Specification
Shelf ID Dip Switches
Per site equipage
Ethernet LAN verification
Verified per procedure
Comments
Comments:_________________________________________________________
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Pre-Power and Initial Power Tests
Table A3a: Pre-power Checklist
OK
Parameter
Pre-power-up tests
Specification
Verify power supply
output voltage at the top
of each BTS frame is
within specifications
Internal Cables:
ISB (all cages)
CSM (all cages)
Power (all cages)
Ethernet Connectors
LAN A ohms
LAN B ohms
LAN A shield
LAN B shield
Ethernet Boots
Air Impedance Cage (single cage)
installed
Initial power-up tests
Verify power supply
output voltage at the top
of each BTS frame is
within specifications:
Comments
verified
verified
verified
verified
verified
isolated
isolated
installed
Comments:_________________________________________________________
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Site Operation Verification
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General Optimization Checklist
Table A3b: Pre-power Checklist
OK
Parameter
Specification
LEDs
Frame fans
illuminated
operational
LMF to BTS Connection
Preparing the LMF
Log into the LMF PC
Create site specific BTS directory
Download device loads
per procedure
per procedure
per procedure
per procedure
Ping LAN A
Ping LAN B
per procedure
per procedure
Download/Enable MGLI3s
Download/Enable GLI3s
Set Site Span Configuration
Download CSMs
Enable CSMs
Enable CSMs
Download/Enable MCCs*
Download BBXs*
Download TSU (in RFDS)
Program TSU NAM
per procedure
per procedure
per procedure
per procedure
per procedure
per procedure
per procedure
per procedure
per procedure
Test Set Calibration
per procedure
Comments
*MCCs may be MCC8Es, MCC24s or MCC-1Xs. BBXs may be BBXs or BBX-1Xs
Comments:_________________________________________________________
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GPS Receiver Operation
Table A-4: GPS Receiver Operation
OK
Parameter
Specification
GPS Receiver Control Task State:
tracking satellites
Verify parameter
Initial Position Accuracy:
Verify Estimated
or Surveyed
Current Position:
lat
lon
height
RECORD in
msec and cm also
convert to deg
min sec
Current Position: satellites tracked
Estimated:
(>4) satellites tracked,(>4) satellites visible
Surveyed:
(>1) satellite tracked,(>4) satellites visible
Verify parameter
as appropriate:
GPS Receiver Status:Current Dilution of
Precision
(PDOP or HDOP): (<30)
Verify parameter
Current reference source:
Number: 0; Status: Good; Valid: Yes
Verify parameter
Comments
Comments:_________________________________________________________
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LFR Receiver Operation
Table A-5: LFR Receiver Operation
OK
Parameter
Specification
Station call letters M X Y Z
assignment.
SN ratio is > 8 dB
LFR Task State: 1fr
locked to station xxxx
Verify parameter
Current reference source:
Number: 1; Status: Good; Valid: Yes
Verify parameter
Comments
as specified in site
documentation
Comments:_________________________________________________________
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LPA IM Reduction
Table A-6: LPA IM Reduction
Parameter
OK
Comments
CARRIER
LPA
Specification
4:1 & 2:1
3-Sector
2:1
6-Sector
Dual BP
3-Sector
Dual BP
6-Sector
1A
C1
C1
C1
C1
No Alarms
1B
C1
C1
C1
C1
No Alarms
1C
C1
C1
C1
C1
No Alarms
1D
C1
C1
C1
C1
No Alarms
2A
C2
C2
C2
No Alarms
2B
C2
C2
C2
No Alarms
2C
C2
C2
C2
No Alarms
2D
C2
C2
C2
No Alarms
3A
C3
C1
C1
No Alarms
3B
C3
C1
C1
No Alarms
3C
C3
C1
C1
No Alarms
3D
C3
C1
C1
No Alarms
4A
C4
C2
No Alarms
4B
C4
C2
No Alarms
4C
C4
C2
No Alarms
4D
C4
C2
No Alarms
Comments:_________________________________________________________
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TX Bay Level Offset / Power Output Verification for 3-Sector Configurations
1-Carrier
2-Carrier Non-adjacent Channels
4-Carrier Non-adjacent Channels
Table A-7: TX BLO Calibration (3-Sector: 1-Carrier, 2-Carrier and 4-Carrier Non-adjacent Channels)
OK
Parameter
Specification
Comments
BBX-1, ANT-1 =
BBX-r , ANT-1 =
dB
dB
BBX-2, ANT-2 =
BBX-r , ANT-2 =
dB
dB
BBX-3, ANT-3 =
BBX-r , ANT-3 =
dB
dB
BBX-7, ANT-1 =
BBX-r , ANT-1 =
dB
dB
BBX-8, ANT-2 =
BBX-r , ANT-2 =
dB
dB
BBX-9, ANT-3 =
BBX-r , ANT-3 =
dB
dB
BBX-4, ANT-1 =
BBX-r , ANT-1 =
dB
dB
BBX-5, ANT-2 =
BBX-r , ANT-2 =
dB
dB
BBX-6, ANT-3 =
BBX-r , ANT-3 =
dB
dB
BBX-10, ANT-1 =
BBX-r , ANT-1 =
dB
dB
BBX-1 1, ANT-2 =
BBX-r , ANT-2 =
dB
dB
BBX-12, ANT-3 =
BBX-r , ANT-3 =
dB
dB
BBX-1, ANT-1 =
BBX-r , ANT-1 =
dB
dB
BBX-2, ANT-2 =
BBX-r , ANT-2 =
dB
dB
BBX-3, ANT-3 =
BBX-r , ANT-3 =
dB
dB
Calibrate
carrier 1
Calibrate
carrier 2
Calibrate
carrier 3
Calibrate
carrier 4
Calibration
Audit
carrier 1
TX Bay Level Offset = 37 dB (+4 dB)
prior to calibration
TX Bay Level Offset = 37 dB (+4 dB)
prior to calibration
TX Bay Level Offset = 37 dB (+4 dB)
prior to calibration
TX Bay Level Offset = 37 dB (+4 dB)
prior to calibration
0 dB (+0.5 dB) for gain set resolution
post calibration
. . . continued on next page
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Table A-7: TX BLO Calibration (3-Sector: 1-Carrier, 2-Carrier and 4-Carrier Non-adjacent Channels)
OK
Parameter
Specification
Comments
BBX-7, ANT-1 =
BBX-r , ANT-1 =
dB
dB
BBX-8, ANT-2 =
BBX-r , ANT-2 =
dB
dB
BBX-9, ANT-3 =
BBX-r , ANT-3 =
dB
dB
BBX-4, ANT-1 =
BBX-r , ANT-1 =
dB
dB
BBX-5, ANT-2 =
BBX-r , ANT-2 =
dB
dB
BBX-6, ANT-3 =
BBX-r , ANT-3 =
dB
dB
BBX-10, ANT-1 =
BBX-r , ANT-1 =
dB
dB
BBX-1 1, ANT-2 =
BBX-r , ANT-2 =
dB
dB
BBX-12, ANT-3 =
BBX-r , ANT-3 =
dB
dB
Calibration
Audit
carrier 2
Calibration
Audit
carrier 3
Calibration
Audit
carrier 4
0 dB (+0.5 dB) for gain set resolution
post calibration
0 dB (+0.5 dB) for gain set resolution
post calibration
0 dB (+0.5 dB) for gain set resolution
post calibration
Comments:________________________________________________________
__________________________________________________________________
2-Carrier Adjacent Channel
Table A-8: TX Bay Level Offset Calibration (3-Sector: 2-Carrier Adjacent Channels)
OK
Parameter
Specification
Calibrate
carrier 1
TX Bay Level Offset = 42 dB (typical),
38 dB (minimum) prior to calibration
Comments
BBX-1, ANT-1 =
BBX-r , ANT-1 =
dB
dB
BBX-2, ANT-2 =
BBX-r , ANT-2 =
dB
dB
BBX-3, ANT-3 =
BBX-r , ANT-3 =
dB
dB
. . . continued on next page
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Table A-8: TX Bay Level Offset Calibration (3-Sector: 2-Carrier Adjacent Channels)
OK
Parameter
Specification
Comments
BBX-7, ANT-4 =
BBX-r , ANT-4 =
dB
dB
BBX-8, ANT-5 =
BBX-r , ANT-5 =
dB
dB
BBX-9, ANT-6 =
BBX-r , ANT-6 =
dB
dB
BBX-1, ANT-1 =
BBX-r , ANT-1 =
dB
dB
BBX-2, ANT-2 =
BBX-r , ANT-2 =
dB
dB
BBX-3, ANT-3 =
BBX-r , ANT-3 =
dB
dB
BBX-7, ANT-4 =
BBX-r , ANT-4 =
dB
dB
BBX-8, ANT-5 =
BBX-r , ANT-5 =
dB
dB
BBX-9, ANT-6 =
BBX-r , ANT-6 =
dB
dB
Calibrate
carrier 2
Calibration
Audit
carrier 1
Calibration
Audit
carrier 2
TX Bay Level Offset = 42 dB (typical),
38 dB (minimum) prior to calibration
0 dB (+0.5 dB) for gain set resolution
post calibration
0 dB (+0.5 dB) for gain set resolution
post calibration
Comments:________________________________________________________
__________________________________________________________________
3-Carrier Adjacent Channels
4-Carrier Adjacent Channels
Table A-9: TX Bay Level Offset Calibration (3-Sector: 3 or 4-Carrier Adjacent Channels)
OK
Parameter
Specification
Calibrate
carrier 1
TX Bay Level Offset = 37 dB before
calibration
Comments
BBX-1, ANT-1 =
BBX-r , ANT-1 =
dB
dB
BBX-2, ANT-2 =
BBX-r , ANT-2 =
dB
dB
BBX-3, ANT-3 =
BBX-r , ANT-3 =
dB
dB
. . . continued on next page
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Table A-9: TX Bay Level Offset Calibration (3-Sector: 3 or 4-Carrier Adjacent Channels)
OK
Parameter
Specification
Comments
BBX-7, ANT-1 =
BBX-r , ANT-1 =
dB
dB
BBX-8, ANT-2 =
BBX-r , ANT-2 =
dB
dB
BBX-9, ANT-3 =
BBX-r , ANT-3 =
dB
dB
BBX-4, ANT-4 =
BBX-r , ANT-4 =
dB
dB
BBX-5, ANT-5 =
BBX-r , ANT-5 =
dB
dB
BBX-6, ANT-6 =
BBX-r , ANT-6 =
dB
dB
BBX-10, ANT-4 =
BBX-3, ANT-4 =
dB
dB
BBX-1 1, ANT-5 =
BBX-r , ANT-5 =
dB
dB
BBX-12, ANT-6 =
BBX-r , ANT-6 =
dB
dB
BBX-1, ANT-1 =
BBX-r , ANT-1 =
dB
dB
BBX-2, ANT-2 =
BBX-r , ANT-2 =
dB
dB
BBX-3, ANT-3 =
BBX-r , ANT-3 =
dB
dB
BBX-7, ANT-1 =
BBX-r , ANT-1 =
dB
dB
BBX-8, ANT-2 =
BBX-r , ANT-2 =
dB
dB
BBX-9, ANT-3 =
BBX-r , ANT-3 =
dB
dB
Calibrate
carrier 2
Calibrate
carrier 3
Calibrate
carrier 4
Calibration
Audit
carrier 1
Calibration
Audit
carrier 2
TX Bay Level Offset =37 dB before
calibration
TX Bay Level Offset = 37 dB before
calibration
TX Bay Level Offset = 37 dB before
calibration
0 dB (+0.5 dB) for gain set resolution
post calibration
0 dB (+0.5 dB) for gain set resolution
post calibration
. . . continued on next page
Aug 2002
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A-13
Site Operation Verification
68P09255A57-2
Table A-9: TX Bay Level Offset Calibration (3-Sector: 3 or 4-Carrier Adjacent Channels)
OK
Parameter
Specification
Comments
BBX-4, ANT-4 =
BBX-r , ANT-4 =
dB
dB
BBX-5, ANT-5 =
BBX-r , ANT-5 =
dB
dB
BBX-6, ANT-6 =
BBX-r , ANT-6 =
dB
dB
BBX-10, ANT-4 =
BBX-r , ANT-4 =
dB
dB
BBX-1 1, ANT-5 =
BBX-r , ANT-5 =
dB
dB
BBX-12, ANT-6 =
BBX-r , ANT-6 =
dB
dB
Calibration
Audit
carrier 3
Calibration
Audit
carrier 4
0 dB (+0.5 dB) for gain set resolution
post calibration
0 dB (+0.5 dB) for gain set resolution
post calibration
Comments:________________________________________________________
__________________________________________________________________
A-14
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Aug 2002
Site Operation Verification
68P09255A57-2
TX Bay Level Offset / Power Output Verification for 6-Sector Configurations
1-Carrier
2-Carrier Non-adjacent Channels
Table A-10: TX BLO Calibration (6-Sector: 1-Carrier, 2-Carrier Non-adjacent Channels)
OK
Parameter
Specification
Comments
BBX-1, ANT-1 =
BBX-r , ANT-1 =
dB
dB
BBX-2, ANT-2 =
BBX-r , ANT-2 =
dB
dB
BBX-3, ANT-3 =
BBX-r , ANT-3 =
dB
dB
BBX-4, ANT-4 =
BBX-r , ANT-4 =
dB
dB
BBX-5, ANT-5 =
BBX-r , ANT-5 =
dB
dB
BBX-6, ANT-6 =
BBX-r , ANT-6 =
dB
dB
BBX-7, ANT-1 =
BBX-r , ANT-1 =
dB
dB
BBX-8, ANT-2 =
BBX-r , ANT-2 =
dB
dB
BBX-9, ANT-3 =
BBX-r , ANT-3 =
dB
dB
BBX-10, ANT-4 =
BBX-3, ANT-4 =
dB
dB
BBX-1 1, ANT-5 =
BBX-r , ANT-5 =
dB
dB
BBX-12, ANT-6 =
BBX-r , ANT-5 =
dB
dB
Calibrate
carrier 1
Calibrate
carrier 2
TX Bay Level Offset = 42 dB (typical),
38 dB (minimum) prior to calibration
TX Bay Level Offset = 42 dB (typical),
38 dB (minimum) prior to calibration
. . . continued on next page
Aug 2002
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A-15
Site Operation Verification
68P09255A57-2
Table A-10: TX BLO Calibration (6-Sector: 1-Carrier, 2-Carrier Non-adjacent Channels)
OK
Parameter
Specification
Comments
BBX-1, ANT-1 =
BBX-r , ANT-1 =
dB
dB
BBX-2, ANT-2 =
BBX-r , ANT-2 =
dB
dB
BBX-3, ANT-3 =
BBX-r , ANT-3 =
dB
dB
BBX-4, ANT-4 =
BBX-r , ANT-4 =
dB
dB
BBX-5, ANT-5 =
BBX-r , ANT-5 =
dB
dB
BBX-6, ANT-6 =
BBX-r , ANT-6 =
dB
dB
BBX-7, ANT-1 =
BBX-r , ANT-1 =
dB
dB
BBX-8, ANT-2 =
BBX-r , ANT-2 =
dB
dB
BBX-9, ANT-3 =
BBX-r , ANT-3 =
dB
dB
BBX-10, ANT-4 =
BBX-r , ANT-4 =
dB
dB
BBX-1 1, ANT-5 =
BBX-r , ANT-5 =
dB
dB
BBX-12, ANT-6 =
BBX-r , ANT-6 =
dB
dB
Calibration
Audit
carrier 1
Calibration
Audit
carrier 2
0 dB (+0.5 dB) for gain set resolution
post calibration
0 dB (+0.5 dB) for gain set resolution
post calibration
Comments:________________________________________________________
__________________________________________________________________
A-16
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Aug 2002
Site Operation Verification
68P09255A57-2
TX Antenna VSWR
Table A-11: TX Antenna VSWR
OK
Parameter
Specification
VSWR Antenna 1
< (1.5 : 1)
VSWR Antenna 2
< (1.5 : 1)
VSWR Antenna 3
< (1.5 : 1)
VSWR Antenna 4
< (1.5 : 1)
VSWR Antenna 5
< (1.5 : 1)
VSWR Antenna 6
< (1.5 : 1)
Data
Comments:________________________________________________________
__________________________________________________________________
RX Antenna VSWR
Table A-12: RX Antenna VSWR
OK
Parameter
Specification
VSWR Antenna 1
< (1.5 : 1)
VSWR Antenna 2
< (1.5 : 1)
VSWR Antenna 3
< (1.5 : 1)
VSWR Antenna 4
< (1.5 : 1)
VSWR Antenna 5
< (1.5 : 1)
VSWR Antenna 6
< (1.5 : 1)
Data
Comments:_________________________________________________________
Aug 2002
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A-17
Site Operation Verification
68P09255A57-2
Alarm Verification
Table A-13: CDI Alarm Input Verification
OK
Parameter
Verify CDI alarm input
operation per Table 3-1.
Specification
Data
BTS Relay #XX Contact Alarm
Sets/Clears
Comments:_________________________________________________________
A-18
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Aug 2002
Site Operation Verification
68P09255A57-2
C-CCP Shelf
Site I/O A & B
C-CCP Shelf
CSM-1
CSM-2
HSO
CCD-1
CCD-2
AMR-1
AMR-2
MPC-1
MPC-2
Fans 1-3
GLI3-1
GLI3-2
BBX-1
BBX-2
BBX-3
BBX-4
BBX-5
BBX-6
BBX-7
BBX-8
BBX-9
BBX-10
BBX-1 1
BBX-12
BBX-r
MCC-1
MCC-2
MCC-3
MCC-4
MCC-5
MCC-6
MCC-7
MCC-8
MCC-9
MCC-10
CIO
SWITCH
PS-1
PS-2
PS-3
Aug 2002
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PRELIMINARY
A-19
Site Operation Verification
68P09255A57-2
LPAs
LPA 1A
LPA 1B
LPA 1C
LPA 1D
LPA 2A
LPA 2B
LPA 2C
LPA 2D
LPA 3A
LPA 3B
LPA 3C
LPA 3D
LPA 4A
LPA 4B
LPA 4C
LPA 4D
A-20
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Aug 2002
B
Appendix B
ATP Matrix Table
Aug 2002
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PRELIMINARY
B-1
Re-optimization
68P09255A57-2
Re-optimization
Usage & Background
Periodic maintenance of a site may also mandate re-optimization of
specific portions of the site. An outline of some basic guidelines is
included in the following tables.
NOTE
Re-optimization steps listed for any assembly detailed in the
tables below must be performed anytime an RF cable associated
with it is replaced.
Detailed Optimization/ATP Test Matrix
Table B-1 outlines in more detail the tests that would need to be
performed if one of the BTS components were to fail and be replaced. It
is also assumes that all modules are placed OOS-ROM via the LMF
until full redundancy of all applicable modules is implemented.
The following guidelines should also be noted when using this table.
NOTE
Not every procedure required to bring the site back in service is
indicated in Table B-1. It is meant to be used as a guideline
ONLY. The table assumes that the user is familiar enough with
the BTS Optimization/ATP procedure to understand which test
equipment set ups, calibrations, and BTS site preparation will be
required before performing the Table # procedures referenced.
Various passive BTS components (such as the DRDCs, filter; etc.) only
require a TX calibration audit to be performed in lieu of a full path
calibration. If the TX path calibration audit fails, the entire RF path
calibration will need to be repeated. If the RF path calibration fails,
further troubleshooting is warranted.
Whenever any C-CCP BACKPLANE is replaced, it is assumed that
only power to the C-CCP shelf being replaced is turned off via the
breaker supplying that shelf.
NOTE
If any significant change in signal level results from any
component being replaced in the RX or TX signal flow paths, it
would be identified by re-running the RX and TX calibration
audit command.
When the CIO is replaced, the C-CCP shelf remains powered up. The
BBX boards may need to be removed, then re-installed into their
original slots, and re-downloaded (code and BLO data). RX and TX
calibration audits should then be performed.
B-2
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Re-optimization
68P09255A57-2
Table 3-41
TX Path Calibration
Table 3-42
Download Offsets to BBX
Table 3-43
TX Path Audit
Table 3-52
RFDS Path Calibration and
Offset Data Download
Table 4-1
Spectral Purity TX Mask
Table 4-1
Waveform Quality (rho)
Table 4-1
Pilot Time Offset
Table 4-1
Code Domain Power /
Noise Floor
Table 4-1
FER Test
Table 3-54/
Table 3-63
 
  
RFDS
RFDS cables
LFR Initialization /
Verification
LPA Bandpass Filter or Combiner
Table 3-27
Swithch Card
LPA or LPA Trunking Module
LPAC Cable
GPS &HSO Initialization /
Verification
GLI3
Table 3-26
ETIB or Associated Cables
RGD/20-pair Punchblock w/RGD
CCD Card
Enable CSMs
50-pair Punchblock w/RGPS
CSM/GPS
Table 3-23
HSO/HSOX
MCC24E/MCC8E/MCC-1X
LFR
BBX2/BBX-1X
CIO
MPC / EMPC
RX Cables
Download Code/Data
Description
TX Cables
Table 3-20/
Table 3-21/
Doc
Tbl
DRDC or TRDC
SCCP Shelf Assembly (Backplane)
Table B-1: SC 4812ET BTS Optimization and ATP Test Matrix
Alarm Tests
. . . continued on next page
Aug 2002
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B-3
Re-optimization
68P09255A57-2
RFDS
RFDS cables
LPA Bandpass Filter or Combiner
Swithch Card
LPA or LPA Trunking Module
LPAC Cable
GLI3
ETIB or Associated Cables
CCD Card
RGD/20-pair Punchblock w/RGD
50-pair Punchblock w/RGPS
HSO/HSOX
LFR
CSM/GPS
MCC24E/MCC8E/MCC-1X
BBX2/BBX-1X
CIO
MPC / EMPC
TX Cables
Description
RX Cables
Doc
Tbl
DRDC or TRDC
SCCP Shelf Assembly (Backplane)
Table B-1: SC 4812ET BTS Optimization and ATP Test Matrix
OPTIMIZATION AND TEST LEGEND:
D Required
* Perform if determined necessary for addtional fault isolation, repair assurance, or required for site
certification.
** Replace power supply modules one at a time so that power to the C-CCP shelf is not interrupted. If power
to the shelf is lost, all cards in the shelf must be downloaded again.
1.
Perform on all carrier and sector TX paths to the C-CCP cage.
2.
Perform on all carrier and sector RX paths to the C-CCP cage.
3.
Perform on all primary and redundant TX paths of the affected carrier.
4.
Perform on the affected carrier and sector TX path(s) (BBXR replacement affects all carrier
and sector TX paths)
5.
Perform on the affected carrier and sector RX path(s) (BBXR replacement affects all carrier
RX paths)
6.
Perform on all RF paths of the affected carrier and sector (RFDS replacement affects all
carriers)
7.
Perform with redundant BBX for at least one sector on one carrier.
8.
Verify performance by performing on one sector of one carrier only.
10
B-4
Perform only if RGD/RGPS, LFR antenna, or HSO or LFR expansion was installed
Verify performance by performing testing on one sector of each carrier.
SC
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PRELIMINARY
Aug 2002
C
Appendix C
BBX Gain
Aug 2002
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C-1
BBX Gain Set Point
68P09255A57-2
BBX Gain Set Point
Usage & Background
Table C-1 outlines the relationship between the total of all code domain
channel element gain settings (digital root sum of the squares) and the
BBX Gain Set Point between 33.0 dBm and 44.0 dBm. The resultant
RF output (as measured at the top of the BTS in dBm) is shown in the
table. The table assumes that the BBX Bay Level Offset (BLO) values
have been calculated.
As an illustration, consider a BBX keyed up to produce a CDMA carrier
with only the Pilot channel (no MCCs forward link enabled). Pilot gain
is set to 262. In this case, the BBX Gain Set Point is shown to correlate
exactly to the actual RF output anywhere in the 33 to 44 dBm output
range. (This is the level used to calibrate the BTS).
Table C-1: BBX Gain Set Point vs. Actual BTS Output (in dBm)
44
43
42
41
40
39
38
37
36
35
34
33
541
43.3
42.3
41.3
40.3
39.3
533
43.2
42.2
41.2
40.2
39.2
525
43
42
41
40
39
517
42.9
41.9
40.9
39.9
38.9
509
42.8
41.8
40.8
39.8
38.8
501
42.6
41.6
40.6
39.6
38.6
493
43.5
42.5
41.5
40.5
39.5
38.5
485
43.4
42.4
41.4
40.4
39.4
38.4
477
43.2
42.2
41.2
40.2
39.2
38.2
469
43.1
42.1
41.1
40.1
39.1
38.1
461
42.9
41.9
40.9
39.9
38.9
37.9
453
42.8
41.8
40.8
39.8
38.8
37.8
445
43.6
42.6
41.6
40.6
39.6
38.6
37.6
437
43.4
42.4
41.4
40.4
39.4
38.4
37.4
429
43.3
42.3
41.3
40.3
39.3
38.3
37.3
421
43.1
42.1
41.1
40.1
39.1
38.1
37.1
413
43
42
41
40
39
38
37
405
42.8
41.8
40.8
39.8
38.8
37.8
36.8
397
43.6
42.6
41.6
40.6
39.6
38.6
37.6
36.6
389
43.4
42.4
41.4
40.4
39.4
38.4
37.4
36.4
dBm
Gain
. . . continued on next page
C-2
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BBX Gain Set Point
68P09255A57-2
Table C-1: BBX Gain Set Point vs. Actual BTS Output (in dBm)
44
43
42
41
40
39
38
37
36
35
34
33
381
43.3
42.3
41.3
40.3
39.3
38.3
37.3
36.3
374
43.1
42.1
41.1
40.1
39.1
38.1
37.1
36.1
366
42.9
41.9
40.9
39.9
38.9
37.9
36.9
35.9
358
42.7
41.7
40.7
39.7
38.7
37.7
36.7
35.7
350
43.5
42.5
41.5
40.5
39.5
38.5
37.5
36.5
35.5
342
43.3
42.3
41.3
40.3
39.3
38.3
37.3
36.3
35.3
334
43.1
42.1
41.1
40.1
39.1
38.1
37.1
36.1
35.1
326
42.9
41.9
40.9
39.9
38.9
37.9
36.9
35.9
34.9
318
42.7
41.7
40.7
39.7
38.7
37.7
36.7
35.7
34.7
310
43.5
42.5
41.5
40.5
39.5
38.5
37.5
36.5
35.5
34.5
302
43.2
42.2
41.2
40.2
39.2
38.2
37.2
36.2
35.2
34.2
294
43
42
41
40
39
38
37
36
35
34
286
42.8
41.8
40.8
39.8
38.8
37.8
36.8
35.8
34.8
33.8
278
43.5
42.5
41.5
40.5
39.5
38.5
37.5
36.5
35.5
34.5
33.5
270
43.3
42.3
41.3
40.3
39.3
38.3
37.3
36.3
35.3
34.3
33.3
262
43
42
41
40
39
38
37
36
35
34
33
254
42.7
41.7
40.7
39.7
38.7
37.7
36.7
35.7
34.7
33.7
32.7
246
43.4
42.4
41.4
40.4
39.4
38.4
37.4
36.4
35.4
34.4
33.4
32.4
238
43.2
42.2
41.2
40.2
39.2
38.2
37.2
36.2
35.2
34.2
33.2
32.2
230
42.9
41.9
40.9
39.9
38.9
37.9
36.9
35.9
34.9
33.9
32.9
31.9
222
42.6
41.6
40.6
39.6
38.6
37.6
36.6
35.6
34.6
33.6
32.6
31.6
214
42.2
41.2
40.2
39.2
38.2
37.2
36.2
35.2
34.2
33.2
32.2
31.2
dBm
Gain
Aug 2002
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C-3
BBX Gain Set Point
68P09255A57-2
Notes
C-4
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Aug 2002
Appendix D
CDMA Operating Frequency
Programming
Aug 2002
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D-1
Channel Frequencies
68P09255A57-2
Channel Frequencies
Introduction
Programming of each of the BTS BBX synthesizers is performed by the
BTS GLIs via the CHI bus. This programming data determines the
transmit and receive transceiver operating frequencies (channels) for
each BBX2.
1900 MHz PCS Channels
Figure D-1 shows the valid channels for the North American PCS
1900 MHz frequency spectrum. There are 10 CDMA wireline or
non-wireline band channels used in a CDMA system (unique per
customer operating system).
Figure D-1: North America PCS Frequency Spectrum (CDMA Allocation)
CHANNEL
25
1851.25
1931.25
1863.75
1943.75
1871.25
1951.25
1883.75
1963.75
1896.25
1976.25
1908.75
1988.75
275
ÉÉÉ
ÉÉÉ
ÉÉÉ
425
675
ÉÉÉ
ÉÉÉ
ÉÉÉ
925
1175
D-2
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FW00463
Aug 2002
Channel Frequencies
68P09255A57-2
Calculating 1900 MHz Center Frequencies
Table D-1 shows selected 1900 MHz CDMA candidate operating
channels, listed in both decimal and hexadecimal, and the corresponding
transmit, and receive frequencies. Center frequencies (in MHz) for
channels not shown in the table may be calculated as follows:
 TX = 1930 + 0.05 * Channel#
Example: Channel 262
TX = 1930 + 0.05*262 = 1943.10 MHz
 RX = TX - 80
Example: Channel 262
RX = 1943.10 - 50 = 1863.10 MHz
Actual frequencies used depend on customer CDMA system frequency
plan.
Each CDMA channel requires a 1.77 MHz frequency segment. The
actual CDMA carrier is 1.23 MHz wide, with a 0.27 MHz guard band on
both sides of the carrier.
Minimum frequency separation required between any CDMA carrier and
the nearest NAMPS/AMPS carrier is 900 kHz (center-to-center).
Table D-1: 1900 MHz TX and RX Frequency vs. Channel
Channel Number
Decimal
Hex
25
0019
50
0032
75
004B
100
0064
125
007D
150
0096
175
00AF
200
00C8
225
00E1
250
00FA
275
0113
300
012C
325
0145
350
015E
375
0177
400
0190
425
01A9
450
01C2
475
01DB
500
01F4
525
020D
550
0226
575
023F
600
0258
625
0271
650
028A
Transmit Frequency (MHz)
Center Frequency
1931.25
1932.50
1933.75
1935.00
1936.25
1937.50
1938.75
1940.00
1941.25
1942.50
1943.75
1945.00
1946.25
1947.50
1948.75
1950.00
1951.25
1952.50
1953.75
1955.00
1956.25
1957.50
1958.75
1960.00
1961.25
1962.50
Receive Frequency (MHz)
Center Frequency
1851.25
1852.50
1853.75
1855.00
1856.25
1857.50
1858.75
1860.00
1861.25
1862.50
1863.75
1865.00
1866.25
1867.50
1868.75
1870.00
1871.25
1872.50
1873.75
1875.00
1876.25
1877.50
1878.75
1880.00
1881.25
1882.50
. . . continued on next page
Aug 2002
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D-3
Channel Frequencies
68P09255A57-2
Table D-1: 1900 MHz TX and RX Frequency vs. Channel
Transmit Frequency (MHz)
Center Frequency
1963.75
1965.00
1966.25
1967.50
1968.75
1970.00
1971.25
1972.50
1973.75
1975.00
1976.25
1977.50
1978.75
1980.00
1981.25
1982.50
1983.75
1985.00
1986.25
1987.50
1988.75
Receive Frequency (MHz)
Center Frequency
1883.75
1885.00
1886.25
1887.50
1888.75
1890.00
1891.25
1892.50
1893.75
1895.00
1896.25
1897.50
1898.75
1900.00
1901.25
1902.50
1903.75
1905.00
1906.25
1807.50
1908.75
800 MHz CDMA Channels
Figure D-2 shows the valid channels for the North American cellular
telephone frequency spectrum. There are 10 CDMA wireline or
non-wireline band channels used in a CDMA system (unique per
customer operating system).
OVERALL WIRELINE (B) BANDS
D-4
893.970
848.970
799
777
CDMA NON-WIRELINE (A) BAND
CDMA WIRELINE (B) BAND
SC
4812ET Optimization/ATP Manual Software Release R16.1.x.x
PRELIMINARY
ËËË
ËËË
ËËË
ËËË
739
846.480
846.510
891.480
891.510
694
689
666
667
844.980
845.010
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ËË
ÉÉ
ËË
716
717
889.980
890.010
OVERALL NON-WIRELINE (A) BANDS
644
ËËË
ËËË
ËËË
ËËË
ËËË
ËËË
ËËË
ËËË
356
834.990
835.020
879.990
880.020
311
333
334
870.000
870.030
825.000
825.030
1023
CHANNEL
ÉÉ
ÉÉÉÉ
ÉÉÉÉ
ÉÉ
ÉÉÉÉ
ÉÉÉÉ
ÉÉ
ÉÉÉÉ
ÉÉÉÉ
ÉÉ
ÉÉÉÉ
ÉÉÉÉ
1013
RX FREQ
(MHz)
824.040
TX FREQ
(MHz)
869.040
Figure D-2: North American Cellular Telephone System Frequency Spectrum (CDMA Allocation).
991
Channel Number
Decimal
Hex
675
02A3
700
02BC
725
02D5
750
02EE
775
0307
800
0320
825
0339
850
0352
875
036B
900
0384
925
039D
950
03B6
975
03CF
1000
03E8
1025
0401
1050
041A
1075
0433
1100
044C
1125
0465
1150
047E
1175
0497
FW00402
Aug 2002
Channel Frequencies
68P09255A57-2
Calculating 800 MHz Center Frequencies
Table D-2 shows selected 800 MHz CDMA candidate operating
channels, listed in both decimal and hexadecimal, and the corresponding
transmit, and receive frequencies. Center frequencies (in MHz) for
channels not shown in the table may be calculated as follows:
 Channels 1-777
TX = 870 + 0.03 * Channel#
Example: Channel 262
TX = 870 + 0.03*262 = 877.86 MHz
 Channels 1013-1023
TX = 870 + 0.03 * (Channel# - 1023)
Example: Channel 1015
TX = 870 +0.03 *(1015 - 1023) = 869.76 MHz
 RX = TX - 45 MHz
Example: Channel 262
RX = 877.86 -45 = 832.86 MHz
Table D-2: 800 MHz TX and RX Frequency vs. Channel
Channel Number
Decimal Hex
Transmit Frequency (MHz)
Center Frequency
Receive Frequency (MHz)
Center Frequency
0001
870.0300
825.0300
25
0019
870.7500
825.7500
50
0032
871.5000
826.5000
75
004B
872.2500
827.2500
100
0064
873.0000
828.0000
125
007D
873.7500
828.7500
150
0096
874.5000
829.5000
175
00AF
875.2500
830.2500
200
00C8
876.0000
831.0000
225
00E1
876.7500
831.7500
250
00FA
877.5000
832.5000
275
0113
878.2500
833.2500
300
012C
879.0000
834.0000
325
0145
879.7500
834.7500
350
015E
880.5000
835.5000
375
0177
881.2500
836.2500
400
0190
882.0000
837.0000
425
01A9
882.7500
837.7500
450
01C2
883.5000
838.5000
475
01DB
884.2500
839.2500
500
01F4
885.0000
840.0000
525
020D
885.7500
840.7500
550
0226
886.5000
Aug 2002
841.5000
. . . continued on next page
SC
4812ET Optimization/ATP Manual Software Release R16.1.x.x
PRELIMINARY
D-5
Channel Frequencies
68P09255A57-2
Table D-2: 800 MHz TX and RX Frequency vs. Channel
Channel Number
Decimal Hex
Transmit Frequency (MHz)
Center Frequency
Receive Frequency (MHz)
Center Frequency
575
023F
887.2500
842.2500
600
0258
888.0000
843.0000
625
0271
888.7500
843.7500
650
028A
889.5000
844.5000
675
02A3
890.2500
845.2500
700
02BC
891.0000
846.0000
725
02D5
891.7500
846.7500
750
02EE
892.5000
847.5000
775
0307
893.2500
848.2500
Channel numbers 778 through 1012 are not used.
1013
03F5
869.7000
824.7000
NOTE
1023
D-6
03FF
870.0000
825.0000
SC
4812ET Optimization/ATP Manual Software Release R16.1.x.x
PRELIMINARY
Aug 2002
Appendix E
PN Offset
Aug 2002
SC
4812ET Optimization/ATP Manual Software Release R16.1.x.x
PRELIMINARY
E-1
PN Offset
68P09255A57-2
PN Offset
Background
All channel elements transmitted from a BTS in a particular 1.25 MHz
CDMA channel are orthonogonally spread by 1 of 64 possible Walsh
code functions; additionally, they are also spread by a quadrature pair of
PN sequences unique to each sector.
Overall, the mobile uses this to differentiate multiple signals transmitted
from the same BTS (and surrounding BTS) sectors, and to synchronize
to the next strongest sector.
The PN offset per sector is stored on the BBXs, where the
corresponding I & Q registers reside.
The PN offset values are determined on a per BTS/per sector(antenna)
basis as determined by the appropriate cdf file content. A breakdown of
this information is found in Table E-1.
Usage
There are three basic RF chip delays currently in use. It is important to
determine what RF chip delay is valid to be able to test the BTS
functionality. This can be done by ascertaining if the CDF file
FineTxAdj value was set to “on” when the MCC was downloaded with
“image data”. The FineTxAdj value is used to compensate for the
processing delay (approximately 20 mS) in the BTS using any type of
mobile meeting IS-97 specifications.
Observe the following guidelines:
 If the FineTxAdj value in the cdf file is 101 (65 HEX), the
FineTxAdj has not been set. The I and Q values from the 0 table
MUST be used.
If the FineTxAdj value in the cdf file is 213 (D5 HEX), FineTxAdj has
been set for the 14 chip table.
 If the FineTxAdj value in the cdf file is 197 (C5 HEX), FineTxAdj
has been set for the 13 chip table.
NOTE
CDF file I and Q values can be represented in DECIMAL or
HEX. If using HEX, add 0x before the HEX value. If necessary,
convert HEX values in Table E-1 to decimal before comparing
them to cdf file I & Q value assignments.
- If you are using a Qualcomm mobile, use the I and Q values from
the 13 chip delay table.
- If you are using a mobile that does not have the 1 chip offset
problem, (any mobile meeting the IS-97 specification), use the 14
chip delay table.
NOTE
E-2
If the wrong I and Q values are used with the wrong
FineTxAdj parameter, system timing problems will occur. This
will cause the energy transmitted to be “smeared” over several
Walsh codes (instead of the single Walsh code that it was
assigned to), causing erratic operation. Evidence of smearing is
usually identified by Walsh channels not at correct levels or
present when not selected in the Code Domain Power Test.
SC
4812ET Optimization/ATP Manual Software Release R16.1.x.x
PRELIMINARY
Aug 2002
PN Offset
68P09255A57-2
Table E-1: PnMaskI and PnMaskQ Values for PilotPn
Pilot
PN
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
14-Chip Delay
(Dec.)
(Hex.)
17523
32292
4700
14406
14899
17025
14745
2783
5832
12407
31295
7581
18523
29920
25184
26282
30623
15540
23026
20019
4050
1557
30262
18000
20056
12143
17437
17438
5102
9302
17154
5198
4606
24804
17180
10507
10157
23850
31425
4075
10030
16984
14225
26519
27775
30100
7922
14199
17637
23081
5099
23459
32589
17398
26333
4011
2256
18651
1094
21202
13841
31767
18890
30999
22420
20168
12354
11187
11834
10395
28035
27399
22087
2077
13758
11778
3543
7184
2362
25840
12177
10402
1917
17708
10630
6812
14350
10999
25003
2652
19898
2010
25936
28531
11952
31947
25589
11345
28198
13947
8462
9595
4473
7E24
125C
3846
3A33
4281
3999
0ADF
16C8
3077
7A3F
1D9D
485B
74E0
6260
66AA
779F
3CB4
59F2
4E33
0FD2
0615
7636
4650
4E58
2F6F
441D
441E
13EE
2456
4302
144E
11FE
60E4
431C
290B
27AD
5D2A
7AC1
0FEB
272E
4258
3791
6797
6C7F
7594
1EF2
3777
44E5
5A29
13EB
5BA3
7F4D
43F6
66DD
0FAB
08D0
48DB
0446
52D2
3611
7C17
49CA
7917
5794
4EC8
3042
2BB3
2E3A
289B
6D83
6B07
5647
081D
35BE
2E02
0DD7
1C10
093A
64F0
2F91
28A2
077D
452C
2986
1A9C
380E
2AF7
61AB
0A5C
4DBA
07DA
6550
6F73
2EB0
7CCB
63F5
2C51
6E26
367B
210E
257B
13-Chip Delay
(Dec.)
(Hex.)
29673
16146
2350
7203
19657
28816
19740
21695
2916
18923
27855
24350
30205
14960
12592
13141
27167
7770
11513
30409
2025
21210
15131
9000
10028
18023
29662
8719
2551
4651
8577
2599
2303
12402
8590
17749
16902
11925
27824
22053
5015
8492
18968
25115
26607
15050
3961
19051
29602
31940
22565
25581
29082
8699
32082
18921
1128
27217
547
10601
21812
28727
9445
29367
11210
10084
6177
23525
5917
23153
30973
31679
25887
18994
6879
5889
18647
3592
1181
12920
23028
5201
19842
8854
5315
3406
7175
23367
32489
1326
9949
1005
12968
31109
5976
28761
32710
22548
14099
21761
4231
23681
73E9
3F12
092E
1C23
4CC9
7090
4D1C
54BF
0B64
49EB
6CCF
5F1E
75FD
3A70
3130
3355
6A1F
1E5A
2CF9
76C9
07E9
52DA
3B1B
2328
272C
4667
73DE
220F
09F7
122B
2181
0A27
08FF
3072
218E
4555
4206
2E95
6CB0
5625
1397
212C
4A18
621B
67EF
3ACA
0F79
4A6B
73A2
7CC4
5825
63ED
719A
21FB
7D52
49E9
0468
6A51
0223
2969
5534
7037
24E5
72B7
2BCA
2764
1821
5BE5
171D
5A71
78FD
7BBF
651F
4A32
1ADF
1701
48D7
0E08
049D
3278
59F4
1451
4D82
2296
14C3
0D4E
1C07
5B47
7EE9
052E
26DD
03ED
32A8
7985
1758
7059
7FC6
5814
3713
5501
1087
5C81
0-Chip Delay
(Dec.)
(Hex.)
4096
9167
22417
966
14189
29150
18245
1716
11915
20981
24694
11865
6385
27896
25240
30877
30618
26373
314
17518
21927
2245
18105
8792
21440
15493
26677
11299
12081
23833
20281
10676
16981
31964
26913
14080
23842
27197
22933
30220
12443
19854
14842
15006
702
21373
23874
3468
31323
29266
16554
4096
1571
7484
6319
2447
24441
27351
23613
29008
5643
28085
18200
21138
21937
25222
109
6028
22034
15069
4671
30434
11615
19838
14713
241
24083
7621
19144
1047
26152
22402
21255
30179
7408
115
1591
1006
32263
1332
12636
4099
386
29231
25711
10913
8132
20844
13150
18184
19066
29963
1000
23CF
5791
03C6
376D
71DE
4745
06B4
2E8B
51F5
6076
2E59
18F1
6CF8
6298
789D
779A
6705
013A
446E
55A7
08C5
46B9
2258
53C0
3C85
6835
2C23
2F31
5D19
4F39
29B4
4255
7CDC
6921
3700
5D22
6A3D
5995
760C
309B
4D8E
39FA
3A9E
02BE
537D
5D42
0D8C
7A5B
7252
40AA
1000
0623
1D3C
18AF
098F
5F79
6AD7
5C3D
7150
160B
6DB5
4718
5292
55B1
6286
006D
178C
5612
3ADD
123F
76E2
2D5F
4D7E
3979
00F1
5E13
1DC5
4AC8
0417
6628
5782
5307
75E3
1CF0
0073
0637
03EE
7E07
0534
315C
1003
0182
722F
646F
2AA1
1FC4
516C
335E
4708
4A7A
750B
. . . continued on next page
Aug 2002
SC
4812ET Optimization/ATP Manual Software Release R16.1.x.x
PRELIMINARY
E-3
PN Offset
68P09255A57-2
Table E-1: PnMaskI and PnMaskQ Values for PilotPn
Pilot
PN
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
14-Chip Delay
(Dec.)
(Hex.)
32743
7114
7699
19339
28212
29587
19715
14901
20160
22249
26582
7153
15127
15274
23149
16340
27052
13519
10620
15978
27966
12479
1536
3199
4549
17888
13117
7506
27626
31109
29755
26711
20397
18608
7391
23168
23466
15932
25798
28134
28024
6335
21508
26338
17186
22462
3908
25390
27891
9620
4670
14672
29415
20610
6479
10957
18426
22726
5247
29953
5796
16829
4528
5415
10294
17046
7846
10762
13814
16854
795
9774
24291
3172
2229
21283
16905
7062
7532
25575
14244
28053
30408
5094
16222
7159
174
25530
2320
23113
23985
2604
1826
30853
15699
2589
25000
18163
12555
8670
7FE7
1BCA
1E13
4B8B
6E34
7393
4D03
3A35
4EC0
56E9
67D6
1BF1
3B17
3BAA
5A6D
3FD4
69AC
34CF
297C
3E6A
6D3E
30BF
0600
0C7F
11C5
45E0
333D
1D52
6BEA
7985
743B
6857
4FAD
48B0
1CDF
5A80
5BAA
3E3C
64C6
6DE6
6D78
18BF
5404
66E2
4322
57BE
0F44
632E
6CF3
2594
123E
3950
72E7
5082
194F
2ACD
47FA
58C6
147F
7501
16A4
41BD
11B0
1527
2836
4296
1EA6
2A0A
35F6
41D6
031B
262E
5EE3
0C64
08B5
5323
4209
1B96
1D6C
63E7
37A4
6D95
76C8
13E6
3F5E
1BF7
00AE
63BA
0910
5A49
5DB1
0A2C
0722
7885
3D53
0A1D
61A8
46F3
310B
21DE
13-Chip Delay
(Dec.)
(Hex.)
28195
3557
24281
29717
14106
26649
30545
19658
10080
31396
13291
23592
19547
7637
31974
8170
13526
19383
5310
7989
13983
18831
768
22511
22834
8944
18510
3753
13813
27922
27597
26107
30214
9304
24511
11584
11733
7966
12899
14067
14012
23951
10754
13169
8593
11231
1954
12695
26537
4810
2335
7336
30543
10305
17051
23386
9213
11363
17411
29884
2898
28386
2264
17583
5147
8523
3923
5381
6907
8427
20401
4887
24909
1586
19046
26541
28472
3531
3766
32719
7122
30966
15204
2547
8111
17351
87
12765
1160
25368
24804
1302
913
29310
20629
19250
12500
27973
22201
4335
6E23
0DE5
5ED9
7415
371A
6819
7751
4CCA
2760
7AA4
33EB
5C28
4C5B
1DD5
7CE6
1FEA
34D6
4BB7
14BE
1F35
369F
498F
0300
57EF
5932
22F0
484E
0EA9
35F5
6D12
6BCD
65FB
7606
2458
5FBF
2D40
2DD5
1F1E
3263
36F3
36BC
5D8F
2A02
3371
2191
2BDF
07A2
3197
67A9
12CA
091F
1CA8
774F
2841
429B
5B5A
23FD
2C63
4403
74BC
0B52
6EE2
08D8
44AF
141B
214B
0F53
1505
1AFB
20EB
4FB1
1317
614D
0632
4A66
67AD
6F38
0DCB
0EB6
7FCF
1BD2
78F6
3B64
09F3
1FAF
43C7
0057
31DD
0488
6318
60E4
0516
0391
727E
5095
4B32
30D4
6D45
56B9
10EF
0-Chip Delay
(Dec.)
(Hex.)
22575
31456
8148
19043
25438
10938
2311
7392
30714
180
8948
16432
9622
7524
1443
1810
6941
3238
8141
10408
18826
22705
3879
21359
30853
18078
15910
20989
28810
30759
18899
7739
6279
9968
8571
4143
19637
11867
7374
10423
9984
7445
4133
22646
15466
2164
16380
15008
31755
31636
6605
29417
22993
27657
5468
8821
20773
4920
5756
28088
740
23397
19492
26451
30666
15088
26131
15969
24101
12762
19997
22971
12560
31213
18780
16353
12055
30396
24388
1555
13316
31073
6187
21644
9289
4624
467
18133
1532
1457
9197
13451
25785
4087
31190
8383
12995
27438
9297
1676
582F
7AE0
1FD4
4A63
635E
2ABA
0907
1CE0
77FA
00B4
22F4
4030
2596
1D64
05A3
0712
1B1D
0CA6
1FCD
28A8
498A
58B1
0F27
536F
7885
469E
3E26
51FD
708A
7827
49D3
1E3B
1887
26F0
217B
102F
4CB5
2E5B
1CCE
28B7
2700
1D15
1025
5876
3C6A
0874
3FFC
3AA0
7C0B
7B94
19CD
72E9
59D1
6C09
155C
2275
5125
1338
167C
6DB8
02E4
5B65
4C24
6753
77CA
3AF0
6613
3E61
5E25
31DA
4E1D
59BB
3110
79ED
495C
3FE1
2F17
76BC
5F44
0613
3404
7961
182B
548C
2449
1210
01D3
46D5
05FC
05B1
23ED
348B
64B9
0FF7
79D6
20BF
32C3
6B2E
2451
068C
. . . continued on next page
E-4
SC
4812ET Optimization/ATP Manual Software Release R16.1.x.x
PRELIMINARY
Aug 2002
PN Offset
68P09255A57-2
Table E-1: PnMaskI and PnMaskQ Values for PilotPn
Pilot
PN
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
14-Chip Delay
(Dec.)
(Hex.)
6491
16876
17034
32405
27417
8382
5624
1424
13034
15682
27101
8521
30232
6429
27116
4238
5128
14846
13024
10625
31724
13811
24915
1213
2290
31551
12088
7722
27312
23130
594
25804
31013
32585
3077
17231
31554
8764
15375
13428
17658
13475
22095
24805
4307
23292
1377
28654
6350
16770
1290
4407
1163
12215
7253
8978
25547
3130
31406
6222
20340
25094
23380
10926
22821
31634
4403
689
27045
27557
16307
22338
27550
22096
23136
12199
1213
936
6272
32446
13555
8789
24821
21068
31891
5321
551
12115
4902
1991
14404
17982
19566
2970
23055
15158
29094
653
19155
23588
195B
41EC
428A
7E95
6B19
20BE
15F8
0590
32EA
3D42
69DD
2149
7618
191D
69EC
108E
1408
39FE
32E0
2981
7BEC
35F3
6153
04BD
08F2
7B3F
2F38
1E2A
6AB0
5A5A
0252
64CC
7925
7F49
0C05
434F
7B42
223C
3C0F
3474
44FA
34A3
564F
60E5
10D3
5AFC
0561
6FEE
18CE
4182
050A
1137
048B
2FB7
1C55
2312
63CB
0C3A
7AAE
184E
4F74
6206
5B54
2AAE
5925
7B92
1133
02B1
69A5
6BA5
3FB3
5742
6B9E
5650
5A60
2FA7
04BD
03A8
1880
7EBE
34F3
2255
60F5
524C
7C93
14C9
0227
2F53
1326
07C7
3844
463E
4C6E
0B9A
5A0F
3B36
71A6
028D
4AD3
5C24
13-Chip Delay
(Dec.)
(Hex.)
23933
8438
8517
28314
25692
4191
2812
712
6517
7841
25918
16756
15116
23902
13558
2119
2564
7423
6512
17680
15862
19241
24953
21390
1145
27727
6044
3861
13656
11565
297
12902
27970
28276
22482
28791
15777
4382
20439
6714
8829
19329
31479
24994
22969
11646
21344
14327
3175
8385
645
18087
19577
23015
16406
4489
32729
1565
15703
3111
10170
12547
11690
5463
25262
15817
18085
20324
31470
31726
20965
11169
13775
11048
11568
23023
19554
468
3136
16223
21573
24342
32326
10534
28789
17496
20271
22933
2451
19935
7202
8991
9783
1485
25403
7579
14547
20346
27477
11794
5D7D
20F6
2145
6E9A
645C
105F
0AFC
02C8
1975
1EA1
653E
4174
3B0C
5D5E
34F6
0847
0A04
1CFF
1970
4510
3DF6
4B29
6179
538E
0479
6C4F
179C
0F15
3558
2D2D
0129
3266
6D42
6E74
57D2
7077
3DA1
111E
4FD7
1A3A
227D
4B81
7AF7
61A2
59B9
2D7E
5360
37F7
0C67
20C1
0285
46A7
4C79
59E7
4016
1189
7FD9
061D
3D57
0C27
27BA
3103
2DAA
1557
62AE
3DC9
46A5
4F64
7AEE
7BEE
51E5
2BA1
35CF
2B28
2D30
59EF
4C62
01D4
0C40
3F5F
5445
5F16
7E46
2926
7075
4458
4F2F
5995
0993
4DDF
1C22
231F
2637
05CD
633B
1D9B
38D3
4F7A
6B55
2E12
0-Chip Delay
(Dec.)
(Hex.)
25414
7102
20516
19495
17182
11572
25570
6322
8009
26708
6237
32520
31627
3532
24090
20262
18238
2033
25566
25144
29679
5064
27623
13000
31373
13096
26395
15487
29245
26729
12568
24665
8923
19634
29141
73
26482
6397
29818
8153
302
28136
29125
8625
26671
6424
12893
18502
7765
25483
12596
19975
20026
8958
19143
17142
19670
30191
5822
22076
606
9741
9116
12705
17502
18952
15502
17819
4370
31955
30569
7350
26356
32189
1601
19537
25667
4415
2303
16362
28620
6736
2777
24331
9042
107
4779
13065
30421
20210
5651
31017
30719
23104
7799
17865
26951
25073
32381
16581
6346
1BBE
5024
4C27
431E
2D34
63E2
18B2
1F49
6854
185D
7F08
7B8B
0DCC
5E1A
4F26
473E
07F1
63DE
6238
73EF
13C8
6BE7
32C8
7A8D
3328
671B
3C7F
723D
6869
3118
6059
22DB
4CB2
71D5
0049
6772
18FD
747A
1FD9
012E
6DE8
71C5
21B1
682F
1918
325D
4846
1E55
638B
3134
4E07
4E3A
22FE
4AC7
42F6
4CD6
75EF
16BE
563C
025E
260D
239C
31A1
445E
4A08
3C8E
459B
1112
7CD3
7769
1CB6
66F4
7DBD
0641
4C51
6443
113F
08FF
3FEA
6FCC
1A50
0AD9
5F0B
2352
006B
12AB
3309
76D5
4EF2
1613
7929
77FF
5A40
1E77
45C9
6947
61F1
7E7D
40C5
. . . continued on next page
Aug 2002
SC
4812ET Optimization/ATP Manual Software Release R16.1.x.x
PRELIMINARY
E-5
PN Offset
68P09255A57-2
Table E-1: PnMaskI and PnMaskQ Values for PilotPn
Pilot
PN
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
14-Chip Delay
(Dec.)
(Hex.)
14726
25685
21356
12149
28966
22898
1713
30010
2365
27179
29740
5665
23671
1680
25861
25712
19245
26887
30897
11496
1278
31555
29171
20472
5816
30270
22188
6182
32333
14046
15873
19843
29367
13352
22977
31691
10637
25454
18610
6368
7887
7730
23476
889
21141
20520
21669
15967
21639
31120
10878
31060
30875
11496
24545
9586
20984
30389
7298
18934
23137
24597
23301
7764
14518
21634
11546
26454
15938
9050
3103
758
16528
20375
10208
17698
8405
28634
1951
20344
26696
3355
11975
31942
9737
9638
30643
13230
22185
2055
8767
15852
16125
6074
31245
15880
20371
8666
816
22309
3986
6455
536C
2F75
7126
5972
06B1
753A
093D
6A2B
742C
1621
5C77
0690
6505
6470
4B2D
6907
78B1
2CE8
04FE
7B43
71F3
4FF8
16B8
763E
56AC
1826
7E4D
36DE
3E01
4D83
72B7
3428
59C1
7BCB
298D
636E
48B2
18E0
1ECF
1E32
5BB4
0379
5295
5028
54A5
3E5F
5487
7990
2A7E
7954
789B
2CE8
5FE1
2572
51F8
76B5
1C82
49F6
5A61
6015
5B05
1E54
38B6
5482
2D1A
6756
3E42
235A
0C1F
02F6
4090
4F97
27E0
4522
20D5
6FDA
079F
4F78
6848
0D1B
2EC7
7CC6
2609
25A6
77B3
33AE
56A9
0807
223F
3DEC
3EFD
17BA
7A0D
3E08
4F93
21DA
0330
5725
13-Chip Delay
(Dec.)
(Hex.)
7363
25594
10678
18026
14483
11449
21128
15005
21838
25797
14870
23232
32747
840
25426
12856
29766
25939
28040
5748
639
27761
26921
10236
2908
15135
11094
3091
28406
7023
20176
30481
26763
6676
32048
27701
17686
12727
9305
3184
24247
3865
11738
20588
30874
10260
31618
20223
31635
15560
5439
15530
29297
5748
25036
4793
10492
30054
3649
9467
25356
32310
25534
3882
7259
10817
5773
13227
7969
4525
18483
379
8264
27127
5104
8849
24150
14317
19955
10172
13348
18609
22879
15971
23864
4819
30181
6615
25960
19007
24355
7926
20802
3037
29498
7940
27125
4333
408
26030
1CC3
63FA
29B6
466A
3893
2CB9
5288
3A9D
554E
64C5
3A16
5AC0
7FEB
0348
6352
3238
7446
6553
6D88
1674
027F
6C71
6929
27FC
0B5C
3B1F
2B56
0C13
6EF6
1B6F
4ED0
7711
688B
1A14
7D30
6C35
4516
31B7
2459
0C70
5EB7
0F19
2DDA
506C
789A
2814
7B82
4EFF
7B93
3CC8
153F
3CAA
7271
1674
61CC
12B9
28FC
7566
0E41
24FB
630C
7E36
63BE
0F2A
1C5B
2A41
168D
33AB
1F21
11AD
4833
017B
2048
69F7
13F0
2291
5E56
37ED
4DF3
27BC
3424
48B1
595F
3E63
5D38
12D3
75E5
19D7
6568
4A3F
5F23
1EF6
5142
0BDD
733A
1F04
69F5
10ED
0198
65AE
0-Chip Delay
(Dec.)
(Hex.)
15408
6414
8164
10347
29369
10389
24783
18400
22135
4625
22346
2545
7786
20209
26414
1478
15122
24603
677
13705
13273
14879
6643
23138
28838
9045
10792
25666
11546
15535
16134
8360
14401
26045
24070
30300
13602
32679
16267
9063
19487
12778
27309
12527
953
15958
6068
23577
32156
32709
32087
97
7618
93
16052
14300
11129
6602
14460
25458
15869
27047
26808
7354
27834
11250
552
27058
14808
9642
32253
26081
21184
11748
32676
2425
19455
19889
18177
2492
15086
30632
27549
6911
9937
2467
25831
32236
12987
11714
19283
11542
27928
26637
10035
10748
24429
29701
14997
32235
3C30
190E
1FE4
286B
72B9
2895
60CF
47E0
5677
1211
574A
09F1
1E6A
4EF1
672E
05C6
3B12
601B
02A5
3589
33D9
3A1F
19F3
5A62
70A6
2355
2A28
6442
2D1A
3CAF
3F06
20A8
3841
65BD
5E06
765C
3522
7FA7
3F8B
2367
4C1F
31EA
6AAD
30EF
03B9
3E56
17B4
5C19
7D9C
7FC5
7D57
0061
1DC2
005D
3EB4
37DC
2B79
19CA
387C
6372
3DFD
69A7
68B8
1CBA
6CBA
2BF2
0228
69B2
39D8
25AA
7DFD
65E1
52C0
2DE4
7FA4
0979
4BFF
4DB1
4701
09BC
3AEE
77A8
6B9D
1AFF
26D1
09A3
64E7
7DEC
32BB
2DC2
4B53
2D16
6D18
680D
2733
29FC
5F6D
7405
3A95
7DEB
. . . continued on next page
E-6
SC
4812ET Optimization/ATP Manual Software Release R16.1.x.x
PRELIMINARY
Aug 2002
PN Offset
68P09255A57-2
Table E-1: PnMaskI and PnMaskQ Values for PilotPn
Pilot
PN
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
14-Chip Delay
(Dec.)
(Hex.)
3698
16322
17429
21730
17808
30068
12737
28241
20371
13829
13366
25732
19864
5187
23219
28242
6243
445
21346
13256
18472
25945
31051
1093
5829
31546
29833
18146
24813
47
3202
21571
7469
25297
8175
28519
4991
7907
17728
14415
30976
26376
19063
19160
3800
8307
12918
19642
24873
22071
29563
13078
10460
17590
20277
19988
6781
32501
6024
20520
31951
26063
27203
6614
10970
5511
17119
16064
31614
4660
13881
16819
6371
24673
6055
10009
5957
11597
22155
15050
16450
27899
2016
17153
15849
30581
3600
4097
671
20774
24471
27341
19388
25278
9505
26143
13359
2154
13747
27646
0E72
3FC2
4415
54E2
4590
7574
31C1
6E51
4F93
3605
3436
6484
4D98
1443
5AB3
6E52
1863
01BD
5362
33C8
4828
6559
794B
0445
16C5
7B3A
7489
46E2
60ED
002F
0C82
5443
1D2D
62D1
1FEF
6F67
137F
1EE3
4540
384F
7900
6708
4A77
4AD8
0ED8
2073
3276
4CBA
6129
5637
737B
3316
28DC
44B6
4F35
4E14
1A7D
7EF5
1788
5028
7CCF
65CF
6A43
19D6
2ADA
1587
42DF
3EC0
7B7E
1234
3639
41B3
18E3
6061
17A7
2719
1745
2D4D
568B
3ACA
4042
6CFB
07E0
4301
3DE9
7775
0E10
1001
029F
5126
5F97
6ACD
4BBC
62BE
2521
661F
342F
086A
35B3
6BFE
13-Chip Delay
(Dec.)
(Hex.)
1849
8161
29658
10865
8904
15034
18736
26360
30233
19154
6683
12866
9932
23537
31881
14121
24033
20750
10673
6628
9236
25468
28021
21490
23218
15773
27540
9073
24998
20935
1601
31729
24390
24760
24103
26211
22639
24225
8864
19959
15488
13188
29931
9580
1900
16873
6459
9821
24900
31435
30593
6539
5230
8795
27046
9994
17154
28998
3012
10260
28763
31963
31517
3307
5485
17663
28499
8032
15807
2330
21792
28389
16973
32268
17903
23984
17822
22682
25977
7525
8225
30785
1008
28604
20680
30086
1800
17980
20339
10387
25079
31578
9694
12639
23724
32051
21547
1077
21733
13823
0739
1FE1
73DA
2A71
22C8
3ABA
4930
66F8
7619
4AD2
1A1B
3242
26CC
5BF1
7C89
3729
5DE1
510E
29B1
19E4
2414
637C
6D75
53F2
5AB2
3D9D
6B94
2371
61A6
51C7
0641
7BF1
5F46
60B8
5E27
6663
586F
5EA1
22A0
4DF7
3C80
3384
74EB
256C
076C
41E9
193B
265D
6144
7ACB
7781
198B
146E
225B
69A6
270A
4302
7146
0BC4
2814
705B
7CDB
7B1D
0CEB
156D
44FF
6F53
1F60
3DBF
091A
5520
6EE5
424D
7E0C
45EF
5DB0
459E
589A
6579
1D65
2021
7841
03F0
6FBC
50C8
7586
0708
463C
4F73
2893
61F7
7B5A
25DE
315F
5CAC
7D33
542B
0435
54E5
35FF
0-Chip Delay
(Dec.)
(Hex.)
23557
17638
3545
9299
6323
19590
7075
14993
19916
6532
17317
16562
26923
9155
20243
32391
20190
27564
20869
9791
714
7498
23278
8358
9468
23731
25133
2470
17501
24671
11930
9154
7388
3440
27666
22888
13194
26710
7266
15175
15891
26692
14757
28757
31342
19435
2437
20573
18781
18948
30766
5985
6823
20973
10197
9618
22705
5234
12541
8019
22568
5221
25216
1354
29335
6682
26128
29390
8852
6110
11847
10239
6955
10897
14076
12450
8954
19709
1252
15142
26958
8759
12696
11936
25635
17231
22298
7330
30758
6933
2810
8820
7831
19584
2944
19854
10456
17036
2343
14820
5C05
44E6
0DD9
2453
18B3
4C86
1BA3
3A91
4DCC
1984
43A5
40B2
692B
23C3
4F13
7E87
4EDE
6BAC
5185
263F
02CA
1D4A
5AEE
20A6
24FC
5CB3
622D
09A6
445D
605F
2E9A
23C2
1CDC
0D70
6C12
5968
338A
6856
1C62
3B47
3E13
6844
39A5
7055
7A6E
4BEB
0985
505D
495D
4A04
782E
1761
1AA7
51ED
27D5
2592
58B1
1472
30FD
1F53
5828
1465
6280
054A
7297
1A1A
6610
72CE
2294
17DE
2E47
27FF
1B2B
2A91
36FC
30A2
22FA
4CFD
04E4
3B26
694E
2237
3198
2EA0
6423
434F
571A
1CA2
7826
1B15
0AFA
2274
1E97
4C80
0B80
4D8E
28D8
428C
0927
39E4
. . . continued on next page
Aug 2002
SC
4812ET Optimization/ATP Manual Software Release R16.1.x.x
PRELIMINARY
E-7
PN Offset
68P09255A57-2
Table E-1: PnMaskI and PnMaskQ Values for PilotPn
Pilot
PN
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
14-Chip Delay
(Dec.)
(Hex.)
13904
27198
3685
16820
22479
6850
15434
19332
8518
14698
21476
30475
23984
1912
26735
15705
3881
20434
16779
31413
16860
8322
28530
26934
18806
20216
9245
8271
18684
8220
6837
9613
31632
27448
12417
30901
9366
12225
21458
6466
8999
26718
3230
27961
28465
6791
17338
11832
11407
15553
1056
1413
3311
4951
749
6307
961
2358
28350
31198
11467
8862
6327
7443
28574
25093
6139
22047
32545
7112
28535
10378
15065
5125
12528
23215
20959
3568
26453
29421
24555
10779
25260
16084
26028
29852
14978
12182
25143
15838
5336
21885
20561
30097
21877
23589
26060
9964
25959
3294
3650
6A3E
0E65
41B4
57CF
1AC2
3C4A
4B84
2146
396A
53E4
770B
5DB0
0778
686F
3D59
0F29
4FD2
418B
7AB5
41DC
2082
6F72
6936
4976
4EF8
241D
204F
48FC
201C
1AB5
258D
7B90
6B38
3081
78B5
2496
2FC1
53D2
1942
2327
685E
0C9E
6D39
6F31
1A87
43BA
2E38
2C8F
3CC1
0420
0585
0CEF
1357
02ED
18A3
03C1
0936
6EBE
79DE
2CCB
229E
18B7
1D13
6F9E
6205
17FB
561F
7F21
1BC8
6F77
288A
3AD9
1405
30F0
5AAF
51DF
0DF0
6755
72ED
5FEB
2A1B
62AC
3ED4
65AC
749C
3A82
2F96
6237
3DDE
14D8
557D
5051
7591
5575
5C25
65CC
26EC
6567
0CDE
13-Chip Delay
(Dec.)
(Hex.)
6952
13599
22242
8410
31287
3425
7717
9666
4259
7349
10738
27221
11992
956
26087
20348
22084
10217
28949
27786
8430
4161
14265
13467
9403
10108
17374
16887
9342
4110
23690
17174
15816
13724
18832
28042
4683
17968
10729
3233
16451
13359
1615
26444
26184
23699
8669
5916
18327
20400
528
19710
18507
18327
20298
17005
20444
1179
14175
15599
22617
4431
16999
16565
14287
32574
17857
25907
29100
3556
31111
5189
21328
17470
6264
25451
26323
1784
32150
30538
25033
23345
12630
8042
13014
14926
7489
6091
32551
7919
2668
25730
26132
29940
25734
24622
13030
4982
31887
1647
1B28
351F
56E2
20DA
7A37
0D61
1E25
25C2
10A3
1CB5
29F2
6A55
2ED8
03BC
65E7
4F7C
5644
27E9
7115
6C8A
20EE
1041
37B9
349B
24BB
277C
43DE
41F7
247E
100E
5C8A
4316
3DC8
359C
4990
6D8A
124B
4630
29E9
0CA1
4043
342F
064F
674C
6648
5C93
21DD
171C
4797
4FB0
0210
4CFE
484B
4797
4F4A
426D
4FDC
049B
375F
3CEF
5859
114F
4267
40B5
37CF
7F3E
45C1
6533
71AC
0DE4
7987
1445
5350
443E
1878
636B
66D3
06F8
7D96
774A
61C9
5B31
3156
1F6A
32D6
3A4E
1D41
17CB
7F27
1EEF
0A6C
6482
6614
74F4
6486
602E
32E6
1376
7C8F
066F
0-Chip Delay
(Dec.)
(Hex.)
23393
5619
17052
21292
2868
19538
24294
22895
27652
29905
21415
1210
22396
26552
24829
8663
991
21926
23306
13646
148
24836
24202
9820
12939
2364
14820
2011
13549
28339
25759
11116
31448
27936
3578
12371
12721
10264
25344
13246
544
9914
4601
16234
24475
26318
6224
13381
30013
22195
1756
19068
28716
31958
16097
1308
3320
16682
6388
12828
3518
3494
6458
10717
8463
27337
19846
9388
21201
31422
166
28622
6477
10704
25843
25406
21523
8569
9590
22466
12455
27506
21847
28392
1969
30715
23674
22629
12857
30182
21880
6617
27707
16249
24754
31609
22689
3226
4167
25624
5B61
15F3
429C
532C
0B34
4C52
5EE6
596F
6C04
74D1
53A7
04BA
577C
67B8
60FD
21D7
03DF
55A6
5B0A
354E
0094
6104
5E8A
265C
328B
093C
39E4
07DB
34ED
6EB3
649F
2B6C
7AD8
6D20
0DFA
3053
31B1
2818
6300
33BE
0220
26BA
11F9
3F6A
5F9B
66CE
1850
3445
753D
56B3
06DC
4A7C
702C
7CD6
3EE1
051C
0CF8
412A
18F4
321C
0DBE
0DA6
193A
29DD
210F
6AC9
4D86
24AC
52D1
7ABE
00A6
6FCE
194D
29D0
64F3
633E
5413
2179
2576
57C2
30A7
6B72
5557
6EE8
07B1
77FB
5C7A
5865
3239
75E6
5578
19D9
6C3B
3F79
60B2
7B79
58A1
0C9A
1047
6418
. . . continued on next page
E-8
SC
4812ET Optimization/ATP Manual Software Release R16.1.x.x
PRELIMINARY
Aug 2002
PN Offset
68P09255A57-2
Table E-1: PnMaskI and PnMaskQ Values for PilotPn
Pilot
PN
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
14-Chip Delay
(Dec.)
(Hex.)
17418
14952
52
27254
15064
10942
377
14303
24427
26629
20011
16086
24374
9969
29364
25560
28281
7327
32449
26334
14760
15128
29912
4244
8499
9362
10175
30957
12755
19350
1153
29304
6041
21668
28048
10096
23388
15542
24013
2684
19018
25501
4489
31011
29448
25461
11846
30331
10588
32154
30173
15515
5371
10242
28052
14714
19550
8866
15297
10898
31315
19475
1278
11431
31392
4381
14898
23959
16091
9037
24162
6383
27183
16872
9072
12966
28886
25118
20424
6729
20983
12372
13948
27547
8152
17354
17835
14378
7453
26317
5955
10346
13200
30402
7311
3082
21398
31104
24272
27123
440A
3A68
0034
6A76
3AD8
2ABE
0179
37DF
5F6B
6805
4E2B
3ED6
5F36
26F1
72B4
63D8
6E79
1C9F
7EC1
66DE
39A8
3B18
74D8
1094
2133
2492
27BF
78ED
31D3
4B96
0481
7278
1799
54A4
6D90
2770
5B5C
3CB6
5DCD
0A7C
4A4A
639D
1189
7923
7308
6375
2E46
767B
295C
7D9A
75DD
3C9B
14FB
2802
6D94
397A
4C5E
22A2
3BC1
2A92
7A53
4C13
04FE
2CA7
7AA0
111D
3A32
5D97
3EDB
234D
5E62
18EF
6A2F
41E8
2370
32A6
70D6
621E
4FC8
1A49
51F7
3054
367C
6B9B
1FD8
43CA
45AB
382A
1D1D
66CD
1743
286A
3390
76C2
1C8F
0C0A
5396
7980
5ED0
69F3
13-Chip Delay
(Dec.)
(Hex.)
8709
7476
26
13627
7532
5471
20844
19007
32357
26066
30405
8043
12187
17064
14682
12780
26348
24479
28336
13167
7380
7564
14956
2122
16713
4681
16911
28070
18745
9675
21392
14652
23068
10834
14024
5048
11694
7771
32566
1342
9509
24606
22804
27969
14724
24682
5923
27373
5294
16077
29906
20593
17473
5121
14026
7357
9775
4433
21468
5449
29461
26677
639
22639
15696
18098
7449
24823
20817
24474
12081
16971
31531
8436
4536
6483
14443
12559
10212
17176
26311
6186
6974
31729
4076
8677
27881
7189
16562
32090
17821
5173
6600
15201
16507
1541
10699
15552
12136
31429
2205
1D34
001A
353B
1D6C
155F
516C
4A3F
7E65
65D2
76C5
1F6B
2F9B
42A8
395A
31EC
66EC
5F9F
6EB0
336F
1CD4
1D8C
3A6C
084A
4149
1249
420F
6DA6
4939
25CB
5390
393C
5A1C
2A52
36C8
13B8
2DAE
1E5B
7F36
053E
2525
601E
5914
6D41
3984
606A
1723
6AED
14AE
3ECD
74D2
5071
4441
1401
36CA
1CBD
262F
1151
53DC
1549
7315
6835
027F
586F
3D50
46B2
1D19
60F7
5151
5F9A
2F31
424B
7B2B
20F4
11B8
1953
386B
310F
27E4
4318
66C7
182A
1B3E
7BF1
0FEC
21E5
6CE9
1C15
40B2
7D5A
459D
1435
19C8
3B61
407B
0605
29CB
3CC0
2F68
7AC5
0-Chip Delay
(Dec.)
(Hex.)
30380
15337
10716
13592
2412
15453
13810
12956
30538
10814
18939
19767
20547
29720
31831
26287
11310
25724
21423
5190
258
13978
4670
23496
23986
839
11296
30913
27297
10349
32504
18405
3526
19161
23831
21380
4282
32382
806
6238
10488
19507
27288
2390
19094
13860
9225
2505
27806
2408
10924
23096
22683
10955
17117
15837
22647
10700
30293
5579
11057
30238
14000
22860
27172
307
20380
26427
10702
30024
14018
4297
13938
25288
27294
31835
8228
12745
6746
1456
27743
27443
31045
12225
21482
14678
30656
13721
21831
30208
9995
3248
12030
5688
2082
23143
25906
15902
21084
25723
76AC
3BE9
29DC
3518
096C
3C5D
35F2
329C
774A
2A3E
49FB
4D37
5043
7418
7C57
66AF
2C2E
647C
53AF
1446
0102
369A
123E
5BC8
5DB2
0347
2C20
78C1
6AA1
286D
7EF8
47E5
0DC6
4AD9
5D17
5384
10BA
7E7E
0326
185E
28F8
4C33
6A98
0956
4A96
3624
2409
09C9
6C9E
0968
2AAC
5A38
589B
2ACB
42DD
3DDD
5877
29CC
7655
15CB
2B31
761E
36B0
594C
6A24
0133
4F9C
673B
29CE
7548
36C2
10C9
3672
62C8
6A9E
7C5B
2024
31C9
1A5A
05B0
6C5F
6B33
7945
2FC1
53EA
3956
77C0
3599
5547
7600
270B
0CB0
2EFE
1638
0822
5A67
6532
3E1E
525C
647B
. . . continued on next page
Aug 2002
SC
4812ET Optimization/ATP Manual Software Release R16.1.x.x
PRELIMINARY
E-9
PN Offset
68P09255A57-2
Table E-1: PnMaskI and PnMaskQ Values for PilotPn
Pilot
PN
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
14-Chip Delay
(Dec.)
(Hex.)
29572
13173
10735
224
12083
22822
2934
27692
10205
7011
22098
2640
4408
102
27632
19646
26967
32008
7873
655
25274
16210
11631
8535
19293
12110
21538
10579
13032
14717
11666
25809
5008
32418
22175
11742
22546
21413
133
4915
8736
1397
18024
15532
26870
5904
24341
13041
23478
1862
5578
25731
10662
11084
31098
16408
6362
2719
14732
22744
1476
8445
21118
22198
22030
10363
25802
2496
31288
24248
14327
23154
13394
1806
17179
10856
25755
15674
7083
29096
3038
16277
25525
20465
28855
32732
20373
9469
26155
6957
12214
21479
31914
32311
11276
20626
423
2679
15537
10818
7384
3375
29EF
00E0
2F33
5926
0B76
6C2C
27DD
1B63
5652
0A50
1138
0066
6BF0
4CBE
6957
7D08
1EC1
028F
62BA
3F52
2D6F
2157
4B5D
2F4E
5422
2953
32E8
397D
2D92
64D1
1390
7EA2
569F
2DDE
5812
53A5
0085
1333
2220
0575
4668
3CAC
68F6
1710
5F15
32F1
5BB6
0746
15CA
6483
29A6
2B4C
797A
4018
18DA
0A9F
398C
58D8
05C4
20FD
527E
56B6
560E
287B
64CA
09C0
7A38
5EB8
37F7
5A72
3452
070E
431B
2A68
649B
3D3A
1BAB
71A8
0BDE
3F95
63B5
4FF1
70B7
7FDC
4F95
24FD
662B
1B2D
2FB6
53E7
7CAA
7E37
2C0C
5092
01A7
0A77
3CB1
2A42
13-Chip Delay
(Dec.)
(Hex.)
14786
18538
17703
112
17993
11411
1467
13846
16958
23649
11049
1320
2204
51
13816
9823
25979
16004
24240
20631
12637
8105
18279
16763
29822
6055
10769
17785
6516
19822
5833
25528
2504
16209
31391
5871
11273
30722
20882
22601
4368
21354
9012
7766
13435
2952
32346
18600
11739
931
2789
31869
5331
5542
15549
8204
3181
19315
7366
11372
738
24130
10559
11099
11015
23041
12901
1248
15644
12124
21959
11577
6697
903
28593
5428
31857
7837
17385
14548
1519
20982
32742
27076
30311
16366
27126
23618
32041
17322
6107
26575
15957
28967
5638
10313
20207
19207
20580
5409
39C2
486A
4527
0070
4649
2C93
05BB
3616
423E
5C61
2B29
0528
089C
0033
35F8
265F
657B
3E84
5EB0
5097
315D
1FA9
4767
417B
747E
17A7
2A11
4579
1974
4D6E
16C9
63B8
09C8
3F51
7A9F
16EF
2C09
7802
5192
5849
1110
536A
2334
1E56
347B
0B88
7E5A
48A8
2DDB
03A3
0AE5
7C7D
14D3
15A6
3CBD
200C
0C6D
4B73
1CC6
2C6C
02E2
5E42
293F
2B5B
2B07
5A01
3265
04E0
3D1C
2F5C
55C7
2D39
1A29
0387
6FB1
1534
7C71
1E9D
43E9
38D4
05EF
51F6
7FE6
69C4
7667
3FEE
69F6
5C42
7D29
43AA
17DB
67CF
3E55
7127
1606
2849
4EEF
4B07
5064
1521
0-Chip Delay
(Dec.)
(Hex.)
13347
7885
6669
8187
18145
14109
14231
27606
783
6301
5067
15383
1392
7641
25700
25259
19813
20933
638
16318
6878
1328
14744
22800
25919
4795
18683
32658
1586
27208
17517
599
16253
8685
29972
22128
19871
19405
17972
8599
10142
26834
23710
27280
6570
7400
26374
22218
29654
13043
13427
31084
24023
23931
15836
6085
30324
27561
13821
269
28663
29619
2043
6962
29119
22947
9612
18698
16782
29735
2136
8086
10553
11900
19996
5641
28328
25617
26986
5597
14078
13247
499
30469
17544
28510
23196
13384
4239
20725
6466
28465
19981
16723
4522
678
15320
29116
5388
22845
3423
1ECD
1A0D
1FFB
46E1
371D
3797
6BD6
030F
189D
13CB
3C17
0570
1DD9
6464
62AB
4D65
51C5
027E
3FBE
1ADE
0530
3998
5910
653F
12BB
48FB
7F92
0632
6A48
446D
0257
3F7D
21ED
7514
5670
4D9F
4BCD
4634
2197
279E
68D2
5C9E
6A90
19AA
1CE8
6706
56CA
73D6
32F3
3473
796C
5DD7
5D7B
3DDC
17C5
7674
6BA9
35FD
010D
6FF7
73B3
07FB
1B32
71BF
59A3
258C
490A
418E
7427
0858
1F96
2939
2E7C
4E1C
1609
6EA8
6411
696A
15DD
36FE
33BF
01F3
7705
4488
6F5E
5A9C
3448
108F
50F5
1942
6F31
4E0D
4153
11AA
02A6
3BD8
71BC
150C
593D
. . . continued on next page
E-10
SC
4812ET Optimization/ATP Manual Software Release R16.1.x.x
PRELIMINARY
Aug 2002
PN Offset
68P09255A57-2
Table E-1: PnMaskI and PnMaskQ Values for PilotPn
Pilot
PN
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
14-Chip Delay
(Dec.)
(Hex.)
5850
5552
12589
23008
27636
17600
17000
21913
30320
28240
7260
17906
5882
22080
12183
23082
17435
18527
31902
18783
20027
7982
20587
10004
13459
13383
28930
4860
13108
24161
20067
2667
13372
28743
24489
249
19960
29682
31101
27148
26706
5148
4216
5762
245
21882
3763
206
28798
32402
23074
20250
14629
29175
13943
11072
29492
5719
7347
12156
25623
27725
28870
31478
28530
24834
9075
32265
3175
17434
12178
25613
31692
25384
18908
25816
4661
31115
7691
1311
16471
15771
16112
21062
29690
10141
19014
22141
11852
26404
30663
32524
28644
10228
23536
18045
25441
27066
13740
13815
16DA
15B0
312D
59E0
6BF4
44C0
4268
5599
7670
6E50
1C5C
45F2
16FA
5640
2F97
5A2A
441B
485F
7C9E
495F
4E3B
1F2E
506B
2714
3493
3447
7102
12FC
3334
5E61
4E63
0A6B
343C
7047
5FA9
00F9
4DF8
73F2
797D
6A0C
6852
141C
1078
1682
00F5
557A
0EB3
00CE
707E
7E92
5A22
4F1A
3925
71F7
3677
2B40
7334
1657
1CB3
2F7C
6417
6C4D
70C6
7AF6
6F72
6102
2373
7E09
0C67
441A
2F92
640D
7BCC
6328
49DC
64D8
1235
798B
1E0B
051F
4057
3D9B
3EF0
5246
73FA
279D
4A46
567D
2E4C
6724
77C7
7F0C
6FE4
27F4
5BF0
467D
6361
69BA
35AC
35F7
13-Chip Delay
(Dec.)
(Hex.)
2925
2776
18758
11504
13818
8800
8500
31516
15160
14120
3630
8953
2941
11040
17947
11541
29661
30207
15951
30079
30413
3991
31205
5002
19353
19443
14465
2430
6554
32480
30433
21733
6686
27123
32260
20908
9980
14841
28014
13574
13353
2574
2108
2881
20906
10941
22153
103
14399
16201
11537
10125
21166
30407
21767
5536
14746
17687
16485
6078
31799
30746
14435
15739
14265
12417
24453
28984
18447
8717
6089
31802
15846
12692
9454
12908
18214
29433
16697
19635
28183
20721
8056
10531
14845
24050
9507
25858
5926
13202
30175
16262
14322
5114
11768
27906
32652
13533
6870
21703
0B6D
0AD8
4946
2CF0
35FA
2260
2134
7B1C
3B38
3728
0E2E
22F9
0B7D
2B20
461B
2D15
73DD
75FF
3E4F
757F
76CD
0F97
79E5
138A
4B99
4BF3
3881
097E
199A
7EE0
76E1
54E5
1A1E
69F3
7E04
51AC
26FC
39F9
6D6E
3506
3429
0A0E
083C
0B41
51AA
2ABD
5689
0067
383F
3F49
2D11
278D
52AE
76C7
5507
15A0
399A
4517
4065
17BE
7C37
781A
3863
3D7B
37B9
3081
5F85
7138
480F
220D
17C9
7C3A
3DE6
3194
24EE
326C
4726
72F9
4139
4CB3
6E17
50F1
1F78
2923
39FD
5DF2
2523
6502
1726
3392
75DF
3F86
37F2
13FA
2DF8
6D02
7F8C
34DD
1AD6
54C7
0-Chip Delay
(Dec.)
(Hex.)
24457
17161
21314
28728
22162
26259
22180
2266
10291
26620
19650
14236
11482
25289
12011
13892
17336
10759
26816
31065
8578
24023
16199
22310
30402
16613
13084
3437
1703
22659
26896
1735
16178
19166
665
20227
24447
16771
27209
6050
29088
7601
4905
5915
6169
21303
28096
8905
26997
15047
28430
8660
2659
8803
19690
22169
8511
17393
11336
13576
22820
13344
20107
8013
18835
16793
9818
4673
13609
10054
10988
14744
17930
25452
11334
15451
11362
2993
11012
5806
20180
8932
23878
20760
32764
32325
25993
3268
25180
12149
10193
9128
7843
25474
11356
11226
16268
14491
8366
26009
5F89
4309
5342
7038
5692
6693
56A4
08DA
2833
67FC
4CC2
379C
2CDA
62C9
2EEB
3644
43B8
2A07
68C0
7959
2182
5DD7
3F47
5726
76C2
40E5
331C
0D6D
06A7
5883
6910
06C7
3F32
4ADE
0299
4F03
5F7F
4183
6A49
17A2
71A0
1DB1
1329
171B
1819
5337
6DC0
22C9
6975
3AC7
6F0E
21D4
0A63
2263
4CEA
5699
213F
43F1
2C48
3508
5924
3420
4E8B
1F4D
4993
4199
265A
1241
3529
2746
2AEC
3998
460A
636C
2C46
3C5B
2C62
0BB1
2B04
16AE
4ED4
22E4
5D46
5118
7FFC
7E45
6589
0CC4
625C
2F75
27D1
23A8
1EA3
6382
2C5C
2BDA
3F8C
389B
20AE
6599
. . . continued on next page
Aug 2002
SC
4812ET Optimization/ATP Manual Software Release R16.1.x.x
PRELIMINARY
E-11
PN Offset
68P09255A57-2
Table E-1: PnMaskI and PnMaskQ Values for PilotPn
Pilot
PN
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
14-Chip Delay
(Dec.)
(Hex.)
13463
15417
23101
14957
23429
12990
12421
28875
4009
1872
15203
30109
24001
4862
14091
6702
3067
28643
21379
20276
25337
19683
10147
16791
17359
13248
22740
13095
10345
30342
27866
9559
8808
12744
11618
27162
17899
29745
31892
23964
23562
2964
18208
15028
21901
24566
18994
13608
27492
11706
3684
23715
15314
32469
9816
4444
5664
7358
27264
28128
30168
29971
3409
16910
20739
10191
12819
19295
10072
15191
27748
720
29799
27640
263
24734
16615
20378
25116
19669
14656
27151
28728
25092
22601
2471
25309
15358
17739
12643
32730
19122
16870
10787
18400
20295
1937
17963
7438
12938
3497
3C39
5A3D
3A6D
5B85
32BE
3085
70CB
0FA9
0750
3B63
759D
5DC1
12FE
370B
1A2E
0BFB
6FE3
5383
4F34
62F9
4CE3
27A3
4197
43CF
33C0
58D4
3327
2869
7686
6CDA
2557
2268
31C8
2D62
6A1A
45EB
7431
7C94
5D9C
5C0A
0B94
4720
3AB4
558D
5FF6
4A32
3528
6B64
2DBA
0E64
5CA3
3BD2
7ED5
2658
115C
1620
1CBE
6A80
6DE0
75D8
7513
0D51
420E
5103
27CF
3213
4B5F
2758
3B57
6C64
02D0
7467
6BF8
0107
609E
40E7
4F9A
621C
4CD5
3940
6A0F
7038
6204
5849
09A7
62DD
3BFE
454B
3163
7FDA
4AB2
41E6
2A23
47E0
4F47
0791
462B
1D0E
328A
13-Chip Delay
(Dec.)
(Hex.)
19355
20428
31950
19686
31762
6495
18834
27061
22020
936
19553
27422
32560
2431
19029
3351
21549
26145
30737
10138
24748
30625
16897
28955
28727
6624
11370
18499
17892
15171
13933
17275
4404
6372
5809
13581
29477
27592
15946
11982
11781
1482
9104
7514
31510
12283
9497
6804
13746
5853
1842
24685
7657
29014
4908
2222
2832
3679
13632
14064
15084
29877
18580
8455
26301
24027
22325
27539
5036
21399
13874
360
29711
13820
20159
12367
28239
10189
12558
26710
7328
31547
14364
12546
25112
19183
32594
7679
27801
22157
16365
9561
8435
23341
9200
27039
19956
27945
3719
6469
4B9B
4FCC
7CCE
4CE6
7C12
195F
4992
69B5
5604
03A8
4C61
6B1E
7F30
097F
4A55
0D17
542D
6621
7811
279A
60AC
77A1
4201
711B
7037
19E0
2C6A
4843
45E4
3B43
366D
437B
1134
18E4
16B1
350D
7325
6BC8
3E4A
2ECE
2E05
05CA
2390
1D5A
7B16
2FFB
2519
1A94
35B2
16DD
0732
606D
1DE9
7156
132C
08AE
0B10
0E5F
3540
36F0
3AEC
74B5
4894
2107
66BD
5DDB
5735
6B93
13AC
5397
3632
0168
740F
35FC
4EBF
304F
6E4F
27CD
310E
6856
1CA0
7B3B
381C
3102
6218
4AEF
7F52
1DFF
6C99
568D
3FED
2559
20F3
5B2D
23F0
699F
4DF4
6D29
0E87
1945
0-Chip Delay
(Dec.)
(Hex.)
17460
17629
10461
21618
11498
193
16140
13419
10864
28935
18765
27644
21564
5142
1211
1203
5199
16945
4883
25040
7119
17826
4931
25705
10726
17363
2746
10952
19313
29756
14297
21290
1909
8994
13295
21590
26468
13636
5207
29493
18992
12567
12075
26658
21077
15595
4921
14051
5956
21202
5164
17126
21566
21845
28149
9400
19459
7190
3101
491
25497
29807
26508
4442
4871
31141
9864
12589
5417
8549
14288
8503
20357
15381
18065
24678
23858
7610
18097
20918
7238
30549
16320
20853
26736
10327
24404
7931
5310
554
27311
6865
7762
15761
12697
24850
15259
24243
30508
13982
4434
44DD
28DD
5472
2CEA
00C1
3F0C
346B
2A70
7107
494D
6BFC
543C
1416
04BB
04B3
144F
4231
1313
61D0
1BCF
45A2
1343
6469
29E6
43D3
0ABA
2AC8
4B71
743C
37D9
532A
0775
2322
33EF
5456
6764
3544
1457
7335
4A30
3117
2F2B
6822
5255
3CEB
1339
36E3
1744
52D2
142C
42E6
543E
5555
6DF5
24B8
4C03
1C16
0C1D
01EB
6399
746F
678C
115A
1307
79A5
2688
312D
1529
2165
37D0
2137
4F85
3C15
4691
6066
5D32
1DBA
46B1
51B6
1C46
7755
3FC0
5175
6870
2857
5F54
1EFB
14BE
022A
6AAF
1AD1
1E52
3D91
3199
6112
3B9B
5EB3
772C
369E
. . . continued on next page
E-12
SC
4812ET Optimization/ATP Manual Software Release R16.1.x.x
PRELIMINARY
Aug 2002
PN Offset
68P09255A57-2
Table E-1: PnMaskI and PnMaskQ Values for PilotPn
Pilot
PN
501
502
503
504
505
506
507
508
509
510
511
14-Chip Delay
(Dec.)
(Hex.)
14301
23380
11338
2995
23390
14473
6530
20452
12226
1058
12026
19272
29989
8526
18139
3247
28919
7292
20740
27994
2224
6827
37DD
5B54
2C4A
0BB3
5B5E
3889
1982
4FE4
2FC2
0422
2EFA
4B48
7525
214E
46DB
0CAF
70F7
1C7C
5104
6D5A
08B0
1AAB
13-Chip Delay
(Dec.)
(Hex.)
19006
11690
5669
21513
11695
19860
3265
10226
6113
529
6013
9636
29870
4263
27985
18539
30279
3646
10370
13997
1112
17257
4A3E
2DAA
1625
5409
2DAF
4D94
0CC1
27F2
17E1
0211
177D
25A4
74AE
10A7
6D51
486B
7647
0E3E
2882
36AD
0458
4369
0-Chip Delay
(Dec.)
(Hex.)
11239
30038
30222
13476
2497
31842
24342
25857
27662
24594
16790
25039
24086
21581
21346
28187
23231
18743
11594
7198
105
4534
2BE7
7556
760E
34A4
09C1
7C62
5F16
6501
6C0E
6012
4196
61CF
5E16
544D
5362
6E1B
5ABF
4937
2D4A
1C1E
0069
11B6
Aug 2002
SC
4812ET Optimization/ATP Manual Software Release R16.1.x.x
PRELIMINARY
E-13
PN Offset
68P09255A57-2
Notes
E-14
SC
4812ET Optimization/ATP Manual Software Release R16.1.x.x
PRELIMINARY
Aug 2002
Appendix F
Test Preparation
Aug 2002
SC
4812ET Optimization/ATP Manual Software Release R16.1.x.x
PRELIMINARY
F-1
Test Equipment Setup
68P09255A57-2
Test Equipment Setup
Purpose
This appendix provides information on setting up the HP8921 with PCS
interface, the HP8935 and the Advantest R3465. The Cybertest test set
doesn’t require any setup.
HP8921A Test Equipment Connections
Table F-1 depicts the rear panels of the HP 8921A test equipment as
configured to perform automatic tests. All test equipment is controlled
by the LMF via an IEEE-488/GPIB bus. The LMF expects each piece
of test equipment to have a factory-set GPIB address (refer to Table F-4).
If there is a communications problem between the LMF and any piece
of test equipment, you should verify that the GPIB addresses have been
set correctly and that the GPIB cables are firmly connected to the test
equipment.
Figure F-1 shows the connections when not using an external 10 MHz
Rubidium reference.
Table F-1: HP8921A/600 Communications Test Set Rear Panel Connections Without Rubidium
From Test Set:
8921A
CW RF OUT
114.3 MHZ IF OUT
IQ RF IN
DET OUT
CONTROL I/O
10 MHZ OUT
HPIB INTERFACE
To Interface:
83203B CDMA
CW RF IN
114.3 MHZ IF IN
IQ RF OUT
AUX DSP IN
CONTROL I/O
SYNTH REF IN
10 MHZ OUT
F-2
83236A PCS
HPIB INTERFACE
REF IN
Connector Type
SMC-female - SMC-female
SMC-female - SMC-female
SMC-female - SMC-female
SMC-female - SMC-female
45-pin custom BUS
BNC-male - BNC-male
HPIB cable
BNC-male - BNC-male
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Figure F-1: HP8921A/600 Cables Connection for 10 MHz Signal and GPIB without Rubidium
HP83203B CDMA
CELLULAR ADAPTER
TO POWER
METER GPIB
CONNECTOR
ÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌ
TO GPIB
INTERFACE
BOX
HP8921A CELL
SITE TEST SET
HP83236A PCS
INTERFACE
REF IN
HP-IB
FW00368
REAR PANEL
COMMUNICATIONS TEST SET
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Test Equipment Setup
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Figure F-2 shows the connections when using an external 10 MHz
Rubidium reference.
Table F-2: HP8921A/600 Communications Test Set Rear Panel Connections With Rubidium
From Test Set:
8921A
CW RF OUT
114.3 MHZ IF OUT
IQ RF IN
DET OUT
CONTROL I/O
10 MHZ OUT
HPIB INTERFACE
10 MHZ INPUT
To Interface:
83203B CDMA
83236A PCS
CW RF IN
114.3 MHZ IF IN
IQ RF OUT
AUX DSP IN
CONTROL I/O
REF IN
HPIB INTERFACE
10 MHZ OUT
Connector Type
SMC-female - SMC-female
SMC-female - SMC-female
SMC-female - SMC-female
SMC-female - SMC-female
45-pin custom BUS
BNC-male - BNC-male
HPIB cable
BNC-male - BNC-male
F-4
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Test Equipment Setup
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Figure F-2: HP8921A Cables Connection for 10 MHz Signal and GPIB with Rubidium
10 MHZ WITH
RUBIDIUM STANDARD
HP83203B CDMA
CELLULAR ADAPTER
TO POWER
METER GPIB
CONNECTOR
ÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌ
TO GPIB
INTERFACE
BOX
HP8921A CELL
SITE TEST SET
HP83236A PCS
INTERFACE
REF IN
HP-IB
FW00369
REAR PANEL
COMMUNICATIONS TEST SET
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Test Equipment Setup
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HP8921A System Connectivity Test
Follow the steps in Table F-3 to verify that the connections between the
PCS Interface and the HP8921A are correct and cables are intact. The
software also performs basic functionality checks of each instrument.
NOTE
Disconnect other GPIB devices, especially system controllers,
from the system before running the connectivity software.
Table F-3: System Connectivity
Step
Action
* IMPORTANT
- Perform this procedure after test equipment has been allowed to warm-up and stabilize for a
minimum of 60 minutes.
Insert HP 83236A Manual Control/System card into memory card slot.
Press the [PRESET] pushbutton.
Press the Screen Control [TESTS] pushbutton to display the “Tests” Main Menu screen.
Position the cursor at Select Procedure Location and select it by pressing the cursor control knob. In
the Choices selection box, select Card.
Position the cursor at Select Procedure Filename and select it by pressing the cursor control knob. In
the Choices selection box, select SYS_CONN.
Position the cursor at RUN TEST and select it. The software will prompt you through the
connectivity setup.
Do the following when the test is complete,
 position cursor on STOP TEST and select it
 OR press the [K5] pushbutton.
To return to the main menu, press the [K5] pushbutton.
Press the [PRESET] pushbutton.
Setting HP8921A and HP83236A/B GPIB Address
Follow the steps in Table F-4 to set the HP8921A GPIB address.
Table F-4: Setting HP8921A GPIB Address
Step
Action
If you have not already done so, turn the HP8921A power on.
Verify that the GPIB addresses are set correctly.
 HP8921A HP-IB Adrs = 18, accessed by pushing LOCAL and selecting More and I/O Configure
on the HP8921A/600. (Consult test equipment OEM documentation for additional info as required).
 HP83236A (or B) PCS Interface GPIB address=19. Set dip switches as follows:
- A1=1, A2=1, A3=0, A4=0, A5=1, HP-IB/Ser = 1
F-6
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Pretest Setup for HP8921A
Before the HP8921A CDMA analyzer is used for LMF controlled testing
it must be set up correctly for automatic testing.
Table F-5: Pretest Setup for HP8921A
Step
Action
Unplug the memory card if it is plugged in.
Press the CURSOR CONTROL knob.
Position the cursor at IO CONFIG (under To Screen and More) and select it.
Select Mode and set for Talk&Lstn.
Pretest Setup for HP8935
Before the HP8935 CDMA analyzer is used for LMF controlled testing
it must be set up correctly for automatic testing.
Table F-6: Pretest Setup for HP8935
Step
Action
Unplug the memory card if it is plugged in.
Press the Shift button and then press the I/O Config button.
Press the Push to Select knob.
Position the cursor at IO CONFIG and select it.
Select Mode and set for Talk&Lstn.
Advantest R3465 Connection
The following diagram depicts the rear panels of the Advantest test
equipment as configured to perform automatic tests. All test equipment
is controlled by the LMF via an IEEE-488/GPIB bus. The LMF expects
each piece of test equipment to have a factory-set GPIB address (refer to
Table F-7). If there is a communications problem between the LMF and
any piece of test equipment, you should verify that the GPIB addresses
have been set correctly and that the GPIB cables are firmly connected to
the test equipment.
Figure F-3 shows the connections when not using an external 10 MHz
Rubidium reference.
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Test Equipment Setup
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Figure F-3: Cable Connections for Test Set without 10 MHz Rubidium Standard
SERIAL I/O CDMA CLOCK OUT
R3561L
REAR PANEL
SYN REF IN
LOCAL IN
TO POWER METER
GPIB CONNECTOR
PARALLEL
10 MHZ OUT
AC POWER
SERIAL I/O
R3465
REAR PANEL
GATE IN EXT TRIGGER
AC POWER
GPIB
TO GPIB
INTERFACE BOX
10 MHZ REF
IF OUT
421 MHZ
FW00370
GPIB
CONNECTOR
ADVANTEST R3465
REAR PANEL
TO T-CONNECTOR
ON FRONT PANEL
(EVEN/SEC/SYNC IN)
F-8
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Figure F-4 shows the connections when using an external 10 MHz
Rubidium reference.
Figure F-4: Cable Connections for Test Set with 10 MHz Rubidium Standard
FROM 10 MHZ
RUBIDIUM REFERENCE
SERIAL I/O CDMA CLOCK OUT
R3561L
REAR PANEL
SYN REF IN
LOCAL IN
TO POWER METER
GPIB CONNECTOR
PARALLEL
10 MHZ OUT
AC POWER
SERIAL I/O
R3465/3463
REAR PANEL
GATE IN EXT TRIGGER
AC POWER
GPIB
TO GPIB
INTERFACE BOX
10 MHZ REF
IF OUT
421 MHZ
FW00371
GPIB
CONNECTOR
Aug 2002
ADVANTEST R3465
REAR PANEL
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TO T-CONNECTOR
ON FRONT PANEL
(EVEN SEC/SYNC IN)
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Test Equipment Setup
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R3465 GPIB Address & Clock setup
Follow the steps in Table F-7 to set the GPIB address and clock for the
Advantest R3465 equipment.
Table F-7: Advantest R3465 GPIB Address and Clock Setup
Step
Action
Communications test set GPIB address=18 (perform the following to view/set as required)
Perform the following to set the standard parameters on the test set:
 Push the SHIFT then PRESET pushbutton (just below the CRT display).
 Push the LCL pushbutton (CW in Measurement just below the CRT display)
- Push the GPIB and Others CRT menu key to view the current address.
- If required, change GPIB address to 18 (rotate the vernier knob to set, push the vernier knob to
enter)
Verify the current Date and Time in upper/right of the CRT display (perform the following to set if
required)
Communications test set GPIB address=18 (perform the following to view/set as required)
 Push the Date/Time CRT menu key
 If required, change to correct Date/Time (rotate the vernier knob to select and set, push the vernier
knob to enter)
 Push the SHIFT then PRESET pushbutton (just below the CRT display).
Pretest Setup for Advantest R3465
Before the Advantest R3465 analyzer is used for LMF controlled testing
it must be set up correctly for automatic testing.
Table F-8: Pretest Setup for Advantest R3465
Step
Action
Press the SHIFT button so the LED next to it is illuminated.
Press the RESET button.
F-10
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